Semiconductor device

Abstract

This semiconductor device is provided with: first and second electrodes provided on first and second main surfaces of a semiconductor layer, respectively; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a plurality of insulating regions extending from the first main surface to the first semiconductor region in a second direction orthogonal to a first direction from the second electrode toward the first electrode; the plurality of third electrodes are arranged in the plurality of insulating areas and extend in the second direction; a second semiconductor region of a second conductivity type, which is sandwiched by the plurality of insulating regions, is positioned on the first semiconductor region, and extends in the second direction; a third semiconductor region of the first conductivity type between the second semiconductor region and the first electrode; and a carrier conduction part which extends in the second direction in the second semiconductor region and is electrically connected to the first electrode via a connection part that does not penetrate the third semiconductor region.

Description

[0001]

Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2023-153941 (filing date: September 20, 2023). This application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Art

[0004] Inverters for driving motors, etc. use power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). In order to prevent the element from being destroyed by the back electromotive force generated during switching, the power MOSFET needs to have avalanche resistance.

[0005] As a method for improving avalanche tolerance, it is considered to suppress the action of the parasitic bipolar of the MOSFET. The parasitic bipolar is easily acted by the minority carriers accumulated in the base region, so the avalanche tolerance can be improved by discharging the minority carriers accumulated in the base region to the outside. Therefore, for example, a contact composed of a p-type semiconductor region or a metal material is formed in a manner that penetrates the source region from the source electrode and reaches the base layer. However, such a contact is set in a manner that penetrates the source region, so the area of ​​the source region is reduced and the on-resistance of the semiconductor device is increased. Summary of the invention

[0006] The semiconductor device of this embodiment comprises: a semiconductor layer having a first main surface and a second main surface; a first electrode arranged on the first main surface; a second electrode arranged on the second main surface; a first semiconductor region of a first conductivity type arranged in the semiconductor layer and located above the second electrode; a plurality of insulating regions arranged in the semiconductor layer, reaching the first semiconductor region from the first main surface, and extending in a second direction orthogonal to the first direction from the second electrode toward the first electrode; a plurality of third electrodes arranged in the plurality of insulating regions and extending in the second direction; a second semiconductor region of a second conductivity type arranged in the semiconductor layer, sandwiched by the plurality of insulating regions, so as to be located above the first semiconductor region and extending in the second direction; a third semiconductor region of a first conductivity type arranged in the semiconductor layer, so as to be located between the second semiconductor region and the first electrode; and a carrier conduction portion arranged in the second semiconductor region so as to extend in the second direction, and electrically connected to the first electrode via a connection portion that does not penetrate the third semiconductor region.

[0007] According to the embodiment of the present invention, it is possible to provide a semiconductor device capable of suppressing an increase in on-resistance and improving avalanche resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a top view of the semiconductor device according to the first embodiment.

[0009] Figure 2 is a cross-sectional view of the semiconductor device of the first embodiment, taken along Figure 1 Cross-sectional view of line II.

[0010] Figure 3 is another cross-sectional view of the semiconductor device according to the first embodiment, showing the semiconductor device along the Figure 1 FIG. 1 is a diagram of a portion of a cross section taken along line II-II.

[0011] Figure 4A It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0012] Figure 4B Then Figure 4A A cross-sectional view for explaining an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0013] Figure 4C Then Figure 4B A cross-sectional view for explaining an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0014] Figure 4D Then Figure 4C A cross-sectional view for explaining an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0015] Figure 5 is a cross-sectional view of a semiconductor device according to a second embodiment, taken along Figure 1 Cross-sectional view of line II.

[0016] Figure 6 is another cross-sectional view of the semiconductor device according to the second embodiment, showing the semiconductor device along the Figure 1 FIG. 1 is a diagram of a portion of a cross section taken along line II-II.

[0017] Fig. 7A It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the second embodiment.

[0018] Figure 7B Then Fig. 7A A cross-sectional view for explaining an example of a manufacturing process of a semiconductor device according to a second embodiment.

[0019] Figure 7CThen Figure 7B A cross-sectional view for explaining an example of a manufacturing process of a semiconductor device according to a second embodiment.

[0020] Fig.7D Then Figure 7C A cross-sectional view for explaining an example of a manufacturing process of a semiconductor device according to a second embodiment.

[0021] Fig. 7E Then Fig.7D A cross-sectional view for explaining an example of a manufacturing process of a semiconductor device according to a second embodiment.

[0022] Figure 8 It is a top view of the semiconductor device according to the third embodiment.

[0023] Fig. 9 is a cross-sectional view of a semiconductor device according to a third embodiment, taken along Figure 8 Cross-sectional view along line III-III.

[0024] [Explanation of Reference Numerals]

[0025] 1 Semiconductor devices

[0026] 11 Source electrode

[0027] 12 Drain electrode

[0028] 13. Gate electrode

[0029] 21 Drift Zone

[0030] 221 Base area

[0031] 222, 223, 224 connection area

[0032] 23 Source region

[0033] 24 Drain region

[0034] 31. Gate insulating film

[0035] 32 interlayer insulation film

[0036] 41, 43 Carrier conduction unit

[0037] 42, 44 connection

[0038] 50 Gate pad

[0039] 51 Gate wiring DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments do not limit the present invention. The accompanying drawings are schematic or conceptual, and the ratios of the various parts may not be the same as in reality. In the specification and the accompanying drawings, the same reference numerals are given to the same elements as those previously described with respect to the accompanying drawings that have already appeared, and detailed descriptions are appropriately omitted.

[0041] In addition, for the sake of convenience, Figure 1 to Figure 3 As shown in the figure, an XYZ orthogonal coordinate system is used. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. In addition, the source electrode side in the Z-axis direction is also called "upper", and the drain electrode side is also called "lower". However, this expression is for convenience and has nothing to do with the direction of gravity. The X-axis direction is the second direction in the claims. The Z-axis direction is the first direction in the claims.

[0042] In the following description, n is sometimes used to indicate the relative high and low impurity concentrations in each conductivity type. + 、n、n - , and p + ,p,p - That is, n + Indicates that the concentration of n-type impurities is relatively higher than n, n - Indicates that the n-type impurity concentration is relatively lower than n. In addition, p + Indicates that the p-type impurity concentration is relatively higher than p, p - Indicates that the p-type impurity concentration is relatively lower than p. These expressions indicate the relative height of the actual impurity concentration after compensation of these impurities when both p-type and n-type impurities are contained in each region. + Type and n - The p-type is an example of the first conductivity type in the claims. + Type and p - The first conductivity type is an example of the second conductivity type in the claims. In addition, in the following description, the n-type and the p-type may be reversed. That is, the first conductivity type may also be the p-type.

[0043] (First Embodiment)

[0044] <Semiconductor Device>

[0045] Reference Figure 1 to Figure 3 , a semiconductor device 1 according to a first embodiment will be described. Figure 1 It is a top view of the semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view of the semiconductor device of the first embodiment, taken along Figure 1 Cross-sectional view of line II. Figure 3 is another cross-sectional view of the semiconductor device according to the first embodiment, showing Figure 1FIG. 1 is a diagram of a portion of a cross section taken along line II-II.

[0046] The semiconductor device 1 of the present embodiment is a vertical MOSFET, etc. Hereinafter, a case where the semiconductor device 1 is a vertical MOSFET will be described.

[0047] like Figure 2 As shown, the semiconductor device 1 includes a semiconductor layer 2, a source electrode 11 provided on an upper surface (first main surface) 2a of the semiconductor layer 2, and a drain electrode 12 provided on a lower surface (second main surface) 2b of the semiconductor layer 2. Figure 1 In the figure, the source electrode 11 provided on the upper surface 2a of the semiconductor layer 2 and the interlayer insulating film 32 described later are omitted. Figure 1 1 shows one of the plurality of carrier conducting portions 41. In addition, for convenience of explanation, the upper surface 2a and the lower surface 2b of the semiconductor layer 2 are substantially planar, but this does not limit the shape of the semiconductor layer 2.

[0048] The semiconductor layer 2 is arranged on the drain electrode 12. The semiconductor layer 2 may be an epitaxial layer, or a semiconductor substrate, or a semiconductor substrate and an epitaxial layer arranged thereon. In the present embodiment, the semiconductor layer 2 is silicon (Si). In this case, as an n-type impurity, for example, arsenic (As), phosphorus (P) or antimony (Sb) is used, and as a p-type impurity, for example, boron (B) is used. In addition, the semiconductor layer 2 may also be composed of compound semiconductors such as silicon carbide (SiC) and gallium nitride (GaN).

[0049] The source electrode 11 is an electrode that functions as a source electrode of the MOSFET. The source electrode 11 is made of, for example, copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), etc. The source electrode 11 is an example of a first electrode in the claims.

[0050] The drain electrode 12 is an electrode that functions as a drain electrode of the MOSFET. The drain electrode 12 is made of, for example, a metal such as copper, titanium, tungsten, or aluminum. The drain electrode 12 is an example of a second electrode in the claims.

[0051] The semiconductor layer 2 includes a drift region 21, a drain region 24, a gate insulating film 31, a gate electrode 13, a base region 221, a connection region 222, a connection region 223, and a source region 23. In addition, an interlayer insulating film 32 is provided on a portion of the upper surface 2a of the semiconductor layer 2. The components provided in the semiconductor layer 2 are described below.

[0052] The drift region 21 is a semiconductor region that functions as a drift region of the MOSFET. The drift region 21 is disposed on the drain region 24 (above the drain electrode 12). The drift region 21 is, for example, n - The n-type impurity concentration of the drift region 21 is, for example, 1×10 15 cm -3 And 2×10 16 cm -3 The drift region 21 is an example of a first semiconductor region in the claims.

[0053] A drain region 24 is disposed between the drift region 21 and the drain electrode 12. The drain region 24 is a semiconductor region that functions as a drain region of the MOSFET. The drain region 24 is, for example, n + The n-type impurity concentration of the drain region 24 is, for example, 1×10 18 cm -3 Above and 1×10 21 cm -3 The drain region 24 is an example of a first semiconductor region in the claims.

[0054] Furthermore, the first semiconductor region in the claims may include both the drift region 21 and the drain region 24 , or may include only one of the drift region 21 and the drain region 24 .

[0055] like Figure 3 As shown in FIG. 2 , the plurality of gate insulating films 31 are provided so as to extend from the upper surface 2a of the semiconductor layer 2 to the drift region 21. Figure 1 As shown in the figure, each gate insulating film 31 extends in the X direction. The gate insulating film 31 is composed of a dielectric that covers the sidewalls of a plurality of gate trenches that are provided on the upper surface 2a of the semiconductor layer 2 in a manner extending in the X direction. The gate insulating film 31 is composed of a dielectric such as silicon oxide or silicon nitride. The gate insulating film 31 is an example of an insulating region in the claims. In addition, in the present embodiment, a gate trench is provided on the upper surface 2a of the semiconductor layer 2, but this does not limit the shape of the semiconductor layer 2.

[0056] like Figure 3 As shown in FIG. 1 , a gate electrode 13 is provided in each gate insulating film 31 . The gate electrode 13 is an electrode that functions as a gate electrode of a MOSFET. Each gate electrode 13 extends in the X direction. The gate electrode 13 is electrically insulated from the semiconductor layer 2 by the gate insulating film 31 . Figure 3In the example shown, the upper end of the gate electrode 13 is located at a position higher than the upper end of the base region 221 described later, and the lower end of the gate electrode 13 is located at a position lower than the lower end of the base region 221. The gate electrode 13 is arranged adjacent to (opposed to) the base region 221 via the gate insulating film 31. The gate electrode 13 is composed of, for example, polysilicon containing p-type or n-type impurities. The gate electrode 13 is an example of a third electrode in the claims.

[0057] In addition, although not shown, field plate (FP) electrodes may be provided below the gate electrode 13 in each gate insulating film 31. Each FP electrode is electrically connected to the source electrode 11. By providing such FP electrodes, when the MOSFET is in the off state, the depletion layer extends to the drift region 21 around the FP electrode by applying a voltage between the source electrode 11 and the drain electrode 12. This depletion layer is connected to the depletion layer extending around the adjacent FP electrode, and the withstand voltage of the semiconductor device 1 can be improved.

[0058] like Figure 3 As shown in FIG. 1 , the base regions 221 are provided in a manner sandwiched by the gate insulating film 31. Figure 2 As shown, the base region 221 is located above the drift region 21 and extends in the X-axis direction. The base region 221 is a semiconductor region that functions as a base region of the MOSFET. When a voltage is applied to the gate electrode 13, a channel is formed in the base region 221, and carriers flow between the drift region 21 and the source region 23. The base region 221 is, for example, a p-type semiconductor region. The p-type impurity concentration of the base region 221 is, for example, 1×10 16 cm -3 Above and 1×10 20 cm -3 The base region 221 is an example of a second semiconductor region in the claims.

[0059] like Figure 2 As shown in FIG. 1 , a connection region 222 and a connection region 223 are provided between the two ends of the base region 221 in the X-axis direction and the source electrode 11. More specifically, the connection region 222 extends from one end of the base region 221 in the X-axis direction (at Figure 2 The connection region 223 extends from the other end of the base region 221 in the X-axis direction (at the left end in the middle) to the source electrode 11 along the Z-axis direction, connecting the base region 221 to the source electrode 11. Figure 2 The connection region 222 is an example of a first connection region in the claims. The connection region 223 is an example of a second connection region in the claims.

[0060] The connection region 222 and the connection region 223 separate the drift region 21 from the source region 23 described later, and separate the drift region 21 from the connection portion 42 described later. In the present embodiment, the connection region 222 and the connection region 223 are p-type semiconductor regions having an impurity concentration equal to that of the base region 221. Thus, the base region 221, the connection region 222, and the connection region 223 can be formed together. In addition, both or either of the connection region 222 and the connection region 223 may be p-type semiconductor regions having an impurity concentration different from that of the base region 221, or may be insulating regions made of insulating materials such as silicon oxide or silicon nitride.

[0061] In the present embodiment, the widths of the connection region 222 and the connection region 223 in the X-axis direction are equal to each other, but the widths of the connection region 222 and the connection region 223 in the X-axis direction may be different from each other.

[0062] A carrier conducting portion 41 is disposed in each base region 221. Figure 1 and Figure 2 As shown in FIG. 4 , the carrier conducting portion 41 extends along the X-axis direction. Figure 3 As shown in the figure, the carrier conducting portion 41 is provided at a position equidistant from the gate electrodes 13 adjacent in the Y-axis direction, and is located at the center of the base region 221 in the Z-axis direction. In addition, as long as the position of the carrier conducting portion 41 in the Y-axis direction is within a range that does not contact the gate insulating film 31, it may be biased toward one of the adjacent gate electrodes 13. In addition, as long as the position of the carrier conducting portion 41 in the Z-axis direction is within a range that does not contact the drift region 21, it may not be located at the center of the base region 221. For example, the upper end of the carrier conducting portion 41 may be at substantially the same height as the upper end of the base region 221.

[0063] The carriers accumulated in the base region 221 are conducted inside the carrier conducting portion 41. In the present embodiment, the carrier conducting portion 41 is a p-type region having a higher impurity concentration than the base region 221. + The p-type impurity concentration of the carrier conducting portion 41 is, for example, 5×10 18 cm -3 Above and 1×10 22 cm -3 As described above, since the carrier conducting portion 41 has a higher p-type impurity concentration than the base region 221 , carriers can move more easily in the carrier conducting portion 41 than in the base region 221 .

[0064] In addition, the carrier conducting portion 41 is electrically connected to the source electrode 11 via a connection portion that does not penetrate the source region 23 (is not sandwiched by the source region 23). Minority carriers injected from the base region 221 into the carrier conducting portion 41 are conducted toward the source electrode 11 through the connection portion. Figure 2 As shown in FIG. 1 , in this embodiment, the connection portion 42 is respectively provided in the connection region 222 and the connection region 223 to electrically connect the carrier conducting portion 41 to the source electrode 11. More specifically, the connection portion 42 in the connection region 222 connects one end ( Figure 2 The connection portion 42 in the connection region 223 connects the other end ( Figure 2 The connection portion 42 is electrically connected to the source electrode 11 (right end in the middle). None of the connection portions 42 penetrates the source region 23. Thus, carriers that move in the carrier conduction portion 41 and reach both ends of the carrier conduction portion 41 are discharged toward the source electrode 11 through the connection portion 42. The connection portion 42 includes metal or polysilicon doped with impurities. In addition, the connection portion 42 may also be composed of a semiconductor region of the second conductivity type. The connection portion 42 in the connection region 222 is an example of a connection portion in the claims. The connection portion 42 in the connection region 223 is an example of a second connection portion in the claims.

[0065] In addition, one of the connection region 222 and the connection region 223 may be omitted. In this case, the carrier conducting portion 41 and the source electrode 11 are electrically connected via the connection portion 42 provided in the other remaining connection region.

[0066] like Figure 2 As shown, the connection portion 42 in the connection region 222 is located at the center of the connection region 222 in the X-axis direction. That is, the width W1 of the connection region 222 between the connection portion 42 and the source region 23 is substantially equal to the width W2 of the connection region 222 between the connection portion 42 and the drift region 21. In addition, the connection portion 42 in the connection region 223 is located at the center of the connection region 223 in the X-axis direction. That is, the width W3 of the connection region 223 between the connection portion 42 and the source region 23 is substantially equal to the width W4 of the connection region 223 between the connection portion 42 and the drift region 21. In addition, in order to ensure a margin for positional deviation of the connection portion 42 in the X-axis direction, the width W1 may be larger than the width W2, or the width W3 may be larger than the width W4, and conversely, the width W2 may be larger than the width W1, or the width W4 may be larger than the width W3.

[0067] like Figure 2As shown in FIG. 1 , a source region 23 is provided between the base region 221 and the source electrode 11. The source region 23 is a semiconductor region that functions as a source region of the MOSFET. The source region 23 is, for example, n + The n-type impurity concentration of the source region 23 is, for example, 1×10 18 cm -3 Above and 1×10 22 cm -3 The source region 23 is an example of a third semiconductor region in the claims.

[0068] like Figure 1 As shown, a gate pad 50 and a gate wiring 51 connected to the gate pad 50 are provided on the upper surface 2 a of the semiconductor layer 2 . The plurality of gate electrodes 13 are electrically connected to the gate pad 50 via the gate wiring 51 .

[0069] The planar shape of the semiconductor device 1, that is, the arrangement of the components on the upper surface 2a of the semiconductor layer 2 is not limited to Figure 1 The examples shown are arbitrary.

[0070] <Method for Manufacturing Semiconductor Device>

[0071] Next, refer to Figure 4A to Figure 4D , an example of a method for manufacturing the semiconductor device 1 according to the present embodiment will be described. Figure 4A to Figure 4D is a cross-sectional view for explaining a method for manufacturing a semiconductor device 1, and is a cross-sectional view taken along Figure 1 A portion of the cross section of line II-II corresponds to FIG.

[0072] First, if Figure 4A As shown, a semiconductor layer including a drift region 21 , a gate insulating film 31 extending from the upper surface 2 a to the drift region 21 , a plurality of gate electrodes 13 provided in each gate insulating film 31 , and a plurality of base regions 221 sandwiched by the gate insulating films 31 is prepared.

[0073] The semiconductor layer is obtained, for example, as follows. First, a semiconductor layer having a drift region 21 is prepared. Then, a gate trench is formed from the upper surface 2a of the semiconductor layer by reactive ion etching (RIE) or the like. Then, an insulating material is deposited in the gate trench by chemical vapor deposition (CVD) or the like to form a gate insulating film 31. Then, a portion of the gate insulating film 31 is removed by RIE or the like.

[0074] Thereafter, a conductive material such as polysilicon is deposited by CVD or the like, and the remaining conductive material is etched back to form the gate electrode 13. Thereafter, an insulating material is deposited by CVD or the like to bury the gate electrode 13.

[0075] Thereafter, the base region 221, the connection region 222, and the connection region 223 are formed by ion implantation of p-type impurities into the upper surface 2a of the semiconductor layer. Specifically, the base region 221 is formed by ion implantation of p-type impurities into the surface sandwiched by the gate insulating film 31 in the upper surface 2a of the semiconductor layer. The connection region 222 and the connection region 223 are formed by ion implantation of p-type impurities around both ends in the X-axis direction of the gate insulating film 31 in the upper surface 2a of the semiconductor layer. The connection region 222 and the connection region 223 may also be formed in the same ion implantation process as the base region 221.

[0076] Through the above process, Figure 4A The semiconductor layer shown.

[0077] Then, if Figure 4B As shown, the carrier conducting portion 41 is formed by ion implanting p-type impurities into the base region 221 .

[0078] Then, if Figure 4C As shown, n-type impurities are ion-implanted into carrier conducting portion 41 from upper surface 2a, thereby reducing the p-type impurity concentration in the upper portion of carrier conducting portion 41. Figure 4C In the example shown, the p-type impurity concentration in the upper portion of carrier conducting portion 41 is reduced to the same level as base region 221. The ion implantation in this step may be performed using the resist or the like used to form carrier conducting portion 41 as it is.

[0079] Then, if Figure 4D As shown, n-type impurities are ion-implanted into the base region 221 from the upper surface 2 a , thereby forming the source region 23 .

[0080] Next, although not shown, a groove from the upper surface 2a to the carrier conducting portion 41 is formed in the connection region 222 and the connection region 223 by RIE or the like. Thereafter, a conductive material is deposited by CVD or physical vapor deposition (PVD) or the like to fill the groove, thereby forming the connection portion 42. The conductive material is, for example, a metal material including copper, titanium, tungsten, aluminum, or polycrystalline silicon. In the case of polycrystalline silicon, p-type or n-type impurities may also be included.

[0081] Next, an interlayer insulating film 32 for insulating the source electrode 11 from the drift region 21 is formed on a portion of the upper surface 2a of the semiconductor layer 2. Thereafter, the source electrode 11 is formed so as to bury the interlayer insulating film 32 and contact the source region 23.

[0082] Next, n-type impurities are ion-implanted into the lower surface 2 b of the semiconductor layer 2 to form the drain region 24 . Thereafter, the drain electrode 12 is formed so as to cover the lower surface 2 b of the semiconductor layer 2 .

[0083] Through the above-mentioned steps, the semiconductor device 1 is manufactured.

[0084] As described above, the semiconductor device 1 of the present embodiment includes the carrier conducting portion 41, which is provided in a manner extending in the X-axis direction in the base region 221 and is electrically connected to the source electrode 11 via the connecting portion 42 that does not penetrate the source region 23. Thus, the area of ​​the source region 23 in the upper surface 2a of the semiconductor layer 2 can be maintained, and the minority carriers remaining in the base region 221 can be quickly discharged to the source electrode 11 through the carrier conducting portion 41 and the connecting portion 42.

[0085] Therefore, according to the present embodiment, it is possible to improve avalanche resistance while suppressing an increase in on-resistance of the semiconductor device 1 .

[0086] In addition, in the case where a contact is provided from the upper surface 2a of the semiconductor layer 2 to the base region 221 instead of providing the carrier conduction portion 41 in the base region 221, in order to fully discharge the minority carriers remaining in the base region 221, it is necessary to extend the contact in the X-axis direction. However, when such a contact is formed, a positional offset in the Y-axis direction occurs, and the position of the contact may be offset from the center of the source region 23 in the Y-axis direction. In this case, the area of ​​the upper surface 2a of the semiconductor layer 2 becomes smaller with respect to a part of the source region 23, thereby increasing the resistance, and thus the on-resistance of the semiconductor device may increase. In addition, in the case where the contact is composed of a p-type semiconductor region, the base region 221 between the contact and the gate insulating film 31 becomes narrower, making it difficult to form a channel. As a result, the threshold voltage of the MOSFET may be affected.

[0087] On the other hand, in the semiconductor device 1 of the present embodiment, the carrier conducting portion 41 is embedded in the base region 221 and is formed independently (without interfering) with the source region 23. Thus, the influence of the positional deviation of the carrier conducting portion 41 in the Y-axis direction on the source region 23 can be suppressed. For example, even when the position of the carrier conducting portion 41 is deviated in the Y-axis direction, the generation of a conduction path with a large resistance in the source region 23 can be suppressed, and the increase in the on-resistance of the semiconductor device 1 can be suppressed. In addition, the influence on the threshold voltage can also be suppressed.

[0088] (Second Embodiment)

[0089] Reference Figure 5 and Figure 6, a semiconductor device 1A according to a second embodiment will be described. Figure 5 is a cross-sectional view of a semiconductor device 1A according to a second embodiment, showing a semiconductor device 1A along the Figure 1 FIG. 1 is a diagram of a portion of a cross section of line II. Figure 6 is another cross-sectional view of the semiconductor device 1A according to the second embodiment, showing the semiconductor device 1A along the Figure 1 FIG. 1 is a diagram of a portion of a cross section taken along line II-II.

[0090] One of the differences between the second embodiment and the first embodiment is the constituent material of the carrier conducting portion. Hereinafter, the semiconductor device 1A of the present embodiment will be described mainly focusing on the differences from the first embodiment.

[0091] like Figure 5 and Figure 6 As shown, the semiconductor device 1A of this embodiment includes a carrier conducting portion 43 instead of the carrier conducting portion 41 of the first embodiment. The carrier conducting portion 43 is a conductor including metal or polysilicon doped with impurities. Therefore, similarly to the first embodiment, carriers are more likely to move in the carrier conducting portion 43 than in the base region 221.

[0092] In addition, as long as the position of the carrier conducting portion 43 in the Z-axis direction is within a range that does not contact the drift region 21, it may also be Figure 6 For example, the upper end of the carrier conducting portion 43 may be at substantially the same height as the upper end of the base region 221 .

[0093] <Manufacturing method of the second embodiment>

[0094] Next, refer to Figure 4A and Figure 7A to Figure 7E , an example of a method for manufacturing the semiconductor device 1A according to the present embodiment is described. Figure 7A to Figure 7E is a cross-sectional view for explaining a method for manufacturing a semiconductor device 1A, and is a cross-sectional view taken along Figure 1 A portion of the cross section of line II-II corresponds to FIG.

[0095] First, similarly to the first embodiment, prepare Figure 4A The semiconductor layer shown.

[0096] Then, if Fig. 7A As shown, the base region 221 is partially removed by RIE or the like to form the trench T1. In this embodiment, trenches (not shown) are also formed in the connection region 222 and the connection region 223 at the same time as the trench T1 is formed.

[0097] Then, if Figure 7BAs shown, a conductive material is deposited by CVD or PVD to fill the trench T1, thereby forming a carrier conducting portion 43. In this embodiment, while forming the carrier conducting portion 43, a conductive material is also deposited in the trenches formed in the connection region 222 and the connection region 223, thereby forming the connection portion 42. The conductive material is, for example, a metal material including copper, titanium, tungsten, aluminum, or polysilicon.

[0098] Then, if Figure 7C As shown, a portion of the deposited carrier conducting portion 43 is removed by wet etching or the like, thereby forming a trench T2 on the carrier conducting portion 43. In addition, in the connection region 222 and the connection region 223, the connection portion 42 is not removed.

[0099] Then, if Fig.7D As shown, by growing a p-type epitaxial layer, the carrier conducting portion 43 is buried in the base region 221. In addition, the p-type epitaxial layer is also formed on the base region 221 in the upper surface 2a of the semiconductor layer, but this portion is removed by RIE or CMP (Chemical Mechanical Polishing).

[0100] Then, if Fig. 7E As shown, n-type impurities are ion-implanted into the upper portion of the base region 221 , thereby forming the source region 23 .

[0101] Next, the interlayer insulating film 32 , the drain region 24 , and the drain electrode 12 are formed in the same manner as in the first embodiment.

[0102] Through the above-described steps, the semiconductor device 1A is manufactured.

[0103] As described above, according to the semiconductor device 1A of the second embodiment, similarly to the first embodiment, it is possible to improve avalanche resistance while suppressing an increase in the on-resistance of the semiconductor device 1A.

[0104] In addition, in the present embodiment, since the carrier conducting portion 43 is a conductor, even if the carrier conducting portion 43 is offset in the Y-axis direction, it is not easy to hinder the formation of a channel in the base region 221. Therefore, the carrier conducting portion 43 of the present embodiment is allowed to be offset in the Y-axis direction compared with the carrier conducting portion 41 of the first embodiment. As a result, for example, the semiconductor device 1A can be manufactured more easily.

[0105] Furthermore, in the present embodiment, the carrier conducting portion 43 and the connecting portion 42 can be formed simultaneously, so that the manufacturing process can be simplified.

[0106] in addition, Fig.7DThe regrowth of the epitaxial layer described in the above can also be applied to the manufacturing method of the first embodiment. Figure 4B After the carrier conducting portion 41 is formed in the substrate, the upper portion of the carrier conducting portion 41 is removed by RIE or the like to form a trench. Then, the epitaxial layer is regrown to form a p-type semiconductor region similar to the base region 221 in the trench. By such a process, a similar p-type semiconductor region can be obtained. Figure 4C Same structure.

[0107] (Third Embodiment)

[0108] Reference Figure 8 and Fig. 9 , a semiconductor device 1B according to a third embodiment will be described. Figure 8 It is a plan view of a semiconductor device 1B according to the third embodiment. Fig. 9 is a cross-sectional view of a semiconductor device 1B according to the third embodiment, taken along Figure 8 Cross-sectional view along line III-III.

[0109] One of the differences between the third embodiment and the first embodiment is the number of connection portions. Hereinafter, the semiconductor device 1B of the present embodiment will be described mainly focusing on the differences from the first embodiment.

[0110] like Figure 8 and Fig. 9 As shown, the semiconductor device 1B of this embodiment further includes two connection regions 224 located between the connection region 222 and the connection region 223 in the X-axis direction and sandwiched by the source region 23. The connection region 224 extends from the base region 221 to the source electrode 11 along the Z-axis direction, and connects the base region 221 to the source electrode 11. The connection region 224 is an example of a third connection region in the claims. In addition, the number of the connection regions 224 located between the connection region 222 and the connection region 223 in the X-axis direction is not limited to two, and is arbitrary.

[0111] In this embodiment, the connection region 224 is a p-type semiconductor region having an impurity concentration equal to that of the base region 221, the connection region 222, and the connection region 223. Thus, the base region 221, the connection region 222, the connection region 223, and the connection region 224 can be formed together. In addition, the connection region 224 may be a p-type semiconductor region having an impurity concentration different from that of the base region 221, the connection region 222, and the connection region 223, or may be an insulating region made of an insulating material such as silicon oxide or silicon nitride.

[0112] A connection portion 44 is provided in the connection region 224 to electrically connect the carrier conducting portion 41 to the source electrode 11. The connection portion 44 includes metal or polysilicon doped with impurities. Alternatively, the connection portion 44 may be formed of a semiconductor region of the second conductivity type. The connection portion 44 is an example of a third connection portion in the claims.

[0113] Thus, according to the semiconductor device 1B of the present embodiment, at least one connection region 224 is further provided, which is located between the connection region 222 and the connection region 223 and is sandwiched by the source region 23, and the connection portion 44 is provided in the connection region 224. Thus, the carriers remaining in the base region 221 are discharged more quickly. As a result, although the on-resistance of the semiconductor device 1 is increased by the connection region 224, the avalanche withstand capability of the semiconductor device 1B can be further improved.

[0114] In the semiconductor device 1B of the present embodiment, similarly to the second embodiment, a carrier conducting portion 43 of a conductor may be provided in place of the carrier conducting portion 41 which is a semiconductor region.

[0115] In addition, the structure for electrically connecting the carrier conducting portions 41 and 43 to the source electrode 11 in the above-mentioned embodiments is not limited to Figure 2 , Figure 5 as well as Fig. 9 The examples shown are arbitrary. For example, the connection region 222 and the connection region 223 may not be provided at the two ends of the base region 221, but may be provided further inside. In addition, as another example, one or more connection regions extending from any portion of the base region 221 in the X-axis direction to the source electrode 11 may be provided, and the carrier conduction portion 41 may be electrically connected to the source electrode 11 via one or more connection portions respectively provided in the connection region. As another example, a connection region extending from the base region 221 to the side surface of the semiconductor layer 2 may be provided, and the carrier conduction portions 41 and 43 may be electrically connected to the source electrode 11 via the connection portions provided in the connection region and other wiring.

[0116] The embodiments of the present invention have been described, but the embodiments and examples are presented as examples and are not intended to limit the scope of the invention. The embodiments and examples can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the main purpose of the invention. These embodiments and examples and their variations are included in the scope and main purpose of the invention, and are also included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device comprising: A semiconductor layer having a first main surface and a second main surface; A first electrode, disposed on the first main surface; A second electrode is disposed on the second main surface; A first semiconductor region of a first conductivity type, disposed in the semiconductor layer and located above the second electrode; a plurality of insulating regions provided in the semiconductor layer, extending from the first main surface to the first semiconductor region and in a second direction orthogonal to the first direction from the second electrode toward the first electrode; a plurality of third electrodes, disposed in the plurality of insulating regions and extending in the second direction; A second semiconductor region of the second conductivity type, sandwiched by the plurality of insulating regions in the semiconductor layer, disposed above the first semiconductor region and extending in the second direction; A third semiconductor region of the first conductivity type, disposed in the semiconductor layer and located between the second semiconductor region and the first electrode; as well as The carrier conducting portion is provided in the second semiconductor region so as to extend in the second direction, and is electrically connected to the first electrode via a connecting portion that does not penetrate the third semiconductor region.

2. The semiconductor device according to claim 1, The carrier conducting portion includes a second conductivity type semiconductor having a higher impurity concentration than that of the second semiconductor region.

3. The semiconductor device according to claim 1, The carrier conducting portion includes metal or polysilicon.

4. The semiconductor device according to claim 1, The carrier conducting portion is disposed at a position equidistant from the adjacent third electrodes.

5. The semiconductor device according to any one of claims 1 to 4, The connection portion is connected to one end of the carrier conducting portion and is provided in a first connection region which is a semiconductor region of the second conductivity type. The first connection region is provided in the semiconductor layer, and extends from one end of the second semiconductor region in the second direction to the first electrode along the first direction.

6. The semiconductor device according to claim 5, further comprising a second connection portion that does not penetrate the third semiconductor region but electrically connects the other end of the carrier conducting portion to the first electrode, the second connection portion being provided in a second connection region that is a semiconductor region of the second conductivity type, The second connection region is provided in the semiconductor layer, and extends from the other end of the second semiconductor region in the second direction along the first direction to the first electrode.

7. The semiconductor device according to claim 6, The first connection region and the second connection region include a second conductivity type semiconductor having an impurity concentration equal to that of the second semiconductor region.

8. The semiconductor device according to claim 6, further comprising: A third connection region is provided in the semiconductor layer, is located between the first connection region and the second connection region, and is sandwiched by the third semiconductor region; and The third connection portion is disposed in the third connection region and electrically connects the carrier conduction portion and the first electrode.

9. The semiconductor device according to claim 1, The connection portion includes metal or polysilicon.

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