Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. The semiconductor device includes a first dummy epitaxial layer and a second dummy epitaxial layer disposed in a first substrate structure and a second substrate structure; the first active epitaxial layer and the second active epitaxial layer are arranged on the first pseudo epitaxial layer and the second pseudo epitaxial layer; a first active nanostructure layer disposed adjacent to and in contact with the first active epitaxial layer; a second active nanostructure layer disposed adjacent to and in contact with the second active epitaxial layer; a dummy nanostructure layer disposed adjacent to and in contact with the second dummy epitaxial layer; a first gate structure surrounding the first active nanostructure layer; and a second gate structure surrounding the second active nanostructure layer and the dummy nanostructure layer.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] As advances in semiconductor technology continue, there is an ever-increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and gate-all-around field effect transistors (GAA FETs). Such shrinking increases the complexity of semiconductor manufacturing processes. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device, including: a first substrate structure and a second substrate structure; a first dummy layer and a second dummy layer, respectively arranged in the first substrate structure and the second substrate structure, wherein the height of the second dummy layer is greater than the height of the first dummy layer; a first active epitaxial layer and a second active epitaxial layer, respectively arranged on the first dummy layer and the second dummy layer, wherein the height of the first active epitaxial layer is greater than the height of the second active epitaxial layer; a first active nanostructure layer, arranged to be adjacent to the first active epitaxial layer and in contact with the first active epitaxial layer; a second active nanostructure layer, arranged to be adjacent to the second active epitaxial layer and in contact with the second active epitaxial layer; a dummy nanostructure layer, arranged to be adjacent to the second dummy layer and in contact with the second dummy layer; a first gate structure, surrounding the first active nanostructure layer; and a second gate structure, surrounding the second active nanostructure layer and the dummy nanostructure layer.

[0004] Other embodiments of the present application provide a semiconductor device, including: a substrate structure; a pseudo-nanostructure layer, arranged on the substrate structure; an active nanostructure layer, arranged on the pseudo-nanostructure layer; a first source / drain (S / D) region, arranged to be adjacent to a first end of the active nanostructure layer; a second source / drain region, arranged to be adjacent to a second end of the active nanostructure layer; an isolation layer, arranged on a back side of the first source / drain region; a first contact structure, arranged on a front side of the first source / drain region; a second contact structure, arranged on a back side of the second source / drain region; and a gate structure, surrounding the active nanostructure layer and the pseudo-nanostructure layer.

[0005] Some other embodiments of the present application provide a method, comprising: forming a superlattice structure on a substrate, comprising a first nanostructure layer, a nanostructure sacrificial layer on the first nanostructure layer, and a second nanostructure layer on the nanostructure sacrificial layer; forming a polysilicon layer on the superlattice structure; forming a first opening and a second opening in the superlattice structure; epitaxially growing a first semiconductor layer and a second semiconductor layer in the first opening and the second opening, respectively, wherein the first semiconductor layer and the second semiconductor layer are in contact with the sidewalls of the first nanostructure layer; epitaxially growing a third semiconductor layer and a fourth semiconductor layer on the first semiconductor layer and the second semiconductor layer, respectively, wherein the third semiconductor layer and the fourth semiconductor layer are in contact with the second nanostructure layer and the nanostructure sacrificial layer; replacing the polysilicon layer and the nanostructure sacrificial layer with a gate structure; and replacing the first semiconductor layer with a contact structure on the back side of the third semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the disclosed embodiments are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1 An isometric view of a semiconductor device in accordance with some embodiments is shown.

[0008] FIG. 2A to FIG. 6A and Figures 2B to 6B Different cross-sectional views of a semiconductor device with transistors having different drive current characteristics according to some embodiments are shown.

[0009] Figure 7 is a flow chart of a method for manufacturing a semiconductor device having transistors with different driving current characteristics according to some embodiments.

[0010] FIG. 8A to FIG. 28A and FIG. 8B to FIG. 28B Cross-sectional views of a semiconductor device having transistors with different drive current characteristics at various stages of its manufacturing process are shown according to some embodiments.

[0011] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, embodiments for forming a first component above a second component may include embodiments in which the first component and the second component are directly in contact with each other, and may also include embodiments in which additional components may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. As used herein, forming a first component on a second component means that the first component is formed in direct contact with the second component. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0013] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "an exemplary embodiment," etc. indicate that the described embodiment may include a particular component, structure, or characteristic, but each embodiment may not necessarily include the particular component, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular component, structure, or characteristic is described in conjunction with an embodiment, it will be within the knowledge of those skilled in the art to implement such component, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0015] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology of this specification will be interpreted by those skilled in the relevant art based on the teachings herein.

[0016] In some embodiments, the terms "about" and "substantially" may indicate a value of a given amount that varies within 5-20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by a person skilled in the relevant art based on the teachings herein.

[0017] The GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. The double patterning or multiple patterning process can combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0018] The GAA FET may include a base structure (also referred to as a "sheet base" and a "fin base") disposed on a substrate, a source / drain (S / D) region disposed on the substrate, a nanostructure layer disposed on the base structure and between the S / D regions, and a gate structure surrounding each of the nanostructure layers. The nanostructure layer between the S / D regions serves as a channel region of the GAA FET, and a driving current characteristic (e.g., a driving current value) of the GAA FET may depend on the number of nanostructure layers between the S / D regions.

[0019] The disclosed embodiments provide exemplary structures of GAAFETs with different drive current characteristics on the same substrate of a semiconductor device, and also provide exemplary methods for manufacturing these GAAFETs. In some embodiments, the first GAAFET may have a first nanostructure layer between the first S / D region pair, and the second GAAFET may have a second nanostructure layer between the second S / D region pair. The number of the first nanostructure layer may be greater than the number of the second nanostructure layer to achieve a higher drive current in the first GAAFET than in the second GAAFET. The semiconductor device may have GAAFETs with different drive current values ​​to optimize the overall power consumption of the semiconductor device. In some embodiments, the number of the first nanostructure layer and the second nanostructure layer in contact with the first S / D region pair and the second S / D region pair can be controlled by using a first electrically non-active ("pseudo") epitaxial layer and a second electrically non-active ("pseudo") epitaxial layer disposed under the first S / D region pair and the second S / D region pair. In some embodiments, the first pseudo epitaxial layer and the second pseudo epitaxial layer may also be used to form a self-aligned backside contact structure on the backside surface of the first S / D region pair and the second S / D region pair. In some embodiments, the first dummy epitaxial layer and the second dummy epitaxial layer may be replaced with a backside isolation layer to reduce current leakage from the first S / D region pair and the second S / D region pair to the substrate.

[0020] Figure 1An isometric view of a semiconductor device 100 having GAA FETs 102A and 102B according to some embodiments is shown. In some embodiments, the GAA FETs 102A and 102B may both be p-type GAA FETs or n-type GAA FETs, or may be one of each conductivity type GAA FET. FIG. 2A to FIG. 6A The GAA FET 102A is shown along the Figure 1 Different cross-sectional views of line AA. Figures 2B to 6B GAA FET 102B is shown along the Figure 1 Different cross-sectional views of line BB. FIG. 2A to FIG. 6A and Figures 2B to 6B For simplicity, the Figure 1 Cross-sectional view of additional structures not shown. Figure 1 , FIG. 2A to FIG. 6A and Figures 2B to 6B Discussions of elements having the same annotation apply to each other unless otherwise stated.

[0021] The semiconductor device 100 may be formed on a substrate 104, wherein the GAA FETs 102A and 102B are formed on different regions of the substrate 104. There may be other GAA FETs and / or structures (e.g., isolation structures) between the GAA FETs 102A and 102B formed on the substrate 104. In some embodiments, the substrate 104 may be a semiconductor material such as silicon (Si), Ge, silicon germanium (SiGe), a silicon on insulator (SOI) structure, and combinations thereof. In addition, the substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic). The semiconductor device 100 may also include a shallow trench isolation (STI) region 105 disposed on the substrate 104. In some embodiments, the STI region 105 may include an insulating material such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon germanium oxide (SiGeO2). x ).

[0022] refer to Figure 1 and Figure 2AIn some embodiments, the GAA FET 102A may include: (i) a fin-shaped base structure 106A (also referred to as a "sheet base 106A" or a "fin base 106A") disposed on the substrate 104; (ii) an active nanostructure layer 208A disposed on the base structure 106A; (iii) an S / D region 110A disposed adjacent to the active nanostructure layer 208A; (iv) a gate structure 112A surrounding the active nanostructure layer 208A; (v) an external gate spacer 114A; (vi) an internal gate spacer 216A; (vii) a backside (BS) etch stop layer (ESL) 118A (also referred to as a "cap layer 118A" or a "seed layer 118A"); (viii) a pseudo-epitaxial layer 120A; (ix) a frontside (FS) ESL 122A; (x) an interlayer dielectric (ILD) layer 124A; and (xi) a FS contact structure 226A.

[0023] Similarly, refer to Figure 1 and Figure 2B In some embodiments, the GAA FET 102B may include: (i) a fin-shaped base structure 106B (also referred to as a "sheet base 106B" or a "fin base 106B") disposed on the substrate 104; (ii) a pseudo-nanostructure layer 208C disposed on the base structure 106B; (iii) an active nanostructure layer 208B disposed on the pseudo-nanostructure layer 208C; (iv) an S / D region 110B disposed adjacent to the active nanostructure layer 208B; (v) a gate structure 112B surrounding the active nanostructure layer 208B and the pseudo-nanostructure layer 208C; (vi) an external gate spacer 114B; (vii) an internal gate spacer 216B; (viii) a BS ESL 118B (also referred to as a "capping layer 118B" or a "seed layer 118B"); (ix) a pseudo-epitaxial layer 120B; (x) a FSESL 122B; (xi) ILD layer 124B; and (xii) FS contact structure 226B. In some embodiments, base structures 106A and 106B may include a material similar to substrate 104. Base structures 106A and 106B may have elongated sides extending along the X-axis.

[0024] refer to Figure 2A and Figure 2BIn some embodiments, the active nanostructure layers 208A and 208B and the pseudo nanostructure layer 208C may be in the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanostructure shapes. As used herein, the term "nanostructure" defines a structure, layer, and / or region as having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) of less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm. In some embodiments, the active nanostructure layers 208A and 208B and the pseudo nanostructure layer 208C may include a semiconductor material similar to or different from the substrate 104. In some embodiments, the active nanostructure layers 208A and 208B and the dummy nanostructure layer 208C may include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), III-V semiconductor compounds, or other suitable semiconductor materials.

[0025] In some embodiments, each of the active nanostructure layers 208A and 208B and the dummy nanostructure layer 208C may have a thickness of about 3 nm to about 15 nm along the Z-axis. Although rectangular cross-sections of the active nanostructure layers 208A and 208B and the dummy nanostructure layer 208C are shown, the active nanostructure layers 208A and 208B and the dummy nanostructure layer 208C may have cross-sections of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal).

[0026] In some embodiments, the active nanostructure layers 208A and 208B and the dummy nanostructure layer 208C may be similar to each other in structure and composition, but may be different from each other in function. Since the active nanostructure layer 208A is disposed between and in contact with the S / D regions 110A, the active nanostructure layer 208A may be electrically active and may be used as a channel region of the GAA FET 102A. Similarly, since the active nanostructure layer 208B is disposed between and in contact with the S / D regions 110B, the active nanostructure layer 208B may be electrically active and may be used as a channel region of the GAA FET 102B. On the other hand, since the dummy nanostructure layer 208C is not in contact with the S / D regions 110B, the dummy nanostructure layer 208C may be electrically inactive and not used as a channel region of the GAA FET 102B. Therefore, even though the GAA FETs 102A and 102B have an equal number of nanostructure layers between adjacent S / D regions, the GAA FET 102A may have a greater number of active nanostructure layers (also referred to as “nanostructure channel regions”) than the GAA FET 102B. Since the number of active nanostructure layers 208A between adjacent S / D regions 110A is greater than the number of active nanostructure layers 208B between adjacent S / D regions 110B, the GAA FET 102A may have a higher drive current than the GAA FET 102B. Although three active nanostructure layers 208A are shown between adjacent S / D regions 110A, and two active nanostructure layers 208B are shown between adjacent S / D regions 110B, the GAA FETs 102A and 102B may have any number of active nanostructure layers 208A and 208B, except that (i) the number of active nanostructure layers 208A between adjacent S / D regions 110A is greater than the number of active nanostructure layers 208B between adjacent S / D regions 110B; and (ii) the total number of active nanostructure layers 208A between adjacent S / D regions 110A is equal to the sum of the active nanostructure layers 208B and the dummy nanostructure layers 208C between adjacent S / D regions 110B.

[0027] refer to Figure 1 , Figure 2A and Figure 2B In some embodiments, the S / D regions 110A and 110B (also referred to as “active epitaxial layers 110A and 110B”) may include epitaxially grown semiconductor materials such as Si and n-type dopants such as phosphorus, arsenic, and other suitable n-type dopants for n-type GAA FETs 102A and / or 102B. In some embodiments, the n-type dopant may have a relative density of about 5×10 19 cm -3 About 5×1021 cm -3 The S / D regions 110A and 110B may include an epitaxially grown semiconductor material (such as Si and SiGe) and a p-type dopant (such as boron and other suitable p-type dopants for p-type GAA FETs 102A and / or 102B). In some embodiments, the p-type dopant may have a concentration of about 5×10 19 cm -3 About 5×10 21 cm -3 Each of the S / D regions 110A and 110B may be referred to as a source or a drain, individually or collectively depending on the context.

[0028] refer to Figure 2A and Figure 2B In some embodiments, each of the gate structures 112A and 112B may have an outer gate portion 113A and an inner gate portion 113B. In some embodiments, the outer gate portion 113A may be disposed on and in physical contact with the topmost active nanostructure layers 208A and 208B, respectively. In some embodiments, the inner gate portion 113B of the gate structure 112A may be disposed between adjacent active nanostructure layers 208A and between adjacent inner gate spacers 216A. Similarly, in some embodiments, the inner gate portion 113B of the gate structure 112B may be disposed between adjacent active nanostructure layers 208B and between adjacent inner gate spacers 216B.

[0029] Each of the gate structures 112A and 112B may be a multi-layer structure and may include: (i) an interface oxide (IL) layer (not shown); (ii) a high-k (HK) gate dielectric layer 228; and (iii) a conductive layer 230. In some embodiments, the IL layer may be disposed directly on the topmost active nanostructure layers 208A and 208B. In some embodiments, the IL layer may include SiO2, SiGeO x or germanium oxide (GeO x ), and may have a thickness of about 1 nm to about 20 nm. In some embodiments, the HK gate dielectric layer 228 may be disposed directly on the IL layer, and may include a high-k dielectric material such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). In some embodiments, the sidewalls of the IL layer and the HK gate dielectric layer 228 may contact the sidewalls of the external gate spacers 114A and 114B.

[0030] In some embodiments, the conductive layer 230 may be disposed on the HK gate dielectric layer 228 and may be a multi-layer structure. For simplicity, the different layers of the conductive layer 230 are not shown. In some embodiments, the conductive layer 230 may include a work function metal (WFM) layer disposed on the HK gate dielectric layer 230 and a gate metal filling layer disposed on the WFM layer. In some embodiments, the WFM layer may include a Ti-based or Ta-based nitride or alloy that is substantially free of Al (e.g., without Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu). In some embodiments, the WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials. In some embodiments, the gate metal fill layer may include a suitable conductive material, such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0031] refer to Figure 2A and Figure 2B , the external gate spacers 114A and 114B can electrically isolate the external gate portion 113A from the adjacent S / D regions 110A and 110B, and form adjacent FS contact structures 226A and 226B. In some embodiments, the external gate spacers 114A and 114B can be directly disposed on the topmost active nanostructure layers 208A and 208B, respectively. In some embodiments, the external gate spacers 114A and 114B can include dielectric materials such as SiO2, SiN, SiON, SiCN, SiOC, and SiOCN, as well as any other suitable dielectric materials. The internal gate spacers 216A and 216B can electrically isolate the internal gate portion 113B from the adjacent S / D regions 110A and 110B, and can include dielectric materials such as SiO2, SiN, SiON, SiCN, SiOC, and SiOCN, as well as any other suitable dielectric materials.

[0032] refer to Figure 1 , Figure 2A and Figure 2BIn some embodiments, BS ESLs 118A and 118B may be disposed below and in contact with the BS surfaces of S / D regions 110A and 110B, respectively. Sidewalls of BS ESL 118A may be in contact with bottommost internal gate spacer 216A and base structure 106A. Sidewalls of BS ESL 118B may be in contact with sidewalls of pseudo-nanostructure layer 208C and bottommost internal gate spacer 216B. In some embodiments, BS ESLs 118A and 118B may include the same semiconductor material (e.g., Si or SiGe) as S / D regions 110A and 110B, respectively, and may be used as seed layers for epitaxially growing S / D regions 110A and 110B. In some embodiments, the BS ESLs 118A and 118B may include a dielectric material such as SiN, SiON, SiCN, SiOC, and SiOCN instead of a semiconductor material, and may function as a barrier layer to prevent current leakage from the S / D regions 110A and 110B to the substrate 104. In some embodiments, the BS ESLs 118A and 118B may have thicknesses T1 and T2 of about 1 nm to about 10 nm to function sufficiently as a seed layer or a barrier layer.

[0033] In some embodiments, the pseudo epitaxial layers 120A and 120B may be electrically non-active and may include undoped SiGe or SiGe doped with boron atoms. In some embodiments, the doped or undoped SiGe may have a Ge concentration of about 10 atomic % to about 50 atomic %. In some embodiments, the pseudo epitaxial layers 120A and 120B may be disposed below the BS surface of the BSESL 118A and 118B, respectively, and in contact with the BS surface of the BS ESL 118A and 118B. The pseudo epitaxial layers 120A and 120B may be used to control the height of the S / D regions 110A and 110B. Controlling the height of the S / D regions 110A and 110B may control the number of nanostructure layers that contact the S / D regions 110A and 110B to form active nanostructure layers 208A and 208B. In the GAAFET 102B, the dummy epitaxial layer 120B together with the BS ESL 118B prevents the S / D region 110B from making contact with the bottommost nanostructure layer, which produces the dummy nanostructure layer 208C. In some embodiments, the dummy epitaxial layer 120A may have a height H1 less than the height H2 of the dummy epitaxial layer 120B to form the S / D region 110A having a height greater than the height of the S / D region 110B. Therefore, more nanostructure layers are in contact with the S / D region 110A than the S / D region 110B, thereby forming a greater number of active nanostructure layers 208A than active nanostructure layers 208B. In some embodiments, the heights H1 and H2 may be about 5 nm to about 70 nm. In some embodiments, for the n-type doped S / D regions 110A and / or 110B, the dummy epitaxial layers 120A and / or 120B may include undoped SiGe or doped SiGe.

[0034] In some embodiments, FS ESLs 122A and 122B (in Figure 1 can be seen in Figure 2A and Figure 2B The FS ESL 122A and 122B may have a dielectric constant of about 4 to about 7 in some embodiments, and may include dielectric materials such as lanthanum oxide (LaO), aluminum oxide (Al2O3), yttrium oxide (Y2O3), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), SiOCN, SiOC, SiCN, zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), TiO2, Ta2O3, ZrO2, HfO2, SiN, hafnium silicide (HfSi), aluminum oxynitride (AlON), SiO2, SiC, SiN, and zinc oxide (ZnO). In some embodiments, the ILD layers 124A and 124B (in Figure 1 can be seen in Figure 2A and Figure 2B The ILD layers 124A and 124B may be disposed directly on the FS ESLs 122A and 122B. In some embodiments, the ILD layers 124A and 124B may include insulating materials such as SiO2, SiN, SiON, SiCN, SiOC, and SiOCN.

[0035] In some embodiments, each of the FS contact structures 226A and 226B may include: (i) a silicide layer 232; (ii) a contact plug 234 disposed on the silicide layer 232; and (iii) a dielectric liner 236 surrounding the contact plug 234. In some embodiments, the silicide layer 232 in the n-type GAA FETs 102A and 102B may include titanium silicide (Ti x Si y ), Tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y ), zirconium silicide (Zr x Si y ), Hafnium Silicide (Hf x Si y ), scandium silicide (Sc x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb x Si y ), Lutetium silicide (Lu x Si y ), Erbium Silicide (Er x Si y ), Ytterbium silicide (Yb x Si y ), europium silicide (Eu x Si y ), Thorium Silicide (Th x Si y ), other suitable metal silicide materials, or combinations thereof. In some embodiments, the silicide layer 232 in the p-type GAA FETs 102A and 102B may include nickel silicide (Ni x Si y ), cobalt silicide (Co x Si y ), manganese silicide (Mn x Si y ), tungsten silicide (W x Si y ), iron silicide (Fe x Si y ), rhodium silicide (Rh x Si y), palladium silicide (Pd x Si y ), ruthenium silicide (Ru x Si y ), platinum silicide (Pt x Si y ), iridium silicide (Ir x Si y ), Os x Si y ), other suitable metal silicide materials, or combinations thereof. In some embodiments, the contact plug 234 may include a conductive material such as Co, W, Ru, Al, Mo, Ir, Ni, osmium (Os), rhodium (Rh), other suitable conductive materials, and combinations thereof. In some embodiments, the dielectric liner 236 may include a dielectric material such as SiN, SiON, SiCN, SiOC, and SiOCN.

[0036] refer to Figure 3A and Figure 3B In some embodiments, the GAA FETs 102A and 102B may have BS contact structures 338A and 338B disposed on the BS surface of one or more of the S / D regions 110A and 110B, rather than Figure 2A and Figure 2B The BSESL 118A and 118B and the pseudo epitaxial layers 120A and 120B of the embodiment of the present invention are shown in FIG. 3. The BS contact structures 338A and 338B can electrically connect the S / D regions 110A and 110B to a BS power rail (not shown) disposed on the BS contact structures 338A and 338B. The BS power rail can include a metal line (not shown) for providing a power supply to the S / D regions 110A and 110B through the BS contact structures 338A and 338B. In the case of using the BS power rail, the device area for placing interconnects between the S / D regions 110A and 110B and the power supply can be reduced, thereby reducing power consumption compared to other GAA FETs without a BS power rail.

[0037] In some embodiments, each of the BS contact structures 338A and 338B may include: (i) a silicide layer 340; (ii) a contact plug 342 disposed on the silicide layer 340; and (iii) a dielectric liner 344 surrounding the contact plug 342. In some embodiments, the silicide layer 340 may include Ti x Si y 、 x Si y 、Mo x Si y 、Zr x Si y , Hf xSi y Sc x Si y , Y x Si y , Tb x Si y 、Lu x Si y , Er x Si y , Yb x Si y 、Chromium silicide (Cr x Si y ), holmium silicide (Ho x Si y ), Gadolinium silicide (Gd x Si y ), dysprosium silicide (Dy x Si y ), other suitable metal silicide materials, or combinations thereof. In some embodiments, the silicide layer 340 may have a thickness of about 1 nm to about 10 nm to minimize the contact resistance between the S / D region 110A and the contact plug 342 of the BS contact structure 338A and between the S / D region 110B and the contact plug 342 of the BS contact structure 338B. In some embodiments, the contact plug 342 may include a conductive material such as Co, W, Ru, Mo, Ir, Cu, other suitable conductive materials, and combinations thereof.

[0038] In some embodiments, the contact plug 342 of the BS contact structure 338A may have a height H3 of about 5 nm to about 70 nm, and the contact plug 342 of the BS contact structure 338B may have a height H4 of about 5 nm to about 70 nm. In some embodiments, the height H3 is less than the height H4. Since the BS contact structures 338A and 338B are formed by replacing the pseudo epitaxial layers 120A and 120B (described in detail below), respectively, the relative relationship between the heights H1 and H2 of the pseudo epitaxial layers 120A and 120B is applicable to the relative relationship between the heights H3 and H4. In some embodiments, the contact plug 342 of the BS contact structure 338A may have a top surface width W1 of about 5 nm to about 50 nm and a bottom surface width W2 of about 5 nm to about 40 nm, and the width W2 may be equal to or less than the width W1. Similarly, contact plug 342 of BS contact structure 338B may have a top surface width W3 of about 5 nm to about 50 nm and a bottom surface width W4 of about 5 nm to about 40 nm, and width W4 may be equal to or less than width W3. In some embodiments, dielectric liner 344 may include a dielectric material such as SiN, SiON, SiCN, SiOC, and SiOCN, and may have a thickness of about 0.5 nm to about 5 nm.

[0039] refer to Figure 4A and Figure 4B In some embodiments, the GAA FETs 102A and 102B may have BS contact structures 438A and 438B instead of Figure 3A and Figure 3B BS contact structures 338A and 338B. The discussion of BS contact structures 338A and 338B applies to BS contact structures 438A and 438B unless otherwise stated. In some embodiments, each of BS contact structures 438A and 438B may include: (i) a silicide layer 340; (ii) a barrier layer 446 disposed on the silicide layer 340; (iii) a contact plug 342 disposed on the inner sidewall and bottom surface of the barrier layer 446; and (iv) a dielectric liner 344 disposed on the outer sidewall of the barrier layer 446. In some embodiments, the barrier layer 446 may prevent oxidation of the metal of the contact plug 342 and may include Ti, TiN, TaN, W, or Ru. In some embodiments, the barrier layer 446 may have a thickness of about 0.1 nm to about 2 nm to sufficiently prevent oxidation of the metal of the contact plug 342.

[0040] refer to Figure 5A In some embodiments, the GAA FET 102A may have a BS contact structure 338A and a BS isolation layer 548A disposed on the BS surface of the S / D region 110A, instead of Figure 2A BS ESL 118A and dummy epitaxial layer 120A. Similarly, reference Figure 5B , the GAA FET 102B may have a BS contact structure 338B and a BS isolation layer 548B disposed on the BS surface of the S / D region 110B, instead of Figure 2B BS ESL 118B and pseudo epitaxial layer 120B. In some embodiments, BS isolation layers 548A and 548B can electrically isolate S / D regions 110A and 110B from substrate structures 106A and 106B and / or other BS structures (e.g., BS power rails; not shown) disposed on the BS surface of substrate structures 106A and 106B. In addition, BS isolation layer 548B and dielectric liner 344 of BS contact structure 338B can prevent S / D region 110B from contacting pseudo nanostructure layer 208C.

[0041] In some embodiments, the BS isolation layers 548A and 548B may include a dielectric material such as LaO, Al2O3, Y2O3, TaCN, SiOCN, SiOC, SiCN, TiO2, Ta2O3, ZrO2, ZrAlO, HfO2, SiN, AlON, SiO2, SiN, and ZnO. In some embodiments, the BS isolation layers 548A and 548B may have heights H5 and H6 of about 5 nm to about 70 nm. In some embodiments, the height H5 is less than the height H6. Since the BS isolation layers 548A and 548B are formed by replacing the pseudo-epitaxial layers 120A and 120B (described in detail below), respectively, the relative relationship between the heights H1 and H2 of the pseudo-epitaxial layers 120A and 120B is applicable to the relative relationship between the heights H5 and H6. In some embodiments, the BS isolation layers 548A and 548B may have top widths W5 and W7 of about 5 nm to about 50 nm and bottom widths W6 and W8 of about 5 nm to about 50 nm, and the widths W6 and W8 may be equal to or less than the widths W5 and W7.

[0042] refer to Fig. 6A In some embodiments, the GAA FET 102A may have a BS contact structure 438A and a BS isolation layer 548A disposed on the BS surface of the S / D region 110A, instead of Figure 2A BS ESL 118A and dummy epitaxial layer 120A. Similarly, reference Figure 6B , the GAA FET 102B may have a BS contact structure 438B and a BS isolation layer 548B disposed on the BS surface of the S / D region 110B, instead of Figure 2B BS ESL 118B and dummy epitaxial layer 120B.

[0043] Figure 7 According to some embodiments, a method for manufacturing a FIG. 2A to FIG. 6A and Figures 2B to 6B 1 is a flow chart of an exemplary method 700 of a cross-sectional view of a semiconductor device 100. For illustration purposes, Figure 7 The operations shown in the reference will be used to make FIG. 8A to FIG. 28A and FIG. 8B to FIG. 28B 1 is described with reference to an exemplary manufacturing process of the semiconductor device 100 shown in FIG. FIG. 8A to FIG. 28A According to some embodiments, the semiconductor device 100 is Figure 1 A cross-sectional view of line AA, and FIG. 8B to FIG. 28B The semiconductor device 100 according to some embodiments is processed at various stages of the manufacturing of the semiconductor device 100. Figure 1BB. Depending on the specific application, the operations may be performed in a different order or not performed. It should be noted that method 700 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 700, and some other processes may only be briefly described herein. Figure 1 , FIG. 2A to FIG. 6A , Figures 2B to 6B , FIG. 8A to FIG. 28A and FIG. 8B to FIG. 28B Discussions of elements having the same annotation apply to each other unless otherwise stated.

[0044] refer to Figure 7 In operation 705, a first superlattice structure and a second superlattice structure having a nanostructure layer and a nanostructure sacrificial layer are formed on the base structure. Fig. 8A and Figure 8B As described, superlattice structures 807A and 807B (also referred to as "nanosheet stacks 807A and 807B") are formed on base structures 106A and 106B, respectively, and base structures 106A and 106B are formed on substrate 104. Each of superlattice structures 807A and 807B may include nanostructure layers 208 and nanostructure sacrificial layers 808 arranged in an alternating configuration. In some embodiments, nanostructure layers 208 may include Si, and nanostructure sacrificial layers 808 may include SiGe.

[0045] refer to Figure 7 In operation 710, a polysilicon structure is formed on the first superlattice structure and the second superlattice structure. Fig. 8A and Figure 8B As described, polysilicon structures 812A and 812B are formed on superlattice structures 807A and 807B, respectively. In some embodiments, before forming polysilicon structures 812A and 812B, SiO2 layer 850 can be formed on superlattice structures 807A and 807B. During subsequent processing, polysilicon structures 812A and 812B, SiO2 layer 850, and nanostructure sacrificial layer 808 can be replaced with gate structures 112A and 112B in a gate replacement process. In some embodiments, forming polysilicon structures 812A and 812B can be followed by forming external gate spacers 114A and 114B, such as Fig. 8A and Figure 8B as shown in .

[0046] refer to Figure 7 In operation 715, a first S / D opening and a second S / D opening are formed in the first superlattice structure and the second superlattice structure. Fig. 9A and Fig. 9BAs described, a first S / D opening 910A is formed in the superlattice structure 807A, and a second S / D opening 910B is formed in the superlattice structure 807B. The S / D openings 910A and 910B can be formed by etching portions of the superlattice structures 807A and 807B that are not covered by the polysilicon structures 812A and 812B. In some embodiments, the etching of the superlattice structures 807A and 807B may include a plasma-based dry etching process using an etching gas (such as carbon tetrafluoride (CF4), sulfur dioxide (SO2), hexafluoroethane (C2F6), chlorine (Cl2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and hydrogen bromide (HBr)) with a mixed gas (such as hydrogen (H2), oxygen (O2), nitrogen (N2), and argon (Ar)). Etching can be performed at a temperature ranging from about 25°C to about 200°C and at a pressure ranging from about 5mTorr to about 50mTorr. The flow rate of the etching gas may be in a range from about 5 standard cubic centimeters per minute (sccm) to about 100 sccm. The plasma power may be in a range from about 50 W to about 200 W with a bias voltage from about 30 V to about 200 V. In some embodiments, the formation of the S / D openings 910A and 910B may be followed by the formation of the internal gate spacers 216A and 216B, such as Fig. 9A and Fig. 9B as shown in .

[0047] refer to Figure 7 In operation 720, a first dummy epitaxial layer, a first BS ESL, and a first S / D region are formed in the first S / D opening. FIG. 10A to FIG. 13A and FIG. 10B to FIG. 13B As described above, the dummy epitaxial layer 120A, the BS ESL 118A, and the S / D region 110A are formed in the S / D opening 910A. The formation of the dummy epitaxial layer 120A, the BS ESL 118A, and the S / D region 110A may include the following sequential operations: (i) Fig. 9A and Fig. 9B A hard mask layer 1052 (eg, a SiN layer) is deposited on the structure to form Fig. 10A and Fig. 10B (ii) removing (eg, by etching) the hard mask layer 1052 located at Fig. 10A The portion of the structure located on the hard mask layer 1052 is not removed. Fig. 10B The structural part to form Fig.11A and Fig. 11B (iii) epitaxially growing a semiconductor material (eg, doped or undoped SiGe) of a pseudo epitaxial layer 120A in the S / D opening 910A to a height of H1, such as Fig. 12AAs shown in FIG. 1 , the semiconductor material of the dummy epitaxial layer 120A is not grown in the S / D opening 910B, as shown in FIG. Fig. 12B (iv) epitaxially growing or depositing a BS ESL 118A having a thickness of T1 on the pseudo epitaxial layer 120A, as shown in FIG. Fig. 12A As shown in FIG. 1 , instead of growing BS ESL 118A in S / D opening 910B, as shown in FIG. Fig. 12B (v) epitaxially growing a semiconductor material (eg, doped Si or doped SiGe) of the S / D region 110A on the BS ESL 118A, as shown in FIG. Fig. 12A As shown in FIG. 1 , the semiconductor material of the S / D region 110A is not grown in the S / D opening 910B, as shown in FIG. Fig. 12B as shown in; and (vi) from Fig. 12B The hard mask layer 1052 is removed without etching the S / D region 110A to form Fig.13A and Fig. 13B structure. Fig. 12B The dielectric material of the hard mask layer 1052 on the structure prevents the pseudo epitaxial layer 120A, the BS ESL 118A and the S / D region 110A from growing in the S / D opening 910B, as shown in FIG. Fig. 12B In some embodiments, BS ESL 118A is epitaxially grown or deposited on dummy epitaxial layer 120A if BS ESL 118A is formed of a semiconductor material. In some embodiments, BS ESL 118A is deposited on dummy epitaxial layer 120A if BS ESL 118A is formed of a dielectric material.

[0048] refer to Figure 7 In operation 725, a second dummy epitaxial layer, a second BS ESL, and a second S / D region are formed in the second S / D opening. FIG. 14A to FIG. 16A and FIG. 14B to FIG. 16B As described above, the dummy epitaxial layer 120B, the BS ESL 118B, and the S / D region 110B are formed in the S / D opening 910B. The formation of the dummy epitaxial layer 120B, the BS ESL 118B, and the S / D region 110B may include the following sequential operations: (i) Fig.13A and Fig. 13B A hard mask layer 1452 (eg, a SiN layer) is deposited on the structure to form Fig.14A and Fig. 14B (ii) removing (eg, by etching) the hard mask layer 1452 located at Fig. 14B The portion of the structure located on the hard mask layer 1452 is not removed. Fig.14A The structural part to form Fig.15A and Fig. 15B(iii) epitaxially growing a semiconductor material (eg, doped or undoped SiGe) of a pseudo epitaxial layer 120B in the S / D opening 910B to a height of H2, such as Fig. 16B As shown in FIG. 1 , the semiconductor material of the dummy epitaxial layer 120B is not grown in the S / D opening 910A, as shown in FIG. Fig.16A (iv) epitaxially growing or depositing a BS ESL 118B having a thickness of T2 on the pseudo epitaxial layer 120B, as shown in FIG. Fig. 16B As shown in FIG. 1 , instead of growing BS ESL 118B in S / D opening 910A, as shown in FIG. Fig.16A (v) epitaxially growing a semiconductor material (eg, doped Si or doped SiGe) of the S / D region 110B on the BS ESL 118B, as shown in FIG. Fig. 16B As shown in FIG. 1 , the semiconductor material of the S / D region 110B is not grown in the S / D opening 910A, as shown in FIG. Fig.16A as shown in; and (vi) from Fig.16A The hard mask layer 1452 is removed from the structure without etching the S / D region 110B. In some embodiments, the BS ESL 118B is epitaxially grown or deposited on the dummy epitaxial layer 120B if the BS ESL 118B is formed of a semiconductor material. In some embodiments, the BS ESL 118B is deposited on the dummy epitaxial layer 120B if the BS ESL 118B is formed of a dielectric material.

[0049] The dummy epitaxial layer 120B grown to a height of H2 and the BS ESL 118B having a thickness of T2 prevents the S / D region 110B from being formed adjacent to and in contact with the bottommost nanostructure layer 208 of the superlattice structure 807B. Therefore, the bottommost nanostructure layer 208 of the superlattice structure 807B forms the dummy nanostructure layer 208C, and the nanostructure layer 208 of the superlattice structure 807B adjacent to and in contact with the S / D region 110B forms the active nanostructure layer 208B, as shown in FIG. Fig. 16B as shown in . Fig.16A The dielectric material of the hard mask layer 1452 on the structure prevents the pseudo epitaxial layer 120B, the BS ESL 118B and the S / D region 110B from growing on the S / D region 110A. The formation of the S / D region 110B may be followed by the formation of the FS ESL 122A and 122B and the ILD layers 124A and 124B, as shown in FIG. Fig.17A and Fig. 17B as shown in .

[0050] refer to Figure 7 In operation 730, the polysilicon structure and the nanostructure sacrificial layer are replaced with a gate structure. Fig.18A and Fig.18B As described, polysilicon structures 812A and 812B and nanostructure sacrificial layer 808 are replaced with gate structures 112A and 112B. Forming gate structures 112A and 112B may include: (i) Fig.17A and Fig. 17B The structure of removing polysilicon structures 812A and 812B, SiO2 layer 850 and nanostructure sacrificial layer 808 to form a gate opening (not shown); and (ii) forming gate structures 112A and 112B in the gate opening, such as Fig.18A and Fig.18B In some embodiments, the formation of gate structures 112A and 112B may be followed by the formation of FS contact structures 226A on S / D regions 110A and the formation of FS contact structures 226B on S / D regions 110B, as shown in FIG. Fig.18A and Fig.18B as shown in .

[0051] refer to Figure 7 In operation 735, a BS contact structure is formed on one of the first S / D regions and one of the second S / D regions. FIG. 19A to FIG. 25A and FIG. 19B to FIG. 25B As described, a BS contact structure 338A is formed on the BS surface of one of the S / D regions 110A, and a BS contact structure 338B is formed on the BS surface of one of the S / D regions 110B. Forming the BS contact structures 338A and 338B may include the following sequential operations: (i) removing the substrate 104 to expose the backside surfaces of the base structures 106A and 106B and the dummy epitaxial layers 120A and 120B, as shown in FIG. Fig.19A and Fig.19B (ii) depositing a hard mask layer 2054 (eg, a SiN layer) on the backside surfaces of the base structures 106A and 106B and the pseudo epitaxial layers 120A and 120B, as shown in FIG. Fig. 20A and Fig. 20B (iii) using a photolithography patterning process and an etching process to form openings 2138A and 2138B in the hard mask layer 2054, as shown in Fig.21A and Fig.21B (iv) etching the pseudo epitaxial layers 120A and 120B through the openings 2138A and 2138B, respectively, as shown in FIG. Fig.22A and Fig. 22B (v) etching BS ESL118A and 118B through openings 2138A and 2138B, respectively, to form contact openings 2238A and 2238B, as shown in FIG. Fig.22A and Fig. 22B(vi) a dielectric layer 2344 having a dielectric liner 344 of a material is deposited on the hard mask layer 2054 and in the openings 2238A and 2238B, as shown in FIG. Fig.23A and Fig. 23B (vii) removing (eg, by etching) a horizontal portion of dielectric layer 2344 without removing a vertical portion of dielectric layer 2344 to form dielectric layer 2344*, such as Fig.24A and Fig. 24B (viii) forming a silicide layer 340, as shown in Fig.24A and Fig. 24B (ix) depositing a conductive layer 2442 of a material having contact plugs 342 to fill the openings 2238A and 2238B, as shown in FIG. Fig.24A and Fig. 24B as shown in; and (x) Fig.24A and Fig. 24B A chemical mechanical polishing (CMP) process is performed on the structure to make the backside surfaces of the base structures 106A and 106B, the contact plugs 342, the dielectric liner 344, and the dummy epitaxial layers 120A and 120B coplanar, as shown in FIG. Fig.25A and Fig.25B In the case of using the pseudo epitaxial layers 120A and 120B, self-aligned BS contact structures 338A and 338B of different heights can be formed simultaneously in the GAA FETs 102A and 102B, as shown in FIG. Fig.25A and Fig.25B In some embodiments, barrier layer 446 may be formed after forming silicide layer 340 and before depositing conductive layer 2442 .

[0052] refer to Figure 7 In operation 740, a BS isolation layer is formed on the other of the first S / D region and the other of the second S / D region. FIG. 26A to FIG. 28A and FIG. 26B to FIG. 28B As described above, a BS isolation layer 548A is formed on the BS surface of another one of the S / D regions 110A, and a BS isolation layer 548B is formed on the BS surface of another one of the S / D regions 110B. Forming the BS isolation layers 548A and 548B may include the following sequential operations: (i) forming a BS isolation layer 548A from the BS surface of the S / D region 110A; and (ii) forming a BS isolation layer 548B from the BS surface of the S / D region 110B. Fig.25A and Fig.25B The pseudo-epitaxial layers 120A and 120B and the BS ESLs 118A and 118B are etched to form isolation openings 2648A and 2648B, as shown in FIG. Fig.26A and Fig.26B (ii) depositing a dielectric layer 2748 of a material having BS isolation layers 548A and 548B to fill openings 2648A and 2648B, as shown in FIG. Fig.27A and Fig.27B and (iii) performing a CMP process on the dielectric layer 2748 to make the backside surfaces of the base structures 106A and 106B, the contact plugs 342, the dielectric liner 344 and the BS isolation layers 548A and 548B coplanar, as shown in FIG. Fig.28A and Fig.28B In the case of using the pseudo epitaxial layers 120A and 120B, self-aligned BS isolation layers 548A and 548B of different heights can be formed simultaneously in the GAA FETs 102A and 102B, as shown in FIG. Fig.28A and Fig.28B as shown in .

[0053] The disclosed embodiments provide exemplary structures of GAA FETs (e.g., GAA FETs 102A and 102B) having different drive current characteristics on the same substrate (e.g., substrate 104) of a semiconductor device (e.g., semiconductor device 100), and also provide exemplary methods (e.g., method 700) for manufacturing these GAA FETs. In some embodiments, a first GAA FET (e.g., GAA FET 102A) may have a first nanostructure layer (e.g., nanostructure layer 208A) between a first S / D region pair (e.g., S / D region 110A), and a second GAA FET (e.g., GAA FET 102B) may have a second nanostructure layer (e.g., nanostructure layer 208B) between a second S / D region pair (e.g., S / D region 110B). The number of the first nanostructure layer may be greater than the number of the second nanostructure layer to achieve a higher drive current in the first GAA FET than in the second GAA FET. The semiconductor device may have GAA FETs with different drive current values ​​to optimize the overall power consumption of the semiconductor device. In some embodiments, the number of first and second nanostructure layers in contact with the first and second S / D region pairs can be controlled by using a first electrically non-active (“dummy”) epitaxial layer and a second electrically non-active (“dummy”) epitaxial layer (e.g., dummy epitaxial layers 120A and 120B) disposed below the first and second S / D region pairs. In some embodiments, the first and second dummy epitaxial layers can also be used to form self-aligned backside contact structures (e.g., BS contact structures 338A and 338B) on the backside surfaces of the first and second S / D region pairs. In some embodiments, the first and second dummy epitaxial layers can be replaced with backside isolation layers (e.g., BS isolation layers 548A and 548B) to reduce current leakage from the first and second S / D region pairs to the substrate.

[0054] In some embodiments, the semiconductor device includes: a first substrate structure and a second substrate structure; a first dummy epitaxial layer and a second dummy epitaxial layer, respectively disposed in the first substrate structure and the second substrate structure; a first active epitaxial layer and a second active epitaxial layer, respectively disposed on the first dummy epitaxial layer and the second dummy epitaxial layer; a first active nanostructure layer, disposed adjacent to and in contact with the first active epitaxial layer; a second active nanostructure layer, disposed adjacent to and in contact with the second active epitaxial layer; a dummy nanostructure layer, disposed adjacent to and in contact with the second dummy epitaxial layer; a first gate structure, surrounding the first active nanostructure layer; and a second gate structure, surrounding the second active nanostructure layer and the dummy nanostructure layer. The height of the second dummy epitaxial layer is greater than the height of the first dummy epitaxial layer. The height of the first active epitaxial layer is greater than the height of the second active epitaxial layer.

[0055] In some embodiments, the semiconductor device includes: a substrate structure; a pseudo-nanostructure layer disposed on the substrate structure; an active nanostructure layer disposed on the pseudo-nanostructure layer; a first S / D region disposed adjacent to a first end of the active nanostructure layer; a second S / D region disposed adjacent to a second end of the active nanostructure layer; an isolation layer disposed on the BS of the first S / D region; a first contact structure disposed on the FS of the first S / D region; a second contact structure disposed on the BS of the second S / D region; and a gate structure surrounding the active nanostructure layer and the pseudo-nanostructure layer.

[0056] In some embodiments, the method includes: forming a superlattice structure having a first nanostructure layer, a nanostructure sacrificial layer on the first nanostructure layer, and a second nanostructure layer on the nanostructure sacrificial layer; forming a polysilicon layer on the superlattice structure; forming a first opening and a second opening in the superlattice structure; epitaxially growing a first semiconductor layer and a second semiconductor layer in the first opening and the second opening, respectively; epitaxially growing a third semiconductor layer and a fourth semiconductor layer on the first semiconductor layer and the second semiconductor layer, respectively; replacing the polysilicon layer and the nanostructure sacrificial layer with a gate structure; and replacing the first semiconductor layer with a contact structure on the BS of the third semiconductor layer. The first semiconductor layer and the second semiconductor layer are in contact with the sidewall of the first nanostructure layer. The third semiconductor layer and the fourth semiconductor layer are in contact with the second nanostructure layer and the nanostructure sacrificial layer.

[0057] Some embodiments of the present application provide a semiconductor device, including: a first substrate structure and a second substrate structure; a first dummy layer and a second dummy layer, respectively arranged in the first substrate structure and the second substrate structure, wherein the height of the second dummy layer is greater than the height of the first dummy layer; a first active epitaxial layer and a second active epitaxial layer, respectively arranged on the first dummy layer and the second dummy layer, wherein the height of the first active epitaxial layer is greater than the height of the second active epitaxial layer; a first active nanostructure layer, arranged to be adjacent to the first active epitaxial layer and in contact with the first active epitaxial layer; a second active nanostructure layer, arranged to be adjacent to the second active epitaxial layer and in contact with the second active epitaxial layer; a dummy nanostructure layer, arranged to be adjacent to the second dummy layer and in contact with the second dummy layer; a first gate structure, surrounding the first active nanostructure layer; and a second gate structure, surrounding the second active nanostructure layer and the dummy nanostructure layer.

[0058] In some embodiments, the semiconductor device further comprises a semiconductor layer disposed between the first active epitaxial layer and the first dummy layer. In some embodiments, the semiconductor device further comprises a dielectric layer disposed between the first active epitaxial layer and the first dummy layer. In some embodiments, the semiconductor device further comprises a semiconductor layer disposed between the second active epitaxial layer and the second dummy layer and in contact with the dummy nanostructure layer. In some embodiments, the semiconductor device further comprises a dielectric layer disposed between the second active epitaxial layer and the second dummy layer and in contact with the dummy nanostructure layer. In some embodiments, the semiconductor device further comprises: a first conductive structure disposed in the first base structure; and a second conductive structure disposed in the second base structure, wherein a height of the second conductive structure is greater than a height of the first conductive structure. In some embodiments, the semiconductor device further comprises a conductive structure disposed in the second base structure, wherein the dummy nanostructure layer is disposed between the conductive structure and the second dummy layer. In some embodiments, the semiconductor device further comprises a third active epitaxial layer and a fourth active epitaxial layer, wherein: the first active nanostructure layer is disposed between the first active epitaxial layer and the third active epitaxial layer and contacts the first active epitaxial layer and the third active epitaxial layer, and the second active nanostructure layer is disposed between the second active epitaxial layer and the fourth active epitaxial layer and contacts the second active epitaxial layer and the fourth active epitaxial layer. In some embodiments, the material of the first dummy layer is different from the material of the first active epitaxial layer. In some embodiments, the second active nanostructure layer and the dummy nanostructure layer comprise the same semiconductor material.

[0059] Other embodiments of the present application provide a semiconductor device, including: a substrate structure; a pseudo-nanostructure layer, arranged on the substrate structure; an active nanostructure layer, arranged on the pseudo-nanostructure layer; a first source / drain (S / D) region, arranged to be adjacent to a first end of the active nanostructure layer; a second source / drain region, arranged to be adjacent to a second end of the active nanostructure layer; an isolation layer, arranged on a back side of the first source / drain region; a first contact structure, arranged on a front side of the first source / drain region; a second contact structure, arranged on a back side of the second source / drain region; and a gate structure, surrounding the active nanostructure layer and the pseudo-nanostructure layer.

[0060] In some embodiments, the isolation layer includes a dielectric layer. In some embodiments, the pseudo nanostructure layer is disposed between the isolation layer and the second contact structure and contacts the isolation layer and the second contact structure. In some embodiments, the active nanostructure layer contacts the first source / drain region and the second source / drain region. In some embodiments, the semiconductor device further includes an internal gate spacer in contact with the isolation layer. In some embodiments, the semiconductor device further includes an internal gate spacer in contact with the second contact structure.

[0061] Some other embodiments of the present application provide a method, comprising: forming a superlattice structure on a substrate, comprising a first nanostructure layer, a nanostructure sacrificial layer on the first nanostructure layer, and a second nanostructure layer on the nanostructure sacrificial layer; forming a polysilicon layer on the superlattice structure; forming a first opening and a second opening in the superlattice structure; epitaxially growing a first semiconductor layer and a second semiconductor layer in the first opening and the second opening, respectively, wherein the first semiconductor layer and the second semiconductor layer are in contact with the sidewalls of the first nanostructure layer; epitaxially growing a third semiconductor layer and a fourth semiconductor layer on the first semiconductor layer and the second semiconductor layer, respectively, wherein the third semiconductor layer and the fourth semiconductor layer are in contact with the second nanostructure layer and the nanostructure sacrificial layer; replacing the polysilicon layer and the nanostructure sacrificial layer with a gate structure; and replacing the first semiconductor layer with a contact structure on the back side of the third semiconductor layer.

[0062] In some embodiments, the method further comprises replacing the second semiconductor layer with a dielectric layer on the back side of the fourth semiconductor layer. In some embodiments, the method further comprises removing the substrate before replacing the first semiconductor layer. In some embodiments, the method further comprises depositing a first dielectric layer and a second dielectric layer on the first semiconductor layer and the second semiconductor layer, respectively, before epitaxially growing the third semiconductor layer and the fourth semiconductor layer.

[0063] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a substrate to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: a first base structure and a second base structure; A first dummy layer and a second dummy layer are respectively arranged in the first substrate structure and the second substrate structure, wherein a height of the second dummy layer is greater than a height of the first dummy layer; A first active epitaxial layer and a second active epitaxial layer are respectively disposed on the first dummy layer and the second dummy layer, wherein a height of the first active epitaxial layer is greater than a height of the second active epitaxial layer; a first active nanostructure layer disposed adjacent to and in contact with the first active epitaxial layer; a second active nanostructure layer disposed adjacent to and in contact with the second active epitaxial layer; a pseudo-nanostructure layer disposed adjacent to and in contact with the second pseudo-layer; a first gate structure surrounding the first active nanostructure layer; and The second gate structure surrounds the second active nanostructure layer and the dummy nanostructure layer. 2 . The semiconductor device according to claim 1 , further comprising a semiconductor layer disposed between the first active epitaxial layer and the first dummy layer. 3 . The semiconductor device according to claim 1 , further comprising a dielectric layer disposed between the first active epitaxial layer and the first dummy layer. 4 . The semiconductor device according to claim 1 , further comprising a semiconductor layer disposed between the second active epitaxial layer and the second dummy layer and in contact with the dummy nanostructure layer. 5 . The semiconductor device according to claim 1 , further comprising a dielectric layer disposed between the second active epitaxial layer and the second dummy layer and in contact with the dummy nanostructure layer.

6. The semiconductor device according to claim 1, further comprising: A first conductive structure, disposed in the first substrate structure; as well as A second conductive structure is disposed in the second substrate structure, wherein a height of the second conductive structure is greater than a height of the first conductive structure.

7. The semiconductor device according to claim 1, further comprising a conductive structure disposed in the second substrate structure, wherein: The dummy nanostructure layer is disposed between the conductive structure and the second dummy layer.

8. The semiconductor device according to claim 1, further comprising a third active epitaxial layer and a fourth active epitaxial layer, wherein: The first active nanostructure layer is disposed between the first active epitaxial layer and the third active epitaxial layer and is in contact with the first active epitaxial layer and the third active epitaxial layer, and The second active nanostructure layer is disposed between and in contact with the second active epitaxial layer and the fourth active epitaxial layer.

9. A semiconductor device comprising: Base structure; A pseudo-nanostructure layer is disposed on the base structure; an active nanostructure layer, disposed on the pseudo nanostructure layer; a first source / drain (S / D) region disposed adjacent to a first end of the active nanostructure layer; a second source / drain region disposed adjacent to a second end of the active nanostructure layer; an isolation layer, disposed on the back side of the first source / drain region; a first contact structure disposed on a front side of the first source / drain region; a second contact structure disposed on the back side of the second source / drain region; as well as The gate structure surrounds the active nanostructure layer and the dummy nanostructure layer.

10. A method for manufacturing a semiconductor device, comprising: forming a superlattice structure including a first nanostructure layer, a nanostructure sacrificial layer on the first nanostructure layer, and a second nanostructure layer on the nanostructure sacrificial layer on the substrate; forming a polysilicon layer on the superlattice structure; forming a first opening and a second opening in the superlattice structure; Epitaxially growing a first semiconductor layer and a second semiconductor layer in the first opening and the second opening, respectively, wherein the first semiconductor layer and the second semiconductor layer are in contact with a sidewall of the first nanostructure layer; Epitaxially growing a third semiconductor layer and a fourth semiconductor layer on the first semiconductor layer and the second semiconductor layer, respectively, wherein the third semiconductor layer and the fourth semiconductor layer are in contact with the second nanostructure layer and the nanostructure sacrificial layer; replacing the polysilicon layer and the nanostructure sacrificial layer with a gate structure; and The first semiconductor layer is replaced with a contact structure on the back side of the third semiconductor layer.

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