Highly-doped straight MOS (Metal Oxide Semiconductor) device capable of bearing extremely high voltage
By deepening the depth of the second type heavily doped region and floating ring in V-DMOS, the collapse problem caused by electric field concentration of traditional high-voltage semiconductor components is solved, the voltage stability and reliability of the components are improved, and economic benefits are maintained.
Patent Information
- Application Number
- CN202311194451.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-15
- Publication Date
- 2025-03-25
AI Technical Summary
Traditional high-voltage semiconductor components are prone to electric field concentration under reverse bias, resulting in early collapse of components, too low voltage and concentrated burst current, which in turn affects the reliability and performance of components.
By partially deepening the depth of the second type heavily doped region and floating ring in V-DMOS, the active region and floating ring structure are effectively matched, and the dispersing element is concentrated under the reverse bias, thereby improving the voltage performance of the high-voltage element.
The stability and reliability of high-voltage components at a larger voltage are achieved, and component collapse problems caused by excessive concentration of electric fields is avoided, while not increasing manufacturing costs and bringing economic benefits.
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Figure CN119698036A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a power semiconductor element, and in particular to a highly doped vertical MOS device capable of withstanding extremely high voltage. Background Art
[0002] MOSFET is a semiconductor switching element. When the gate voltage is high, the impedance between the drain and the source decreases, causing the two electrodes to conduct, and the drain is the main flow channel for current. The larger the structure of the source (second-type semiconductor), the more it squeezes the drain current, resulting in an increase in on-resistance, insufficient voltage of high-voltage components, and excessive on-resistance.
[0003] Traditional planar high-voltage semiconductor components often use voltage floating rings as the component terminal structure design to extend the component voltage performance premature collapse caused by the local electric field concentration phenomenon caused by the termination of the depletion layer in the terminal area under reverse bias. Therefore, the deeper the floating ring structure, the better its ability to disperse the electric field in the structure. Conversely, the larger the active area second-type semiconductor structure is, the less conducive it is to the passage of current.
[0004] The interior of the floating ring is doped with a high concentration of type II semiconductor, which serves to extend the voltage distribution in space and disperse the electric field concentration phenomenon formed by the space charge in the depletion region of the active region structure. The difference between the depth of the floating ring structure and the depth of the active region in the traditional way needs to be optimized. If the difference is too large, the electric field will be overly concentrated in the active region or the floating ring, resulting in premature component collapse, low voltage, surge current concentration and premature component failure. Therefore, in order to avoid insufficient voltage of high-voltage components and excessive on-resistance, locally increasing the structural depth of the type II semiconductor can optimize the voltage and on-resistance performance of the high-voltage MOSFET to a limited extent.
[0005] Therefore, the present invention hopes to propose a new highly doped vertical MOS device that can withstand extremely high voltages, by deepening the depth of the second type heavily doped region and the floating ring of the V-DMOS, so that the entire VD MOS can withstand a higher voltage. Summary of the invention
[0006] Therefore, the purpose of the present invention is to solve the above-mentioned problems in the prior art. The present invention proposes a highly doped vertical MOS device that can withstand extremely high voltages, which is formed by partially deepening a semiconductor of the same type as the source. The structure of the source can be partially deepened by deepening the structure of P Plus or N Plus. Increasing the structural depth of the active region and the floating ring is beneficial to the design of high-voltage components, allowing the active region and the floating ring structure to be effectively matched, effectively dispersing the electric field concentration phenomenon of the component under reverse bias, and improving the voltage performance of the high-voltage component. And the component impedance does not increase due to the comprehensive deepening of the source limit shrinkage current channel. Since P Plus or N Plus is an existing structure of the component, there is no need to design additional masks and yellow light processes. Therefore, the structure of partially deepening the source can not only effectively disperse the electric field concentration phenomenon of the component under reverse bias to improve the voltage performance of the high-voltage component, but also will not increase the manufacturing cost, which can bring extremely high economic benefits.
[0007] To achieve the above-mentioned purpose, the present invention proposes a highly doped vertical MOS device capable of withstanding extremely high voltage, comprising: a VD MOS, the VD MOS comprising: a first-type substrate, at least two second-type doping wells, each arranged side by side on the upper portion of the first-type substrate, so that the upper surface of the second-type doping well is exposed to the first-type substrate; wherein two separated first-type heavily doped regions are implanted above each second-type doping well, and the upper surface of the implanted first-type heavily doped region is exposed to the first-type substrate; wherein a second-type heavily doped region is located between the two first-type heavily doped regions, and penetrates a distance below the first-type heavily doped region, so that the first-type heavily doped region is located on the left and right sides thereof respectively; wherein the second-type heavily doped region is implanted toward The second-type heavily doped region extends downward and passes through the second-type doped well for a distance and penetrates into the first-type substrate; that is, the depth of the second-type heavily doped region is greater than the depth of the second-type doped well; wherein a gate structure is formed between each second-type doped well above the first-type substrate, the gate structure includes a gate, and a dielectric layer composed of oxide is formed below the gate to isolate the first-type substrate; wherein the gate and the dielectric layer are surrounded by an oxide layer, and the oxide layer is used to isolate the gate from a source located above the first-type substrate and surrounding the gate structure.
[0008] The highly doped vertical MOS device capable of withstanding extremely high voltage also includes a terminal region parallel to the VD MOS, wherein the terminal region releases carriers when providing high voltage, enlarging the depletion region, thereby enabling the entire highly doped vertical MOS device to withstand a higher voltage; wherein the terminal region includes: a first-type terminal region substrate connected to the right side of the first-type substrate of the VD MOS, wherein the first-type terminal region substrate is first-type doped; the first-type substrate and the first-type terminal region substrate are integrally formed; a terminal region oxide layer located above the first-type terminal region substrate, wherein the terminal region oxide layer is a field effect oxide layer (Field Oxide) is used to isolate the active areas of different components to prevent charge loss or crosstalk; a terminal area gate is located in the terminal area oxide layer and above the first type terminal area substrate, and is used to control the formation and conduction of the channel, so as to adjust the current between the terminal area gate on the terminal area and a drain located below the first type terminal area substrate, and a terminal area dielectric layer composed of oxide is formed below the terminal area gate to isolate the first type terminal area substrate; a terminal area gate bus is located above the terminal area gate, and is used to distribute the voltage of the terminal area gate to each doped area on the terminal area, and reduce the consumption of the terminal area gate charge, thereby improving the switching speed and efficiency; wherein the terminal area gate bus is connected in parallel with other gates and the terminal area gate, so all the gates and the terminal area gate can be enabled at the same time through the terminal area gate bus.
[0009] The highly doped vertical MOS device capable of withstanding extremely high voltage, the terminal region further comprises: a plurality of second-type floating rings, which are spaced apart from each other and whose upper surfaces are exposed on the upper portion of the first-type terminal region substrate; the interior of each second-type floating ring is doped with a high concentration of second-type semiconductor, which functions to extend the voltage distribution in space and disperse the electric field concentration phenomenon formed by the space charge in the depletion region of the active region structure; wherein the depth of the second-type heavily doped region on the VD MOS is less than or equal to the depth of each second-type floating ring on the terminal region; wherein the deeper the depth of the second-type floating ring structure, the better the effect of dispersing the electric field in the structure, which is beneficial to the design of high-voltage components; the deeper the second-type floating ring makes the depletion layer formed on the terminal region move to the right, and the area of the depletion layer is also larger, so a greater capacitance effect is generated, so that the overall structure can withstand a greater voltage.
[0010] The highly doped vertical MOS device capable of withstanding extremely high voltage, the terminal region further comprises: a second type terminal guard ring, the upper surface of which is exposed on the upper portion of the first type terminal region substrate; a metal field plate, located in the oxide layer of the terminal region and connected to the second type terminal guard ring; the metal field plate is used to provide potential extension, control and influence the formation and shape of the depletion region in the first type terminal region substrate.
[0011] The highly doped vertical MOS device capable of withstanding extremely high voltage, when a high voltage is applied to the gate, the second-type doped well near the surface of the first-type substrate is attracted by the voltage of the gate to generate high-concentration electrons or holes, and a low-impedance current channel is formed near the surface of the first-type substrate by the second-type doped well, and current can flow from the source to a drain located under the first-type terminal region substrate.
[0012] The highly doped vertical MOS device capable of withstanding extremely high voltage has the first type being N-type and the second type being P-type.
[0013] The highly doped vertical MOS device capable of withstanding extremely high voltage has a first type of P type and a second type of N type.
[0014] The features and advantages of the present invention may be further understood from the following description, which is to be read with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 A schematic diagram showing the structure of a device according to a first aspect of the present invention; Figure 2 A schematic diagram showing the current path of the present invention, wherein the current flow direction is represented by a dotted line; Figure 3A A schematic diagram showing a deepening of the floating ring structure of the present invention, wherein the dotted line represents the depletion layer region; Figure 3B A schematic diagram showing a floating ring structure of the prior art is shown, wherein the dotted line represents a depletion layer region; Figure 4 A schematic diagram showing the structure of a device according to a second aspect of the present invention; Figure 5 A schematic diagram showing the structure of a device according to a third aspect of the present invention; Figure 6 A schematic diagram showing the structure of a device according to a fourth aspect of the present invention; Figure 7 A schematic diagram showing the terminal region gate bus of the present invention enabling all the gates and the terminal region gates at the same time. DETAILED DESCRIPTION
[0016] Hereby, the structural composition of the present invention, and the effects and advantages it can produce are described in detail as follows with reference to the accompanying drawings, with a preferred embodiment of the present invention: MOSFET is a semiconductor switching element. When the gate voltage is high, the impedance between the drain and the source decreases, causing the two electrodes to conduct. The drain is the main flow channel for current. The larger the structure of the source (second-type semiconductor), the more it squeezes the drain current channel, resulting in an increase in on-resistance. In order to avoid insufficient voltage of high-voltage components and excessive on-resistance, the present invention partially increases the structural depth of the second-type semiconductor, thereby optimizing the voltage and on-resistance performance of the high-voltage MOSFET.
[0017] Please refer to Figure 1 , showing a highly doped vertical MOS device capable of withstanding extremely high voltage of the present invention, wherein Figure 1 In the present invention, an N-type semiconductor is used as the first type doped semiconductor, and a P-type semiconductor is used as the second type doped semiconductor, but this is not used to limit the present invention. In the present invention, a P-type semiconductor can also be used as the first type doped semiconductor, and an N-type semiconductor can be used as the second type doped semiconductor, which is within the scope of the present invention.
[0018] The highly doped vertical MOS device capable of withstanding extremely high voltage of the present invention comprises the following elements: A VD MOS (Vertical Double Diffusion MOSFET) 5 includes the following components: a first type substrate 10, At least two second type doping wells 15 are arranged side by side on the upper portion of the first type substrate 10 to form a second type doping well (P well or N well). Figure 1 and Figure 4 As shown), the upper surface of the second type doping well 15 is exposed on the first type substrate 10.
[0019] Two separated first-type heavily doped regions 20 are implanted above each second-type doping well 15 , and the upper surfaces of the implanted first-type heavily doped regions 20 are exposed to the first-type substrate 10 .
[0020] One of the second-type heavily doped regions 25 is located between the two first-type heavily doped regions 20 and extends a certain distance below the first-type heavily doped region 20, so that the first-type heavily doped region 20 is located on the left and right sides thereof. The second-type heavily doped region 25 extends downward and passes through the second-type doping well 15 for a certain distance and extends into the first-type substrate 10. That is, the depth of the second-type heavily doped region 25 on the V-DMOS 5 is greater than the depth of the second-type doping well 15.
[0021] A gate structure is formed between each second type doping well 15 above the first type substrate 10, and the gate structure includes a gate 30, and a dielectric layer (Gox) 35 composed of oxide is formed below the gate 30 to isolate the first type substrate 10. The periphery of the gate 30 and the dielectric layer 35 is surrounded by an oxide layer (ILD) 40, and the oxide layer 40 is used to isolate the gate 30 from a source 33 located above the first type substrate 10 and surrounding the gate structure.
[0022] A terminal region 45 is parallel to the VD MOS 5, wherein the terminal region 45 includes: A first type termination area substrate 50 is connected to the right side of the first type substrate 10 of the VD MOS 5, wherein the first type termination area substrate 50 is first type doped. The first type substrate 10 and the first type termination area substrate 50 are connected substrates and can be formed integrally during the manufacturing process.
[0023] A terminal region oxide layer 60 is located above the first type terminal region substrate 50. The terminal region oxide layer 60 is a field oxide layer, which is used to isolate the active areas of different components to prevent charge loss or crosstalk. The field oxide layer is thicker than the ordinary gate oxide layer, so it can improve the insulation performance and stability of the component.
[0024] The first type terminal area substrate 50 further comprises: A plurality of second-type floating rings 55 are spaced apart from each other, and their upper surfaces are exposed on the upper part of the first-type terminal region substrate 50. The interior of each second-type floating ring 55 is doped with a high concentration of second-type semiconductor, which serves to extend the voltage distribution in space and disperse the electric field concentration phenomenon formed by the space charge in the depletion region of the active region structure. The depth of the second-type heavily doped region 25 on the VD MOS 5 is less than or equal to the depth of each second-type floating ring 55 on the terminal region 45. That is, the distance between the second-type heavily doped region 25 and the bottom of the first-type substrate 10 is greater than the distance between each second-type floating ring 55 and the bottom of the first-type terminal region substrate 50.
[0025] The deeper the structure of the second type floating ring 55 is, the better the effect of dispersing the electric field in the structure is, which is beneficial to the design of high voltage components.
[0026] A second terminal guard ring 72 (Guarding Ring), such as Figure 1 and Figure 4The second type terminal guard ring 72 is a region formed by a high concentration of P-type dopants or N-type dopants on an N-type semiconductor substrate or a P-type semiconductor substrate, and provides a reverse cutoff voltage for the device and a channel for the MOSFET.
[0027] A terminal region gate 62 is located in the terminal region oxide layer 60 and above the second type terminal guard ring 72, which is used to control the formation and conduction of the current channel. A terminal region dielectric layer 65 composed of oxide is formed below the terminal region gate 62 to isolate the first type terminal region substrate 50.
[0028] A terminal region gate bus 64 is located above the terminal region gate 62 and is used to distribute the voltage of the terminal region gate 62 to each doped region on the terminal region 45, thereby reducing the charge consumption of the terminal region gate 62 and improving the switching speed and efficiency. Figure 7 As shown, the terminal region gate bus 64 is connected in parallel with other gates 30 and the terminal region gate 62 , so by applying voltage to the terminal region gate bus 64 , all the gates 30 and the terminal region gate 62 can be enabled at the same time.
[0029] A metal field plate 66 is located in the termination region oxide layer 60 and connected to the second type termination guard ring 72. The metal field plate 66 is used to provide potential extension, control and influence the formation and shape of the depletion region in the first type termination region substrate 50.
[0030] like Figure 2 As shown, by using the above structure, when a high voltage is applied to the gate 30, the second type doping well 15 near the surface of the first type substrate 10 is attracted by the voltage of the gate 30 to generate high-concentration electrons (or holes), and a low-impedance current channel is formed near the surface of the first type substrate 10 by the second type doping well 15, so that current can flow from the source 33 to a drain 36 located under the first type terminal area substrate 50. The deeper second type heavily doped region 25 in the present invention can effectively enhance the depletion capacity of the second type doping region in the active region, so that the overall structure can withstand a larger voltage.
[0031] like Figure 3A and Figure 3B As shown (where Figure 3B The second type floating ring 55 (such as the floating ring structure in the prior art) in the structure of the present invention is deeper. Figure 3A ) can move the depletion layer formed on the terminal region 45 to the right, and the area of the depletion layer is also larger, so a larger capacitance effect is generated, so that the overall structure can withstand a larger voltage.
[0032] Wherein P Plus or N Plus is the local area of the source of the second-type semiconductor structure in the MOSFET element, and is electrically connected to the metal on the surface of the element. The original excessively high concentration of the second-type semiconductor can reduce the on-resistance of the heterojunction. Therefore, the present invention adds the overall second-type semiconductor to form a depletion capability in the first-type substrate for the second-type semiconductor P Plus or N Plus structure by designing the depth of the second-type heavily doped region 25 on the VD MOS 5 to be greater than the depth of the second-type doping well 15, and the depth of the second-type heavily doped region 25 is less than or equal to the depth of each second-type floating ring 55 on the terminal area 45, so that the overall structure can withstand a larger voltage.
[0033] The present invention has two embodiments. In the first embodiment, (e.g. Figure 1 As shown in FIG. 1 , the first type semiconductor is an N-type semiconductor, and the second type semiconductor is a P-type semiconductor. In the second embodiment, as shown in FIG. Figure 4 As shown, the first type semiconductor is a P type semiconductor, and the second type semiconductor is an N type semiconductor.
[0034] like Figure 5 As shown, in the present invention, the terminal area 45 may not have the floating ring 55, and the other components are the same as Figure 1 as shown in the embodiments; or as Figure 6 As shown, the terminal region 45 of the present invention may not have the metal field plate 66 and the second type terminal guard ring 72, and the other components are the same as Figure 1 These aspects are all within the scope of the present invention.
[0035] The advantage of the present invention is that it is formed by locally deepening a semiconductor of the same type as the source. The structure of the source can be locally deepened by deepening the structure of P Plus or N Plus. Increasing the structural depth of the active region and the floating ring is beneficial to the design of high-voltage components, allowing the active region and the floating ring structure to be effectively matched, effectively dispersing the electric field concentration phenomenon of the component under reverse bias, and improving the voltage performance of the high-voltage component. And the component impedance does not increase due to the full deepening of the source limit shrinking current channel. Since P Plus or N Plus is an existing structure of the component, there is no need to design additional masks and yellow light processes. Therefore, the structure of locally deepening the source can not only effectively disperse the electric field concentration phenomenon of the component under reverse bias to improve the voltage performance of the high-voltage component, but also will not increase the manufacturing cost, which can bring extremely high economic benefits.
[0036] In summary, the humanized and considerate design of the present invention is quite in line with the actual needs. It specifically improves the existing deficiencies and has obvious breakthrough advantages compared with the existing technology. It does have the improvement of efficacy and is not easy to achieve. The present invention has not been published or disclosed in domestic and foreign literature and markets.
[0037] The above detailed description is a specific description of a feasible embodiment of the present invention, but the embodiment is not intended to limit the patent scope of the present invention. Any equivalent implementation or modification that does not deviate from the technical spirit of the present invention should be included in the patent scope of the present invention.
Claims
1. A highly doped vertical MOS device capable of withstanding extremely high voltage, characterized in that: include: A VD MOS includes: a first type substrate (10), At least two second-type doping wells (15), each arranged side by side on the upper portion of the first-type substrate, such that the upper surface of the second-type doping well (15) is exposed to the first-type substrate; Two separated first-type heavily doped regions (20) are implanted above each second-type doping well (15), and the upper surfaces of the implanted first-type heavily doped regions (20) are exposed on the first-type substrate 10; A second type heavily doped region (25) is located between the two first type heavily doped regions (20) and penetrates a distance below the first type heavily doped region (20), so that the first type heavily doped region (20) is located on the left and right sides thereof respectively; wherein the second type heavily doped region (25) extends downward and passes through the second type doping well (15) for a distance and penetrates the first type substrate (10); A gate structure is formed between each second-type doping well (15) above the first-type substrate (10), and the gate structure includes a gate (30), and a dielectric layer (35) composed of oxide is formed below the gate to isolate the first-type substrate (10); wherein the gate (30) and the dielectric layer (35) are surrounded by an oxide layer (40) on the periphery, and the oxide layer (40) is used to isolate the gate (30) from a source (33) located above the first-type substrate (10) and surrounding the gate structure.
2. The highly doped vertical MOS device capable of withstanding extremely high voltage as claimed in claim 1, characterized in that: It also includes a terminal region (45) parallel to the VD MOS (5), wherein the terminal region (45) releases carriers when providing high voltage, enlarges the depletion region, and enables the entire high-doped vertical MOS device to withstand a higher voltage; The terminal area (45) comprises: A first-type terminal region substrate (50) is connected to the right side of the first-type substrate (10) of the VD MOS, wherein the first-type terminal region substrate (50) is first-type doped; the first-type substrate (10) and the first-type terminal region substrate (50) are integrally formed; A terminal region oxide layer (60) is located above the first type terminal region substrate (50), and the terminal region oxide layer (60) is a field effect oxide layer used to isolate active regions of different components to prevent charge loss or crosstalk; A terminal region gate (62) is located in the terminal region oxide layer (60) and above the first type terminal region substrate (50) for controlling the formation and conduction of a current channel, and a terminal region dielectric layer (65) composed of oxide is formed below the terminal region gate (62) to isolate the first type terminal region substrate (50); A terminal region gate bus (64) is located above the terminal region gate (62) and is used to distribute the voltage of the terminal region gate (62) to each doped region on the terminal region (45), and reduce the consumption of the charge of the terminal region gate (62), thereby improving the switching speed and efficiency; The terminal region gate bus (64) is connected in parallel to the other gates (30) and the terminal region gate (62), and all the gates (30) and the terminal region gate (62) can be enabled simultaneously by applying voltage to the terminal region gate bus (64).
3. The highly doped vertical MOS device capable of withstanding extremely high voltage as claimed in claim 2, characterized in that: The terminal area (45) also includes: A plurality of second-type floating rings (55), the second-type floating rings (55) are spaced apart from each other, and their upper surfaces are exposed on the upper portion of the first-type terminal region substrate (50); the interior of each second-type floating ring (55) is doped with a high concentration of second-type semiconductor to extend the voltage distribution in space and disperse the electric field concentration phenomenon formed by the space charge in the depletion region of the active region structure; The depth of the second type heavily doped region (25) on the VD MOS (5) is less than or equal to the depth of each second type floating ring (55) on the terminal region (45).
4. The highly doped vertical MOS device capable of withstanding extremely high voltage as claimed in claim 2, characterized in that: The terminal area (45) also includes: A second type terminal guard ring (72) whose upper surface is exposed on the upper part of the first type terminal region substrate (50); a metal field plate (66) located in the terminal region oxide layer (60) and connected to the second type terminal guard ring (72); the metal field plate (66) is used to provide potential extension, control and influence the formation and shape of the depletion region in the first type terminal region substrate (50).
5. The highly doped vertical MOS device capable of withstanding extremely high voltage as claimed in claim 3, characterized in that: When a high voltage is applied to the gate (30), the second-type doping well (15) near the surface of the first-type substrate (10) is attracted by the voltage of the gate (30) to generate high-concentration electrons or holes, and a low-impedance current channel is formed near the surface of the first-type substrate (10) at the second-type doping well (15), and the current flows from the source (33) to a drain (36) located under the first-type terminal region substrate (50).
6. The highly doped vertical MOS device capable of withstanding extremely high voltage according to any one of claims 1 to 5, characterized in that: The first type is N-type, and the second type is P-type.
7. The highly doped vertical MOS device capable of withstanding extremely high voltage according to any one of claims 1 to 5, characterized in that: The first type is P type, and the second type is N type.