Power semiconductor device and power converter including the same

Abstract

A power semiconductor device according to an embodiment may include a substrate, a first epitaxial layer of a first conductivity type disposed on the substrate, a second epitaxial layer of the first conductivity type disposed on the first epitaxial layer of the first conductivity type, a first well of a second conductivity type partially disposed in the first epitaxial layer of the first conductivity type, and a second well of the second conductivity type partially disposed in the second epitaxial layer of the first conductivity type. A second well of a second conductivity type disposed in the second epitaxial layer of the first conductivity type, an ion implantation region and a source region of the second conductivity type disposed in the second well of the second conductivity type, a source electrode disposed on the source region, a gate insulating layer disposed in the trench region, and a gate electrode disposed on the gate insulating layer. A trench region in which the ion implantation region of the second conductivity type and a portion of the second epitaxial layer of the first conductivity type are removed, a trench gate disposed on the gate insulating layer, an interlayer insulating layer disposed on the trench gate, and a gate electrode electrically connected to the trench gate.

Description

Technical Field

[0001] Embodiments relate to a power semiconductor device, a power semiconductor module, a power converter, and a method of manufacturing the same. Background Art

[0002] Power semiconductors are one of the key components that determine the efficiency, speed, durability and reliability of power electronic systems.

[0003] With the recent development of the power electronics industry, previously used silicon (Si) power semiconductors have reached their physical limits. WBG (Wide Band Gap) power semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) are being actively studied to replace silicon power semiconductors.

[0004] The band gap energy of WBG power semiconductor devices is approximately three times that of Si power semiconductor devices, so it has the characteristics of low intrinsic carrier concentration, high breakdown electric field (approximately 4 to 20 times), high thermal conductivity (approximately 3 to 13 times) and large electron saturation rate (approximately 2 to 2.5 times).

[0005] These characteristics allow operation in high temperature and high voltage environments, with high switching speeds and low switching losses. Among them, gallium nitride (GaN) power semiconductor devices can be used in low-voltage systems, and silicon carbide (SiC) power semiconductor devices can be used in high-voltage systems.

[0006] The SiC MOSFET power semiconductor of the prior art is generally represented as a VDMOSFET with a vertical diffusion structure, and can also be simply represented as a double diffusion structure DMOSFET. In addition, according to the direction of the channel, SiC MOSFET can be divided into planar MOSFET and trench MOSFET.

[0007] Among them, the trench MOSFET is a structure in which a channel is provided on the side wall of a trench. To this end, a gate insulating film is provided on the side wall of the trench, and a gate electrode is provided in the trench.

[0008] SiC MOSFET has high on-resistance due to low channel mobility and large channel resistance, so trench MOSFET is proposed to reduce channel resistance. Trench MOSFET has the advantage of increasing channel density by forming a channel on the sidewall of the trench.

[0009] However, since trench MOSFET has a larger electric field in the trench gate oxide, its drift distance is shorter than the P base (P well), and in particular, the electric field is concentrated at the trench edge, there is a problem that gate oxide breakdown occurs quickly and BV is reduced.

[0010] For example, in the case of SiC trench MOSFET, the breakdown field strength is 10 times that of silicon (Si), so SiC semiconductor devices use a voltage close to 10 times that of Si devices. For this reason, an electric field 10 times stronger than that of silicon devices is applied to the gate insulating film provided in the trench, which leads to the problem that the gate insulating film is easily destroyed at the corners of the trench.

[0011] Internal technology is studying the process of forming a p-type well (p-base) deeper than the gate trench to prevent electric field concentration at the corner of the trench, but in order to form such a deep p-type well, there is a problem that the ion implantation energy exceeds the level of general processes. In addition, since it is difficult to control lateral dispersion, high-energy ion implantation causes severe ion implantation outside the target area, which causes the problem of reducing the cell pitch. Summary of the invention

[0012] One of the technical purposes of the power semiconductor device, the power converter including the power semiconductor device, and the method for manufacturing the power semiconductor device according to the embodiment is to prevent electric field concentration at the corners of the trench while preventing the cells from being dispersed laterally and also preventing the problem of reduced cell pitch.

[0013] The technical problems of the embodiment are not limited to the technical problems described in this item, and include technical problems that can be understood through the description of the invention.

[0014] According to the embodiment, the power semiconductor device may include a substrate 111, a first epitaxial layer 112a of a first conductivity type disposed on the substrate 111, a second epitaxial layer 112b of the first conductivity type disposed on the first epitaxial layer 112a of the first conductivity type, a first well 121a of the second conductivity type partially disposed in the first epitaxial layer 112a of the first conductivity type, a second well 121b of the second conductivity type disposed in the second epitaxial layer 112b of the first conductivity type, an ion implantation region 122 of the second conductivity type disposed in the second well 121b of the second conductivity type and a source region 115, a source electrode 142 disposed on the source region 115, a gate insulating layer 131 disposed in a trench region T, a portion of the ion implantation region 122 of the second conductivity type and the second epitaxial layer 112b of the first conductivity type removed in the trench region T, a trench gate 132 disposed on the gate insulating layer 131, an interlayer insulating layer 150 disposed on the trench gate 132, and a gate electrode electrically connected to the trench gate 132.

[0015] In an embodiment, one side of the second conductivity type first well 121 a and one side of the second conductivity type second well 121 b may be aligned upward on the substrate.

[0016] A doping concentration of a first well of the second conductivity type disposed in a first epitaxial layer of the first conductivity type may be different from a doping concentration of a second well of the second conductivity type disposed in a second epitaxial layer of the first conductivity type.

[0017] A doping concentration of a first well of the second conductivity type disposed in the first epitaxial layer of the first conductivity type may be higher than a doping concentration of a second well of the second conductivity type disposed in the second epitaxial layer of the first conductivity type.

[0018] The doping concentration of the first well of the second conductivity type formed under the trench gate may have a concentration gradient that changes more steeply than the doping concentration of the second well of the second conductivity type formed adjacent to the trench gate.

[0019] The doping concentration of the first well of the second conductivity type may be 2×10 17 Up to 2×10 19 / cm 3 , the doping concentration of the second well of the second conductivity type may be 1×10 16 Up to 1×10 17 / cm 3 .

[0020] An interface may be formed between the first well of the second conductivity type disposed in the first epitaxial layer 112 a of the first conductivity type and the second well 121 b of the second conductivity type.

[0021] An interface between the first well of the second conductivity type and the second well of the second conductivity type may be disposed at substantially the same position as a lower side of the trench gate.

[0022] A first distance between first wells of the second conductivity type disposed in the first epitaxial layer of the first conductivity type may be different from a second distance between second wells of the second conductivity type disposed in the second epitaxial layer of the first conductivity type.

[0023] A first distance D1 between first wells of the second conductivity type disposed in the first epitaxial layer 112 a of the first conductivity type may be longer than a second distance D2 between second wells of the second conductivity type disposed in the second epitaxial layer 112 b of the first conductivity type.

[0024] A portion of a lower edge of the second well of the second conductivity type may not overlap up and down with the first well of the second conductivity type.

[0025] A first well of the second conductivity type may be disposed below the trench gate, and a second well of the second conductivity type may be disposed at a level with the trench gate.

[0026] The depth of the second well of the second conductivity type may be different from the depth of the first well of the second conductivity type. The depth of the second well of the second conductivity type may be lower than the depth of the first well.

[0027] In addition, a power converter according to an embodiment may include any of the above-described power semiconductor devices.

[0028] In addition, the method for manufacturing a power semiconductor device according to an embodiment may include: growing a first epitaxial layer 112a of a first conductivity type on a substrate 111, partially forming a first well 121a of a second conductivity type by implanting ions into the first epitaxial layer 112a of the first conductivity type, growing a second epitaxial layer 112b of a first conductivity type on the first epitaxial layer 112a of the first conductivity type, partially forming a second well 121b of a second conductivity type by implanting ions into the second epitaxial layer 112b of the first conductivity type, forming an ion implantation region 122 of a second conductivity type and a source region 115 in the second well 121b of the second conductivity type, forming a trench region T by removing a portion of the ion implantation region 122 of the second conductivity type and the second epitaxial layer 112b of the first conductivity type, forming a gate insulating layer 131 and a trench gate 132 in the trench region, forming an interlayer insulating layer 150 on the trench gate 132, and forming a gate electrode electrically connected to the trench gate 132.

[0029] A side surface of the second conductivity type first well 121 a and a side surface of the second conductivity type second well 121 b may be aligned upward on the substrate.

[0030] The doping concentration of the second conductivity type first well 121 a disposed in the first conductivity type first epitaxial layer 112 a may be higher than the doping concentration of the second conductivity type second well 121 b disposed in the first conductivity type second epitaxial layer 112 b .

[0031] A first distance D1 between first wells of the second conductivity type disposed in the first epitaxial layer 112 a of the first conductivity type may be longer than a second distance D2 between second wells of the second conductivity type disposed in the second epitaxial layer 112 b of the first conductivity type.

[0032] Effects of the Invention

[0033] The power semiconductor device, the power converter including the power semiconductor device, and the method for manufacturing the power semiconductor device according to the embodiment have the following technical effects: the problem of pitch reduction due to lateral dispersion can be prevented while preventing electric field concentration at the corners of the trench.

[0034] For example, the power semiconductor device 100 according to the embodiment can form a well 121 of the second conductivity type without using high-energy ion implantation. Therefore, the problem of reduced spacing due to lateral dispersion of dopants can be prevented, and the second well 121b of the second conductivity type can be set in a region deeper than the trench. As a result, the embodiment can disperse the electric field concentrated at the bottom corner of the gate trench, which has a technical effect of preventing damage to the gate insulating layer.

[0035] In addition, according to the embodiment, the doping concentration of the first well 121a of the second conductivity type formed under the trench gate 132 can be formed to be higher than the doping concentration of the second well 121b of the second conductivity type. Accordingly, since the depletion layer expands in the direction of the substrate 111, there is a technical effect of increasing the breakdown voltage. In addition, according to the embodiment, the doping concentration of the second well 121b of the second conductivity type formed around the trench gate 132 is lower than the doping concentration of the first well 121a of the second conductivity type, so there is a comprehensive technical effect of reducing the threshold voltage and increasing the current density.

[0036] Furthermore, according to the second embodiment, a first distance D1 between second conductivity type third wells 121c disposed in the first conductivity type first epitaxial layer 112a may be longer than a second distance D2 between second conductivity type second wells 121b disposed in the first conductivity type second epitaxial layer 112b.

[0037] Furthermore, according to the second embodiment, the first distance D1 between the second conductivity type third wells 121 c disposed at the lower side of the trench gate 132 can be controlled to be longer than the second distance D2 between the second conductivity type second wells 121 b formed around the trench gate 132. Therefore, there is a special technical effect of reducing Ron by expanding the moving range of electrons.

[0038] The technical effects of the embodiment are not limited to the technical effects described in this item, and include technical effects that can be understood through the description of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a diagram showing a configuration of a power converter 1000 according to an embodiment.

[0040] Figure 2 is a cross-sectional view of a power semiconductor device 100 according to an embodiment.

[0041] Figure 3 is a cross-sectional view of a power semiconductor device 100 according to an embodiment.

[0042] Figure 4 is a cross-sectional view of a power semiconductor device 102 according to a second embodiment.

[0043] Figures 5 to 11 is a cross-sectional view of a manufacturing process of the power semiconductor device 100 according to an embodiment. DETAILED DESCRIPTION

[0044] Hereinafter, embodiments are described in detail with reference to the accompanying drawings.

[0045] The suffixes "module" and "unit" of the elements used in the following description are simply given in consideration of ease of writing this specification, and they themselves do not give particularly important meanings or functions. Therefore, "module" and "unit" can be used interchangeably.

[0046] Terms including ordinal numbers (such as first and second) may be used to describe various elements, but the elements are not limited by the terms. These terms are used only for the purpose of distinguishing one element from another.

[0047] A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0048] In the present application, terms such as “includes,” “has,” or “comprising” are intended to indicate the presence of features, numbers, steps, operations, components, parts, or a combination thereof described in the specification, and do not exclude one or other features, numbers, steps, operations, components, parts, or any combination thereof.

[0049] Example

[0050] Figure 1 is an exemplary configuration diagram of a power converter 1000 according to an embodiment.

[0051] The power converter 1000 according to the embodiment may receive DC power from a battery or a fuel cell, convert the DC power into AC power, and provide the AC power to a predetermined load. For example, the power converter 1000 according to the embodiment may include an inverter that receives DC power from a battery, converts the DC power into three-phase AC power, and provides the three-phase AC power to the motor M. In some aspects, the motor M may provide power to an electric vehicle or a fuel cell vehicle.

[0052] The power converter 1000 according to the embodiment may include a power semiconductor device 100. The power semiconductor device 100 may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto, and may include an IGBT (Insulated Gate Bipolar Transistor).

[0053] For example, the power converter 1000 may include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f, and may include a plurality of diodes (not shown). Each of the plurality of diodes may be embedded in each power semiconductor device 100a, 100b, 100c, 100d, 100e, and 100f in the form of an internal diode, but is not limited thereto, and a diode may also be provided separately.

[0054] The embodiment can convert DC power into AC power by on-off control of a plurality of power semiconductor devices 100a to 100f. For example, in the power converter 1000 according to the embodiment, in a first time period of a cycle, the first power semiconductor device 100a can be turned on and the second power semiconductor device 100b can be turned off to provide positive polarity power to the motor M. In addition, in a second time period of a cycle, the first power semiconductor device 100a can be turned off and the second power semiconductor device 100b can be turned on to provide negative polarity power to the motor M.

[0055] A group of power semiconductor devices arranged in series in the high voltage line and the low voltage line on the input side may be referred to as an arm. For example, the first power semiconductor device 100a and the second power semiconductor device 100b may constitute a first arm, and the third power semiconductor device 100c and the fourth power semiconductor device 100d may constitute a second arm. The fifth power semiconductor device 100e and the sixth power semiconductor device 100f may constitute a third arm.

[0056] In an arm, the upper power semiconductor device and the lower power semiconductor device may be controlled not to be turned on at the same time. For example, in a first arm, the first power semiconductor device 100a and the second power semiconductor device 100b may not be turned on at the same time but may be turned on and off alternately.

[0057] In some embodiments, each power semiconductor device 100a to 100f can receive high power in the off state. For example, when the second power semiconductor device 100b is turned off and the first power semiconductor device 100a is turned on, the input voltage can be applied to the second power semiconductor device 100b as it is. The voltage input to the second power semiconductor device 100b can be a relatively high voltage, and the withstand voltage of each power semiconductor device 100a to 100f can be designed to have a high level to withstand such a high voltage.

[0058] Additionally, in some aspects, each power semiconductor device 100a to 100f can conduct a high current in an on state. The motor M can be driven with a relatively high current, and the high current can be provided to the motor M through the on power semiconductor devices.

[0059] The high voltage applied to each power semiconductor device 100a to 100f may cause high switching losses. The high current turned on by the power semiconductor devices 100a to 100f may cause high conduction losses. In order to dissipate the heat generated by such switching losses or conduction losses, the power semiconductor devices 100a to 100f may be packaged as a power semiconductor module including a heat sink.

[0060] In some embodiments, the power semiconductor device 100 may be a silicon carbide (SiC) power semiconductor device. In certain aspects, it may operate in a high temperature, high voltage environment and may have high switching speed and low switching loss.

[0061] In some embodiments, the power converter 1000 according to the embodiment may include a plurality of power semiconductor modules.

[0062] For example, Figure 1 The plurality of power semiconductor devices 100 a to 100 f shown may be packaged into one power semiconductor module, or the power semiconductor devices constituting each arm may be packaged into one power semiconductor module.

[0063] As another example, Figure 1 The first power semiconductor device 100 a , the second power semiconductor device 100 b , the third power semiconductor device 100 c , the fourth power semiconductor device 100 d , the fifth power semiconductor device 100 e , and the sixth power semiconductor device 100 f shown in FIG. 1 may be packaged into one power semiconductor module.

[0064] In addition, there may be an additional power semiconductor device disposed in parallel with each power semiconductor device 100a to 100f to increase current capacity. In this case, the number of power semiconductor devices included in the power semiconductor module may be greater than six.

[0065] In addition to the transistor-type power semiconductor devices 100a to 100f, the power converter 1000 according to the embodiment may also include a diode-type power semiconductor device. For example, a first diode (not shown) may be arranged in parallel with the first power semiconductor device 100a, and a second diode (not shown) may be arranged in parallel with the second power semiconductor device 100b. In addition, these diodes may be packaged together in a power semiconductor module. In addition, a diode may be arranged in each power semiconductor device in the form of an internal diode.

[0066] In some embodiments, the power semiconductor devices constituting each arm may be packaged into one power semiconductor module.

[0067] For example, the first power semiconductor device 100a and the second power semiconductor device 100b constituting the first arm may be packaged into the first power semiconductor module. The third power semiconductor device 100c and the fourth power semiconductor device 100d constituting the second arm may be packaged into the second power semiconductor module. The fifth power semiconductor device 100e and the sixth power semiconductor device 100f constituting the third arm may be packaged into the third power semiconductor module.

[0068] In addition, there may be an additional power semiconductor device arranged in parallel with each power semiconductor device 100a to 100f to increase the current capacity. In this case, the number of power semiconductor devices included in each power semiconductor module may be more than two. In addition, in addition to the transistor-type power semiconductor devices 100a to 100f, each arm may also include a diode-type power semiconductor device (not shown), and these diodes may also be packaged together in one power semiconductor module. In addition, a diode may be provided in each power semiconductor device in the form of an internal diode.

[0069] Next, Figure 2 is a cross-sectional view of a power semiconductor device 100 according to an embodiment.

[0070] The power semiconductor device 100 according to the embodiment may include a source electrode 130 , a gate electrode 175 disposed on an upper side of a predetermined semiconductor epitaxial layer 120 , and a drain electrode 105 disposed under the semiconductor epitaxial layer 120 .

[0071] In the form of MOSFET, the source electrode 130 or the gate electrode 175 may include an Al-based metal. The drain electrode 105 may include a Ti / Ni / Ag metal including a Ti layer, a Ni layer and an Ag layer, or NiV / Ag, V(vanadium) / Ni / Ag, etc., but is not limited thereto.

[0072] One technical purpose of an embodiment is to prevent electric field concentration at a trench corner and to prevent the problem of reduced cell pitch due to lateral dispersion.

[0073] Hereinafter, a power semiconductor device 100 according to an embodiment for solving the above-mentioned technical problems will be described.

[0074] Figure 3 is a cross-sectional view of a power semiconductor device 100 according to an embodiment.

[0075] First, refer to Figure 3According to the embodiment, the power semiconductor device 100 may include a drain electrode 105, a substrate 111, an epitaxial layer 112 of a first conductivity type, a well 121 of a second conductivity type, an ion implantation region 122 of a second conductivity type, a source region 115 of a first conductivity type, a source contact region 141, a contact region 123 of a second conductivity type, a source electrode 142, a gate insulating layer 131, a gate 132, and at least one of an interlayer insulating layer 150.

[0076] The first conductivity type epitaxial layer 112 may include a first conductivity type first epitaxial layer 112 a and a first conductivity type second epitaxial layer 112 b .

[0077] In addition, the second conductivity type well 121 may include a second conductivity type first well 121 a and a second conductivity type second well 121 b .

[0078] The first conductivity type may be an N type, and the second conductivity type may be a P type, but are not limited thereto. The substrate 111 and the first conductivity type epitaxial layer 112 may include silicon carbide (SiC), but are not limited thereto.

[0079] Specifically, the power semiconductor device 100 according to the embodiment may include a substrate 111 , a first conductivity type first epitaxial layer 112 a disposed on the substrate 111 , and a first conductivity type second epitaxial layer 112 b disposed on the first conductivity type first epitaxial layer 112 a .

[0080] Additionally, embodiments may include a first well 121 a of a second conductivity type partially disposed in the first epitaxial layer 112 a of the first conductivity type and a second well 121 b of the second conductivity type disposed in the second epitaxial layer 112 b of the first conductivity type.

[0081] Additionally, embodiments may include a second conductivity type ion implantation region 122 partially disposed in the second conductivity type second well 121 b , and a source region 115 and a second conductivity type contact region 123 disposed on the second conductivity type ion implantation region 122 .

[0082] In addition, the embodiment may include a source electrode 142 disposed on the source region 115 and a contact region 123 of the second conductivity type, a source electrode 142 disposed in the trench region T (refer to Fig. 9 ) on the bottom and side walls of the trench region T (a portion of the second epitaxial layer 112b of the first conductivity type and the ion implantation region 122 of the second conductivity type are removed from the trench region T), a gate 132 arranged on the gate insulating layer 131, an interlayer insulating layer 150 arranged on the trench gate 132, an interlayer insulating layer 150 arranged on the trench gate 132, and a gate electrode (not shown) electrically connected to the trench gate 132.

[0083] According to the power semiconductor device, the power converter including the same, and the method for manufacturing the power semiconductor device of the embodiment, the embodiment has the technical effect of preventing electric field concentration at the corners of the trench and preventing the pitch reduction problem caused by lateral dispersion.

[0084] The lateral dispersion may be an unintentional increase in ion implantation in the lateral direction. When the lateral dispersion occurs, there is a problem that Ron increases because the moving width of electrons becomes narrower.

[0085] To solve this problem, according to an embodiment, the power semiconductor device 100 may include a first epitaxial layer 112a of a first conductivity type and a second epitaxial layer 112b of a first conductivity type sequentially arranged on a substrate 111, and may include a first well 121a of a second conductivity type arranged in the first epitaxial layer 112a of the first conductivity type and a second well 121b of a second conductivity type arranged in the second epitaxial layer 112b of the first conductivity type.

[0086] The power semiconductor device 100 according to the embodiment may be formed by ion-implanting a first well 121a of a second conductivity type into the first epitaxial layer 112a of the first conductivity type after growing the first epitaxial layer 112a of the first conductivity type on the substrate 111. Thereafter, a second epitaxial layer 112b of the first conductivity type may be grown on the first epitaxial layer 112a of the first conductivity type, and a second well 121b of the second conductivity type may be disposed in the second epitaxial layer 112b of the first conductivity type by ion implantation.

[0087] A side surface of the second conductivity type first well 121 a and a side surface of the second conductivity type second well 121 b may be aligned upward on the substrate.

[0088] According to an embodiment, a second conductive type well 121 is formed without using high-energy ion implantation, thereby preventing the spacing reduction problem caused by lateral dispersion of dopants, and at the same time, by forming the second conductive type well 121 in a region deeper than the trench gate 132 formed later, there is a technical effect of preventing the destruction of the gate insulating layer by dispersing the electric field concentrated at the bottom corner of the gate trench.

[0089] In addition, the doping concentration of the second conductivity type first well 121a disposed in the first conductivity type first epitaxial layer 112a of the embodiment may be higher than the doping concentration of the second conductivity type second well 121b disposed in the first conductivity type second epitaxial layer 112b.

[0090] For example, according to an embodiment, there is a technical effect that a concentration gradient can be achieved in which the doping concentration of the second conductivity type first well 121a formed below the trench gate 132 changes more sharply than the doping concentration of the second conductivity type second well 121b formed adjacent to the trench gate 132.

[0091] For example, the doping concentration of the first well 121a of the second conductivity type may be 2×10 17 Up to 2×10 19 / cm 3 , the doping concentration of the second conductive type second well 121 b may be 1×10 16 Up to 1×10 17 / cm 3 , but not limited to this.

[0092] According to the embodiment, when the doping concentration of the first well 121a of the second conductivity type formed under the trench gate 132 is formed to be higher than the doping concentration of the second well 121b of the second conductivity type, there is a technical effect of increasing the breakdown voltage due to the effect of the depletion layer extending in the direction of the substrate 111. In addition, according to the embodiment, the doping concentration of the second well 121b of the second conductivity type formed around the trench gate 132 is formed to be lower than the doping concentration of the first well 121a of the second conductivity type, and there is a comprehensive technical effect of reducing the threshold voltage and increasing the current density.

[0093] Next, Figure 4 is a cross-sectional view of a power semiconductor device 102 according to a second embodiment.

[0094] The second embodiment can adopt the technical features of the previously described embodiments, and the features of the second embodiment will now be described with emphasis.

[0095] refer to Figure 4 In the power semiconductor device 102 according to the second embodiment, the first well 121 of the second conductivity type may include a third well 121c of the second conductivity type arranged in the first epitaxial layer 112a of the first conductivity type and a second well 121b of the second conductivity type arranged in the second epitaxial layer 112b of the first conductivity type.

[0096] According to the second embodiment, the third well 121c of the second conductivity type can be set in the first epitaxial layer 112a of the first conductivity type by ion implantation. Thereafter, the second well 121b of the second conductivity type can be formed in the second epitaxial layer 112b of the first conductivity type grown on the first epitaxial layer 112a of the first conductivity type by ion implantation.

[0097] At this time, a first distance D1 between the second conductivity type third wells 121c disposed in the first conductivity type first epitaxial layer 112a may be longer than a second distance D1 between the second conductivity type second wells 121b disposed in the first conductivity type second epitaxial layer 112b.

[0098] According to the second embodiment, by controlling the first distance D1 between the third wells 121c of the second conductivity type formed below the trench gate 132 to be longer than the second distance D2 between the second wells 121b of the second conductivity type formed around the trench gate 132, there is a special technical effect of reducing Ron by expanding the movement range of electrons.

[0099] Next, we will refer to Figures 5 to 11 Description based on Figure 3 The manufacturing process of the power semiconductor device 100 of the embodiment is shown.

[0100] First, refer to Figure 5 , a first epitaxial layer 112 a of a first conductivity type may be grown on the substrate 111 .

[0101] The first conductivity type first epitaxial layer 112 a may include a first conductivity type buffer layer (not shown) and a first conductivity type drift layer (not shown).

[0102] The substrate 111 and the first conductivity type first epitaxial layer 112a may include, but are not limited to, 4H-SiC material. For example, the substrate 111 and the first conductivity type first epitaxial layer 112a may include 3C-SiC or 6H-SiC.

[0103] Next, a first well 121 a of the second conductivity type may be disposed in the first epitaxial layer 112 a of the first conductivity type by ion implantation.

[0104] Next, refer to Figure 6 A second epitaxial layer 112b of the first conductivity type may be grown on the first epitaxial layer 112a of the first conductivity type. Thereafter, a second well 121b of the second conductivity type may be disposed in the second epitaxial layer 112b of the first conductivity type by ion implantation.

[0105] For example, the second conductivity type first well 121a and the second conductivity type second well 121b may be formed by forming a hard mask pattern (not shown) and ion implantation using the hard mask pattern as a mask. The second conductivity type first well 121a and the second conductivity type second well 121b may be P-type bodies, but are not limited thereto.

[0106] The hard mask pattern may include a polysilicon pattern and an oxide pattern, but is not limited thereto.

[0107] P-type dopant ions may be implanted into the second conductivity type first well 121a and the second conductivity type second well 121b. For example, Al or boron may be implanted, but is not limited thereto.

[0108] According to an embodiment, a second conductive type well 121 can be formed without using high-energy ion implantation, thereby preventing the spacing reduction problem caused by lateral dispersion of dopants, and at the same time, by forming the second conductive type well 121 in a region deeper than the trench gate 132 formed later, there is a technical effect of preventing destruction of the gate insulating layer by dispersing the electric field concentrated at the bottom corner of the gate trench.

[0109] In addition, the doping concentration of the second conductivity type first well 121a disposed in the first conductivity type first epitaxial layer 112a of the embodiment may be higher than the doping concentration of the second conductivity type second well 121b disposed in the first conductivity type second epitaxial layer 112b.

[0110] For example, according to an embodiment, there is the following technical effect: a concentration gradient can be achieved, in which the doping concentration of the second conductivity type first well 121a formed below the trench gate 132 changes more sharply than the doping concentration of the second conductivity type second well 121b formed near the trench gate 132.

[0111] For example, the doping concentration of the first well 121a of the second conductivity type may be 2×10 17 Up to 2×10 19 / cm 3 , the doping concentration of the second conductive type second well 121 b may be 1×10 16 Up to 1×10 17 / cm 3 , but not limited to this.

[0112] According to the embodiment, when the doping concentration of the first well 121a of the second conductivity type formed under the trench gate 132 is formed to be higher than the doping concentration of the second well 121b of the second conductivity type, there is a technical effect of increasing the breakdown voltage due to the effect of the depletion layer extending in the direction of the substrate 111. In addition, according to the embodiment, the doping concentration of the second well 121b of the second conductivity type formed around the trench gate 132 is formed to be lower than the doping concentration of the first well 121a of the second conductivity type, and there is a comprehensive technical effect of reducing the threshold voltage and increasing the current density.

[0113] Next, refer to Figure 7 The second conductivity type ion implantation region 122 may be formed by implanting Al or boron into the first conductivity type second epitaxial layer 112 b and the second conductivity type second well 121 b .

[0114] Next, refer to Figure 8 , the source region 115 of the first conductivity type may be formed by implanting ions into the ion implantation region 122 of the second conductivity type using an ion implantation mask having a second hard mask pattern (not shown). For example, the source region 115 of the first conductivity type may be formed by implanting ions into the ion implantation region 122 of the second conductivity type using a self-alignment method with a thickness of about 1×10 18 cm -3 About 7×10 19 cm -3 N-type dopants (such as nitrogen or phosphorus) are ion-implanted at a concentration of 1:1 to form a source region 115 of the first conductivity type.

[0115] In addition, the third hard mask pattern (not shown) may be used as an ion implantation mask to form a second conductivity type contact region 123. The second conductivity type contact region 123 may be used to maintain a zero potential of the second conductivity type ion implantation region 122 and may function as a body diode.

[0116] Next, refer to Fig. 9 , a trench region T may be formed by partially removing the first conductivity type source region 115 , the second conductivity type ion implantation region 122 , and the first conductivity type second epitaxial layer 112 b using a predetermined hard mask pattern (not shown) as a mask.

[0117] Next, refer to Fig.10 , the gate insulating layer 131 may be disposed in the trench region T, and the trench gate 132 may be disposed on the gate insulating layer 131 .

[0118] The gate insulating layer 131 may be a thermal oxide film or an oxide film deposited using LPCVD, but is not limited thereto. The trench gate 132 may be formed of polysilicon, but is not limited thereto.

[0119] Then, the source contact 141 may be formed. For example, the source contact 141 may be formed using Ti or Ni, but is not limited thereto.

[0120] Alternatively, the drain electrode 105 may be provided on the substrate 111 using Ti / Al.

[0121] Next, refer to Fig.11 , an interlayer insulating layer 150 may be disposed on the trench gate 132 and the gate insulating layer 131 , and a source electrode 142 may be disposed on the interlayer insulating layer 150 and the source contact 141 .

[0122] The interlayer insulating layer 150 may be formed of an oxide film or a nitride film, but is not limited thereto.

[0123] The source electrode 142 may be formed of Al, but is not limited thereto. In addition, the source electrode 142 may further include a barrier metal layer.

[0124] The power semiconductor device, the power converter including the power semiconductor device, and the method for manufacturing the power semiconductor device according to the embodiment have the following technical effects: the problem of pitch reduction due to lateral dispersion can be prevented while preventing electric field concentration at the corners of the trench.

[0125] For example, the power semiconductor device 100 according to the embodiment can form a well 121 of the second conductivity type without using high-energy ion implantation. Therefore, the problem of spacing reduction caused by lateral dispersion of dopants can be prevented, and the second well 121b of the second conductivity type can be set in a region deeper than the trench. As a result, the embodiment can disperse the electric field concentrated at the bottom corner of the gate trench, which has a technical effect of preventing the destruction of the gate insulating layer.

[0126] In addition, according to the embodiment, the doping concentration of the first well 121a of the second conductivity type formed under the trench gate 132 can be formed to be higher than the doping concentration of the second well 121b of the second conductivity type. Therefore, since the depletion layer expands in the direction of the substrate 111, there is a technical effect of increasing the breakdown voltage. In addition, according to the embodiment, since the doping concentration of the second well 121b of the second conductivity type formed around the trench gate 132 is lower than the doping concentration of the first well 121a of the second conductivity type, there is a comprehensive technical effect of reducing the threshold voltage and increasing the current density.

[0127] Furthermore, according to the second embodiment, a first distance D1 between second conductivity type third wells 121c disposed in the first conductivity type first epitaxial layer 112a may be longer than a second distance D2 between second conductivity type second wells 121b disposed in the first conductivity type second epitaxial layer 112b.

[0128] Furthermore, according to the second embodiment, the first distance D1 between the second conductivity type third wells 121 c disposed at the lower side of the trench gate 132 can be controlled to be longer than the second distance D2 between the second conductivity type second wells 121 b formed around the trench gate 132. Therefore, there is a special technical effect of reducing Ron by expanding the moving range of electrons.

[0129] Hereinabove, the present invention has been described with reference to the embodiments, and those skilled in the art will easily appreciate that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims

1. A power semiconductor device, comprising: substrate; A first epitaxial layer of a first conductivity type disposed on the substrate; a second epitaxial layer of the first conductivity type disposed on the first epitaxial layer of the first conductivity type; a first well of a second conductivity type partially disposed in the first epitaxial layer of the first conductivity type; a second well of the second conductivity type disposed in the second epitaxial layer of the first conductivity type; an ion implantation region and a source region of the second conductivity type disposed in the second well of the second conductivity type; a source electrode disposed on the source region; a gate insulating layer in a trench region from which the ion implantation region of the second conductivity type and a portion of the second epitaxial layer of the first conductivity type are removed; A trench gate disposed on the gate insulating layer; An interlayer insulating layer disposed on the trench gate; and A gate electrode is electrically connected to the trench gate.

2. The power semiconductor device according to claim 1, wherein: A side surface of the first well of the second conductivity type is aligned upward on the substrate with a side surface of the second well of the second conductivity type.

3. The power semiconductor device according to claim 1, wherein: A doping concentration of the first well of the second conductivity type disposed in the first epitaxial layer of the first conductivity type is higher than a doping concentration of the second well of the second conductivity type disposed in the second epitaxial layer of the first conductivity type.

4. The power semiconductor device according to claim 1, wherein: An interface is provided between the first well of the second conductivity type and the second well of the second conductivity type.

5. The power semiconductor device according to claim 4, wherein: A first distance between the first wells of the second conductivity type in the first epitaxial layer of the first conductivity type and a second distance between the second wells of the second conductivity type in the second epitaxial layer of the first conductivity type are different from each other.

6. The power semiconductor device according to claim 5, wherein: The first distance between the first wells of the second conductivity type in the first epitaxial layer of the first conductivity type is greater than the second distance between the second wells of the second conductivity type in the second epitaxial layer of the first conductivity type.

7. The power semiconductor device according to claim 6, wherein: A portion of a lower edge of the second well of the second conductivity type is configured not to vertically overlap with the first well of the second conductivity type.

8. The power semiconductor device according to claim 1, wherein: The first well of the second conductivity type is arranged below the trench gate, and the second well of the second conductivity type is arranged at a horizontal position of the trench gate.

9. The power semiconductor device according to claim 8, wherein: The second well of the second conductivity type has a depth lower than the first well of the second conductivity type. 10 . A power converter comprising the power semiconductor device according to claim 1 .

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