High-power gallium oxide enhancement transistor and its fabrication method

Abstract

This invention discloses a high-power figure of merit (HPF) gallium oxide (Ga2O3) enhancement-mode transistor and its fabrication method, primarily addressing the difficulty in achieving enhancement-mode characteristics in existing gallium oxide devices and realizing a Ga2O3 enhancement-mode field-effect transistor with high HPF. The device fabrication scheme involves sequentially growing an unintentionally doped gallium oxide layer and a gallium oxide channel layer on a gallium oxide substrate using MOCVD; and selectively growing p-type NiO in a region below the gate. X Then, gate metal is deposited; source, drain electrodes, and gate dielectric layers are sequentially fabricated on the gallium oxide channel layer, and finally, SiN is fabricated. x The passivation layer and field plate structure complete the fabrication of gallium oxide enhancement-mode transistor devices. In this invention, half of the gate metal is located in NiO. X Above, half lies directly above the β-Ga2O3 layer, forming a Schottky junction between the metal and gallium oxide and NiO. X The PN junction between the transistor and gallium oxide. Both junctions simultaneously regulate the channel, thereby effectively improving the power figure of merit of the gallium oxide enhancement-mode field-effect transistor.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, and specifically relates to a gallium oxide enhancement transistor that can be used as a power electronic device. Background Technology

[0002] Due to the ultra-wide bandgap and high breakdown field strength of Ga2O3 crystal material, power devices made from Ga2O3 exhibit high voltage withstand capability and high power, making them promising for applications in power electronics. However, since high-quality P-type doping of gallium oxide is still not achievable, current methods for achieving enhancement-mode performance in Ga2O3-based power MOSFETs typically involve using high-k materials as the dielectric layer, reducing channel thickness through under-gate etching, or forming a PN junction using a heterojunction structure. While these methods can achieve enhancement-mode operation, the depletion of channel electrons significantly increases the on-resistance of the device. Power figure of merit (PFP) is a key indicator for evaluating the applicability of power devices in power electronic systems. Improving PFP requires devices to possess both high breakdown voltage and low on-resistance. Therefore, the compatibility between breakdown voltage and on-resistance is currently a major technical challenge for Ga2O3-based enhancement-mode power devices; and fabricating Ga2O3 enhancement-mode MOSFETs with high PFP remains a significant difficulty and challenge for Ga2O3 power devices.

[0003] Patent document CN116053312A discloses a P-type gate-enhanced gallium oxide-based current aperture vertical electron transistor (CAVET) device and its fabrication method. The device has a P-type semiconductor layer below the gate, which forms a PN junction with the channel layer. The channel layer electrons are depleted to achieve enhancement. However, as a vertical device, its structure is relatively complex and difficult to fabricate, resulting in high production costs in actual industrial applications and certain disadvantages in large-scale applications.

[0004] Patent document CN117790575A discloses a vertical-type ring-gate field-effect transistor based on a gallium oxide substrate and its fabrication method. The device adopts a columnar channel, with the gate dielectric and gate metal surrounding the channel in a ring shape, which increases the contact area between the gate and the channel, thereby improving the gate control capability. However, since the device has no heterojunction structure, it is difficult to achieve enhancement mode by relying solely on the work function difference between the gate metal and the channel semiconductor, which limits its application scenarios in real-world applications. Summary of the Invention

[0005] The purpose of this invention is to provide a gallium oxide enhancement-mode transistor with high power figure of merit and its fabrication method, so as to solve the technical problems of existing Ga2O3 power transistors having complex structures, high fabrication difficulty, low power figure of merit, and difficulty in achieving enhancement mode.

[0006] To achieve the above objectives, the technical solution of the present invention includes the following:

[0007] 1. A high-power-performance gallium oxide enhancement-mode transistor, comprising an insulating substrate, a barrier layer, a channel layer, and a p-type NiO layer. X Layer, dielectric layer, passivation layer, source, gate, drain and source field plate, characterized in that:

[0008] The gate is provided with two regions, left and right, below it;

[0009] The P-type NiO X The layer is located in the right region of the gate;

[0010] The channel layer is located in the left region of the gate and the P-type NiO. X Below the layer, and in direct contact with both of them, it is respectively in contact with P-type NiO. X The layer forms a PN junction and a Schottky junction with the left region, so as to simultaneously control the channel.

[0011] Furthermore, the insulating substrate, barrier layer, and channel layer are distributed from bottom to top, wherein:

[0012] The substrate may be made of insulating β-Ga2O3 with a crystal orientation of (010), (100), (001), or (-201); the barrier layer may be made of unintentionally doped β-Ga2O3 with a thickness of 100–700 nm and a carrier concentration of 1 × 10⁻⁶. 14 cm -3 ~1×10 16 cm -3 The channel layer is made of β-Ga₂O₃, has a thickness of 100–700 nm, and a doping concentration of 1 × 10⁻⁶. 16 cm -3 ~1×10 19 cm -3 ;

[0013] Furthermore, the P-type NiO X The layer is located above the channel layer, with a thickness of 40–100 nm, a length of 1–9 μm, and a carrier concentration of 1 × 10⁻⁶. 18 cm -3 ~5×10 20 cm -3 ;

[0014] The dielectric layer is located between the channel layer and the P-type NiO. X Above the dielectric layer, the material is Al2O3 or HfO2, with a thickness of 10–30 nm; the passivation layer, located above the dielectric layer, has a thickness of 50–300 nm and is made of SiN. x It could be either SiO2 or Al2O3.

[0015] Furthermore, the source and drain are located on opposite sides above the channel layer, and are made of a metal stack Ti / Au with thicknesses of 20 / 200 nm, respectively; the gate is located between the source and drain, and is relatively close to the source, and is made of a metal stack Ni / Au with thicknesses of 45 / 400 nm, respectively; the source field plate is located above the passivation layer and is connected to the source.

[0016] 2. A method for fabricating a gallium oxide enhancement-mode transistor with high power figure of merit, comprising the following steps:

[0017] 1) An unintentionally doped β-Ga2O3 barrier layer (2) with a thickness of 100–700 nm is grown on a β-Ga2O3 insulating substrate (1) using a metal-organic chemical vapor deposition (MOCVD) apparatus; on the barrier layer (2), a layer with a thickness of 100–700 nm and a doping concentration of 1 × 10⁻⁶ is grown on top of the barrier layer (2) using an MOCVD process. 16 ~1×10 19 cm -3 Si-doped β-Ga2O3 channel layer (3);

[0018] 2) The middle region of the channel layer (3) is thinned by ICP dry etching, and its remaining thickness is less than 50 nm;

[0019] 3) Inject Si ions into the regions above the thinned channel on both sides to form a heavily doped layer, and deposit a Ti / Au stack with a thickness of 20 / 200nm as the source (7) and drain (9) metals;

[0020] 4) A layer with a carrier concentration of 1×10⁻⁶ is sputtered between the source (7) and drain (9) above the thinned channel using a sputtering device. 18 ~5×10 20 cm -3 P-type NiO with a thickness of 40–100 nm and a length of 1–9 μm X Layer (4);

[0021] 5) In part of the channel layer (3) and NiO X (4) A Ni / Au stack with a thickness of 45 / 400 nm is deposited on top as the gate metal (8), which covers a portion of NiO. X The length of layer (4) is 0.5–5 μm;

[0022] 6) Using an ALD device, in the channel layer (3) not covered by the gate metal (8) and P-type NiO XAn Al2O3 or HfO2 layer with a thickness of 10–30 nm is grown on top of layer (4) as the dielectric layer (5). Then, a SiN layer with a thickness of 50–300 nm is grown on the surface of the dielectric layer using a plasma-enhanced chemical vapor deposition (PECVD) device. x Or SiO2 or Al2O3 as passivation layer (6);

[0023] 7) Using an ICP device, etch away the dielectric layer (5) and passivation layer (6) above the source (7), gate (8), and drain (9) to expose the metal electrodes;

[0024] 8) Deposit metal Au on the side of the passivation layer (6) near the source electrode (7) and connect it with the source electrode metal to form a field plate structure (10). Finally, deposit interconnect metal to complete the device fabrication.

[0025] Compared with the prior art, the present invention has the following advantages:

[0026] Firstly, the present invention combines a Schottky junction with a heterojunction in the lower gate portion, which can effectively increase the current density of the device while achieving enhancement mode, thereby reducing the on-resistance of the device.

[0027] Secondly, this invention uses P-type NiO X An extension located below the gate and near the drain can form a field termination structure, effectively improving the breakdown voltage while realizing an enhancement-mode device.

[0028] Third, compared with vertical enhancement devices, the present invention effectively reduces manufacturing costs. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the overall structure of the device of the present invention;

[0030] Figure 2 This is a schematic diagram of the manufacturing process of the device of the present invention. Detailed Implementation

[0031] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] Reference Figure 1 The device of the present invention includes a β-Ga2O3 insulating substrate 1, an unintentionally doped β-Ga2O3 barrier layer 2, a Si-doped β-Ga2O3 channel layer 3, and a P-type NiO layer. X Layer 4, dielectric layer 5, passivation layer 6, Ti / Au source 7, Ni / Au gate 8, Ti / Au drain 9, source field plate 10. Wherein:

[0033] The bottom layer is a β-Ga2O3 insulating substrate 1, and above the substrate is an undoped β-Ga2O3 barrier layer 2 with a thickness of 100-700 nm;

[0034] The β-Ga2O3 channel layer 3 is located above the barrier layer, with a thickness of 100–700 nm and a doping concentration of 1 × 10⁻⁶. 16 cm -3 ~1×10 19 cm -3 ;

[0035] The P-type NiO X Layer 4 is located above the channel layer near the drain end, with a thickness of 40–100 nm and a p-type carrier concentration of 1 × 10⁻⁶. 18 cm -3 ~5×10 20 cm -3 ;

[0036] The dielectric layer 5 is located above the channel layer and has a thickness of 10–30 nm.

[0037] The passivation layer 6 is located above the dielectric layer 5 and has a thickness of 50–300 nm.

[0038] The source electrode 7 and drain electrode 9 are located on both sides above the channel layer 3, and both adopt Ti / Au metal stack with thicknesses of 20 / 200nm respectively.

[0039] The gate 8 is located in P-type NiO. X Above layer 4 and β-Ga2O3 channel layer 3, the thicknesses of the Ni / Au metal stack are 45 / 400 nm, respectively.

[0040] The source field plate 10 is located above the passivation 6 and is connected to the source metal 7.

[0041] Reference Figure 2 The present invention provides the following three embodiments for fabricating the above-mentioned device:

[0042] Example 1: A passivation layer material of SiN was prepared on an Fe-doped (010) oriented insulating β-Ga2O3 substrate. x The dielectric layer material is Al2O3, the barrier layer thickness is 100nm, and the P-type NiO is used. X A gallium oxide enhancement transistor with a layer length of 1μm and a channel layer thickness of 100nm.

[0043] Step 1, epitaxial material growth.

[0044] On a Fe-doped insulating β-Ga2O3 substrate with a (010) crystal orientation, an unintentionally doped β-Ga2O3 barrier layer with a thickness of 100 nm was grown using MOCVD process under the following conditions: reaction chamber temperature of 700 °C, pressure of 40 mba, oxygen source of high purity oxygen, gallium source of TEGa, carrier gas of argon, and TEGa to O2 molar flow ratio of 1:5000.

[0045] Above the barrier layer, using MOCVD technology, a Si-doped β-Ga₂O₃ channel layer with a thickness of 100 nm and a doping concentration of 1 × 10⁻⁶ is grown under the following conditions: reaction chamber temperature of 700 °C, pressure of 40 mbar, oxygen source of high purity, gallium source of TEGa, doping source of silane, carrier gas of argon, TEGa to O₂ molar flow rate of 1:5000, and silane molar flow rate of 50 μmol / min. 19 cm -3 .

[0046] Step 2: Etching of the channel layer and fabrication of the source and drain electrodes.

[0047] 2.1) Using an ICP device, selective etching is performed in the middle region of the channel, with an etching depth of 50 nm or more;

[0048] 2.2) Si ions are implanted on both sides above the Si-doped β-Ga2O3 channel to reduce ohmic contact resistance. The process conditions are: Si ions implanted, implantation angle of 6°, beam current of 25 mA, and implantation concentration of 10. 21 cm -3 Source and drain metals were deposited using an electron beam evaporation stage. The metals used were Ti / Au, with thicknesses of 20 / 200 nm, respectively.

[0049] 2.3) Perform rapid thermal annealing in an annealing furnace at 450℃ in an N2 atmosphere for 30s to alloy the source and drain metals, thus completing the fabrication of the source and drain electrodes.

[0050] Step 3, NiO X Deposition and gate fabrication.

[0051] 3.1) A 40 nm thick, 1 μm long material with a carrier concentration of 5 × 10⁻⁶ was prepared by sputtering using a sputtering device. 20 cm -3 P-type NiO X The process conditions for the layer are as follows: first, the vacuum of the Sputter equipment is broken, the cleaned sample is sent into its chamber, and NiO is placed inside. X The target material is then used, and the chamber is evacuated to a vacuum. The temperature is set to room temperature, the power to be 100W, and the ratio of Ar to O2 to be 10:1.

[0052] 3.2) In the channel layer and NiOX A Ni / Au stack is deposited on top as the gate metal, and the gate metal is covered by a 0.5 μm thick NiO layer. X The remaining gate portion directly covers the Ga2O3 channel;

[0053] 3.3) An Al2O3 dielectric layer with a thickness of 10 nm was grown using an ALD (Al₂O₃) apparatus. The process conditions were as follows: First, the sample was placed in the chamber of the ALD apparatus, with the chamber pressure set to 0.1 torr and the temperature to 150 °C. Trimethylaluminum was selected as the precursor, and trimethylaluminum, nitrogen, H₂O, and nitrogen were sequentially introduced into the chamber. This step was repeated 100 times. Simultaneously, SiN was grown using a PECVD (Pure Chemical Vapor Deposition) apparatus. x The passivation layer has a thickness of 50 nm.

[0054] Step 4, fabrication of interconnecting metal and field plate.

[0055] 4.1) Using an ICP device, the SiN above the gate, source, and drain metals is... x The layer and the Al2O3 dielectric layer were completely etched away;

[0056] 4.2) Ti / Au metals were deposited sequentially using an electron beam evaporation stage, with thicknesses of 20 / 400 nm, respectively, and the interconnect technology and field plate fabrication were completed by stripping.

[0057] Example 2: A passivation layer of SiO2 and a dielectric layer of HfO2 were prepared on an Fe-doped (100) oriented insulating β-Ga2O3 substrate. The barrier layer thickness was 500 nm. P-type NiO was then added. X A gallium oxide enhancement-mode transistor with a layer length of 5μm and a channel layer thickness of 500nm.

[0058] Step A: Epitaxial material growth.

[0059] On a Fe-doped insulating β-Ga2O3 substrate with (100) crystal orientation, an unintentionally doped β-Ga2O3 barrier layer with a thickness of 500 nm was grown using MOCVD process under the following conditions: reaction chamber temperature of 800 °C, pressure of 120 mba, oxygen source of high purity oxygen, gallium source of TEGa, carrier gas of argon, and molar flow ratio of TEGa to O2 of 1:3000.

[0060] On top of the barrier layer, using MOCVD technology, under the following conditions: reaction chamber temperature of 800℃, pressure of 120 mba, oxygen source of high purity, gallium source of TEGa, doping source of silane, carrier gas of argon, TEGa to O2 molar flow rate ratio of 1:3000, and silane molar flow rate of 28 μmol / min, a layer with a thickness of 500 nm and a doping concentration of 5 × 10⁻⁶ was grown. 17 cm -3The Si-doped β-Ga2O3 channel layer.

[0061] Step B: Channel layer etching and source / drain fabrication.

[0062] B1) Using ICP equipment, selective etching is performed in the middle region of the channel layer, with an etching depth of 450nm and above;

[0063] B2) Si ions are implanted on both sides of the Si-doped β-Ga2O3 channel to reduce the ohmic contact resistance. The process conditions are: Si ions implanted, implantation angle of 7°, beam current of 20 mA, and implantation concentration of 10. 20 cm -3 Source and drain metals were deposited using an electron beam evaporation stage. The metals used were Ti / Au, with thicknesses of 20 / 200 nm, respectively.

[0064] B3) Perform rapid thermal annealing in an annealing furnace at 450°C in an N2 atmosphere for 30 seconds to alloy the source and drain metals, thus completing the fabrication of the source and drain electrodes.

[0065] Step C, NiO X Deposition and gate fabrication.

[0066] C1) A 70 nm thick, 5 μm long material with a carrier concentration of 1 × 10⁻⁶ was prepared by sputtering using a sputtering device. 19 cm -3 P-type NiO X The process conditions are as follows: First, the vacuum of the Sputter equipment is broken, and the cleaned sample is sent into its chamber. NiO is then placed inside. X The target material is then evacuated to a vacuum, the temperature is set to room temperature, the power is 150W, and the ratio of Ar to O2 is 10:2.

[0067] C2) In the channel layer and NiO X A Ni / Au stack is deposited on top as the gate metal, which is covered by a 2.5 μm thick NiO layer. X The remaining gate portion directly covers the Ga2O3 channel;

[0068] C3) Using an ALD (Alternating Current Deposition) apparatus, a 20 nm thick HfO2 dielectric layer was grown on the surface. The process conditions were as follows: the sample was first placed in the chamber of the ALD apparatus, the chamber pressure was set to 0.3 torr, and the temperature was set to 300 °C. Tetra(dimethylamino)hafnium was selected as the precursor, and tetra(dimethylamino)hafnium, nitrogen, H2O, and nitrogen were sequentially introduced into the chamber. This step was repeated 400 times. At the same time, a 200 nm thick SiO2 passivation layer was grown using a PECVD (Pure Chemical Vapor Deposition) apparatus.

[0069] Step D: Fabrication of interconnecting metal and field plate.

[0070] D1) Using an ICP device, completely etch away the SiO2 layer and HfO2 dielectric layer above the gate, source and drain metals;

[0071] D2) Ti / Au metals were deposited sequentially using an electron beam evaporation stage, with thicknesses of 20 / 400 nm, respectively, and the interconnect technology and field plate fabrication were completed by stripping.

[0072] Example 3: A passivation layer material of SiN was prepared on an Fe-doped (001) oriented insulating β-Ga2O3 substrate. x The dielectric layer material is HfO2, the barrier layer thickness is 700nm, and the P-type NiO is used. X A gallium oxide enhancement transistor with a layer length of 9μm and a channel layer thickness of 700nm.

[0073] Step 1: Epitaxial material growth.

[0074] On a Fe-doped insulating β-Ga2O3 substrate with a (001) crystal orientation, an unintentionally doped β-Ga2O3 barrier layer with a thickness of 700 nm was grown using MOCVD process under the following conditions: reaction chamber temperature of 900 °C, pressure of 200 mba, oxygen source of high purity oxygen, gallium source of TEGa, carrier gas of argon, and molar flow ratio of TEGa to O2 of 1:200.

[0075] Above the barrier layer, a Si-doped β-Ga₂O₃ channel layer with a thickness of 700 nm and a doping concentration of 1 × 10⁻⁶ was grown using MOCVD under the following conditions: reaction chamber temperature of 900 °C, pressure of 200 mbar, oxygen source of high purity, gallium source of TEGa, doping source of silane, carrier gas of argon, TEGa to O₂ molar flow rate of 1:200, and silane molar flow rate of 5 μmol / min. 16 cm -3 .

[0076] Step two: etching the channel layer and fabricating the source and drain electrodes.

[0077] Using ICP equipment, selective etching is performed in the middle region of the channel, with an etching depth of 650nm and above;

[0078] Si ions were implanted above a Si-doped β-Ga₂O₃ channel to reduce ohmic contact resistance. The process conditions were: Si ions implanted, implantation angle 8°, beam current 15mA, and implantation concentration 10. 19 cm -3 Source and drain metals were deposited using an electron beam evaporation stage. The metals used were Ti / Au, with thicknesses of 20 / 200 nm, respectively.

[0079] The source and drain metals are alloyed by rapid hot annealing in an N2 atmosphere at 450°C for 30 seconds in an annealing furnace, thus completing the fabrication of the source and drain electrodes.

[0080] Step 3, NiO X Deposition and gate fabrication.

[0081] A 100 nm thick, 9 μm long substrate with a carrier concentration of 1 × 10⁻⁶ was prepared by sputtering using a sputtering device. 18 cm -3 P-type NiO X The process conditions for the layer are as follows: first, the vacuum of the Sputter equipment is broken, the cleaned sample is sent into its chamber, and NiO is placed inside. X The target material is then evacuated to a vacuum, the temperature is set to room temperature, the power is 200W, and the ratio of Ar to O2 is 10:3.

[0082] In the channel layer and NiO X A Ni / Au stack is deposited on top as the gate metal, which is covered by a 4.5 μm thick NiO layer. X The remaining gate portion directly covers the Ga2O3 channel;

[0083] Using an ALD (Alternating Current Deposition) apparatus, a 30 nm thick HfO2 dielectric layer was grown on the surface. The process conditions were as follows: first, the sample was placed in the ALD chamber, with the chamber pressure set to 0.5 torr and the temperature to 450 °C. Tetra(dimethylamino)hafnium was selected as the precursor, and tetra(dimethylamino)hafnium, nitrogen, H2O, and nitrogen were sequentially introduced into the chamber, repeating this step 700 times. Simultaneously, SiN was grown using a PECVD (Pure Chemical Vapor Deposition) apparatus. x The passivation layer has a thickness of 300 nm.

[0084] Step 4: Fabrication of interconnecting metal and field plates.

[0085] Using ICP equipment, SiN is deposited on the metals above the gate, source, and drain. x The layer and HfO2 dielectric layer were completely etched away;

[0086] Ti / Au metals were sequentially deposited using an electron beam evaporation stage, with thicknesses of 20 / 400 nm, respectively, and the interconnect technology and field substrate fabrication were completed by stripping.

[0087] The above descriptions are merely three specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and details without departing from the principles and structure of the present invention. For example, the source and drain ohmic electrodes may be Ti / Al / Ni / Au metal stacks in addition to Ti / Au metal stacks; the insulating β-Ga2O3 substrate may be Fe-doped in addition to Mg-doped. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a gallium oxide enhancement-mode transistor with high power figure of merit, comprising the following steps: 1) An unintentionally doped β-Ga2O3 barrier layer (2) with a thickness of 100~700 nm was grown on a β-Ga2O3 insulating substrate (1) using metal-organic chemical vapor deposition (MOCVD); on the barrier layer (2), a layer with a thickness of 100~700 nm and a doping concentration of 1×10⁻⁶ was grown on top of the barrier layer (2) using MOCVD. 16 ~1×10 19 cm -3 Si-doped β-Ga2O3 channel layer (3); 2) The middle region of the channel layer (3) is thinned by ICP dry etching, and its remaining thickness is less than 50 nm; 3) Inject Si ions into the regions above the thinned channel on both sides to form a heavily doped layer, and deposit a Ti / Au stack with a thickness of 20 / 200 nm as the source (7) and drain (9) metals; 4) A layer with a doping concentration of 1×10⁻⁶ is sputtered between the source (7) and drain (9) above the thinned channel using a sputtering device. 18 ~5×10 20 cm -3 P-type NiO with a thickness of 40~100 nm and a length of 1~9 μm X Layer (4); the NiO X Layer (4) is located in the middle region of the channel layer; 5) In part of the channel layer (3) and NiO X (4) A Ni / Au stack with a thickness of 45 / 400 nm is deposited on top as the gate metal (8), the gate metal and NiO X (4) Direct contact, and with NiO X In layer (4), a portion of the channel layer on the source side directly forms a Schottky contact; the gate metal covers a portion of the NiO. X The length of layer (4) is 0.5~5 μm; 6) Using an ALD device, in the channel layer (3) not covered by the gate metal (8) and P-type NiO X An Al2O3 or HfO2 layer with a thickness of 10-30 nm is grown on top of layer (4) as a dielectric layer (5). Then, a SiN layer with a thickness of 50-300 nm is grown on the surface of the dielectric layer using a plasma-enhanced chemical vapor deposition (PECVD) device. x Or SiO2 or Al2O3 as passivation layer (6); 7) Using an ICP device, the passivation layer (6) above the source electrode (7) is etched away to expose the metal electrode; 8) Deposit metal Au on the side of the passivation layer (6) near the source (7) and connect it with the source metal to form a field plate structure (10). Finally, deposit interconnect metal to complete the device fabrication.

2. The method according to claim 1, characterized in that, In step 1), an unintentionally doped β-Ga2O3 barrier layer (2) is grown on the substrate (1) using the MOCVD method. The process conditions are as follows: The reaction chamber temperature is 700~900 ℃, and the pressure is 40 mba~200 mba; The oxygen source is high-purity oxygen, the gallium source is TEGa, and the carrier gas is argon. The molar flow ratio of TEGa to O2 is 1:5000~1:

200.

3. The method according to claim 1, characterized in that, In step 1), a Si-doped β-Ga2O3 channel layer (3) is grown above an unintentionally doped β-Ga2O3 barrier layer (2) using the MOCVD method. The process conditions are as follows: The reaction chamber temperature is 700~900℃, and the pressure is 40 mba~200 mba; The oxygen source is high-purity oxygen, the gallium source is TEGa, the doping source is silane, and the carrier gas is argon. The molar flow ratio of TEGa to O2 is 1:5000~1:200, and the molar flow rate of silane is 5~50 μmol / min.

4. The method according to claim 1, characterized in that... In step 3), Si ion implantation is performed on both sides above the thinned channel, and the process conditions are as follows; The implanted ion is Si. The injection angle is 6~8°. The beam current is 15~25 mA. Injection concentration of 10 19 ~10 21 cm -3 .

5. The method according to claim 1, characterized in that, In step 4), a layer of P-type NiO is sputtered in a portion of the area above the thinned channel using a sputtering device. X The layer is implemented as follows: The vacuum in the Sputter apparatus was broken, and the cleaned sample was sent into its chamber, where NiO was placed. X Target material; The chamber was then evacuated to a vacuum, the temperature was set to room temperature, the power to be 100-200 W, and the Ar to O2 ratio to be 10:1-10:

3. A layer with a thickness of 40-100 nm, a length of 1-9 μm, and a p-type carrier concentration of 1×10⁻⁶ was grown by sputtering. 18 ~5×10 20 cm -3 NiO X layer.

6. The method according to claim 1, characterized in that: In step 6), an ALD atomic layer deposition apparatus is used to deposit P-type NiO in the channel layer. X Al2O3 or HfO2 is deposited on top of the layer to achieve the following: 6a) Place the sample in the chamber of the ALD device, and set the pressure of the chamber to 0.1~0.5 torr and the temperature to 150~450 ℃; 6b) Select trimethylaluminum or tetra(dimethylamino)hafnium as the precursor, and sequentially introduce trimethylaluminum or tetra(dimethylamino)hafnium, nitrogen, H2O, and nitrogen into the chamber; 6c) Repeat step 6b) 100-700 times, using atomic layer deposition to deposit P-type NiO into the channel layer. X An Al2O3 or HfO2 dielectric layer with a thickness of 10nm~30nm is grown on top of the layer.

7. A high-power figure-of-effect gallium oxide enhancement-mode transistor prepared by the method according to claim 1, comprising an insulating substrate (1), a barrier layer (2), a channel layer (3), and a p-type NiO layer. X Layer (4), dielectric layer (5), passivation layer (6), source (7), gate (8), drain (9) and source field plate (10), characterized in that: The gate (8) has two regions, left and right, below it; The P-type NiO X Layer (4) is located in the right region of gate (8); The channel layer (3) is located in the left region of the gate (8) and the P-type NiO. X Below layer (4), and in direct contact with both of them, respectively with P-type NiO X Layer (4) forms a PN junction and a Schottky junction with the left region to simultaneously control the channel.

8. The transistor according to claim 7, characterized in that: The insulating substrate (1), barrier layer (2), and channel layer (3) are distributed from bottom to top, wherein: The substrate (1) may be made of insulating β-Ga2O3 with crystal orientations of (010), (100), (001) or (-201); The barrier layer (2) is made of unintentionally doped β-Ga2O3, with a thickness of 100~700 nm and a carrier concentration of 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3 ; The channel layer (3) is made of β-Ga2O3, has a thickness of 100~700 nm, and a doping concentration of 1×10⁻⁶. 16 cm -3 ~1×10 19 cm -3 .

9. The transistor according to claim 7, characterized in that: The P-type NiO X Layer (4) is located above channel layer (3), with a thickness of 40~100 nm, a length of 1~9 μm, and a doping concentration of 1×10⁻⁶. 18 cm -3 ~5×10 20 cm -3 ; The dielectric layer (5) is located between the channel layer (3) and the P-type NiO. X Above layer (4), the material is Al2O3 or HfO2, with a thickness of 10~30 nm; The passivation layer (6) is located above the dielectric layer (5), and has a thickness of 50~300 nm. The material is SiN. x It could be either SiO2 or Al2O3.

10. The transistor according to claim 7, characterized in that: The source (7) and drain (9) are located on both sides above the channel layer (3), and the material is a metal stack Ti / Au with thicknesses of 20 / 200 nm respectively. The gate (8) is located between the source (7) and the drain (9) and is relatively close to the source (7). Its material is a metal stack Ni / Au with thicknesses of 45 / 400nm respectively. The source field plate (10) is located above the passivation layer (6) and is connected to the source (7).

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