Manufacturing method of semiconductor device and semiconductor device

Abstract

The invention discloses a manufacturing method of a semiconductor device and the semiconductor device, and the method comprises the steps: providing a semiconductor substrate which comprises a substrate and a gate structure formed on the substrate; an isolation side wall layer is formed, the isolation side wall layer covers the two sides of the gate structure, the isolation side wall layer comprises at least one oxide layer and at least two nitride layers, the distance from the first nitride layer to the gate structure is smaller than the distance from the second nitride layer to the gate structure, and the etching rate of the first nitride layer is smaller than that of the second nitride layer. According to the invention, the isolation side wall layers are formed on the two sides of the gate structure on the substrate, each isolation side wall layer comprises at least one oxidation layer and at least two nitridation layers, the removal process of the second nitridation layer can be realized without using a low-temperature phosphoric acid machine, the cost is reduced, and the first nitridation layer is reserved, so that the yield of the device is improved. Therefore, the uniformity of ion implantation can be ensured, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] In semiconductor technology, in order to protect some structures that need to be protected during the manufacturing process of semiconductor devices, a sidewall structure is usually formed for protection; the existing sidewall structure is usually an ON (Oxide-Nitride) structure, that is, an OX / NIT (Oxide-Nitride) structure, that is, a sidewall structure composed of an oxide layer and a nitride layer.

[0003] The researchers of this application found that in the 2X node, the sidewall structure usually uses an OX / NIT (Oxide-Nitride) structure to protect the LDD (Lightly Doped Drain) structure to prevent heavily doped source and drain ions from being injected into the extended area of ​​the LDD structure. And because the sidewalls of the 2X node are relatively small, a low-temperature phosphoric acid machine is required to remove part of the NIT (Nitride), that is, to remove part of the nitride layer, which in turn limits the development of the 2X node and cannot guarantee the uniformity of ion implantation, thereby affecting the performance of semiconductor devices. Summary of the invention

[0004] The main technical problem solved by the present invention is: to provide a method for manufacturing a semiconductor device, to form an isolation sidewall layer on both sides of a gate structure on a substrate, the isolation sidewall layer includes at least one oxide layer and at least two nitride layers, and the etching rates of the first nitride layer and the second nitride layer are different, so that part of the NIT can be removed without a low-temperature phosphoric acid machine, while ensuring the uniformity of ion implantation, thereby improving the performance of the semiconductor device.

[0005] To solve the above technical problems, a technical solution adopted in the present application is: to provide a method for manufacturing a semiconductor device, comprising: providing a semiconductor base, the semiconductor base comprising a substrate and a gate structure formed on the substrate; forming an isolation sidewall layer, the isolation sidewall layer covering both sides of the gate structure, the isolation sidewall layer comprising at least one oxide layer and at least two nitride layers, wherein a distance from a first nitride layer to the gate structure is smaller than a distance from a second nitride layer to the gate structure, and an etching rate of the first nitride layer is smaller than an etching rate of the second nitride layer.

[0006] In one embodiment of the present application, the formation of the isolation sidewall layer includes: forming a first oxide layer, the first oxide layer covers both sides of the gate structure and covers a portion of the substrate to form a first step; forming the first nitride layer, the first nitride layer covers the first oxide layer and covers the first step to form a second step; forming the second nitride layer, the second nitride layer covers the first nitride layer and covers the second step.

[0007] In one embodiment of the present application, the forming of the first oxide layer includes: forming an oxide material layer to cover the substrate, the gate structure and both sides of the gate structure; removing the oxide material layer outside the sidewall region, and using the retained oxide material layer as the first oxide layer, and the formed first step is located in the sidewall region, wherein the sidewall region is at least a portion of the region on both sides of the gate structure.

[0008] In one embodiment of the present application, the forming of the first nitride layer includes: forming a first nitride material layer to cover the substrate, the gate structure and the first oxide layer on both sides of the gate structure; removing the first nitride material layer outside the side wall area to retain the first nitride material layer as the first nitride layer, and the formed second step is located above the first step.

[0009] In one embodiment of the present application, the forming of the second nitride layer includes: forming a second nitride material layer to cover the substrate, the gate structure and the first nitride layer on both sides of the gate structure; removing the second nitride material layer outside the side wall area, so that the retained second nitride material layer serves as the second nitride layer, and the second nitride layer covers the second step.

[0010] In one embodiment of the present application, the first nitride layer is formed by a first forming method, and the second nitride layer is formed by a second forming method; wherein the first forming method is an atomic layer deposition method, and the second forming method is a furnace tube growth method.

[0011] In an embodiment of the present application, an etching rate of the first nitride layer is lower than an etching rate of the second nitride layer.

[0012] In one embodiment of the present application, at least one oxide layer includes a first oxide layer; a first thickness of the first nitride layer in a horizontal direction is greater than a second thickness of the first oxide layer in the horizontal direction, and a third thickness of the first nitride layer in a vertical direction is greater than a fourth thickness of the first oxide layer in the vertical direction.

[0013] In one embodiment of the present application, before forming the isolation spacer layer, it also includes: forming a gate spacer layer, the gate spacer layer covers both sides of the gate structure, wherein the isolation spacer layer covers the gate spacer layer on both sides of the gate structure.

[0014] In one embodiment of the present application, the forming of the gate spacer layer includes: forming a spacer material layer to cover the gate structure and the substrate; removing a portion of the spacer material layer to form the gate spacer layer, wherein the spacer material layer above the gate structure and on the substrate is removed, and the spacer material layer retained on both sides of the gate structure serves as the gate spacer layer.

[0015] In an embodiment of the present application, it further includes: forming a source / drain region, wherein the source / drain region is located in the substrate outside the isolation spacer layer on both sides of the gate structure.

[0016] In one embodiment of the present application, it also includes: forming a buried oxide layer, wherein the buried oxide layer is located on the substrate outside the isolation sidewall layer on both sides of the gate structure, wherein, during the process of forming the buried oxide layer, the first etching rate of the first nitride layer is less than the second etching rate of the second nitride layer, and at least a portion of the second nitride layer is removed.

[0017] In one embodiment of the present application, it also includes: removing the remaining second nitride layer using a selective cleaning method, wherein during the cleaning process using the selective cleaning method, the third etching rate of the first nitride layer is lower than the fourth etching rate of the second nitride layer.

[0018] In order to solve the above technical problems, a technical solution adopted in the present application is: providing a semiconductor device, including a semiconductor base and an isolation sidewall layer, the semiconductor base including a substrate and a gate structure formed on the substrate; the isolation sidewall layer covers both sides of the gate structure, and the isolation sidewall layer includes at least one oxide layer and a first nitride layer; the first nitride layer is the nitride layer remaining after a preset treatment, and the isolation sidewall layer before the preset treatment also includes a second nitride layer, and the etching rate of the first nitride layer is less than the etching rate of the second nitride layer, so that the second nitride layer can be removed after the preset treatment.

[0019] In one embodiment of the present application, the preset treatment includes ion implantation and selective cleaning.

[0020] In one embodiment of the present application, the thickness of the first nitride layer remains consistent before and after the preset treatment.

[0021] In one embodiment of the present application, it further includes: a gate spacer layer, the gate spacer layer covers two sides of the gate structure, wherein the isolation spacer layer covers the gate spacer layer on both sides of the gate structure.

[0022] In one embodiment of the present application, it also includes: a source / drain region, which is located in the substrate outside the isolation sidewalls on both sides of the gate structure; and a buried oxide layer, which is located on the substrate outside the isolation sidewalls on both sides of the gate structure, wherein the buried oxide layer is formed by at least a portion of the substrate.

[0023] Different from the current technology, the manufacturing method of the semiconductor device provided in the present application includes: providing a semiconductor substrate, the semiconductor substrate includes a substrate, and a gate structure formed on the substrate; forming an isolation sidewall layer, the isolation sidewall layer covers both sides of the gate structure, and the isolation sidewall layer includes at least one oxide layer and at least two nitride layers, wherein the etching rate of the first nitride layer is different from that of the second nitride layer. That is, in the present application, by forming an isolation sidewall layer on both sides of the gate structure on the substrate, and the isolation sidewall layer includes at least one oxide layer and at least two nitride layers, wherein the etching rate of the first nitride layer is different from that of the second nitride layer, in the subsequent removal process of part of the nitride layer (NIT, Nitride), it can be achieved without using a low-temperature phosphoric acid machine, thereby reducing the cost, and the retained nitride layer (NIT, Nitride) can ensure the uniformity of ion implantation, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0025] Figure 1 It is a schematic flow chart of an embodiment of a method for manufacturing a semiconductor device in the present application;

[0026] Figure 2 It is a structural schematic diagram of an embodiment of a semiconductor substrate in the present application;

[0027] Figure 3 is a structural schematic diagram of an embodiment of forming a first oxide layer in the present application;

[0028] Figure 4 is a schematic structural diagram of an embodiment of forming a first nitride layer in the present application;

[0029] Figure 5is a schematic structural diagram of an embodiment of forming a second nitride layer in the present application;

[0030] Figure 6 is a schematic structural diagram of a second embodiment of a semiconductor device in the present application;

[0031] Figure 7 It is a structural schematic diagram of an embodiment of removing the second nitride layer in the present application;

[0032] Figure 8 is a schematic structural diagram of an embodiment of forming a metal silicide layer in the present application;

[0033] Fig. 9 It is a structural schematic diagram of an embodiment of forming an interlayer dielectric layer in the present application.

[0034] In the accompanying drawings, there are a substrate 100, a gate structure 200, a second oxide layer 210, a gate material layer 220, an isolation spacer layer 300, a first oxide layer 310, a first nitride layer 320, a second nitride layer 330, a gate spacer layer 400, a metal silicide layer 500, an interlayer dielectric layer 600, a connecting column 610, a spacer region A, a first step S1, a second step S2, a first thickness T1, a second thickness T2, a third thickness T3, and a fourth thickness T4. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0037] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0038] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0039] In the current manufacturing method of semiconductor devices, in the 2X node, the sidewall structure usually uses the OX / NIT (Oxide-Nitride) structure to protect the LDD (Lightly Doped Drain) structure to prevent heavily doped source and drain ions from being injected into the extended area of ​​the LDD structure. And because the sidewall of the 2X node is small, a low-temperature phosphoric acid machine is required to remove part of the nitride layer NIT (Nitride), which limits the development of the 2X node and cannot guarantee the uniformity of ion implantation, which in turn affects the performance of semiconductor devices.

[0040] Therefore, a method for manufacturing a semiconductor device is provided, by changing the composition of the sidewall structure, that is, forming an isolation sidewall layer on both sides of the gate structure on the substrate, and the isolation sidewall layer includes at least one oxide layer and at least two nitride layers, wherein the first nitride layer and the second nitride layer have different etching rates, and in the subsequent removal process of part of the nitride layer NIT (Nitride), it can be achieved without using a low-temperature phosphoric acid machine, thereby reducing the cost, and the retained nitride layer NIT (Nitride) can ensure the uniformity of ion implantation, thereby improving the performance of the semiconductor device.

[0041] See also Figure 1 , Figure 1 It is a flow chart of an embodiment of a method for manufacturing a semiconductor device in the present application.

[0042] like Figure 1 As shown, the method for manufacturing a semiconductor device in the present application may include the following operations.

[0043] S10, providing a semiconductor body, wherein the semiconductor body comprises a substrate and a gate structure formed on the substrate.

[0044] The substrate may be any suitable base material known in the art, and the gate material layer may be any suitable gate material known in the art.

[0045] Specifically, a substrate is provided, and then a gate structure is formed on the substrate. It can be understood that the gate structure may include an oxide layer and a gate material layer, that is, the oxide layer is arranged on the substrate, and the gate material layer is arranged on the oxide layer.

[0046] S20. Form an isolation sidewall layer, where the isolation sidewall layer covers both sides of the gate structure, and the isolation sidewall layer includes at least one oxide layer and at least two nitride layers, wherein a distance from the first nitride layer to the gate structure is smaller than a distance from the second nitride layer to the gate structure, and an etching rate of the first nitride layer is smaller than an etching rate of the second nitride layer.

[0047] The material of the isolation sidewall layer may be an isolation material that can protect the gate structure.

[0048] Specifically, on the basis of a gate structure formed on a substrate, an isolation sidewall layer is formed on both sides of the gate structure so that the isolation sidewall layer covers the side walls of the gate structure, and the isolation sidewall layer includes at least one oxide layer and at least two nitride layers, wherein the first oxide layer covers the side walls of the gate structure, the first nitride layer covers the first oxide layer on both sides of the gate structure, and the second nitride layer covers the first nitride layer on both sides of the gate structure, that is, the distance from the first nitride layer to the gate structure is smaller than the distance from the second nitride layer to the gate structure, that is, the first nitride layer is an intermediate layer, and the second nitride layer is an outermost layer; and the etching rate of the first nitride layer is smaller than the etching rate of the second nitride layer; for example, when etching the isolation sidewall layer, the etching rate of the first nitride layer 320 is 1, and the etching rate of the second nitride layer 330 is 4.

[0049] In the present embodiment, by changing the composition of the sidewall structure, that is, forming an isolation sidewall layer on both sides of the gate structure on the substrate, and the isolation sidewall layer includes at least one oxide layer and at least two nitride layers, wherein the uniformity of the first nitride layer is better than that of the second nitride layer, in the etching process of the subsequent process, the etching rate of the first nitride layer is made lower than the etching rate of the second nitride layer, that is, in the subsequent removal of part of the nitride layer NIT, that is, the removal of the second nitride layer, the second nitride layer can be removed without using a low-temperature phosphoric acid machine, thereby reducing the cost, and the retained nitride layer NIT, that is, the retained first nitride layer, and the thickness remains the same, thereby ensuring the uniformity of ion implantation, thereby improving the performance of the semiconductor device.

[0050] Execute the operation of step S10. The operation flow of step S10 is as follows:

[0051] A substrate 100 is provided, and a gate structure 200 is formed on the substrate 100 , wherein the gate structure 200 may include a second oxide layer 210 and a gate material layer 220 .

[0052] In some embodiments, an isolation structure is further formed in the substrate 100 , and the isolation structure may be a shallow trench isolation structure for isolating different semiconductor devices.

[0053] See also Figure 2 , Figure 2 It is a schematic structural diagram of an embodiment of a semiconductor substrate in the present application.

[0054] like Figure 2 As shown, a substrate 100 is provided, and a second oxide layer 210 is formed on the substrate, and a gate material layer 220 is formed on the second oxide layer 210 , so that the second oxide layer 210 and the gate material layer 220 are used as the gate structure 200 .

[0055] The substrate may be any suitable base material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).

[0056] Next, the operation of step S20 is performed. The operation flow of step S20 is as follows.

[0057] An isolation spacer 300 is formed, and the isolation spacer 300 covers both sides of the gate structure 200 . The isolation spacer 300 includes at least one oxide layer and at least two nitride layers, wherein the etching rates of the first nitride layer and the second nitride layer are different.

[0058] It can be understood that the at least one oxide layer can be a single oxide layer, such as the first oxide layer 310, or a multi-layer oxide layer; the at least two nitride layers can be two nitride layers, such as the first nitride layer 320 and the second nitride layer 330, or more than two nitride layers; the first oxide layer 310, the first nitride layer 320 and the second nitride layer 330 are used as examples for explanation below, and the specific details are as follows. Figure 3-Figure 5 .

[0059] It is necessary to form a first oxide layer 310, a first nitride layer 320 and a second nitride layer 330 in sequence respectively; wherein the first oxide layer 310 covers both sides of the gate structure 200 and covers part of the substrate 100 to form a first step; the first nitride layer 320 covers the first oxide layer 310 on both sides of the gate structure 200, covers the first step, and forms a second step; the second nitride layer 330 covers the first nitride layer 320 on both sides of the gate structure 200 and covers the second step.

[0060] First, a first oxide layer is formed.

[0061] See also Figure 3 , Figure 3 It is a structural schematic diagram of an embodiment of forming a first oxide layer in the present application.

[0062] like Figure 3As shown, an oxide material layer is formed to cover the substrate 100, the gate structure 200 and both sides of the gate structure 200, that is, to cover the top of the gate structure 200 and both sides of the gate structure 200; then the oxide material layer outside the sidewall region A is removed, and the retained oxide material layer is used as the first oxide layer 310, and the formed first step S1 is located in the sidewall region A; wherein the sidewall region A is at least a portion of the region on both sides of the gate structure 200, that is, at least a portion of the region on both sides of the gate structure 200 close to the gate structure 200.

[0063] In some embodiments, the oxide material layer may be an oxide material commonly used in the art.

[0064] Then, a first nitride layer is formed.

[0065] See also Figure 4 , Figure 4 It is a structural schematic diagram of an embodiment of forming a first nitride layer in the present application.

[0066] like Figure 4 As shown, a first nitride material layer is formed to cover the substrate 100, the gate structure 200 and the first oxide layer 310 on both sides of the gate structure 200, that is, the first oxide layer 310 covering the top of the gate structure 200 and both sides of the gate structure 200; then the first nitride material layer outside the sidewall area A is removed to retain the first nitride material layer as the first nitride layer 320, and a second step S2 is formed on the first step S1, and the second step S2 is located above the first step S1.

[0067] In some embodiments, the first nitride layer 320 may be a nitride layer NIT, and main components of the NIT include silicon nitride (SiN) and aluminum nitride (AlN).

[0068] In some embodiments, the first nitride layer 320 may be formed by a first formation method, which may be an atomic layer deposition method (ALD); specifically, the first nitride material is deposited layer by layer on the surface of the substrate 100 and the gate structure 200 in the form of a single atomic film, thereby forming the first nitride layer 320, namely, ALD NIT.

[0069] Then, a second nitride layer is formed.

[0070] See also Figure 5 , Figure 5 It is a structural schematic diagram of an embodiment of forming a second nitride layer in the present application.

[0071] like Figure 5As shown, a second nitride material layer is formed to cover the substrate 100, the gate structure 200 and the first nitride layer 320 on both sides of the gate structure 200, that is, the first nitride layer 320 covering the top of the gate structure 200 and both sides of the gate structure 200; then the second nitride material layer outside the sidewall area A is removed to use the retained second nitride material layer as the second nitride layer 330, and the second nitride layer 330 covers the second step (not marked in the drawing).

[0072] In some embodiments, the second nitride layer 330 may also be a nitride layer NIT.

[0073] In some embodiments, the second nitride layer 330 may be formed by a second forming method, and the second forming method may be furnace tube growth using hexachlorodisilane (HCD), and the specific reaction formula is: 3Si2Cl6+26NH3=2Si3N4+18NH4Cl+11H2.

[0074] Among them, Si2Cl6 is the chemical formula of hexachlorodisilane, NH3 is the chemical formula of ammonia, Si3N4 is the chemical formula of silicon nitride, NH4Cl is the chemical formula of ammonium chloride, and H2 is the chemical formula of ammonia. That is, the main components of the second nitride layer 330 are Si3N4 and NH4Cl.

[0075] Then, a second nitride layer 330 , ie, HCD NIT, is formed.

[0076] In some embodiments, an etching rate of the first nitride layer 320 is lower than an etching rate of the second nitride layer 330 .

[0077] Specifically, because the first nitride layer 320 is formed by atomic layer deposition, it has good uniformity and is relatively dense, so that the first nitride layer 320 has good conformal properties; and the second nitride layer 330 is grown in a furnace tube using hexachlorodisilane (HCD), and its uniformity is lower than that of the first nitride layer 320. Therefore, when etching is performed in the same manner, the etching rate of the second nitride layer 330 is greater than the etching rate of the first nitride layer 320; for example, when etching is performed using hydrofluoric acid (HF), the etching rate of the first nitride layer 320 is 1, and the etching rate of the second nitride layer 330 is 4.

[0078] In some embodiments, a first thickness T1 of the first nitride layer 320 in the horizontal direction is greater than a second thickness T2 of the first oxide layer 310 in the horizontal direction, and a third thickness T3 of the first nitride layer 320 in the vertical direction is greater than a fourth thickness T4 of the first oxide layer 310 in the vertical direction.

[0079] Specifically, the first oxide layer 310 may be L-shaped, and therefore, there is a second thickness T2 in the horizontal direction and a fourth thickness T4 in the vertical direction, wherein the first step S1 is the portion of the first oxide layer 310 in contact with the substrate 100, that is, the L-shaped bottom of the first oxide layer 310 is the first step S1, and its sidewall is in contact with the gate structure 200; the first nitride layer 320 may be L-shaped, and therefore, there is also a first thickness T1 in the horizontal direction and a third thickness T3 in the vertical direction, wherein the second step S2 is the portion of the first nitride layer 320 in contact with the first step S1, that is, the L-shaped bottom of the first nitride layer 320 is the second step S2, and the arrangement of the first step S1 and the second step S2 is specifically referred to. Figure 4 .

[0080] At this point, the isolation spacer layer 300 is formed. The above is the device structure of the first embodiment of the semiconductor device in this application.

[0081] In some embodiments, the device structure of the second embodiment of the semiconductor device may also be included, that is, before forming the isolation spacer layer, a gate spacer layer may also be formed.

[0082] See also Figure 6 , Figure 6 It is a schematic structural diagram of the second embodiment of the semiconductor device in this application.

[0083] like Figure 6 As shown, in Figure 5 On the basis of, and before forming the isolation spacer layer 300 , a gate spacer layer 400 may be formed, and the gate spacer layer 400 covers both sides of the gate structure 200 , and the isolation spacer layer 300 covers the gate spacer layer 400 on both sides of the gate structure 200 .

[0084] In some embodiments, forming the gate spacer 400 may include the following operations.

[0085] A spacer material layer is formed, which covers the gate structure 200 and the substrate 100; then part of the spacer material layer is removed to form a gate spacer layer 400; wherein the spacer material layers above the gate structure 200 and above the substrate 100 are removed, and the spacer material layers on both sides of the retained gate structure 200 serve as the gate spacer layer 400.

[0086] In some embodiments, the spacer material layer may be an oxidized material, that is, the material of the gate spacer layer 400 may be an oxidized material.

[0087] Then, an isolation spacer 300 is formed to cover the gate spacer 400 on both sides of the gate structure 200 , thereby obtaining the device structure of the second embodiment of the semiconductor device.

[0088] In some embodiments, source / drain regions (not shown in the drawings) may also be formed by performing source / drain ion implantation (S / D IMP), where the source / drain regions are located in the substrate 100 outside the isolation spacer layers on both sides of the gate structure 200 .

[0089] In some embodiments, a buried oxide layer may be formed and then the second nitride layer may be removed.

[0090] See also Figure 7 , Figure 7 It is a structural schematic diagram of an embodiment of removing the second nitride layer in the present application.

[0091] like Figure 7 As shown, in Figure 6 On the basis of, a buried oxide layer (not shown in the drawing) is formed, and the buried oxide layer is located on the substrate 100 outside the isolation spacer layer 300 on both sides of the gate structure 200; that is, a buried oxide layer is formed on the substrate surface outside the isolation spacer layer 300 on both sides of the gate structure 200.

[0092] In the process of forming the buried oxide layer, a first etching rate of the first nitride layer 320 is lower than a second etching rate of the second nitride layer 330 , thereby removing at least a portion of the second nitride layer 330 .

[0093] For example, the first nitride layer 320 and the second nitride layer 330 are etched using hydrofluoric acid (HF), wherein a first etching rate for the first nitride layer 320 is 1, and a second etching rate for the second nitride layer 330 is 4, and at least a portion of the second nitride layer 330 is removed.

[0094] Furthermore, the remaining second nitride layer 330 may be removed by a selective cleaning method.

[0095] In the cleaning process using the selective cleaning method, the third etching rate of the first nitride layer 320 is lower than the fourth etching rate of the second nitride layer 330 .

[0096] For example, the remaining second nitride layer 330 is removed by using a highly selective cleaning process, such as a Siconi process, wherein the third etching rate for the first nitride layer 320 is 1 and the fourth etching rate for the second nitride layer 330 is 8, and the remaining second nitride layer 330 can be removed.

[0097] In some embodiments, a metal silicide layer may also be formed.

[0098] See also Figure 8 , Figure 8 It is a structural schematic diagram of an embodiment of forming a metal silicide layer in the present application.

[0099] like Figure 8 As shown, in Figure 7 On the basis of, a metal silicide layer 500 is formed, and the metal silicide layer 500 is located on the substrate 100 outside the isolation spacer layer 300 on both sides of the gate structure 200; that is, the metal silicide layer 500 is generated on the substrate surface outside the isolation spacer layer 300 on both sides of the gate structure 200.

[0100] In some embodiments, a metal silicide layer 500 may be formed on top of the gate structure 200 so that source / drain regions (not shown) on both sides of the gate structure 200 and the gate structure 200 may be connected to the outside through the metal silicide layer 500 .

[0101] In some embodiments, an interlayer dielectric layer may also be formed.

[0102] See also Fig. 9 , Fig. 9 It is a structural schematic diagram of an embodiment of forming an interlayer dielectric layer in the present application.

[0103] like Fig. 9 As shown, in Figure 8 On the basis of, an interlayer dielectric layer 600 is formed, and a plurality of connecting pillars 610 are formed in the interlayer dielectric layer 600, and the connecting pillars 610 are respectively connected to the source / drain regions (not marked in the figure) on both sides of the gate structure 200 and the metal silicide layer 500 corresponding to the gate structure 200, so as to lead the source / drain regions (not marked in the figure) on both sides of the gate structure 200 and the gate structure 200 to be connected to the outside.

[0104] In the present embodiment, a method for manufacturing a semiconductor device is provided, wherein an isolation sidewall layer is formed on both sides of a gate structure on a substrate, and the isolation sidewall layer includes at least one oxide layer and at least two nitride layers, wherein the first nitride layer and the second nitride layer have different etching rates, and in the subsequent removal of a portion of the nitride layer (NIT), that is, the removal of the second nitride layer, it can be achieved without using a low-temperature phosphoric acid machine, thereby reducing the cost, and the retained nitride layer (NIT) is the first nitride layer, which can ensure the uniformity of ion implantation, thereby improving the performance of the semiconductor device.

[0105] The present application also provides a semiconductor device, see Figure 2-9 .

[0106] The semiconductor device includes a substrate 100, a gate structure 200 and an isolation spacer layer 300; wherein the gate structure 200 is arranged on the substrate 100, the isolation spacer layer 300 covers both sides of the gate structure 200, and the isolation spacer layer 300 includes at least one oxide layer and at least two nitride layers, wherein the etching rates of the first nitride layer 320 and the second nitride layer 330 are different.

[0107] In the present embodiment, a semiconductor device is provided, which is manufactured by the above-mentioned semiconductor device manufacturing method, by forming an isolation sidewall layer 300 on both sides of the gate structure 200 on the substrate 100, and the isolation sidewall layer 300 includes a first oxide layer 310 and a first nitride layer 320, wherein the first nitride layer 320 is the nitride layer remaining after a preset treatment, and the isolation sidewall layer 300 before the preset treatment also includes a second nitride layer 330, and the etching rate of the first nitride layer 320 is less than the etching rate of the second nitride layer 330, so that the second nitride layer 330 is removed after the preset treatment, and in a preferred embodiment, the thickness of the first nitride layer 320 before the preset treatment is consistent with the thickness after the preset treatment, that is, the thickness of the first nitride layer 320 remains consistent before and after the preset treatment.

[0108] That is, the isolation spacer layer 300 includes a first oxide layer 310 and a first nitride layer 320. The first oxide layer 310 covers both sides of the gate structure 200 and a portion of the substrate 100 to form a first step S1. The first nitride layer 320 covers the first oxide layer 310 and the first step S1 to form a second step S2.

[0109] In some embodiments, the isolation sidewall layer 300 also includes a second nitride layer 330, which covers the first nitride layer 320 and the second step S2; wherein the distance from the first nitride layer 320 to the gate structure 200 is smaller than the distance from the second nitride layer 330 to the gate structure 200, and the etching rate of the first nitride layer 320 is smaller than the etching rate of the second nitride layer 330, so that the second nitride layer 330 is removed after a preset process.

[0110] The preset treatment may include ion implantation and selective cleaning, and only during the ion implantation and selective cleaning process, the second nitride layer 330 is removed, while the first nitride layer 320 is retained.

[0111] In some embodiments, the semiconductor device further includes a gate spacer 400 , and the gate spacer 400 covers the sidewalls on both sides of the gate structure 200 , wherein the isolation spacer 300 covers the gate spacer 400 on both sides of the gate structure 200 .

[0112] In some embodiments, the semiconductor device also includes a source / drain region (not shown in the drawings), which is located in the substrate outside the isolation sidewall layer 300 on both sides of the gate structure 200; wherein the source / drain region is an area where a source and a drain can be formed subsequently.

[0113] In some embodiments, the semiconductor device also includes a buried oxide layer (not shown in the drawings), which is located on the substrate 100 outside the isolation sidewall layer 300 on both sides of the gate structure 200, wherein the buried oxide layer is formed by at least a portion of the substrate 100, that is, the buried oxide layer is formed on the surface of the substrate 100.

[0114] In this embodiment, a semiconductor device is provided, the semiconductor device includes an isolation spacer layer, the isolation spacer layer includes an oxide layer and a nitride layer, and a portion of the nitride layer is removed during the formation of the semiconductor device, that is, the second nitride layer is removed, that is, in the process of removing the second nitride layer (NIT), it can be achieved without using a low-temperature phosphoric acid machine, thereby reducing costs, and the retained first nitride layer (NIT) can ensure the uniformity of ion implantation, thereby improving the performance of the semiconductor device. In a preferred embodiment, the thickness of the first nitride layer remains the same before and after the preset treatment.

[0115] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor body, the semiconductor body comprising a substrate and a gate structure formed on the substrate; An isolation sidewall layer is formed, wherein the isolation sidewall layer covers both sides of the gate structure, and the isolation sidewall layer includes at least one oxide layer and at least two nitride layers, wherein a distance from a first nitride layer to the gate structure is smaller than a distance from a second nitride layer to the gate structure, and an etching rate of the first nitride layer is smaller than an etching rate of the second nitride layer.

2. The manufacturing method according to claim 1, characterized in that: The forming of the isolation sidewall layer comprises: forming a first oxide layer, wherein the first oxide layer covers both sides of the gate structure and covers a portion of the substrate to form a first step; forming the first nitride layer, wherein the first nitride layer covers the first oxide layer and the first step to form a second step; The second nitride layer is formed, wherein the second nitride layer covers the first nitride layer and the second step.

3. The manufacturing method according to claim 2, characterized in that: The forming of the first oxide layer comprises: forming an oxide material layer to cover the substrate, the gate structure and both sides of the gate structure; The oxide material layer outside the sidewall region is removed to use the remaining oxide material layer as the first oxide layer, and the first step is formed in the sidewall region, wherein the sidewall region is at least a portion of the regions on both sides of the gate structure.

4. The manufacturing method according to claim 3, characterized in that: The forming of the first nitride layer comprises: forming a first nitride material layer to cover the substrate, the gate structure and the first oxide layer on both sides of the gate structure; The first nitride material layer outside the spacer region is removed, and the remaining first nitride material layer is used as the first nitride layer, and the formed second step is located above the first step.

5. The manufacturing method according to claim 3, characterized in that: The forming of the second nitride layer comprises: forming a second nitride material layer to cover the substrate, the gate structure and the first nitride layer on both sides of the gate structure; The second nitride material layer outside the sidewall region is removed, and the remaining second nitride material layer is used as the second nitride layer, and the second nitride layer covers the second step.

6. The manufacturing method according to claim 2, characterized in that: forming the first nitride layer by a first forming method, and forming the second nitride layer by a second forming method; Among them, the first forming method is an atomic layer deposition method, and the second forming method is a furnace tube growth method.

7. The manufacturing method according to claim 1, characterized in that: The at least one oxide layer includes a first oxide layer; A first thickness of the first nitride layer in the horizontal direction is greater than a second thickness of the first oxide layer in the horizontal direction, and a third thickness of the first nitride layer in the vertical direction is greater than a fourth thickness of the first oxide layer in the vertical direction.

8. The manufacturing method according to claim 1, characterized in that: Before forming the isolation spacer layer, the method further includes: A gate spacer layer is formed, wherein the gate spacer layer covers two sides of the gate structure, wherein the isolation spacer layer covers the gate spacer layer on two sides of the gate structure.

9. The manufacturing method according to claim 8, characterized in that: The forming of the gate sidewall layer comprises: Forming a spacer material layer to cover the gate structure and the substrate; A portion of the spacer material layer is removed to form the gate spacer layer, wherein the spacer material layer above the gate structure and on the substrate is removed, and the spacer material layer retained on both sides of the gate structure serves as the gate spacer layer.

10. The manufacturing method according to claim 1, characterized in that: Also includes: A source / drain region is formed, wherein the source / drain region is located in the substrate outside the isolation spacer layer on both sides of the gate structure.

11. The manufacturing method according to claim 1, characterized in that: Also includes: A buried oxide layer is formed, wherein the buried oxide layer is located on the substrate outside the isolation sidewall layer on both sides of the gate structure, wherein, during the formation of the buried oxide layer, a first etching rate for the first nitride layer is less than a second etching rate for the second nitride layer, and at least a portion of the second nitride layer is removed.

12. The manufacturing method according to claim 11, characterized in that: Also includes: The remaining second nitride layer is removed by using a selective cleaning method, wherein during the cleaning process using the selective cleaning method, a third etching rate of the first nitride layer is lower than a fourth etching rate of the second nitride layer.

13. A semiconductor device, characterized in that: include: A semiconductor body, the semiconductor body comprising a substrate and a gate structure formed on the substrate; An isolation spacer layer, wherein the isolation spacer layer covers two sides of the gate structure, and the isolation spacer layer includes a first oxide layer and a first nitride layer; Among them, the first nitride layer is the nitride layer remaining after the preset treatment, and the isolation sidewall layer before the preset treatment also includes a second nitride layer. The etching rate of the first nitride layer is less than the etching rate of the second nitride layer, so that the second nitride layer can be removed after the preset treatment.

14. The semiconductor device according to claim 13, characterized in that The preset process includes an ion implantation process and a selective cleaning process.

15. The semiconductor device according to claim 13, wherein: The thickness of the first nitride layer is consistent before and after the preset treatment.

16. The semiconductor device according to claim 13, wherein: Also includes: A gate spacer layer, wherein the gate spacer layer covers two sides of the gate structure, wherein the isolation spacer layer covers the gate spacer layer on two sides of the gate structure.

17. The semiconductor device according to claim 13, characterized in that Also includes: Source / drain regions, the source / drain regions being located in the substrate outside the isolation spacer layer on both sides of the gate structure; A buried oxide layer is located on the substrate outside the isolation spacer layer on both sides of the gate structure, wherein the buried oxide layer is formed by at least a portion of the substrate.

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