Short-size gallium oxide power device edge terminal structure and preparation method thereof

Abstract

The invention discloses a short-size gallium oxide power device edge terminal structure and a preparation method thereof, and relates to the technical field of semiconductor devices. The short-size gallium oxide power device edge terminal structure comprises a gallium oxide drift layer, an n-type doped gallium oxide substrate and a cathode which are sequentially stacked, an etching mesa terminal structure and a field limiting ring terminal structure are combined, a double-groove buried layer p-type terminal structure is formed, and when the device is under reverse bias, the device can be directly connected with the n-type doped gallium oxide substrate and the cathode. The depletion region can expand along the buried layer p-type layer at the bottom of the groove, so that the electric field distribution at the edge of the device is effectively smoothed, and the breakdown voltage of the device is improved. Under the same-level breakdown voltage, compared with a traditional field limiting ring structure, the double-groove buried layer p-type terminal structure is smaller in size, parasitic parameters of a device can be reduced, and the chip integration degree is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a short-sized gallium oxide power device edge terminal structure and a preparation method thereof. Background Art

[0002] In recent years, relying on the continuous development and breakthrough of power electronics technology, emerging industries such as new energy vehicles, high-speed trains, and 5G communications have flourished, bringing great convenience to people's lives. Among them, semiconductor power devices, as the core of modern power electronics technology, play a role that cannot be ignored. Semiconductor power devices can be used for energy conversion and switch control in circuits, and are a key part of realizing efficient power systems.

[0003] With the increase in high current and high voltage application scenarios, ultra-wide bandgap semiconductors with large bandgap width and high theoretical breakdown field strength have attracted the attention of the industry. Gallium oxide (Ga2O3), as a kind of ultra-wide bandgap semiconductor material, has an ultra-wide bandgap of up to 4.8eV and an ultra-large theoretical breakdown field strength of 8MV / cm, making it an ideal material for preparing high-power semiconductor devices. However, due to the spatial discontinuity at the edge of the device, the electric field distribution in the depletion region is uneven under reverse bias, causing the electric field to be concentrated at the corners of the device, resulting in thermal concentration and premature breakdown of the device.

[0004] In order to mitigate this electric field concentration effect, the prior art usually adds an edge terminal structure at the edge of the device during device design. Among them, the field limiting ring structure can effectively alleviate the electric field concentration and increase the breakdown voltage of the device by expanding the depletion region through the pn junction under reverse bias. However, the field limiting ring structure usually requires dozens of pairs of rings to achieve a good effect, which will greatly increase the area occupied by a single device on the integrated chip and greatly reduce the integration of the chip. In addition, the addition of dozens of pairs of annular pn junctions will also introduce larger parasitic parameters, which is not conducive to the application of the device in high-speed, low-energy consumption scenarios. Summary of the invention

[0005] In order to solve the problems existing in the above-mentioned prior art, the purpose of the present invention is to provide a short-sized gallium oxide power device edge terminal structure and a preparation method, which mainly forms a double-trench buried p-type edge terminal structure by depositing a p-type oxide semiconductor thin layer at the bottom of the double trenches formed by etching, thereby effectively improving the electric field concentration effect of the device, and the size of the structure is much smaller than that of the field limiting ring terminal structure with the same effect.

[0006] In order to achieve the above object, the present invention provides the following technical solutions: On the one hand, the present invention provides a short-sized gallium oxide power device edge terminal structure, comprising a gallium oxide drift layer, an n-type doped gallium oxide substrate and a cathode stacked in sequence; A p-type oxide semiconductor is deposited on one side of the gallium oxide drift layer away from the n-type doped gallium oxide substrate to form a first heterogeneous pn junction region, and an anode is provided on the surface of the p-type oxide semiconductor; The edge of the first heterogeneous pn junction region is etched to form a double trench, and a p-type oxide semiconductor is deposited on the bottom of the double trench and the top of the mesa formed between the double trenches to form a second heterogeneous pn junction region; The double grooves are filled with a passivation layer, a field plate electrode is arranged on the surface of the passivation layer, and the field plate electrode is connected to the anode.

[0007] Preferably, the p-type oxide semiconductor is an amorphous or polycrystalline structure.

[0008] Preferably, the hole concentration of the p-type oxide semiconductor is 1×10 17 / cm 3 ~1×10 20 / cm 3 , and the hole concentration of the p-type oxide semiconductor thin layer is not lower than that of the gallium oxide drift layer.

[0009] Preferably, the thickness of the p-type oxide semiconductor is 10 nm to 1 μm.

[0010] Preferably, the double grooves have a groove depth of 5 μm to 10 μm, a groove width of 2 μm to 5 μm, and a spacing between the double grooves of 2 μm to 5 μm.

[0011] Preferably, the length of the passivation layer is greater than the length of the double trenches.

[0012] Preferably, the field plate electrode is connected to the anode, and the length of the field plate electrode covering the passivation layer is greater than the length of the double trench region.

[0013] On the other hand, the present invention also provides a method for preparing the short-sized gallium oxide power device edge terminal structure as described in any one of the above items, comprising the following steps: S1, epitaxially growing a gallium oxide drift layer on an n-type doped gallium oxide substrate to obtain an n-type doped gallium oxide-based wafer; S2, depositing a cathode on a side of the n-type doped gallium oxide substrate away from the gallium oxide drift layer; S3, forming a double trench structure by etching at an edge of a side of the gallium oxide drift layer away from the n-type doped gallium oxide substrate; S4, depositing a p-type oxide conductor on the side of the gallium oxide drift layer away from the n-type doped gallium oxide substrate to form a first heterogeneous pn junction region, depositing a p-type oxide conductor on the bottom of the double trench structure and the top of the mesa formed between the double trenches to form a second heterogeneous pn junction region; depositing an anode in the first heterogeneous pn junction region; S5, depositing a passivation layer in the double trench region to cover the p-type oxide semiconductor in the second heterogeneous pn junction region and the gallium oxide drift layer at the edge of the n-type doped gallium oxide-based wafer; S6. Deposit a field plate electrode on the surface of the passivation layer and connect the field plate electrode to the anode.

[0014] Preferably, the cathode in step S1 deposits Ti / Au alloy or Ti / Al / Ti / Au alloy by magnetron sputtering or electron beam evaporation, and the anode in step S4 deposits Ni / Au alloy by magnetron sputtering or electron beam evaporation.

[0015] Preferably, the p-type oxide semiconductor in step S4 is prepared by magnetron sputtering, solution method, metal oxidation method, physical or chemical vapor deposition method, and the p-type oxide semiconductor material is a single-layer or multi-layer p-type oxide semiconductor material of NiO or Cu2O; the passivation layer in step S6 is prepared by atomic layer deposition, plasma enhanced chemical vapor deposition, magnetron sputtering, physical or chemical vapor deposition method, and the passivation layer material is a single-layer or multi-layer insulating dielectric material of Al2O3, SiO2 or SiNx.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The short-sized gallium oxide power device edge terminal structure and preparation method thereof provided by the present invention have the advantages that the etched mesa terminal structure is combined with the field limiting ring terminal structure to form a double-groove buried layer p-type terminal structure. When the device is under reverse bias, the depletion region will expand along the buried layer p-type layer at the bottom of the groove, effectively smoothing the electric field distribution at the edge of the device and improving the breakdown voltage of the device. Under the same level of breakdown voltage, compared with the traditional field limiting ring structure, the double-groove buried layer p-type terminal structure has a smaller size, which is conducive to reducing the parasitic parameters of the device and improving the chip integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic diagram of an edge terminal structure of a short-sized gallium oxide power device provided in Example 1 of the present invention.

[0019] Figure 2 This is a simulation diagram of electric field data of an edge terminal structure of a short-sized gallium oxide power device under reverse bias provided in Example 1 of the present invention.

[0020] Description of reference numerals: 101, cathode; 102, n-type doped gallium oxide substrate; 103, gallium oxide drift layer; 104, p-type oxide semiconductor; 105, anode; 106, passivation layer; 107, field plate electrode. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings. The following embodiments are only specific embodiments exemplified in this application, which are used to illustrate the technical solution of the present application, rather than to limit it, and the protection scope of the present application is not limited thereto. In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0022] Example 1

[0023] like Figure 1 As shown, this embodiment provides a short-sized gallium oxide power device edge terminal structure, comprising a cathode 101, an n-type doped gallium oxide substrate 102 and a gallium oxide drift layer 103 which are stacked in sequence, wherein a p-type oxide semiconductor 104 is provided on a side of the gallium oxide drift layer 103 away from the n-type doped gallium oxide substrate 102 to form a first heterogeneous pn junction region, an anode 105 is provided on the surface of the first heterogeneous pn junction region, a double trench structure is formed at the edge of the first heterogeneous pn junction region by etching, a p-type oxide semiconductor 104 is provided at the bottom of the double trench structure and at the top of the mesa formed between the double trenches to form a second heterogeneous pn junction region, the double trench region is filled with a passivation layer 106, and a field plate electrode 107 is provided on the top of the passivation layer 106.

[0024] The p-type oxide semiconductor 104 is an amorphous or polycrystalline structure, and the hole concentration is 1×10 17 / cm 3 ~1×10 20 / cm 3 , and its hole concentration is not lower than that of the gallium oxide drift layer, and the thickness is 10nm to 1μm. The groove depth is 5μm to 10μm, the width is 2μm to 5μm, and the double groove interval is 2μm to 5μm. The gallium oxide drift layer 103 is a single crystal structure with a doping concentration of 5×10 14 cm -3 Up to 1×10 18 cm -3, with a thickness of 2 μm to 5 mm. The length of the passivation layer 106 is greater than the length of the double groove region. The field plate electrode 107 is connected to the anode 105, and the length of the field plate electrode 107 covering the passivation layer 106 is greater than the length of the double groove region.

[0025] The short-sized gallium oxide power device edge terminal structure combines the etched mesa terminal structure with the field-limiting ring terminal structure to form a double-trench buried p-type terminal structure. When the device is under reverse bias, the depletion region will expand along the buried p-type layer at the bottom of the trench, effectively smoothing the electric field distribution at the edge of the device and improving the breakdown voltage of the device. At the same level of breakdown voltage, compared with the traditional field-limiting ring structure, the double-trench buried p-type terminal structure is smaller in size, which is conducive to reducing the parasitic parameters of the device and improving the chip integration.

[0026] Figure 2 This is a simulation diagram of the electric field data of a short-sized gallium oxide power device edge terminal structure under reverse bias provided in Example 1. For the double-trench buried p-type structure, the electric field peak under reverse bias appears at the gallium oxide drift layer at the bottom of the trench; for the field limiting ring structure, the electric field peak under reverse bias appears at the annular pn junction at the very end. According to the electric field distribution curve along the lateral direction at the extraction point, it can be seen that under the same reverse bias, the electric field peaks of the two terminal structures are similar, but the width of the double-trench buried p-type terminal structure is much smaller than that of the field limiting ring terminal structure. In summary, the present invention adopts a double-trench buried p-type terminal structure, which can effectively reduce the device area, reduce parasitic parameters, and improve chip integration.

[0027] Example 2

[0028] This embodiment provides a method for preparing a short-sized gallium oxide power device edge terminal structure, comprising the following steps: S1. Epitaxially grow a gallium oxide drift layer 103 on an n-type doped gallium oxide substrate 102 to obtain an n-type doped gallium oxide-based wafer.

[0029] S2. Depositing metal on the side of the n-type doped gallium oxide substrate 102 away from the gallium oxide drift layer 103 forms a cathode 101, and the cathode 101 forms an ohmic contact with the substrate 102. The cathode 101 can be deposited by magnetron sputtering or electron beam evaporation to form a Ti / Au alloy or a Ti / Al / Ti / Au alloy.

[0030] S3, forming a double trench structure by etching at the edge of one side of the gallium oxide drift layer 103 away from the n-type doped gallium oxide substrate 102, and the etching can be performed by dry etching, wet etching or the like.

[0031] S4. A p-type oxide conductor 104 is deposited on a side of the gallium oxide drift layer 103 away from the substrate 102 to form a first heterogeneous pn junction region. A p-type oxide semiconductor 104 is deposited on the bottom of the double trench structure and on the top of the mesa structure formed between the double trenches to form a second heterogeneous pn junction region. The p-type oxide semiconductor 104 can be prepared by magnetron sputtering, solution method, metal oxidation method, physical or chemical vapor deposition, etc., and the material can be NiO, Cu2O or other single-layer or multi-layer p-type oxide semiconductor materials.

[0032] An electrode pattern is defined on the surface of the p-type oxide semiconductor 104 in the first heterogeneous pn junction region by photolithography, and a metal is deposited to form an anode 105 . The anode 105 can be deposited by a Ni / Au alloy by magnetron sputtering or electron beam evaporation.

[0033] S5. Fill the double trench region with a passivation layer 106 to cover the p-type oxide semiconductor 104 in the second heterogeneous pn junction region and the n-type doped gallium oxide drift layer 103 at the edge of the gallium oxide-based wafer. The passivation layer 106 can be prepared by atomic layer deposition, plasma enhanced chemical vapor deposition, magnetron sputtering, other physical or chemical vapor deposition methods, and the material can be Al2O3, SiO2, SiNx or other single-layer or multi-layer insulating dielectric materials.

[0034] A pattern is defined on the passivation layer 106 by photolithography, and patterning is performed by dry etching, wet etching, or the like.

[0035] S6, defining a pattern on the surface of the passivation layer 106 by photolithography, and depositing metal or polysilicon to form a field plate electrode 107, which can be prepared by magnetron sputtering, electron beam evaporation, other physical or chemical vapor deposition methods, etc. The field plate electrode 107 is connected to the anode 105.

[0036] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0037] The above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the aforementioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the aforementioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical specialties therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A short-sized gallium oxide power device edge terminal structure, characterized in that: It includes a gallium oxide drift layer, an n-type doped gallium oxide substrate and a cathode which are stacked in sequence; A p-type oxide semiconductor is deposited on one side of the gallium oxide drift layer away from the n-type doped gallium oxide substrate to form a first heterogeneous pn junction region, and an anode is provided on the surface of the p-type oxide semiconductor; The edge of the first heterogeneous pn junction region is etched to form a double trench, and a p-type oxide semiconductor is deposited on the bottom of the double trench and the top of the mesa formed between the double trenches to form a second heterogeneous pn junction region; The double grooves are filled with a passivation layer, a field plate electrode is arranged on the surface of the passivation layer, and the field plate electrode is connected to the anode.

2. The short-sized gallium oxide power device edge terminal structure according to claim 1, characterized in that: The p-type oxide semiconductor is of an amorphous or polycrystalline structure.

3. The short-sized gallium oxide power device edge terminal structure according to claim 1, characterized in that: The hole concentration of the p-type oxide semiconductor is 1×10 17 / cm 3 ~1×10 20 / cm 3 , and the hole concentration of the p-type oxide semiconductor thin layer is not lower than that of the gallium oxide drift layer.

4. The short-sized gallium oxide power device edge terminal structure according to claim 1, characterized in that: The thickness of the p-type oxide semiconductor is 10 nm to 1 μm.

5. The short-sized gallium oxide power device edge terminal structure according to claim 1, characterized in that: The double grooves have a groove depth of 5 μm to 10 μm, a width of 2 μm to 5 μm, and a spacing between the double grooves of 2 μm to 5 μm.

6. The short-sized gallium oxide power device edge terminal structure according to claim 1, characterized in that: The length of the passivation layer is greater than the length of the double trenches.

7. The short-sized gallium oxide power device edge terminal structure according to claim 1, characterized in that: The field plate electrode is connected to the anode, and the length of the field plate electrode covering the passivation layer is greater than the length of the double groove region.

8. The method for preparing a short-sized gallium oxide power device edge terminal structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1, epitaxially growing a gallium oxide drift layer on an n-type doped gallium oxide substrate to obtain an n-type doped gallium oxide-based wafer; S2, depositing a cathode on a side of the n-type doped gallium oxide substrate away from the gallium oxide drift layer; S3, forming a double trench structure by etching at an edge of a side of the gallium oxide drift layer away from the n-type doped gallium oxide substrate; S4, depositing a p-type oxide conductor on the side of the gallium oxide drift layer away from the n-type doped gallium oxide substrate to form a first heterogeneous pn junction region, depositing a p-type oxide conductor on the bottom of the double trench structure and the top of the mesa formed between the double trenches to form a second heterogeneous pn junction region; depositing an anode in the first heterogeneous pn junction region; S5, depositing a passivation layer in the double trench region to cover the p-type oxide semiconductor in the second heterogeneous pn junction region and the gallium oxide drift layer at the edge of the n-type doped gallium oxide-based wafer; S6. Deposit a field plate electrode on the surface of the passivation layer and connect the field plate electrode to the anode.

9. The method for preparing a short-sized gallium oxide power device edge terminal structure according to claim 8, characterized in that: The cathode in step S1 deposits Ti / Au alloy or Ti / Al / Ti / Au alloy by magnetron sputtering or electron beam evaporation, and the anode in step S4 deposits Ni / Au alloy by magnetron sputtering or electron beam evaporation.

10. The method for preparing a short-sized gallium oxide power device edge terminal structure according to claim 8, characterized in that: The p-type oxide semiconductor described in step S4 is prepared by magnetron sputtering, solution method, metal oxidation method, physical or chemical vapor deposition method, and the p-type oxide semiconductor material is a single layer or multilayer p-type oxide semiconductor material of NiO or Cu2O; the passivation layer described in step S6 is prepared by atomic layer deposition, plasma enhanced chemical vapor deposition, magnetron sputtering, physical or chemical vapor deposition method, and the passivation layer material is a single layer or multilayer insulating dielectric material of Al2O3, SiO2 or SiNx.

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