Semiconductor device having vertical power transistor with metal silicide gate region

Abstract

The invention relates to a semiconductor device having a vertical power transistor with a metal silicide gate region. A semiconductor device includes a vertical power transistor having a plurality of power transistor cells. Each power transistor cell includes a source region at a first major surface of the semiconductor substrate, a drain region at a second major surface of the semiconductor substrate opposite the first major surface, a gate trench extending from the first major surface into the semiconductor substrate, and a gate electrode in the gate trench and including a polysilicon-doped gate electrode and a dielectric material separating the gate electrode from the semiconductor substrate. An upper central portion of each of the gate electrodes of the power transistor cell is occupied by a metal silicide region adjacent to the doped polysilicon. A method of producing a semiconductor device is also described.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor devices, and in particular to a semiconductor device having a vertical power transistor with a metal silicide gate region. Background Art

[0002] Power silicon technology for high-performance DCDC systems typically uses NMOS (n-type metal oxide semiconductor) power MOSFET (metal oxide semiconductor field effect transistor) primitives with heavily n-doped polysilicon gates. Integrated low-threshold CMOS (complementary metal oxide semiconductor) devices require the use of p-doped polysilicon gates for PMOS (p-type metal oxide semiconductor) primitives and n-doped polysilicon gates for NMOS primitives and NMOS power MOSFETs. However, p-doped polysilicon is a relatively high resistivity material, which can result in relatively high gate resistance and slow signal propagation, especially as gate sizes shrink for lower voltage high-performance circuits. In addition, the boundary between NMOS and PMOS devices results in a pn diode in the complementary doped polysilicon line.

[0003] Therefore, there is a need for an improved power silicon technology that supports the integration of CMOS devices with power transistor devices on the same silicon die (chip). Summary of the invention

[0004] According to an embodiment of a semiconductor device, the semiconductor device includes: a vertical power transistor, including a plurality of power transistor cells, wherein each of the power transistor cells includes a source region on a first main surface of a semiconductor substrate, a drain region on a second main surface of the semiconductor substrate opposite to the first main surface, a gate trench extending from the first main surface into the semiconductor substrate, a gate electrode located in the gate trench and including doped polysilicon, and a dielectric material separating the gate electrode from the semiconductor substrate, wherein an upper central portion of each of the gate electrodes of the power transistor cells is occupied by a metal silicide region, and the metal silicide region is adjacent to the doped polysilicon.

[0005] According to an embodiment of a method for producing a semiconductor device, the method includes: forming a vertical power transistor having a plurality of power transistor cells, wherein each of the power transistor cells includes a source region on a first main surface of a semiconductor substrate, a drain region on a second main surface of the semiconductor substrate opposite to the first main surface, a gate trench extending from the first main surface into the semiconductor substrate, a gate electrode located in the gate trench and including doped polysilicon, and a dielectric material separating the gate electrode from the semiconductor substrate; and forming a metal silicide region adjacent to the doped polysilicon in an upper center portion of each of the gate electrodes of the power transistor cells.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The elements of the drawings are not necessarily drawn to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. The embodiments are depicted in the drawings and detailed in the following description.

[0008] Figure 1 The diagram shows a partial cross-sectional view of a semiconductor device including a vertical power transistor and a CMOS device monolithically integrated in the same semiconductor die.

[0009] Figures 2A to 2M Illustration of the various stages of a method for producing a semiconductor device. Figure 1 A partial cross-sectional view of a portion of the same semiconductor device.

[0010] Figure 3 A partial top plan view of a CMOS device in the region of two (2) adjacent NMOS and PMOS cells is shown. DETAILED DESCRIPTION

[0011] The embodiments described herein provide a power semiconductor technology that can support monolithic integration of CMOS devices by using metal silicide regions in complementary doped polysilicon. Therefore, the p-doped polysilicon gate for PMOS cells and the n-doped polysilicon gate for NMOS cells and power FETs include metal silicide regions that reduce the gate resistance of all devices and improve signal propagation delay. If isolation is not provided between the NMOS and PMOS cells of the CMOS device, the metal silicide region is included in the gate electrodes of the two CMOS cell types to provide a connection of the pn junction / diode across the boundary of the adjacent NMOS and PMOS cells. The power transistor integrated in the same semiconductor die with the CMOS device is formed by a plurality of power transistor cells, each cell including a gate trench and a gate electrode in the gate trench. The gate electrode of the power transistor cell includes doped polysilicon. The upper center portion of each gate electrode of the power transistor cell is occupied by a metal silicide region adjacent to the doped polysilicon.

[0012] The NMOS and PMOS primitives of a CMOS device monolithically integrated in the same semiconductor die may form part or all of a gate driver that drives a power transistor. For example, in the case of a multi-stage driver, the NMOS and PMOS primitives of a monolithically integrated CMOS device may form the last (output) stage of the gate driver. Some or all of the remaining driver stages may be monolithically integrated in the same semiconductor die as the last stage, or formed in separate semiconductor dies.

[0013] Including a metal silicide region in the complementary doped polysilicon gate enables low and matched threshold NMOS and PMOS devices with a single gate oxide thickness shared with the main power transistors. This enables high performance, high frequency DCDC power supplies for energy efficient servers. Other circuit configurations may be realized using the metal silicide embodiments described herein.

[0014] Next, an embodiment of a power semiconductor technology is described with reference to the accompanying drawings, which supports monolithic integration of CMOS devices by using metal silicide regions in complementary doped polysilicon gates. The embodiments are described in the context of Si (silicon) power semiconductor technology, but the embodiments can be applied to other power semiconductor technologies, such as, for example, SiC (silicon carbide) or GaN on Si, where the main power transistor is a GaN device with a CMOS driver integrated in a silicon substrate.

[0015] Figure 1The illustration includes a partial cross-sectional view of a semiconductor device of a vertical power transistor 'FET' and a CMOS device monolithically integrated in the same semiconductor die. The CMOS device can be the last (output) stage of the gate driver of the vertical power transistor, the entire gate driver, or another logic device used in conjunction with the vertical power transistor. The CMOS device includes an NMOS portion 'NMOS' and a PMOS portion 'PMOS'. The CMOS device may include a single NMOS primitive and a single PMOS primitive or multiple NMOS primitives and multiple PMOS primitives. The vertical power transistor may include tens, hundreds, thousands, or more power transistor primitives. Other primitive layouts and configurations may be conceivable and depend on the target application and requirements. In other words, the embodiments described herein are not intended to be limited to the specific primitive layouts and configurations illustrated.

[0016] The vertical power transistor includes a plurality of power transistor primitives, two of which are shown in FIG. Figure 1 Each cell of the vertical power transistor includes: a source region 100 of a first conductivity type at a first major surface 102 of a semiconductor substrate 104; a drain region 106 of a first conductivity type at a second major surface 108 of the semiconductor substrate 104 opposite to the first major surface 102; a gate trench 110 extending from the first major surface 102 into the semiconductor substrate 104; a gate electrode 112 located in the gate trench 110 and including doped polysilicon 114; and a dielectric material 116, such as silicon oxide (e.g., thermally grown SiO2), separating the gate electrode 112 from the semiconductor substrate 104. Figure 1 The drain region 106 is common to all power transistor cells in the embodiment. The semiconductor substrate 104 may be a bulk Si material, or may include one or more Si epitaxial layers grown on a bulk Si material. In another embodiment, the semiconductor substrate 104 includes SiC.

[0017] Each vertical power transistor cell further comprises a body region 118 of a second conductivity type opposite to the first conductivity type. The source region 100 and the body region 118 of the same power transistor cell are adjacent to at least one sidewall of the corresponding gate trench 110. The source region 214 of each power transistor cell is separated from a (common) drift band 120 of the first conductivity type by the corresponding body region 118. Each vertical power transistor cell may further comprise: a field electrode / field plate 122, located below the gate electrode 112 in each gate trench 110 and dielectrically insulated from the semiconductor substrate 104 by a field dielectric 124. The gate trench 110 of the vertical power transistor may be 'striped' in that the gate trenches 110 are 'striped' in shape in the direction of the gate trench 110. Figure 1 The page in the first main surface 102 of the semiconductor substrate 104 is parallel to the depth direction of the semiconductor substrate 104 ( Figure 1In a direction extending transverse to the z-direction in the ordinate (the z-direction in FIG. 1 ), the gate trench 110 may have a longest linear dimension.

[0018] exist Figure 1 In the figure, the vertical power transistor is illustrated as a vertical power MOSFET. However, alternatively, the vertical power transistor can be an IGBT (insulated gate bipolar transistor). In the case of an IGBT as a vertical power transistor, the same or similar MOS element is used in conjunction with a p-doped region (not shown) at the second main surface 108 of the semiconductor substrate 104 to provide carrier flooding. Therefore, the term 'source region' refers to the source region of a power MOSFET or the emitter region of an IGBT, and the term 'drain region' refers to the drain region of a power MOSFET or the collector region of an IGBT.

[0019] For an n-channel device formed from a power transistor cell, the first conductivity type is n-type and the second conductivity type is p-type, while for a p-channel device formed from a power transistor cell, the first conductivity type is p-type and the second conductivity type is n-type. For either an n-channel device or a p-channel device, the source region 100 and the body region 118 form part of a transistor cell, and the transistor cell is electrically connected in parallel between the source and drain terminals S, D of the power semiconductor device to form a vertical power transistor Q1.

[0020] The body region 118 of the power transistor cell may include a body contact region 126 of the second conductivity type. The body contact region 126 has a higher doping concentration than the body region 118 to provide an ohmic connection to a source / emitter metallization 128 through a contact structure (such as a conductive via 130) extending through a single or multiple interlayer dielectric 132 that separates the source metallization 128 from the semiconductor substrate 104. The source region 100 of the vertical power transistor cell is also electrically connected to the source metallization 128 through the contact structure 130. On the side of the semiconductor substrate 104 opposite the source metallization 128, a drain metallization (such as a conductive via 130) electrically connected to the drain region 106 of the vertical power transistor is provided. Figure 1 Not shown) can be arranged.

[0021] By, for example, Figure 1The gate metallization not visible in the figure, the gate electrode 112 of the vertical power transistor cell is electrically connected to the gate terminal G of the power semiconductor device. The gate metallization can be part of the structured power metallization, which also includes the source metallization 128. Such structured power metallization may include: a thick power metal layer, including Cu, Al, AlCu, AlSiCu, etc.; a diffusion barrier layer and / or an adhesion promoter, such as Ti and / or TiN and / or W, located between the thick power metal layer and the interlayer dielectric 132.

[0022] An upper central portion of each of the gate electrodes 112 of the power transistor cell is occupied by a metal silicide region 134, which is adjacent to the doped polysilicon portion 114 of the gate electrode 112. In one embodiment, the vertical power transistor is an n-channel device, and the doped polysilicon portion 114 of each gate electrode 112 is n-doped. In another embodiment, the vertical power transistor is a p-channel device, and the doped polysilicon portion 114 of each gate electrode 112 is p-doped or n-doped.

[0023] In either case, the metal silicide region 134 adjacent to the doped polysilicon 114 in the upper center portion of each gate electrode 112 may be spaced inwardly from the sidewalls 136 and bottom 138 of each gate trench 110 of the power transistor cell. That is, a portion of the doped polysilicon portion 114 may be interposed between the metal silicide region 134 and the sidewalls 136 and bottom 138 of each gate trench 110. Figure 1 As shown in , the gate trench 110 of the vertical power transistor includes a field electrode / field plate 122 located below the gate electrode 112, and the metal silicide region 134 can be separated upward from the portion of the field dielectric 124 that separates the gate electrode 112 from the field electrode / field plate 122 in the vertical direction. That is, a portion of the doped polysilicon 114 can separate the metal silicide region 134 from the portion of the field dielectric 124 that is inserted between the gate electrode 112 and the field electrode / field plate 122 in the vertical direction.

[0024] like Figure 1 As shown in , the upper surface 140 of the doped polysilicon 114 may have a recess 142 that is laterally inwardly separated from the sidewall 138 of each gate trench 110 of the power transistor cell, and the metal silicide region 134 may be formed along the sidewalls and bottom of the recess 142 in each of the gate trenches 110. For example, the metal silicide region 134 may include cobalt silicide. Both oxides and nitrides prevent the formation of cobalt silicide. Therefore, at least a portion of the upper surface 140 of the doped polysilicon 114 must be free of dielectric material to define a window in which cobalt silicide can be formed on the doped polysilicon 114.

[0025] The dielectric window opening process may involve over-etching of the doped polysilicon 114 to ensure that no residual dielectric material remains in the target area, which results in a recess 142, for example, as later incorporated into the Figures 2A to 2M Alternatively, a target area of ​​the upper surface 140 of the doped polysilicon 114 can be cleaned with minimal overetching / recessing of the doped polysilicon 114, or even without overetching / recessing of the doped polysilicon 114. In either case, cobalt silicide can then be formed on the dielectric-free portions of the doped polysilicon 114, including on the exposed sidewalls and bottom of the recess 142 formed in the doped polysilicon 114 (if the recess 142 exists).

[0026] In one embodiment, for each of the gate electrodes 112 of the power transistor cell, the recess 142 etched in the doped polysilicon 114 is in a range of up to 25% of the thickness Tg of the gate electrode 112. Separately or in combination, below the first major surface 102 of the semiconductor substrate 104, the recess 142 may be in a range of, for example, 1 nm to 100 nm, 5 nm to 70 nm, 10 nm to 50 nm, etc.

[0027] like Figure 1 As shown in , the upper surface 140 of each gate electrode 112 of the power transistor cell may be recessed below the first major surface 102 of the semiconductor substrate 104. Alternatively, the upper surface 140 of each gate electrode 112 may be coplanar with the first major surface 102 of the semiconductor substrate 104. Whether the upper surface 140 of each gate electrode 112 is coplanar with the first major surface 102 of the semiconductor substrate 104 depends on, for example, Figures 2A to 2M In addition, Figure 1 As shown in , the upper surface 140 of each gate electrode 112 of the power transistor cell may be completely covered with oxide only. Figure 1 In the embodiment of the present invention, the capping oxide is the interlayer dielectric 132. The capping oxide may include a single layer or multiple layers of oxide and may include all the same oxide composition (e.g., deposited oxide) or a combination of oxide compositions (e.g., thermally grown oxide and deposited oxide). One or more layers of different dielectric materials (such as silicon nitride) may be formed on the capping oxide.

[0028] As described above, the semiconductor device may include a CMOS device, such as a gate driver or a portion of a gate driver, that is monolithically integrated with a vertical power transistor in the same semiconductor substrate 104. The CMOS device includes one or more PMOS cells and one or more NMOS cells. Each PMOS cell and each NMOS cell of the CMOS device includes: a source region 144 at the first major surface 102 of the semiconductor substrate 104; a drift region 146; a gate trench 148 extending from the first major surface 102 into the semiconductor substrate 104; a gate electrode 150 located in the gate trench 148 and including doped polysilicon 152; and a dielectric material 154, such as silicon oxide (e.g., thermally grown SiO2), separating the gate electrode 150 from the semiconductor substrate 104.

[0029] Each NMOS and PMOS cell of the CMOS device also includes a body region 156 of a conductivity type opposite to the source region 144 of the same CMOS cell type. The source region 144 and the body region 156 of the same CMOS cell type are adjacent to at least one sidewall of the corresponding gate trench 148. The gate trench 148 of the CMOS device can be stripe-shaped. For the NMOS cell, the source region, drift region and drain region 144, 146, 164 are n-type, and the body region 156 is p-type. Conversely, for the PMOS cell, the source region, drift region and drain region 144, 146, 164 are p-type, and the body region 156 is n-type. If the semiconductor substrate 104 has an n-type background doping, the drift region 146 of the PMOS cell can be part of a p-well.

[0030] The body region 156 of the CMOS cell may include a body contact region 158 of the same conductivity type as the body region 156 of the same CMOS cell type (e.g., p+ for NMOS cells and n+ for PMOS cells). The body contact region 158 has a higher doping concentration than the corresponding body region 156 to provide an ohmic connection to the source metallization 160 through a contact structure (e.g., conductive via 162) extending through the interlayer dielectric 132 that separates the source metallization 160 from the semiconductor substrate 104. Only the PMOS source metallization 160 is in Figure 1 is visible in.

[0031] A highly doped drain region 164 of each CMOS cell type (e.g., n+ for NMOS cells and p+ for PMOS cells) provides an ohmic connection to the drain metallization 166 through a contact structure (such as a conductive via 168) extending through the interlayer dielectric 132. Figure 1 is visible in.

[0032] In contrast to the vertical power transistor drain connection made on the back side of the substrate, Figure 1 Drain connections to each NMOS and PMOS cell of the CMOS device are made from the front side of the semiconductor substrate 104 in the CMOS device. For example, adjacent gate trenches 148 of the same CMOS cell type may be separated from each other laterally by a dielectric mesa 170, and contacts 168 may extend through the dielectric mesa 170 to or into the semiconductor substrate 104 to provide drain connections. The dielectric mesa 170 may include, for example, TEOS (tetraethoxysilane) sidewall spacers 172 and oxide fillers 174. Other cell layouts and configurations may be envisioned and depend on the target application and requirements. For example, although Figure 1 A recessed drain configuration for a CMOS device is shown, but other drain configurations are possible, for example, the dielectric mesa 170 may be omitted and the source and drain regions 144 , 164 of the CMOS cell may be coplanar at the first major surface 102 of the semiconductor substrate 104 .

[0033] The gate electrode 150 of the CMOS cell is electrically connected to the Figure 1 The gate metallization is not visible in the CMOS. The CMOS metallization can be part of the same structured power metallization used for vertical power transistors.

[0034] Like the vertical power transistor cells, the upper center portion of each CMOS gate electrode 150 is occupied by a metal silicide region 176, which is adjacent to the doped polysilicon portion 152 of the CMOS gate electrode 150. In one embodiment, the vertical power transistor is an n-channel device, the doped polysilicon 134 in each gate trench 110 of the power transistor cell is n-doped, the doped polysilicon 152 in the gate trench 148 of each NMOS cell of the CMOS device is n-doped, and the doped polysilicon 152 in the gate trench 148 of each PMOS cell of the CMOS device is p-doped or n-doped. In another embodiment, the vertical power transistor is a p-channel device, the doped polysilicon 134 in each gate trench 110 of the power transistor cell is p-doped or n-doped, the doped polysilicon 152 in the gate trench 148 of each NMOS cell of the CMOS device is n-doped, and the doped polysilicon 152 in the gate trench 148 of each PMOS cell of the CMOS device is p-doped or n-doped.

[0035] In either case, providing a metal silicide region 176 in the CMOS gate electrode 150 reduces the gate resistance of both CMOS device types, which is particularly beneficial for p-doped polysilicon because the resistance of p-doped polysilicon is greater than that of n-doped polysilicon for equivalent doping levels. However, during source implantation, p- or n-doping of the polysilicon in the CMOS gate electrode 150 can be performed, which can result in a higher gate resistance than when deposited p- or n-doped polysilicon is used. Therefore, providing a metal silicide region 176 in the gate electrode 150 of an NMOS cell can be beneficial. In addition, narrower cell sizes result in increased gate resistance, which can be reduced by including metal or silicide in the CMOS gate electrode 150.

[0036] If the metal silicide region 176 of the CMOS device and the metal silicide region 134 of the vertical power transistor are formed by common processing steps, for example, Figure 2L and 2M , the metal silicide region 176 of the CMOS device may have the same configuration as the metal silicide region 134 of the vertical power transistor. For example, the metal silicide region 176 adjacent to the doped polysilicon portion 152 of each CMOS gate electrode 150 may be spaced inwardly from the sidewalls 178 and the bottom 180 of each gate trench 150 of the CMOS cell. In another example, the upper surface 182 of the doped polysilicon 152 may have a recess 184 that is laterally spaced inwardly from the sidewalls 178 of each CMOS gate trench 148, and the metal silicide region 176 may be formed along the sidewalls and the bottom of the recess 184 in each of the CMOS gate trenches 148.

[0037] The isolation structure 186 ensures sufficient isolation in the semiconductor substrate 104 between the CMOS device and the vertical power transistor. Another isolation structure 188 may be provided between the NMOS and PMOS portions of the CMOS device. The isolation structures 186, 188 may include, for example, trenches filled with an electrically insulating material such as an oxide. For example, the isolation structure 186 between the CMOS device and the vertical power transistor may be a deep trench isolation structure extending through the entire depth of the semiconductor substrate 104. The isolation 188 between the NMOS and PMOS portions of the CMOS device does not need to pass through the semiconductor substrate 104 all the way. For example, junction isolation may be used, where a version of a p-well or deeper vertical FET trench can be used as an isolation structure. In this case, the gate and source features of the trench are not connected.

[0038] Figures 2A to 2M Illustration of the various stages of a method for producing a semiconductor device. Figure 1 A partial cross-sectional view of a portion of the same semiconductor device.

[0039] Figure 2A The semiconductor substrate 104 is shown after an isolation structure 186 is formed in the semiconductor substrate 104 between the CMOS device and the vertical power transistor and an optional isolation structure 188 is formed in the semiconductor substrate 104 between the NMOS and PMOS portions of the CMOS device. Figure 2A The semiconductor substrate 104 is also shown after a hard mask layer 200, such as a deposited or thermally grown oxide, is formed on the first major surface 102 of the semiconductor substrate 104. For example, using a photolithography process, the hard mask layer 200 is etched to form openings 202 in the hard mask layer 200. The device gate trenches 110, 148 are then etched into the first major surface 102 of the semiconductor substrate 104 through the openings 202 in the hard mask layer 200.

[0040] If the gate trench 110 of the vertical power transistor extends deeper in the semiconductor substrate 104 than the CMOS gate trench 148, for example to accommodate the field electrode / field plate 122, both types of device gate trenches 110, 148 can be etched to a first depth corresponding to the depth of the CMOS gate trench 148. For example, using a photolithography process, the CMOS gate trench 148 can then be covered, and the gate trench 110 of the vertical power transistor etched deeper in the semiconductor substrate 104 while the CMOS gate trench 148 is covered.

[0041] Figure 2B The semiconductor substrate 104 is shown after the hard mask layer 200 is removed and a field oxide 204 is formed on the first major surface 102 of the semiconductor substrate 104. For example, the field oxide 204 can be thermally grown or deposited SiO2 or both. Another dielectric material can be used for the field oxide 204. Polycrystalline silicon (i.e., poly-Si) 206 is then deposited on the field oxide 204. The polycrystalline silicon 206 can be heavily doped, for example with phosphorus.

[0042] Figure 2C The semiconductor substrate 104 is shown after polysilicon 206 has been removed from the CMOS gate trench 148 and recessed in the power transistor gate trench 110 to define an optional field electrode / field plate 122. The polysilicon 206 can be removed from the first major surface 102 of the semiconductor substrate 104 by stopping the CMP (chemical mechanical polishing) on ​​the field oxide 204. Plasma recessing of the polysilicon 206 can then be performed to the desired depth of the power transistor field electrode / field plate 122. The recess depth is selected to be sufficient to remove all of the polysilicon 206 from the CMOS gate trench 148. The field electrode / field plate 122 is formed at the bottom of the power transistor gate trench 110. Figure 2C2 as including only polysilicon 206. However, the field electrode / field plate 122 may alternatively be made of metal, silicide, TiN, or a combination thereof.

[0043] Figure 2D The semiconductor substrate 104 is shown after etching of the exposed field oxide 204 and a subsequent oxide formation process. The oxide formation process may include HDP (high density plasma) deposition of oxide to fill all device trenches 110, 148, followed by a planarization process (such as CMP) that stops on the semiconductor mesas between the gate trenches 110, 148. A wet recess etch of the oxide in the trenches 110, 148 is then performed to the depth required for the power transistor channel and to provide dielectric isolation from the field electrode / field plate 122, resulting in Figure 1 1. The field oxide 124 can remain at the bottom of the CMOS gate trench 148 to cover the transistor drift region along this portion of the CMOS gate trench 148. A thicker oxide 124 in the CMOS device region reduces the capacitance (Cgd) between the gate and the drain.

[0044] Figure 2E The semiconductor substrate 104 is shown after forming gate oxides 116, 154 and gate electrodes 112, 150 in both device regions. According to this embodiment, the gate oxides 116, 154 and gate electrodes 112, 150 of both device types are formed using a common process. The gate oxides 116, 154 may be formed by oxide deposition or thermal growth. The gate electrodes 112, 150 may be formed by depositing polycrystalline or amorphous silicon on the first major surface 102 of the semiconductor substrate 104 and in the gate trenches 110, 148 of both device types.

[0045] For example, via CMP, the polycrystalline or amorphous silicon is then removed outside of the gate trenches 110, 148. Optionally, a recess etch may be performed to recess the polycrystalline or amorphous silicon below the first major surface 102 of the semiconductor substrate 104 in the gate trenches 110, 148 of one or both device types. For example, a plasma etch selective to SiO2 may be used so that the gate oxide material remains on the first major surface 102 of the semiconductor substrate 104 between the gate trenches 110, 148. For example, the polycrystalline or amorphous silicon may be recessed about 100 nm below the first major surface 102 of the semiconductor substrate 104 to optimize the device and improve manufacturability. Alternatively, the polycrystalline or amorphous silicon is not recessed below the first major surface 102 of the semiconductor substrate 104.

[0046] Figure 2FThe semiconductor substrate 104 is shown after the device region of the PMOS cell is formed. An implant mask 208 (such as a photoresist) that is thick enough to block high energy implants protects both the power transistor region and the NMOS portion of the CMOS device. A high energy implant of a p-type dopant species (such as boron) is then performed to define the drift / p-well region 146 of each PMOS cell, using an energy sufficient to counter-dope the n-type epitaxial layer 209 to p-type and a dose optimized to produce a desired breakdown voltage. An n-type dopant species (such as arsenic or phosphorus) is implanted to define the body region 156 of each PMOS cell. A high dose implant of a p-type dopant species (such as boron or BF2) defines the source region 144 and dopes the polysilicon / amorphous Si gate electrode 150 to p-type in each PMOS cell. The implant mask 208 is then removed, and an anneal is performed to drive in the p-type dopant, thereby doping the polycrystalline or amorphous silicon 152 in the PMOS gate trench 148. Alternatively, the polycrystalline or amorphous silicon 152 in the PMOS gate trench 148 may be n-doped.

[0047] Figure 2G The semiconductor substrate 104 is shown after the device regions of the CMOS cell and the power transistor cell are simultaneously formed. According to this embodiment, the gate electrode 112 of each power transistor cell and the gate electrode 150 of each NMOS cell are simultaneously doped with a dopant species of a first doping type while each PMOS cell is masked. More particularly, the implantation mask 210 (such as a photoresist) can protect the PMOS portion of the CMOS device. For example, the drift region 146 of each NMOS cell and the drift region 120 of each power transistor cell can be realized by background doping of the semiconductor substrate 104. A p-type dopant species (such as boron or BF2) is implanted to define the body region 156 of each NMOS cell and the body region 118 of each power transistor cell. A high dose implantation of an n-type dopant species (such as arsenic or phosphorus) defines the source region 144 and the source region 100 of each NMOS cell, and dopes the polysilicon / amorphous Si gate electrode 112 to N-type in each power transistor cell. Implant mask 210 is then removed and an anneal is performed to drive in n-type dopants, thereby doping poly or amorphous silicon 152 in NMOS gate trench 148 and doped poly or doped amorphous silicon 114 in power transistor gate trench 110. Drain region 106 of the vertical power transistor is not visible and can be formed earlier or later.

[0048] Figure 2H The semiconductor substrate 104 is shown after an oxide 212 has been deposited on the first major surface 102 of the semiconductor substrate 104. If the gate electrodes 112, 150 were previously recessed, e.g. Figure 2EAs shown in , the oxide 212 fills the recess in the gate electrode 112 , 150 .

[0049] Fig.2I The semiconductor substrate 104 is shown after the oxide 212 has been planarized, for example, by CMP. If the gate electrodes 112, 150 were previously recessed, for example, Figure 2E As shown in , the CMP stops on the semiconductor mesa between the gate trenches 110 , 148 .

[0050] Figure 2J The semiconductor substrate 104 is shown after etching the semiconductor substrate 104 to form a recess 214 between adjacent gate trenches 148 of the same primitive type of CMOS device. An etch mask 216 (such as a photoresist) exposes the drain mesa and protects the source mesa in the CMOS device area, and also protects the vertical power transistor area. A selective isotropic silicon plasma etch (such as SF6) can be used, and it is highly selective to the oxide that protects the CMOS gate dielectric material 154 from the top and sides. The etch mask 216 is then removed.

[0051] Figure 2K The semiconductor substrate 104 is shown after filling the recess 214 in the CMOS device area with a dielectric material 218 and covering the first major surface 102 of the semiconductor substrate 104. The recess filling process may include TEOS deposition to form sidewall spacers 172, followed by deposition of an oxide filler 174. The oxide filler 174 can be formed by depositing USG (undoped silicate glass) and HDP oxide.

[0052] Figure 2L The semiconductor substrate 104 is shown after planarizing the upper surface of the dielectric material 218 facing away from the semiconductor substrate 104 to form dielectric mesas in the recesses between adjacent gate trenches 148 of the same CMOS (NMOS or PMOS) cell type. For example, the upper surface of the dielectric material 218 can be planarized by a timed CMP process that leaves a thin oxide layer (e.g., 20 nm to 150 nm) on the semiconductor mesas between adjacent gate trenches 110, 148. The planarized upper surface of the dielectric material 218 is then covered by a photoresist 220 having an opening 222 that is aligned in a vertical direction with the gate electrode 112 of the vertical power transistor and the gate electrode 150 of the CMOS device. For example, alignment marks can be used to ensure vertical alignment.

[0053] An opening is then formed in the dielectric material 218, aligned in the vertical direction with the opening 222 of the photoresist 220. Optionally, the exposed gate electrodes 112 of the vertical power transistors and the gate electrodes 150 of the CMOS devices may be recessed through the opening 222 of the photoresist 220 and the opening 224 of the dielectric material to ensure that no residual dielectric material remains in the desired area targeted for metal silicide formation. According to this embodiment, a recess 142 is formed in the upper center portion of the doped polycrystalline or doped amorphous silicon 114 of each power transistor gate electrode 112, and in the upper center portion of the doped polycrystalline or doped amorphous silicon 152 of each CMOS gate electrode 150. The recess 142 in the vertical power transistor portion and the recess 184 in the CMOS portion may be in the range of up to 25% of the thickness Tg of the respective gate electrodes 112, 150. Separately or in combination, the recesses 142, 184 may be in the range of 1 nm to 100 nm, 5 nm to 70 nm, 10 nm to 50 nm, etc., below the first major surface 102 of the semiconductor substrate 104. Alternatively, a target area of ​​the upper surface 140 of the doped polycrystalline or doped amorphous silicon 114, 152 can be cleaned with minimal or even no over-etching / recessing of the doped polycrystalline or doped amorphous silicon 114, 152.

[0054] Figure 2M The semiconductor substrate 104 is shown after removing the photoresist 220 and then forming metal silicide regions 134, 176 in the corresponding gate trenches 110, 148. The metal silicide regions 134, 176 may be formed by depositing cobalt on the first major surface 102 of the semiconductor substrate 104 so that the cobalt contacts the dielectric-free portion of the power transistor gate electrode 112 and the dielectric-free portion of the CMOS gate electrode 150. As explained above, the dielectric-free portion of the power transistor gate electrode 112 and the dielectric-free portion of the CMOS gate electrode 150 may or may not be recessed. If Figure 2L , the recesses 142, 184 are spaced laterally inwardly from the sidewalls of the corresponding gate trenches 110, 148, and cobalt is deposited along the sidewalls 226 and bottom 228 of the recesses 142, 184 in each gate trench 110, 148. On the other hand, each gate electrode 112, 150 has a planar upper surface 140, 182, and cobalt is deposited along the planar upper surface 140, 182 of each gate electrode 112, 150. In either case, the cobalt is then annealed to form the metal silicide regions 134, 176.

[0055] In one embodiment, by, for example, Figure 2LThe power transistor gate electrode 112 and the CMOS gate electrode 150 are recessed as shown in , cobalt is deposited on the first main surface 102 of the semiconductor substrate 104 so that the cobalt contacts the recessed portion 142 of each gate electrode 112 of the vertical power transistor and the recessed portion 184 of each gate electrode 150 of the CMOS device, and titanium or TiN is deposited on the cobalt, and the metal silicide region 134, 176 is formed in the upper center portion of the power transistor gate electrode 112 and in the upper center portion of the CMOS gate electrode 150. A first low temperature annealing process (e.g., in a range of, for example, between 550°C and 650°C) is then performed in a nitrogen environment. The first annealing process produces CoSi in contact with the recessed portion 142 of each gate electrode 112 of the vertical power transistor and the recessed portion 184 of each gate electrode 150 of the CMOS device. The first annealing process also produces a TiN layer on the CoSi. Using a suitable wet etching process, the TiN layer and the unreacted Co are removed. A second annealing process is then performed at a temperature higher than the first annealing process but less than 900° C. to form lower resistivity CoSi 2 .

[0056] After forming the metal silicide regions 134, 176, Figure 1 The source, body, and drain contacts shown in FIG. 1 are then formed. The interlayer dielectric 132 is completed, for example, by depositing BPSG (boron phosphosilicate glass). The interlayer dielectric 132 is then planarized, for example, by CMP. Contact photolithography, etching, and metal deposition processes are then performed to form Figure 1 The desired contactor is shown in FIG. Other primitive layouts and configurations can be envisioned and depend on the target application and requirements. In other words, the embodiments described herein are not intended to be limited to the specific primitive layouts and configurations shown.

[0057] Figure 3 A partial top plan view of a CMOS device in the region of two (2) adjacent NMOS and PMOS cells is shown. Figure 3 In the embodiment, no isolation is provided between the NMOS and PMOS cells of the CMOS device. According to this embodiment, the metal silicide region 176 occupying the upper center portion of each of the gate electrodes 150 of the CMOS device provides a connection of the pn junction / diode 300 across the boundary of the adjacent NMOS and PMOS cells.

[0058] Although the present disclosure is not limited in this regard, the following numbered examples demonstrate one or more aspects of the present disclosure.

[0059] Example 1. A semiconductor device, comprising: a vertical power transistor, comprising a plurality of power transistor cells, wherein each of the power transistor cells comprises a source region at a first major surface of a semiconductor substrate, a drain region at a second major surface of the semiconductor substrate opposite to the first major surface, a gate trench extending from the first major surface into the semiconductor substrate, a gate electrode located in the gate trench and comprising doped polysilicon, and a dielectric material separating the gate electrode from the semiconductor substrate, wherein an upper central portion of each of the gate electrodes of the power transistor cells is occupied by a metal silicide region, the metal silicide region being adjacent to the doped polysilicon.

[0060] Example 2. The semiconductor device of Example 1, wherein the vertical power transistor is an n-channel device, and wherein the doped polysilicon is n-doped.

[0061] Example 3. The semiconductor device of Example 1, wherein the vertical power transistor is a p-channel device, and wherein the doped polysilicon is p-doped or n-doped.

[0062] Example 4. The semiconductor device of any of Examples 1 to 3, wherein the metal silicide region is spaced inwardly from a sidewall and a bottom of each of the gate trenches of the power transistor cell.

[0063] Example 5. A semiconductor device as described in any one of Examples 1 to 4, wherein the upper surface of the doped polysilicon has a recessed portion, the recessed portion being laterally inwardly spaced apart from the sidewall of each of the gate trenches of the power transistor cell, and wherein the metal silicide region is formed along the sidewall and bottom of the recessed portion in each of the gate trenches of the power transistor cell.

[0064] Example 6. The semiconductor device of Example 5, wherein for each of the gate electrodes, the recess is in a range of up to 25% of a thickness of the gate electrode.

[0065] Example 7. The semiconductor device of Example 5 or 6, wherein for each of the gate electrodes, the recess is in a range of 10 nm to 100 nm below the first major surface of the semiconductor substrate.

[0066] Example 8. A semiconductor device as described in any one of Examples 1 to 7, further comprising: a CMOS (complementary metal oxide semiconductor) device, monolithically integrated in the same semiconductor substrate as the vertical power transistor, and comprising one or more PMOS cells and one or more NMOS cells, wherein each PMOS cell and each NMOS cell of the CMOS device comprises a source region at the first main surface, a drift region, a gate trench extending from the first main surface into the semiconductor substrate, a gate electrode located in the gate trench and comprising doped polysilicon, and a dielectric material separating the gate electrode from the semiconductor substrate, wherein an upper central portion of each of the gate electrodes of the CMOS device is occupied by a metal silicide region, and the metal silicide region is adjacent to the doped polysilicon.

[0067] Example 9. The semiconductor device of Example 8, wherein adjacent gate trenches of the same primitive type of the CMOS device are laterally separated from each other by a dielectric mesa surface, and wherein a contact extends through the dielectric mesa surface to or into the semiconductor substrate to provide a drain connection.

[0068] Example 10. The semiconductor device of Example 8 or 9, wherein the vertical power transistor is an n-channel device, wherein the doped polysilicon in each of the gate trenches of the power transistor cell is n-doped, wherein the doped polysilicon in the gate trench of each NMOS cell of the CMOS device is n-doped, and wherein the doped polysilicon in the gate trench of each PMOS cell of the CMOS device is p-doped or n-doped.

[0069] Example 11. A semiconductor device as described in Example 8 or 9, wherein the vertical power transistor is a p-channel device, wherein the doped polysilicon in each of the gate trenches of the power transistor cells is p-doped or n-doped, wherein the doped polysilicon in the gate trench of each NMOS cell of the CMOS device is n-doped, and wherein the doped polysilicon in the gate trench of each PMOS cell of the CMOS device is p-doped or n-doped.

[0070] Example 12. The semiconductor device of any one of Examples 8 to 11, wherein the upper surface of the doped polysilicon has a recess that is laterally inwardly spaced from a sidewall of each of the gate trenches of both the vertical power transistor and the CMOS device, and wherein the metal silicide region is formed along the sidewall and bottom of the recess in each of the gate trenches of both the vertical power transistor and the CMOS device.

[0071] Example 13. The semiconductor device of any of Examples 8 to 12, wherein the metal silicide region occupying the upper central portion of the gate electrode of adjacent NMOS and PMOS cells provides connection across a pn junction at a boundary of adjacent NMOS and PMOS cells.

[0072] Example 14. The semiconductor device of any of Examples 1 to 13, wherein an upper surface of each of the gate electrodes is coplanar with the first major surface of the semiconductor substrate.

[0073] Example 15. The semiconductor device of any of Examples 1 to 13, wherein an upper surface of each of the gate electrodes is recessed below the first major surface of the semiconductor substrate.

[0074] Example 16. The semiconductor device of any one of Examples 1 to 15, wherein an upper surface of each of the gate electrodes is completely covered only with oxide.

[0075] Example 17. A method of producing a semiconductor device, the method comprising: forming a vertical power transistor having a plurality of power transistor cells, wherein each of the power transistor cells comprises a source region at a first major surface of a semiconductor substrate, a drain region at a second major surface of the semiconductor substrate opposite to the first major surface, a gate trench extending from the first major surface into the semiconductor substrate, a gate electrode located in the gate trench and comprising doped polysilicon, and a dielectric material separating the gate electrode from the semiconductor substrate; and forming a metal silicide region adjacent to the doped polysilicon in an upper center portion of each of the gate electrodes of the power transistor cells.

[0076] Example 18. The method as described in Example 17 further includes: monolithically integrating a CMOS (complementary metal oxide semiconductor) device in the same semiconductor substrate as the vertical power transistor, the CMOS device including one or more PMOS cells and one or more NMOS cells, wherein each PMOS cell and each NMOS cell of the CMOS device includes a source region at the first main surface, a drift region, a gate trench extending from the first main surface into the semiconductor substrate, a gate electrode located in the gate trench and including doped polysilicon, and a dielectric material separating the gate electrode from the semiconductor substrate; and forming a metal silicide region adjacent to the doped polysilicon in an upper center portion of each of the gate electrodes of the CMOS device.

[0077] Example 19. The method as described in Example 18 further includes: before forming the metal silicide region in the upper central portion of each gate electrode of the vertical power transistor and before forming the metal silicide region in the upper central portion of each gate electrode of the CMOS device, while each PMOS cell is masked, the gate electrode of each power transistor cell and the gate electrode of each NMOS cell are doped with a dopant species of a first doping type, and while each power transistor cell and each NMOS cell are masked, the gate electrode of each PMOS cell is doped with a dopant species of the first doping type or a dopant species of a second doping type opposite to the first doping type.

[0078] Example 20. The method as described in Example 18 or 19 further includes: after doping the polycrystalline or amorphous silicon in each gate electrode of the CMOS device and doping the polycrystalline or amorphous silicon in each gate electrode of the vertical power transistor, etching the semiconductor substrate to form a recess between adjacent gate trenches of the same primitive type of the CMOS device; forming a dielectric mesa surface in the recess between adjacent gate trenches of the same primitive type of the CMOS device; and after forming the metal silicide region, forming a contact extending through the dielectric mesa surface to or into the semiconductor substrate.

[0079] Example 21. The method of Example 20, wherein forming the dielectric mesa surface in the recess comprises: filling the recess with a dielectric material and covering the first major surface of the semiconductor substrate; and planarizing an upper surface of the dielectric material facing away from the semiconductor substrate.

[0080] Example 22. The method of Example 21, wherein forming the metal silicide region in the upper central portion of each gate electrode of the vertical power transistor and forming the metal silicide region in the upper central portion of each gate electrode of the CMOS device comprises: covering the planarized upper surface of the dielectric material with a photoresist, the photoresist having an opening, the opening being aligned in a vertical direction with the gate electrode of the vertical power transistor and the gate electrode of the CMOS device; forming an opening in the dielectric material, the opening being aligned in a vertical direction with the opening of the photoresist; after filling the recess with the dielectric material and covering the first major surface of the semiconductor substrate, removing the photoresist; recessing the gate electrode of the vertical power transistor and the gate electrode of the CMOS device through the opening of the photoresist and the opening of the dielectric material; after removing the photoresist, depositing cobalt on the first major surface of the semiconductor substrate so that the cobalt contacts the recessed gate electrode of the vertical power transistor and the recessed gate electrode of the CMOS device; and annealing the cobalt.

[0081] Example 23. A method as described in any one of Examples 18 to 22, wherein forming the metal silicide region in the upper center portion of each gate electrode of the vertical power transistor and forming the metal silicide region in the upper center portion of each gate electrode of the CMOS device comprises: recessing the gate electrode of the vertical power transistor and the gate electrode of the CMOS device; depositing cobalt on the first main surface of the semiconductor substrate so that the cobalt contacts the recessed portion of each gate electrode of the vertical power transistor and the recessed portion of each gate electrode of the CMOS device; depositing titanium on the cobalt; performing a first annealing process, the first annealing process producing CoSi in contact with the recessed portion of each gate electrode of the vertical power transistor and the recessed portion of each gate electrode of the CMOS device, and producing a TiN layer on the CoSi; removing the TiN layer and unreacted Co; and performing a second annealing process at a temperature higher than the first annealing process but less than 1000°C.

[0082] Terms such as "first", "second", etc. are used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Similar terms refer to similar elements throughout the description.

[0083] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0084] It will be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

[0085] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device comprising: A vertical power transistor comprising a plurality of power transistor primitives, wherein each of the power transistor primitives comprises a source region at a first main surface of a semiconductor substrate, a drain region at a second main surface of the semiconductor substrate opposite to the first main surface, a gate trench extending from the first main surface into the semiconductor substrate, a gate electrode located in the gate trench and comprising doped polysilicon, and a dielectric material separating the gate electrode from the semiconductor substrate, An upper central portion of each of the gate electrodes of the power transistor cell is occupied by a metal silicide region, the metal silicide region being adjacent to the doped polysilicon.

2. The semiconductor device of claim 1, wherein the vertical power transistor is an n-channel device, and wherein the doped polysilicon is n-doped.

3. The semiconductor device of claim 1, wherein the vertical power transistor is a p-channel device, and wherein the doped polysilicon is p-doped or n-doped. 4 . The semiconductor device of claim 1 , wherein the metal silicide region is spaced inwardly from a sidewall and a bottom of each of the gate trenches of the power transistor cell.

5. A semiconductor device as described in claim 1, wherein the upper surface of the doped polysilicon has a recess, which is separated from the sidewalls of each of the gate trenches of the power transistor cell laterally inward, and wherein the metal silicide region is formed along the sidewalls and bottom of the recess in each of the gate trenches of the power transistor cell. 6 . The semiconductor device according to claim 5 , wherein for each of the gate electrodes, the recessed portion is in a range of up to 25% of a thickness of the gate electrode. 7 . The semiconductor device of claim 5 , wherein for each of the gate electrodes, the recess is in a range of 10 nm to 100 nm below the first major surface of the semiconductor substrate.

8. The semiconductor device according to claim 1, further comprising: a CMOS (Complementary Metal Oxide Semiconductor) device monolithically integrated in the same semiconductor substrate as the vertical power transistor and comprising one or more PMOS cells and one or more NMOS cells, wherein each PMOS cell and each NMOS cell of the CMOS device comprises a source region at the first main surface, a drift region, a gate trench extending from the first main surface into the semiconductor substrate, a gate electrode located in the gate trench and comprising doped polysilicon, and a dielectric material separating the gate electrode from the semiconductor substrate, An upper central portion of each of the gate electrodes of the CMOS device is occupied by a metal silicide region, and the metal silicide region is adjacent to the doped polysilicon.

9. The semiconductor device of claim 8, wherein adjacent gate trenches of the same primitive type of the CMOS device are laterally separated from each other by a dielectric mesa surface, and wherein a contact extends through the dielectric mesa surface to or into the semiconductor substrate to provide a drain connection.

10. A semiconductor device as described in claim 8, wherein the vertical power transistor is an n-channel device, wherein the doped polysilicon in each of the gate trenches of the power transistor cell is n-doped, wherein the doped polysilicon in the gate trench of each NMOS cell of the CMOS device is n-doped, and wherein the doped polysilicon in the gate trench of each PMOS cell of the CMOS device is p-doped or n-doped.

11. The semiconductor device of claim 8, wherein the vertical power transistor is a p-channel device, wherein the doped polysilicon in each of the gate trenches of the power transistor cell is p-doped or n-doped, wherein the doped polysilicon in the gate trench of each NMOS cell of the CMOS device is n-doped, and wherein the doped polysilicon in the gate trench of each PMOS cell of the CMOS device is p-doped or n-doped.

12. The semiconductor device of claim 8 , wherein the upper surface of the doped polysilicon has a recess that is laterally inwardly separated from the sidewalls of each of the gate trenches of both the vertical power transistor and the CMOS device, and wherein the metal silicide region is formed along the sidewalls and bottom of the recess in each of the gate trenches of both the vertical power transistor and the CMOS device.

13. The semiconductor device of claim 8, wherein the metal silicide region occupying the upper central portion of the gate electrode of adjacent NMOS and PMOS cells provides connection across a pn junction at a boundary of adjacent NMOS and PMOS cells. 14 . The semiconductor device of claim 1 , wherein an upper surface of each of the gate electrodes is coplanar with the first major surface of the semiconductor substrate. 15 . The semiconductor device according to claim 1 , wherein an upper surface of each of the gate electrodes is recessed below the first major surface of the semiconductor substrate. 16 . The semiconductor device according to claim 1 , wherein an upper surface of each of the gate electrodes is completely covered with only oxide.

17. A method for producing a semiconductor device, the method comprising: forming a vertical power transistor having a plurality of power transistor cells, wherein each of the power transistor cells comprises a source region at a first major surface of a semiconductor substrate, a drain region at a second major surface of the semiconductor substrate opposite to the first major surface, a gate trench extending from the first major surface into the semiconductor substrate, a gate electrode located in the gate trench and comprising doped polysilicon, and a dielectric material separating the gate electrode from the semiconductor substrate; and A metal silicide region is formed in an upper central portion of each of the gate electrodes of the power transistor cell adjacent to the doped polysilicon.

18. The method of claim 17, further comprising: monolithically integrating a CMOS (complementary metal oxide semiconductor) device in the same semiconductor substrate as the vertical power transistor, the CMOS device comprising one or more PMOS cells and one or more NMOS cells, wherein each PMOS cell and each NMOS cell of the CMOS device comprises a source region at the first major surface, a drift region, a gate trench extending from the first major surface into the semiconductor substrate, a gate electrode located in the gate trench and comprising doped polysilicon, and a dielectric material separating the gate electrode from the semiconductor substrate; and A metal silicide region is formed in an upper center portion of each of the gate electrodes of the CMOS device adjacent to the doped polysilicon.

19. The method of claim 18, further comprising: Before forming the metal silicide region in the upper center portion of each gate electrode of the vertical power transistor and before forming the metal silicide region in the upper center portion of each gate electrode of the CMOS device, the gate electrode of each power transistor cell and the gate electrode of each NMOS cell are doped simultaneously with a first doping type dopant while each PMOS cell is masked, and the gate electrode of each PMOS cell is doped with a first doping type dopant or a second doping type dopant opposite to the first doping type while each power transistor cell and each NMOS cell are masked.

20. The method of claim 18, further comprising: After doping the polycrystalline or amorphous silicon in each gate electrode of the CMOS device and doping the polycrystalline or amorphous silicon in each gate electrode of the vertical power transistor, etching the semiconductor substrate to form a recess between adjacent gate trenches of the same primitive type of the CMOS device; forming a dielectric mesa surface in the recess between adjacent gate trenches of the same cell type of the CMOS device; and After forming the metal silicide region, a contact is formed that extends through the dielectric mesa surface to or into the semiconductor substrate.

21. The method of claim 20, wherein forming the dielectric mesa in the recess comprises: filling the recess with a dielectric material and covering the first major surface of the semiconductor substrate; and An upper surface of the dielectric material facing away from the semiconductor substrate is planarized.

22. The method of claim 21 , wherein forming the metal silicide region in the upper central portion of each gate electrode of the vertical power transistor and forming the metal silicide region in the upper central portion of each gate electrode of the CMOS device comprises: covering the planarized upper surface of the dielectric material with a photoresist, the photoresist having an opening aligned in a vertical direction with the gate electrode of the vertical power transistor and the gate electrode of the CMOS device; forming an opening in the dielectric material, the opening being aligned in a vertical direction with the opening of the photoresist; After filling the recess with the dielectric material and covering the first major surface of the semiconductor substrate, removing the photoresist; recessing the gate electrode of the vertical power transistor and the gate electrode of the CMOS device through the opening of the photoresist and the opening of the dielectric material; depositing cobalt on the first major surface of the semiconductor substrate after removing the photoresist so that the cobalt contacts the recessed gate electrode of the vertical power transistor and the recessed gate electrode of the CMOS device; and The cobalt is annealed.

23. The method of claim 18, wherein forming the metal silicide region in the upper central portion of each gate electrode of the vertical power transistor and forming the metal silicide region in the upper central portion of each gate electrode of the CMOS device comprises: recessing the gate electrode of the vertical power transistor and the gate electrode of the CMOS device; depositing cobalt on the first major surface of the semiconductor substrate such that the cobalt contacts a recessed portion of each gate electrode of the vertical power transistor and a recessed portion of each gate electrode of the CMOS device; depositing titanium on the cobalt; performing a first annealing process that produces CoSi in contact with the concave portion of each gate electrode of the vertical power transistor and the concave portion of each gate electrode of the CMOS device and produces a TiN layer on the CoSi; removing the TiN layer and unreacted Co; and The second annealing process is performed at a temperature higher than the first annealing process but less than 1000°C.

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