Grid-based integrated circuit and method of designing same

Abstract

An integrated circuit includes devices arranged in a grid configuration and a first metal layer on the devices, where the grid includes: first grid lines arranged in a first direction based on a first pitch and extending in a second direction; and second grid lines arranged in the second direction based on the second pitch and extending in the first direction. At least one of the plurality of devices includes gate lines extending in the second direction and having a first pitch, and the first metal layer includes first metal lines extending in the first direction and having a second pitch.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0125011 filed in the Korean Intellectual Property Office on September 19, 2023, and Korean Patent Application No. 10-2024-0018413 filed in the Korean Intellectual Property Office on February 6, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to an integrated circuit based on a grid design and a method of designing the integrated circuit. Background Art

[0004] An integrated circuit may include various intellectual property rights (IPs), such as analog blocks, digital blocks, and mixed signal blocks. In this case, the blocks, units, or devices included in these various IPs may have different sizes depending on their functions and characteristics. Since buffer space is required between these blocks, units, devices, and / or IPs, the integrated circuit manufacturing process becomes more difficult and there are limitations in reducing the chip size of the integrated circuit. Summary of the invention

[0005] According to some embodiments, the present disclosure relates to an integrated circuit, the integrated circuit comprising: a plurality of devices arranged in a grid configuration; and a first metal layer on the plurality of devices. The grid comprises: a plurality of first grid lines arranged in a first direction based on a first spacing and extending in a second direction intersecting the first direction; and a plurality of second grid lines arranged in a second direction based on a second spacing and extending in the first direction. At least one of the plurality of devices comprises a plurality of gate lines extending in the second direction and having a first spacing, and the first metal layer comprises a plurality of first metal lines extending in the first direction and having a second spacing.

[0006] According to some embodiments, the present disclosure relates to an integrated circuit comprising a plurality of cells arranged in a grid configuration having a first spacing. The grid comprises a plurality of grid lines arranged in a first direction based on the first spacing and extending in a second direction intersecting the first direction. The plurality of cells comprises: a first cell comprising a first gate line, the first gate line respectively overlapping with a first grid line among the plurality of grid lines and each extending in a second direction; and a second cell comprising at least one second gate line, the at least one second gate line overlapping with a second grid line among the plurality of grid lines and extending in a second direction. The first spacing corresponds to the spacing of the first gate lines, and the first length of each first gate line in the first direction is less than the second length of at least one second gate line in the first direction.

[0007] According to some embodiments, the present disclosure relates to an integrated circuit, the integrated circuit comprising: a plurality of blocks arranged in a grid configuration having a first spacing; and a first metal layer on the plurality of blocks. The first metal layer comprises a plurality of first metal lines, each of the plurality of first metal lines extending in a first direction and arranged apart from each other in a second direction intersecting the first direction. The first spacing corresponds to the spacing of the plurality of first metal lines. The grid comprises a plurality of grid lines extending in the first direction and arranged in the second direction based on the first spacing. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a layout showing an example of an integrated circuit according to some embodiments.

[0010] Figure 2 is a plan view illustrating an example of an integrated circuit according to some embodiments.

[0011] Figure 3A According to some embodiments, Figure 2 A cross-sectional view taken along line X1-X1', and Figure 3B According to some embodiments, Figure 2 A cross-sectional view taken along line X2-X2'.

[0012] Figure 4 is a plan view illustrating an example of an integrated circuit according to some embodiments.

[0013] Figure 5A According to some embodiments, Figure 4 A cross-sectional view taken along line X3-X3', and Figure 5B According to some embodiments, Figure 4 A cross-sectional view taken along line X4-X4'.

[0014] Figure 6 is a plan view illustrating an example of an integrated circuit according to some embodiments.

[0015] Fig. 7A According to some embodiments, Figure 6 A cross-sectional view taken along the line Y1-Y1', and Figure 7B According to some embodiments, Figure 6 A cross-sectional view taken along line Y2-Y2'.

[0016] Figure 8 is a layout showing an example of an integrated circuit according to some embodiments.

[0017] Fig.9A is a plan view showing an example of an integrated circuit according to some embodiments, and Fig. 9B According to some embodiments, Fig.9A A cross-sectional view taken along line X5-X5'.

[0018] Fig.10 is a layout showing an example of an integrated circuit according to some embodiments.

[0019] Fig.11A is a plan view showing an example of an integrated circuit according to some embodiments, and Fig. 11B According to some embodiments, Fig.11A A cross-sectional view taken along line X6-X6'.

[0020] Fig.12 is a layout showing an example of an integrated circuit according to some embodiments.

[0021] Fig.13A is a plan view showing an example of an integrated circuit according to some embodiments, and Fig. 13B According to some embodiments, Fig.13A A cross-sectional view taken along line X7-X7'.

[0022] Fig.14 is a layout showing an example of an integrated circuit according to some embodiments.

[0023] Fig.15 is a layout showing an example of an integrated circuit according to some embodiments.

[0024] Fig.16 is a layout showing an example of an integrated circuit according to some embodiments.

[0025] FIG. 17A to FIG. 17D is a diagram illustrating an example of a device according to some embodiments.

[0026] Fig.18 is a flow chart illustrating an example of a method of manufacturing an integrated circuit according to some embodiments.

[0027] Fig.19 is a block diagram illustrating an example of a system on a chip (SoC) according to some embodiments.

[0028] Fig. 20 is a block diagram illustrating an example of a computing system including a memory storing programs according to some implementations. DETAILED DESCRIPTION

[0029] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals denote the same elements, and repeated descriptions thereof will be omitted.

[0030] In the present disclosure, the X-axis direction may be referred to as a first horizontal direction or a first direction, the Y-axis direction may be referred to as a second horizontal direction or a second direction, and the Z-axis direction may be referred to as a vertical direction. A plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane, an element arranged along a positive (+) Z-axis direction relative to other elements may be referred to as being located on or above the other elements, and an element arranged along a negative (-) Z-axis direction relative to other elements may be referred to as being located below or under the other elements.

[0031] Figure 1 is a diagram showing an example layout of an integrated circuit according to some embodiments. Figure 1 , the integrated circuit 10 may include a first unit 11 and a metal layer Dx. The integrated circuit 10 may be implemented as a semiconductor device. According to some embodiments, the first unit 11 and the metal layer Dx may be placed or arranged and routed based on a grid or a grid configuration. In this case, the grid may include a first grid line G1 and a second grid line G2. In some embodiments, the first unit 11 may be referred to as a first block or a first device. In some embodiments, the first unit 11 may correspond to a short channel device. For example, the first unit 11 may include a logic device (e.g., a standard cell) or a memory device (e.g., a static random access memory (SRAM) device).

[0032] The first cell 11 may include a gate line GT arranged along a first grid line G1. In addition, the first cell 11 may also include a gate contact CB arranged along the first grid line G1 and a second grid line G2. In addition, the first cell 11 may also include an active pattern AP arranged along the second grid line G2. For example, the first cell 11 may be defined by a boundary BD and may correspond to a standard cell or a functional cell. In addition, the metal layer Dx may include a plurality of metal lines Dx routed along the second grid line G2.

[0033] In some embodiments, the first grid lines G1 may be referred to as vertical grid lines. For example, the first grid lines G1 may include first grid lines G11 to G18 that are separated from each other in the first direction X and extend in the second direction Y. The first grid lines G11 to G18 may have a first pitch P1. In some embodiments, the first pitch P1 may correspond to the pitch of the gate lines GT, i.e., the contact polysilicon pitch (CPP). Therefore, the first grid lines G11 to G18 may be arranged at the first pitch P1 in the first direction X.

[0034] In some embodiments, the second grid lines G2 may be referred to as horizontal grid lines. For example, the second grid lines G2 may include second grid lines G21 to G26, each of which extends in the first direction X and is arranged separately from each other in the second direction Y. The second grid lines G21 to G26 may have a second spacing P2. In some embodiments, the second spacing P2 may correspond to the spacing of the metal lines Dx. Therefore, the second grid lines G21 to G26 may be arranged at a second spacing P2 in the second direction Y. For example, the second spacing P2 may be greater than or equal to the first spacing P1. However, the present disclosure is not limited thereto, and the first spacing P1 and the second spacing P2 may vary according to some embodiments.

[0035] The gate lines GT may include gate lines GT1a to GT1d arranged along the first grid lines G13 to G16. In this case, the spacing of the gate lines GT1a to GT1d, i.e., CPP, may correspond to the first spacing P1. For example, the gate lines GT1a to GT1d may overlap with the first grid lines G13 to G16, respectively. For example, the gate lines GT1a to GT1d may be aligned with the first grid lines G13 to G16, respectively, and the center lines of the gate lines GT1a to GT1d may correspond to the first grid lines G13 to G16, respectively. In some embodiments, the length of each gate line GT1a to GT1d in the first direction X may be the first length L1.

[0036] The gate contacts CB may be disposed on the gate lines GT1a to GT1d, respectively. The gate contacts CB may be arranged along the first grid lines G13 to G16, and the intervals of the gate contacts CB may correspond to the first interval P1. In addition, the gate contacts CB may be arranged along the second grid line G22. For example, the gate contacts CB may be aligned with the second grid line G22, and the center line of the gate contacts CB may correspond to the second grid line G22.

[0037] The active pattern AP may be arranged along the second grid lines G23 to G25, and the pitch of the active pattern AP may correspond to the second pitch P2. For example, the active pattern AP may be aligned with the second grid lines G23 to G25, and the center lines of the active pattern AP may correspond to the second grid lines G23 to G25, respectively. For example, the active pattern AP may be a diffusion region doped with a dopant to change the electrical characteristics of the substrate material, and may form a source / drain region of a transistor.

[0038] In some embodiments, the active pattern AP may correspond to a nanosheet, and in this case, the integrated circuit 10 may include a multi-bridge channel field effect transistor (MBCFET). However, the present disclosure is not limited thereto. In some embodiments, the active pattern AP may correspond to a nanowire, and in this case, the integrated circuit 10 may include a gate-all-around field effect transistor (GAAFET). In addition, in some embodiments, the active pattern AP may correspond to a fin structure or fin, and in this case, the integrated circuit 10 may include a fin field effect transistor (FinFET).

[0039] The metal line Dx may be arranged along the second grid lines G22 to G25, and the pitch of the metal line Dx may correspond to the second pitch P2. For example, the metal line Dx may be aligned with the second grid lines G22 to G25, and the center lines of the metal line Dx may correspond to the second grid lines G22 to G25, respectively. For example, the metal line Dx may be a signal routing level line. For example, the metal line Dx may be disposed above the first unit 11 along the vertical direction Z. For example, the metal line Dx may be included in the uppermost metal layer of the integrated circuit 10, but the present disclosure is not limited thereto.

[0040] The integrated circuit 10 may further include various front wiring layers, such as a front via layer and a front metal layer, disposed above the first unit 11 along the vertical direction Z and electrically connected to the first unit 11. For example, the front via layer and the front metal layer may be disposed between the first unit 11 and the metal line Dx. For example, the front via layer and the front metal layer may be disposed above the metal layer Dx along the vertical direction Z. In this case, the front via layer and the front metal layer may be placed and routed along a grid including the first grid line G1 and the second grid line G2.

[0041] In addition, the integrated circuit 10 may further include various backside wiring layers, such as backside contacts, backside via layers, and backside metal layers, which are arranged below the first unit 11 along the vertical direction Z and are electrically connected to the first unit 11. In this case, the backside contacts, backside via layers, and backside metal layers may be placed and routed along a grid including the first grid line G1 and the second grid line G2. In addition, the integrated circuit 10 may further include through electrodes, such as through silicon vias (TSVs). In this case, the through electrodes may be placed and routed along a grid including the first grid line G1 and the second grid line G2.

[0042] In addition, the integrated circuit 10 may further include another unit, block or device adjacent to the first unit 11 in the first direction X, and another unit, block or device adjacent to the first unit 11 in the second direction Y. In this case, the units, blocks and / or devices may be placed or arranged along a grid including the first grid line G1 and the second grid line G2. Therefore, the integrated circuit 10 may reduce unnecessary space between adjacent units, adjacent blocks and / or adjacent IPs, and may reduce the size of a semiconductor chip including the integrated circuit 10.

[0043] As described above, according to some embodiments, the difficulty of the manufacturing process of the integrated circuit 10 and the chip size of the integrated circuit 10 can be reduced by arranging devices, units and blocks based on a grid and routing wiring lines based on a grid. For example, the difficulty of the manufacturing process and design verification can be reduced by setting vertical grid lines based on the spacing of the gate lines GT, setting horizontal grid lines based on the spacing of the signal routing lines, and arranging patterns, lines and / or areas of the devices based on the vertical grid lines and the horizontal grid lines. In addition, by placing devices, units and blocks based on the vertical grid lines and the horizontal grid lines, the buffer space can be reduced, and the chip size of the integrated circuit 10 can be reduced.

[0044] Figure 2 is a plan view illustrating an example of an integrated circuit according to some embodiments. Figure 3A According to some embodiments, Figure 2 A cross-sectional view taken along line X1-X1', and Figure 3B According to some embodiments, Figure 2 A cross-sectional view taken along line X2-X2'.

[0045] exist Figures 2 to 3B , the integrated circuit 10a may include a gate line GT, an active pattern AP, a source / drain region SD, a source / drain contact CA, and a gate contact CB. The integrated circuit 10a may correspond to the reference Figure 1 The embodiment of the integrated circuit 10 is described and reference is made to Figure 1 The given description can also be applied to the present embodiment.

[0046] The integrated circuit 10a may further include a front via layer and a front metal layer, which are disposed above the source / drain contact CA and the gate contact CB and are electrically connected to the source / drain contact CA and / or the gate contact CB. In addition, the integrated circuit 10a may further include a backside contact, a backside via layer and a backside metal layer, which are disposed below the active pattern AP, the source / drain region SD and the gate line GT and are electrically connected to the source / drain region SD and / or the gate line GT.

[0047] Figure 3A and Figure 3B An example of forming a nanosheet in an active region is shown. For example, an MBCFET can be formed in which multiple nanosheets are stacked in the active region and the gate line surrounds the nanosheet. However, the integrated circuit of the present disclosure is not limited to Figure 3A and Figure 3B For example, a FinFET may be formed that includes a fin and a gate line formed in an active region. In another example, a GAAFET may be formed in which a nanowire formed in an active region is surrounded by a gate line. FIG. 17A to FIG. 17D Give a description.

[0048] The substrate SUB may include a semiconductor substrate. For example, the semiconductor substrate may include at least one selected from the group consisting of silicon, silicon on insulator (SOI), silicon on sapphire, germanium, silicon germanium, and gallium arsenide. The interlayer insulating film may be provided on the upper side of the substrate SUB. The interlayer insulating film may include an insulating material. For example, the insulating material may include at least one selected from the group consisting of an oxide film, a nitride film, and an oxynitride film.

[0049] The gate line GT1 may overlap the first grid line G13 and may extend in the second direction Y. The gate line GT1 may have a first length L1 in the first direction X. The gate contact CB may be disposed on the gate line GT1. The gate contact CB may overlap the first grid line G13. The first metal layer M1 may be disposed on the gate contact CB, and the gate line GT1 may be electrically connected to the first metal layer M1 through the gate contact CB. Therefore, the gate line GT1 may be used as a real gate line. For example, the gate line GT overlapping the first grid lines G11 and G12 and the gate line GT overlapping the first grid lines G14 and G15 may correspond to a dummy gate line.

[0050] The active pattern AP may extend in the first direction X. For example, the active pattern AP may include a nanosheet NS. A nanosheet stack or nanosheet NS extending in the first direction X may be disposed on the upper side of the substrate SUB. The nanosheet stack or nanosheet NS may include a plurality of nanosheets overlapping each other in the vertical direction Z, such as a first nanosheet NS1 to a third nanosheet NS3. For example, a nanosheet NS disposed on an N-well may be doped with a P-type dopant and may form a P-type transistor. In addition, a nanosheet NS disposed on a P-type substrate may be doped with an N-type dopant and may form an N-type transistor. In some embodiments, the nanosheet NS may include silicon (Si), germanium (Ge), or SiGe. In some embodiments, the nanosheet NS may include InGaAs, InAs, GaSb, InSb, or a combination thereof.

[0051] Each of the gate lines GT may cover the nanosheet stack NS and surround each of the first to third nanosheets NS1 to NS3. Therefore, the first to third nanosheets NS1 to NS3 may have a gate-all-around (GAA) structure. The gate line GT may be defined as a conductive segment including polysilicon and a conductive material (e.g., at least one metal). A gate insulating film may be provided between each gate line GT and the first to third nanosheets NS1 to NS3.

[0052] The source / drain regions SD may each include an epitaxial region of a semiconductor material such as silicon (Si), boron (B), phosphorus (P), germanium (Ge), carbon (C), SiGe and / or SiC. The source / drain region SD may include a first source / drain region SD1 and a second source / drain region SD2, which are arranged on both sides of the gate line GT1. The source / drain contacts CA may be arranged on the first source / drain region SD1 and the second source / drain region SD2, respectively. The vias VA may be arranged on the source / drain contacts CA, respectively, and the first metal layer M1 may be disposed on the vias VA. The first source / drain region SD1 and the second source / drain region SD2 may be electrically connected to the first metal layer M1 through the source / drain contacts CA and the vias VA.

[0053] In some embodiments, the integrated circuit 10a may include a front wiring layer disposed on the front side of a substrate SUB and a backside wiring layer disposed on the back side of the substrate SUB, and a power distribution network (PDN) may be implemented using the front wiring layer and the backside wiring layer. Therefore, a portion of the power and / or signal applied to the integrated circuit 10a may be transmitted through the front wiring layer, i.e., the front side PDN (FSPDN), while the remainder may be transmitted through the backside wiring layer, i.e., the backside PDN (BSPDN). According to some embodiments, the routing complexity may be reduced compared to a structure in which wiring is arranged only on the front side of the substrate, and the length of each wiring line or each via may also be reduced, thereby improving the performance of the integrated circuit 10a. Furthermore, according to some embodiments, the front wiring layer and the backside wiring layer may be routed in a grid configuration, thereby routing along a grid including a first grid line G1 and a second grid line G2 (see Figure 1 ), thereby reducing the difficulty of the manufacturing process and the chip size.

[0054] Figure 4 is a plan view illustrating an example of an integrated circuit according to some embodiments. Figure 5A According to some embodiments, Figure 4 A cross-sectional view taken along line X3-X3', and Figure 5B is a cross-sectional view taken along line X4-X4' according to some embodiments.

[0055] exist Figure 4 , Figure 5A and Figure 5BIn the embodiment, the integrated circuit 10b may correspond to Figure 2 The integrated circuit 10b may include a gate line GT arranged along a first grid line G1 having a first pitch P1. For example, the integrated circuit 10b may include a gate line GT1a overlapping the first grid line G13 and a gate line GT1b overlapping the first grid line G14. The gate contacts CB may be disposed on the gate lines GT1a and GT1b, respectively, and the gate lines GT1a and GT1b may be electrically connected to the first metal layer M1 through the gate contacts CB. The length of each of the gate lines GT1a and GT1b in the first direction X may be a first length L1, and the pitch of the gate lines GT1a and GT1b, i.e., CPP, may correspond to the first pitch P1.

[0056] Figure 6 is a plan view illustrating an example of an integrated circuit according to some embodiments. Fig. 7A According to some embodiments, Figure 6 A cross-sectional view taken along the line Y1-Y1', and Figure 7B According to some embodiments, Figure 6 A cross-sectional view taken along line Y2-Y2'.

[0057] exist Figure 6 , Fig. 7A and Figure 7B In the embodiment, the integrated circuit 10c may include a gate line GT, an active pattern AP, a source / drain region SD, a source / drain contact CA, a gate contact CB, and a metal line Dx. The integrated circuit 10c may correspond to Figure 1 Integrated circuit 10, Figure 2 The integrated circuit 10a or Figure 4 A modification of the integrated circuit 10b, and reference Figures 1 to 5B The given description can also be applied to the present embodiment.

[0058] According to some embodiments, the metal lines Dx may be arranged along the second grid lines G2 having the second pitch P2, and the pitch of the metal lines Dx may correspond to the second pitch P2. Although for ease of description, Figure 6 Only metal lines Dx are shown in FIG. 1 , but the integrated circuit 10c may further include multiple metal layers and multiple via layers between the metal lines Dx and the source / drain contacts CA or the gate contacts CB. The number of metal layers and the number of via layers may vary.

[0059] For example, the first metal layer M1 to the third metal layer M3, the first via layer V1 to the third via layer V3 and the via VA may be disposed between the source / drain contact CA and the metal line Dx. The source / drain contact CA may be electrically connected to the first metal layer M1 through the via VA. The first metal layer M1 may be electrically connected to the second metal layer M2 through the first via layer V1. The second metal layer M2 may be electrically connected to the third metal layer M3 through the second via layer V2. The third metal layer M3 may be electrically connected to the metal line Dx through the third via layer V3. However, the present disclosure is not limited thereto, and four or more metal layers and four or more via layers may be disposed below the metal line Dx. In some embodiments, the spacing of the first metal layer to at least one of the third metal layers M1, M2 and M3 may be determined based on the first spacing P1. In some embodiments, the spacing of the first metal layer to at least one of the third metal layers M1, M2 and M3 may be determined based on the second spacing P2.

[0060] In some embodiments, the metal lines Dx may be aligned with the second grid lines G22 to G25, and the center lines of the metal lines Dx may correspond to the second grid lines G22 to G25, respectively. In some embodiments, the active patterns AP may be aligned with the second grid lines G23 to G25, and the center lines of the active patterns AP may correspond to the second grid lines G23 to G25, respectively. In some embodiments, the source / drain regions SD may be aligned with the second grid lines G23 to G25, and the center lines of the source / drain regions SD may correspond to the second grid lines G23 to G25, respectively.

[0061] In some embodiments, the gate contact CB may be aligned with the second grid line G22, and the center line of each gate contact CB may correspond to the second grid line G22. In some embodiments, the vias VA may be aligned with the second grid lines G23 to G25, and the center lines of the vias VA may correspond to the second grid lines G23 to G25, respectively. In some embodiments, the first to third via layers V1 to V3 may be aligned with the second grid lines G22 to G25, and the center lines of the vias of the first to third via layers V1 to V3 may correspond to the second grid lines G22 to G25.

[0062] Figure 8 is a diagram showing an example layout of an integrated circuit according to some embodiments. Figure 8 In the embodiment, the integrated circuit 20 may include a second unit 21 and a metal layer Dx. According to some embodiments, the second unit 21 and the metal layer Dx may be placed and routed in a grid configuration, and thus, are placed and routed along a grid including a first grid line G1 and a second grid line G2. In some embodiments, the second unit 21 may be referred to as a second block or a second device. In some embodiments, the second unit 21 may correspond to a long channel device.

[0063] For example, the second unit 21 may include an input / output device, a one-time programmable (OTP) device, an electrostatic discharge (ESD) device, a passive device, an analog device, etc. For example, the OTP device may include an OTP memory, a fuse device, an electric fuse device, etc. For example, the ESD device may be a diode type, a transistor type, etc. For example, the passive device may include a resistor, a capacitor, an inductor, etc. For example, the analog device may include a sensor, a noise elimination device, a discharge device, etc.

[0064] The first grid lines G1 may include first grid lines G11 to G16 having a first pitch P1, and the first grid lines G11 to G16 may each extend along the second direction Y. The second grid lines G2 may include second grid lines G21 to G26 having a second pitch P2, and the second grid lines G21 to G26 may each extend along the first direction X. The integrated circuit 20 may correspond to the reference Figure 1 Modifications of the integrated circuit 10 described herein and with reference to Figure 1 The description given can also be applied to the present embodiment. In addition, the integrated circuit 20 may also include a reference Figure 1 The first unit 11 and in this case, the first unit 11 , the second unit 21 and the metal layer Dx may be placed and routed along a grid including the first grid line G1 and the second grid line G2 .

[0065] The second unit 21 may include gate lines GT arranged along the first grid lines G11 to G16. In some embodiments, the length of each of the gate lines GT in the first direction X may be a second length L2, and the second length L2 may be greater than the reference length L2. Figure 1 The first length L1 is described. For example, each of the gate lines GT may overlap with a plurality of first grid lines. For example, the gate lines GT may include a gate line overlapping with the first grid lines G11 and G12, a gate line GT2 overlapping with the first grid lines G13 and G14, and a gate line overlapping with the first grid lines G15 and G16. For example, the first pitch P1 may correspond to Figure 1 The CPP shown, and the pitch of the gate lines GT may correspond to 2×CPP.

[0066] The gate contact CB may be disposed on the gate line GT2, the gate line GT2 overlaps the first grid lines G13 and G14, and the gate line GT2 may be used as a real gate line. In addition, the gate contact CB may be disposed along the second grid line G22. For example, the gate contact CB may be aligned with the second grid line G22, and the center line of the gate contact CB may correspond to the second grid line G22.

[0067] In addition, the second unit 21 may include an active pattern AP arranged along the second grid line G2. The active pattern AP may be arranged along the second grid lines G23 to G25, and the pitch of the active pattern AP may correspond to the second pitch P2. For example, the active pattern AP may be aligned with the second grid lines G23 to G25, and the center lines of the active pattern AP may correspond to the second grid lines G23 to G25, respectively. The metal lines Dx may be arranged along the second grid lines G22 to G25, and the pitch of the metal lines Dx may correspond to the second pitch P2. For example, the metal lines Dx may be aligned with the second grid lines G22 to G25, respectively, and the center lines of the metal lines Dx may correspond to the second grid lines G22 to G25, respectively.

[0068] Fig.9A is a plan view showing an example of an integrated circuit according to some embodiments, and Fig. 9B According to some embodiments, Fig.9A A cross-sectional view taken along the line X5-X5'. Fig.9A and Fig. 9B , the integrated circuit 20a may include a gate line GT, an active pattern AP, a source / drain region SD, a source / drain contact CA, and a gate contact CB. The integrated circuit 20a may correspond to the reference Figure 8 An example implementation of the integrated circuit 20 is described, and reference is made to Figure 8 The given description can also be applied to the present embodiment.

[0069] The integrated circuit 20a may further include a front via layer and a front metal layer disposed above the source / drain contact CA and the gate contact CB. In addition, the integrated circuit 20a may further include a backside via layer and a backside metal layer disposed below the active pattern AP, the source / drain region SD, and the gate line GT. In some embodiments, the active pattern AP may correspond to the nanosheet NS, and in this case, the integrated circuit 20a may include an MBCFET.

[0070] The gate line GT2 may overlap with the first grid lines G13 and G14 and may extend in the second direction Y. The gate line GT2 may have a second length L2 in the first direction X. For example, the second length L2 may be greater than or equal to the first pitch P1. The gate contact CB may be disposed on the gate line GT2. The gate contact CB may be disposed between the first grid lines G13 and G14. For example, the gate contact CB may have a length corresponding to the first pitch P1 in the first direction X.

[0071] The first metal layer M1 may be disposed on the gate contact CB, and the gate line GT2 may be electrically connected to the first metal layer M1 through the gate contact CB. For example, the gate line GT overlapping the first grid lines G11 and G12 and the gate line GT overlapping the first grid lines G15 and G16 may correspond to dummy gate lines.

[0072] The active pattern AP may include a nanosheet stack or nanosheet NS disposed over the substrate SUB and extending along the first direction X. The source / drain regions SD may be arranged at both sides of the gate line GT2. The source / drain regions SD may be electrically connected to the first metal layer M1 through source / drain contacts CA and vias VA.

[0073] Fig.10 is a diagram showing an example layout of an integrated circuit according to some embodiments. Fig.10 In the embodiment, the integrated circuit 30 may include a third unit 31 and a metal layer Dx. According to some embodiments, the third unit 31 and the metal layer Dx may be placed and routed in a grid configuration, and thus, are placed and routed along a grid including a first grid line G1 and a second grid line G2. In some embodiments, the third unit 31 may be referred to as a third block or a third device. In some embodiments, the third unit 31 may correspond to a long channel device. For example, the third unit 31 may include an input / output device, an OTP device, an ESD device, a passive device, an analog device, etc.

[0074] The first grid lines G1 may include first grid lines G11 to G17 having a first pitch P1, and the first grid lines G11 to G17 may each extend along the second direction Y. The second grid lines G2 may include second grid lines G21 to G26 having a second pitch P2, and the second grid lines G21 to G26 may each extend along the first direction X. The integrated circuit 30 may correspond to the reference Figure 1 and Figure 8 Modifications of the integrated circuits 10 and 20 described herein and with reference to Figure 1 and Figure 8 The description given may also apply to some embodiments. In addition, the integrated circuit 30 may also include a reference Figure 1 The first unit 11 and / or reference Figure 8 The second unit 21, and in this case, the first unit 11, the second unit 21 and / or the third unit 31 and the metal layer Dx may be placed and routed along a grid including the first grid line G1 and the second grid line G2.

[0075] The third unit 31 may include gate lines GT arranged along the first grid lines G11 to G17. In an embodiment, the length of each of the gate lines GT in the first direction X may be a third length L3, and the third length L3 may be greater than the reference length L2. Figure 1 The first length L1 and the reference Figure 8 The second length L2. In some embodiments, each of the gate lines GT may overlap with a plurality of first grid lines. For example, the gate lines GT may include a gate line overlapping with the first grid lines G11 and G12, a gate line GT3 overlapping with the first grid lines G13, G14, and G15, and a gate line overlapping with the first grid lines G16 and G17.

[0076] The gate contact CB may be disposed on the gate line GT3 overlapping the first grid lines G13, G14, and G15, and the gate line GT3 may be used as a real gate line. In addition, the gate contact CB may be arranged along the second grid line G22. In addition, the gate contact CB may be aligned with the second grid line G22, and the center line of the gate contact CB may correspond to the second grid line G22.

[0077] In addition, the third unit 31 may include an active pattern AP arranged along the second grid line G2. The active pattern AP may be arranged along the second grid lines G23 to G25, and the pitch of the active pattern AP may correspond to the second pitch P2. For example, the active pattern AP may be aligned with the second grid lines G23 to G25, and the center lines of the active pattern AP may correspond to the second grid lines G23 to G25, respectively. The metal lines Dx may be arranged along the second grid lines G22 to G25, and the pitch of the metal lines Dx may correspond to the second pitch P2. For example, the metal lines Dx may be aligned with the second grid lines G22 to G25, respectively, and the center lines of the metal lines Dx may correspond to the second grid lines G22 to G25, respectively.

[0078] Fig.11A is a plan view showing an example of an integrated circuit according to some embodiments, and Fig. 11B According to some embodiments, Fig.11A A cross-sectional view taken along the line X6-X6'. Fig.11A and Fig. 11B , the integrated circuit 30a may include a gate line GT, an active pattern AP, a source / drain region SD, a source / drain contact CA, and a gate contact CB. The integrated circuit 30a may correspond to the reference Fig.10 An example implementation of the integrated circuit 30 is described, and reference is made to Fig.10The description given may also be applied to the present embodiment. The integrated circuit 30a may further include a front via layer and a front metal layer disposed above the source / drain contact CA and the gate contact CB. In addition, the integrated circuit 30a may further include a backside via layer and a backside metal layer disposed below the active pattern AP, the source / drain region SD, and the gate line GT. In some embodiments, the active pattern AP may correspond to a nanosheet NS, and in this case, the integrated circuit 30a may include an MBCFET.

[0079] The gate line GT3 may overlap with the first grid lines G13, G14, and G15, and may extend in the second direction Y. The gate line GT3 may have a third length L3 in the first direction X. For example, the third length L3 may be greater than or equal to twice the first pitch P1. The gate contact CB may be disposed on the gate line GT3. The gate contact CB may be disposed between the first grid lines G13 and G15. For example, the gate contact CB may have a length corresponding to twice the first pitch P1 in the first direction X.

[0080] The first metal layer M1 may be disposed on the gate contact CB, and the gate line GT3 may be electrically connected to the first metal layer M1 through the gate contact CB. For example, the gate line GT overlapping the first grid lines G11 and G12 and the gate line GT overlapping the first grid lines G16 and G17 may correspond to dummy gate lines.

[0081] The active pattern AP may include a nanosheet stack or nanosheet NS disposed over the substrate SUB and extending along the first direction X. The source / drain regions SD may be disposed at both sides of the gate line GT2. The source / drain regions SD may be electrically connected to the first metal layer M1 through source / drain contacts CA and vias VA.

[0082] Fig.12 is a diagram showing an example layout of an integrated circuit according to some embodiments. Fig.12 In some embodiments, the integrated circuit 40 may include a fourth unit 41 and a metal layer Dx. According to some embodiments, the fourth unit 41 and the metal layer Dx may be placed and routed in a grid configuration, and thus, are placed and routed along a grid including the first grid line G1 and the second grid line G2. In some embodiments, the fourth unit 41 may be referred to as a fourth block or a fourth device. In some embodiments, the fourth unit 41 may correspond to a long channel device. For example, the fourth unit 41 may include an input / output device, an OTP device, an ESD device, a passive device, an analog device, etc.

[0083] The first grid lines G1 may include first grid lines G11 to G18 having a first pitch P1, and the first grid lines G11 to G18 may each extend along the second direction Y. The second grid lines G2 may include second grid lines G21 to G26 having a second pitch P2, and the second grid lines G21 to G26 may each extend along the first direction X. The integrated circuit 40 may correspond to the reference Figure 1 , Figure 8 and Fig.10 Modifications of the integrated circuits 10, 20 and 30 described herein and referring to Figure 1 , Figure 8 and Fig.10 The description given may also apply to some embodiments. In addition, the integrated circuit 40 may also include a reference Figure 1 Unit 11 of Description, Reference Figure 8 Unit 21 of description and / or reference Fig.10 The third unit 31 is described. In this case, the first unit 11, the second unit 21, the third unit 31 and / or the fourth unit 41 and the metal layer Dx may be placed and routed along a grid including the first grid line G1 and the second grid line G2.

[0084] The fourth unit 41 may include a gate line GT arranged along the first grid lines G11 to G18. In an embodiment, the length of the gate line GT4 in the first direction X may be a fourth length L4, and the fourth length L4 may be greater than the reference length L4. Figure 1 The first length L1, reference Figure 8 The second length L2 and the reference Fig.10 The third length L3. In some embodiments, each of the gate lines GT may overlap with a plurality of first grid lines. For example, the gate lines GT may include a gate line overlapping with the first grid lines G11 and G12, a gate line GT4 overlapping with the first grid lines G13, G14, G15, and G16, and a gate line overlapping with the first grid lines G17 and G18.

[0085] The gate contact CB may be disposed on the gate line GT4 overlapping the first grid lines G13, G14, G15, and G16, and the gate line GT4 may be used as a real gate line. In addition, the gate contact CB may be arranged along the second grid line G22. In addition, the gate contact CB may be aligned with the second grid line G22, and the center line of the gate contact CB may correspond to the second grid line G22.

[0086] In addition, the fourth unit 41 may include an active pattern AP arranged along the second grid line G2. The active pattern AP may be arranged along the second grid lines G23 to G25, and the pitch of the active pattern AP may correspond to the second pitch P2. For example, the active pattern AP may be aligned with the second grid lines G23 to G25, respectively, and the center lines of the active pattern AP may correspond to the second grid lines G23 to G25, respectively. The metal lines Dx may be arranged along the second grid lines G22 to G25, and the pitch of the metal lines Dx may correspond to the second pitch P2. In addition, the metal lines Dx may be aligned with the second grid lines G22 to G25, respectively, and the center lines of the metal lines Dx may correspond to the second grid lines G22 to G25, respectively.

[0087] Fig.13A is a plan view showing an example of an integrated circuit according to some embodiments, and Fig. 13B According to some embodiments, Fig.13A A cross-sectional view taken along the line X7-X7'. Fig.13A and Fig. 13B , the integrated circuit 40a may include a gate line GT, an active pattern AP, a source / drain region SD, a source / drain contact CA, and a gate contact CB. The integrated circuit 40a may correspond to the reference Fig.12 An example implementation of the integrated circuit 40 is described, and reference is made to Fig.12 The description given may also be applied to some embodiments. The integrated circuit 40a may further include a front via layer and a front metal layer disposed above the source / drain contact CA and the gate contact CB. In addition, the integrated circuit 40a may further include a backside via layer and a backside metal layer disposed below the active pattern AP, the source / drain region SD, and the gate line GT. In some embodiments, the active pattern AP may correspond to a nanosheet NS, and in this case, the integrated circuit 40a may include an MBCFET.

[0088] The gate line GT4 may overlap with the first grid lines G13 to G16 and may extend in the second direction Y. The gate line GT4 may have a fourth length L4 in the first direction X. For example, the fourth length L4 may be greater than or equal to three times the first pitch P1. The gate contact CB may be disposed on the gate line GT4. The gate contact CB may be disposed between the first grid lines G13 and G16. For example, the gate contact CB may have a length corresponding to three times the first pitch P1 in the first direction X.

[0089] The first metal layer M1 may be disposed on the gate contact CB, and the gate line GT4 may be electrically connected to the first metal layer M1 through the gate contact CB. For example, the gate line GT overlapping the first grid lines G11 and G12 and the gate line GT overlapping the first grid lines G17 and G18 may correspond to dummy gate lines.

[0090] The active pattern AP may include a nanosheet stack or nanosheet NS disposed over the substrate SUB and extending along the first direction X. The source / drain regions SD may be disposed at both sides of the gate line GT4. The source / drain regions SD may be electrically connected to the first metal layer M1 through source / drain contacts CA and vias VA.

[0091] Fig.14 is a diagram showing an example layout of an integrated circuit according to some embodiments. Fig.14 , the integrated circuit 50 may include a first unit 51 to a fourth unit 54. In this case, the first unit 51 to the fourth unit 54 may be arranged in a grid configuration and arranged along a grid including a first grid line G1 and a second grid line G2. For example, the first unit 51 and the fourth unit 54 may correspond to short channel devices, while the second unit 52 and the third unit 53 may correspond to long channel devices. As described above, the integrated circuit 50 may include a block or IP including a short channel device and a long channel device. For example, the integrated circuit 50 may include an analog block, a digital block, and / or a complex signal IP.

[0092] Each of the first to fourth units 51 to 54 may include a gate line GT arranged along the first grid line G1, and a gate contact CB may be arranged on some of the gate lines GT. The gate line GT connected to the gate contact CB may be used as a real gate line, and the gate line GT not connected to the gate contact CB may be used as a dummy gate line. For example, the length of each real gate line included in the first unit 51 and the fourth unit 54 in the first direction X may correspond to the reference Figure 1 The first length L1. For example, the length of each real gate line included in the second unit 52 and the third unit 53 in the first direction X may correspond to the reference Figure 8 The second length L2.

[0093] Fig.15 is a diagram showing an example layout of an integrated circuit according to some embodiments. Fig.15 , the integrated circuit 60 may include a gate line GT arranged along a first grid line G1. In some embodiments, the gate line GT may have different lengths in the first direction X, and the integrated circuit 60 may include a short channel device and a long channel device. Therefore, the integrated circuit 60 may include a block including a standard cell, digital logic and / or analog device, i.e., a complex signal block or complex signal IP.

[0094] The gate line GT may include gate lines 61a to 61e overlapping one of the first grid lines G1, and the integrated circuit 60 may include a short channel device including the gate lines 61a to 61e. The gate contact CB may be respectively disposed on the gate lines 61a to 61e, and the gate lines 61a to 61e may be used as real gate lines. The gate line GT may also include gate lines 65a and 65b each overlapping two grid lines in the first grid line G1. The gate lines 65a and 65b may be used as dummy gate lines, and the gate contact CB may not be disposed on the gate lines 65a and 65b. For example, a device including gate lines 61a to 61e, 65a and 65b may correspond to a short channel device.

[0095] The gate line GT may further include a gate line 62 overlapping three of the first grid lines G1. Thus, the integrated circuit 60 may include a long channel device including the gate line 62. The gate contact CB may be disposed on the gate line 62, and the gate line 62 may be used as a real gate line. The gate line GT may further include gate lines 65c and 65d each overlapping two of the first grid lines G1. The gate lines 65c and 65d may be used as dummy gate lines, and the gate contact CB may not be disposed on the gate lines 65c and 65d. For example, a device including the gate lines 62, 65c, and 65d may correspond to a long channel device.

[0096] The gate line GT may further include a gate line 63, which overlaps two grid lines in the first grid line G1. Therefore, the integrated circuit 60 may include a long channel device including the gate line 63. The gate contact CB may be disposed on the gate line 63, and the gate line 63 may be used as a real gate line. The gate line GT may further include gate lines 65e and 65f, each of which overlaps two grid lines in the first grid line G1. The gate lines 65e and 65f may be used as dummy gate lines, and the gate contact CB may not be disposed on the gate lines 65e and 65f. For example, a device including gate lines 63, 65e, and 65f may correspond to a long channel device.

[0097] The gate line GT may also include gate lines 64a and 64b that overlap four grid lines in the first grid line G1, respectively. Therefore, the integrated circuit 60 may include a long channel device including gate lines 64a and 64b. The gate contact CB may be disposed on the gate lines 64a and 64b, respectively, and the gate lines 64a and 64b may be used as real gate lines. The gate line GT may also include a gate line 65g that overlaps two grid lines in the first grid line G1. The gate line 65g may be used as a dummy gate line, and the gate contact CB may not be disposed on the gate line 65g. For example, a device including gate lines 64a, 64b, and 65g may correspond to a long channel device.

[0098] In some embodiments, the gate lines 65a to 65g as dummy gate lines can be used to distinguish different networks. Different voltages can be applied to the source / drain regions disposed on both sides of each dummy gate line. For example, a power supply voltage can be applied to the source / drain region disposed on the left side of the dummy gate line, and a ground voltage can be applied to the source / drain region disposed on the right side of the dummy gate line.

[0099] In some embodiments, the number of dummy gate lines 65a to 65g can vary. In an embodiment, one of dummy gate lines 65b and 65c can be removed. In some embodiments, when the source / drain region disposed on the left side of dummy gate line 65b and the source / drain region disposed on the right side of dummy gate line 65c are regions corresponding to the same network, all dummy gate lines 65b and 65c can be removed. In some embodiments, when the source / drain region disposed on the left side of dummy gate line 65f and the source / drain region disposed on the right side of dummy gate line 65f are regions corresponding to the same network, dummy gate line 65f can be removed.

[0100] Fig.16 is a diagram showing an example layout of an integrated circuit according to some embodiments. Fig.16 , the integrated circuit 70 may include a gate line GT arranged along a first grid line G1. In some embodiments, the gate line GT may have different lengths in the first direction X, and the integrated circuit 70 may include a short channel device and a long channel device. Therefore, the integrated circuit 70 may include a block including a standard cell, digital logic and / or analog device, i.e., a complex signal block or complex signal IP.

[0101] The integrated circuit 70 may further include a first upper metal layer Dx, a second upper metal layer Dx+1, and a via Sx between the first upper metal layer Dx and the second upper metal layer Dx+1. The first upper metal layer Dx may include first metal lines 71 and 72 routed along the second grid line G2. For example, each of the first metal lines 71 and 72 may be aligned with one of the second grid lines G2, and a center line of each of the first metal lines 71 and 72 may correspond to one of the second grid lines G2. The second upper metal layer Dx+1 may include second metal lines 73 and 74 routed along the first grid line G1. For example, the second metal lines 73 and 74 may be aligned with the first grid line G1, and a center line of the second metal lines 73 and 74 may correspond to the first grid line G1. The second metal line 74 may be electrically connected to the first metal lines 71 and 72 through the via Sx. For example, the via Sx may be aligned with the second grid line G2, and a center line of the via Sx may correspond to the second grid line G2.

[0102] The integrated circuit 70 may also include an active pattern, a source / drain region, and a source / drain contact. In this case, the active pattern, the source / drain region, and the source / drain contact may be placed and routed in a grid configuration, so as to be placed and routed along a grid including the first grid line G1 and the second grid line G2. In addition, the integrated circuit 70 may also include a front via layer and a front metal layer disposed between the first upper metal layer Dx and the source / drain contact or the gate contact CB. In this case, the front via layer and the front metal layer may be placed and routed along a grid including the first grid line G1 and the second grid line G2. In addition, the integrated circuit 70 may also include a rear side contact, a rear side via layer, and a rear side metal layer disposed below the active pattern, the source / drain region, and the gate line GT. In this case, the rear side contact, the rear side via layer, and the rear side metal layer may be placed and routed along a grid including the first grid line G1 and the second grid line G2.

[0103] As described above, the integrated circuit 70 can be designed based on the grid including the first grid line G1 and the second grid line G2, and the patterns, lines, devices, cells, blocks, and IPs can be placed and routed along the grid including the first grid line G1 and the second grid line G2. Therefore, the integrated circuit 70 can reduce unnecessary spaces between adjacent cells, adjacent blocks, and / or adjacent IPs, thereby reducing the size of the semiconductor chip including the integrated circuit 70.

[0104] FIG. 17A to FIG. 17D An example of a device according to some embodiments is shown. For example, Fig.17A FinFET 80a is shown, Fig. 17B GAAFET 80b is shown, Fig. 17C MBCFET 80c is shown, and Fig.17D A vertical field effect transistor (VFET) 80d is shown. For ease of illustration, 17A to 17C The state where one of the two source / drain regions is removed is shown respectively, and Fig.17D A cross section obtained by cutting the VFET 80d along a plane parallel to the second direction Y and the vertical direction Z and passing through the channel CH of the VFET 80d is shown.

[0105] exist Fig.17A In the embodiment, the FinFET 80a may be formed of a fin-shaped active pattern extending in a first direction X between device isolation layers STI and a gate G extending in a second direction Y. Source / drain regions S / D may be formed on both sides of the gate G, and thus, the source / drain regions S / D may be separated from each other in the first direction X. An insulating film may be formed between the channel CH and the gate G. In some embodiments, the FinFET 80a may be formed of a plurality of active patterns disposed apart from each other in the second direction Y, and the gate G.

[0106] exist Fig. 17B In the embodiment, the GAAFET 80b may be formed of active patterns (i.e., nanowires) separated from each other in a vertical direction Z and extending in a first direction X, and a gate G extending in a second direction Y. Source / drain regions S / D may be formed on both sides of the gate G, and the source / drain regions S / D may be separated from each other in the first direction X. An insulating film may be formed between the channel CH and the gate G. The number of nanowires of the GAAFET 80b is not limited to Fig. 17B The quantity shown in .

[0107] exist Fig. 17C In the embodiment, the MBCFET 80c may be formed of: active patterns, i.e., nanosheets, which are separated from each other in the vertical direction Z and extend in the first direction X; and a gate G extending in the second direction Y. The source / drain regions S / D may be formed on both sides of the gate G, and thus, the source / drain regions S / D may be separated from each other in the first direction X. An insulating film may be formed between the channel CH and the gate G. The number of nanosheets of the MBCFET 80c is not limited to Fig. 17C The quantity shown in .

[0108] exist Fig.17D , the VFET 80d may include a top source / drain region T_S / D and a bottom source / drain region B_S / D, which are separated from each other in a vertical direction Z, and a channel CH between the top source / drain region T_S / D and the bottom source / drain region B_S / D. The VFET 80d may include a gate G surrounding the channel CH between the top source / drain region T_S / D and the bottom source / drain region B_S / D. An insulating film may be formed between the channel CH and the gate G.

[0109] However, the transistor of the present disclosure is not limited to the structure of the present embodiment. For example, the integrated circuit may include a ForkFET in which the nanosheets of the P-type transistor and the nanosheets of the N-type transistor are separated from each other by a dielectric wall to closely arrange the P-type transistor and the N-type transistor. In addition, the integrated circuit may include a bipolar junction transistor and a field effect transistor (FET), such as a complementary field effect transistor (CFET), a negative capacitance field effect transistor (NCFET), or a carbon nanotube field effect transistor (CNT FET).

[0110] Fig.18 is a flow chart illustrating an example of a method of manufacturing an integrated circuit according to some embodiments. Fig.18In the method for manufacturing an integrated circuit IC including a standard cell, a plurality of operations S10, S30, S50, S70 and S90 may be included. A cell library (or standard cell library) D12 may include information about the standard cell, such as information about the function, characteristic or layout of the standard cell. In some embodiments, the cell library D12 may define a tap cell and a dummy cell and a functional cell, configured to generate an output signal based on an input signal. In some embodiments, the cell library D12 may define a storage cell and a dummy cell with the same footprint. The design rule D14 may include requirements for the layout of the integrated circuit IC. For example, the design rule D14 may include requirements for the spacing between patterns in the same layer, the minimum width of the pattern, the routing direction of the wiring layer, etc. In some embodiments, the design rule D14 may define the minimum spacing distance in the same track of the wiring layer.

[0111] In operation S10, a logic synthesis operation may be performed to generate netlist data D13 based on register transfer level (RTL) data D11. For example, a semiconductor design tool (e.g., a logic synthesis tool) may perform a logic synthesis operation to generate netlist data D13 including a bitstream or a netlist using RTL data D11 written in a hardware description language (HDL) (e.g., very high speed integrated circuit (VHSIC) HDL (VHDL) or Verilog) by referring to a cell library D12. The netlist data D13 may correspond to an input for placement and routing (described later).

[0112] In operation S30, the standard cells may be placed. According to some embodiments, the standard cells may be arranged in a grid configuration, so that along a grid line including a first grid line and a second grid line (eg, reference Figure 1 The grid including the first grid line G1 and the second grid line G2 described above is arranged. For example, a semiconductor design tool (such as a placement and routing (P&R) tool) can refer to the cell library D12 to place the standard cells used in the netlist data D13. In some embodiments, before operation S30, vertical grid lines each extending in the Y-axis direction and horizontal grid lines each extending in the X-axis direction can be pre-set. In some embodiments, the semiconductor design tool can place the standard cells along the horizontal grid lines and the vertical grid lines.

[0113] In operation S50, the pins of the standard cell may be routed. According to some embodiments, the pins of the standard cell may be routed along a first grid line and a second grid line (eg, reference Figure 1The pins are routed according to a grid including the first grid line G1 and the second grid line G2 described above. For example, the semiconductor design tool can generate interconnections that electrically connect the output pins and input pins of the placed standard cells to each other, and layout data D15 that defines the placed standard cells and the generated interconnections. The interconnections may include vias of a via layer and / or a pattern of a wiring layer. The wiring layer may include a front wiring layer disposed on the front upper side of the substrate and a rear wiring layer disposed on the rear side of the substrate. The layout data D15 may have a format such as a graphic design system II (GDSII), and may include geometric information about the standard cells and the interconnections. The semiconductor design tool may refer to the design rule D14 when routing the pins of the standard cells. The layout data D15 may correspond to the output of placement and routing. Operation S50 or operations S30 and S50 may be referred to as a method for designing an integrated circuit.

[0114] In some embodiments, the vias of the via layer, the patterns of the wiring layer, the through electrodes, etc. can be routed along the pre-set horizontal grid lines and vertical grid lines. For example, the spacing of the horizontal grid lines can correspond to the spacing of the signal routing lines. For example, the spacing of the vertical grid lines can correspond to the minimum spacing of the gate lines.

[0115] In operation S70, a mask manufacturing operation may be performed. For example, optical proximity correction (OPC), which is a technique for correcting distortions such as refraction caused by the characteristics of light in a photolithography process, may be applied to the layout data D15. A pattern may be defined on a mask based on the data to which OPC is applied to form a pattern in a plurality of layers, and at least one mask (or photomask) may be manufactured to form a pattern in each of the plurality of layers. In some embodiments, the layout of the integrated circuit IC may be limitedly modified in operation S70. Such modification of the integrated circuit IC in operation S70 may be a post-processing for optimizing the structure of the integrated circuit IC, and may be referred to as design polishing.

[0116] In operation S90, an operation of manufacturing an integrated circuit IC may be performed. For example, an integrated circuit IC may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S70. Front-end process (FEOL) operations may include, for example, planarizing and cleaning the wafer, forming a trench, forming a well, forming a gate line, or forming a source and a drain. A single device, such as a transistor, a capacitor, a resistor, etc., may be formed on a substrate by FEOL operations. In addition, back-end process (BEOL) operations may include, for example, silicide gate, source and drain regions, adding dielectrics, planarizing, forming holes, adding metal layers, forming vias, forming a passivation layer, etc. Single devices, such as transistors, capacitors, resistors, etc., may be connected to each other by BEOL operations. In some embodiments, a middle process (MOL) operation may be performed between the FEOL operation and the BEOL operation, and a contact may be formed on a single device. The integrated circuit IC may then be packaged in a semiconductor package and used as a component in various applications.

[0117] Fig.19 is a block diagram illustrating an example of a system on a chip (SoC) according to some embodiments. Fig.19 In the embodiment of the present invention, SoC 210 may refer to an integrated circuit that integrates components of a computing system or an electronic system. For example, an application processor (AP) as an example of SoC 210 may include a processor and components having other functions. SoC 210 may include a core 211, a digital signal processor (DSP) 212, a graphics processing unit (GPU) 213, an embedded memory 214, a communication interface 215, and a memory interface 216. The components of SoC 210 may communicate with each other through a bus 217.

[0118] The core 211 may process instructions and may control the operation of components included in the SoC 210. For example, the core 211 may drive an operating system and run applications on the operating system by processing a series of instructions. The DSP 212 may generate useful data by processing digital signals (e.g., digital signals received from the communication interface 215). The GPU 213 may generate data for outputting an image through a display device based on image data received from the embedded memory 214 or the memory interface 216, and may encode the image data. In some embodiments, the integrated circuit described above with reference to the accompanying drawings may be included in the core 211, the DSP 212, the GPU 213, and / or the embedded memory 214.

[0119] The embedded memory 214 may store data required for the operation of the core 211, the DSP 212, and the GPU 213. The communication interface 215 may provide an interface for a communication network or one-to-one communication. The memory interface 216 may provide an interface for an external memory (e.g., a dynamic random access memory (DRAM) or a flash memory) of the SoC 210.

[0120] Fig. 20 is a block diagram illustrating an example of a computing system including a memory storing a program according to some embodiments. Fig. 20 In the example, the computing system 220 may execute the integrated circuit design method, for example, referring to Fig.18 The computing system 220 may include a processor 221, an input / output device 222, a network interface 223, a random access memory (RAM) 224, a read-only memory (ROM) 225, and a storage device 226. The processor 221, the input / output device 222, the network interface 223, the RAM 224, the ROM 225, and the storage device 226 may be connected to a bus 227 and may communicate with each other through the bus 227.

[0121] Processor 221 may be referred to as a processing unit. Like a microprocessor, AP, DSP, or GPU, processor 221 may include at least one core capable of executing any instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit extended IA-32, x86-64, PowerPC, Scalable Processor Architecture (SPARC), Microprocessor without Interlocked Pipeline Stages (MIPS), Advanced RISC Machine (ARM), or IA-64). For example, processor 221 may access a memory, i.e., RAM 224 or ROM 225, through bus 227, and may execute instructions stored in RAM 224 or ROM 225.

[0122] The RAM 224 may store a program 224_1 or at least a portion of the program 224_1 for executing the integrated circuit design method according to the embodiment, and the program 224_1 may enable the processor 221 to execute the integrated circuit design method, for example, referring to Fig.18Even when the power supplied to the computing system 220 is cut off, the storage device 226 does not lose the data stored therein. According to some embodiments, the storage device 226 may store the program 224_1, and the program 224_1 or at least a portion of the program 224_1 may be loaded into the RAM 224. Alternatively, the storage device 226 may store a file written in a program language, and the program 224_1 or at least a portion of the program 224_1 may be generated by a compiler or the like according to the file and may be loaded into the RAM 224. In addition, the storage device 226 may store a database 226_1, and the database 226_1 may include information required for designing an integrated circuit, such as information about design blocks, reference codes, and the like. Fig.18 Described in the cell library D12 and / or reference Fig.18 Describes design rule D14.

[0123] The storage device 226 may store data to be processed by the processor 221 or data processed by the processor 221. That is, the processor 221 may generate data by processing the data stored in the storage device 226 according to the program 224_1, and may store the generated data in the storage device 226. For example, the storage device 226 may store reference Fig.18 The RTL data D11, netlist data D13 and / or layout data D15 are described. The input / output device 222 may include an input device (eg, a keyboard or a pointing device) and an output device (eg, a display device or a printer).

[0124] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of possible protection. In a single embodiment, specific features described in the context of independent embodiments in the present disclosure can also be implemented in combination. On the contrary, the different features described in the context of a single embodiment can also be implemented in multiple embodiments separately, or in any appropriate sub-combination. In addition, although features can be described above as working in certain combinations, one or more features from the combination can be deleted from the combination in some cases, and the combination can be for sub-combinations or variants of sub-combinations.

Claims

1. An integrated circuit, comprising: Multiple devices are arranged in a grid configuration; as well as a first metal layer, on the plurality of devices, Wherein, the grid includes: a plurality of first grid lines arranged in a first direction based on a first pitch and extending in a second direction intersecting the first direction; and a plurality of second grid lines, arranged in the second direction based on a second spacing and extending in the first direction, wherein at least one of the plurality of devices comprises a plurality of gate lines extending in the second direction and having the first spacing, and The first metal layer includes a plurality of first metal lines extending in the first direction and having the second spacing.

2. The integrated circuit according to claim 1, in, The plurality of devices include: A first unit includes first gate lines respectively overlapping the plurality of first grid lines, each of the first gate lines extending in the second direction; and a second unit, comprising at least one second gate line overlapping the plurality of first grid lines, the at least one second gate line extending in the second direction, wherein the first spacing corresponds to the spacing of the first gate lines, and Wherein, a first length of each of the first gate lines in the first direction is smaller than a second length of the at least one second gate line in the first direction.

3. The integrated circuit according to claim 2, wherein: The second length is based on the first length and the first spacing.

4. The integrated circuit according to claim 3, wherein: The second length is greater than or equal to the sum of the first length and the first interval.

5. The integrated circuit according to claim 2, in, The first unit further includes a source / drain region, each of the source / drain region is arranged between adjacent first grid lines among the plurality of first grid lines, The integrated circuit further comprises a second metal layer, the second metal layer comprises a plurality of second metal lines extending in the second direction, each of the plurality of second metal lines is electrically connected to the source / drain region, and Wherein, a spacing between the plurality of second metal lines is based on the first spacing.

6. The integrated circuit according to claim 2, in, The second unit further includes a source / drain region disposed on an opposite side of the at least one second gate line, The integrated circuit further comprises a second metal layer, the second metal layer comprises a plurality of second metal lines extending in the second direction, each of the plurality of second metal lines is electrically connected to the source / drain region, and Wherein, a spacing between the plurality of second metal lines is based on the first spacing.

7. The integrated circuit according to claim 2, wherein: The first cell includes at least one of a standard cell, a static random access memory device, and a logic device.

8. The integrated circuit according to claim 2, wherein: The second unit includes at least one of an input / output device, a one-time programmable device, an electrostatic discharge device, a passive device, and an analog device.

9. The integrated circuit according to claim 2, wherein: At least one of the first unit and the second unit includes an active pattern, each of the active patterns extending in the first direction and aligned with the plurality of second grid lines, respectively.

10. The integrated circuit of claim 1, wherein: The plurality of first metal lines are aligned with the plurality of second grid lines, respectively.

11. An integrated circuit comprising: A plurality of cells are arranged in a grid configuration having a first spacing, The grid includes a plurality of grid lines, which are arranged in a first direction based on the first spacing and extend in a second direction intersecting the first direction. Wherein, the multiple units include: A first unit includes first gate lines respectively overlapping with first grid lines among the plurality of grid lines, each of the first gate lines extending in the second direction; and a second unit, comprising at least one second gate line overlapping with a second grid line among the plurality of grid lines, wherein the at least one second gate line extends in the second direction, wherein the first spacing corresponds to the spacing of the first gate lines, and Wherein, a first length of each of the first gate lines in the first direction is smaller than a second length of the at least one second gate line in the first direction.

12. The integrated circuit of claim 11, wherein: The second length is based on the first length and the first spacing.

13. The integrated circuit according to claim 11, in, The first unit further includes a source / drain region, each of the source / drain regions is arranged between adjacent first grid lines among the first grid lines, The integrated circuit further comprises a metal layer, the metal layer comprises a plurality of metal lines extending in the second direction, each of the plurality of metal lines is electrically connected to the source / drain region, and Wherein, the spacing between the plurality of metal lines is based on the first spacing.

14. The integrated circuit according to claim 11, in, The second unit further includes a source / drain region disposed on an opposite side of the at least one second gate line, The integrated circuit further comprises a metal layer, the metal layer comprises a plurality of metal lines extending in the second direction, each of the plurality of metal lines is electrically connected to the source / drain region, and Wherein, the spacing between the plurality of metal lines is based on the first spacing.

15. The integrated circuit of claim 11, wherein: The first cell includes at least one of a standard cell, a static random access memory device, and a logic device.

16. The integrated circuit of claim 11, wherein: The second unit includes at least one of an input / output device, a one-time programmable device, an electrostatic discharge device, a passive device, and an analog device.

17. An integrated circuit comprising: a plurality of blocks arranged in a grid configuration having a first pitch; as well as a first metal layer, on the plurality of blocks, The first metal layer includes a plurality of first metal lines, each of which extends in a first direction and is arranged separately from each other in a second direction intersecting the first direction. The first spacing corresponds to the spacing of the plurality of first metal lines, and The grid includes a plurality of grid lines, which extend in the first direction and are arranged in the second direction based on the first spacing.

18. The integrated circuit according to claim 17, in, The plurality of grid lines correspond to horizontal grid lines, The grid further includes a plurality of vertical grid lines, the plurality of vertical grid lines extend in the second direction and are arranged in the first direction based on a second spacing, The multiple blocks include: a first block including first gate lines, the first gate lines respectively overlapping with first grid lines among the plurality of vertical grid lines, and each of the first gate lines extending in the second direction; and a second block, comprising at least one second gate line, the at least one second gate line overlapping with a second grid line among the plurality of vertical grid lines and extending in the second direction, wherein the second spacing corresponds to the spacing of the first gate lines, and Wherein, a first length of each of the first gate lines in the first direction is smaller than a second length of the at least one second gate line in the first direction.

19. The integrated circuit of claim 18, wherein: The second length is based on the first length and the first spacing.

20. The integrated circuit according to claim 18, in, The first block includes at least one of a standard cell, a static random access memory device, and a logic device, and The second block includes at least one of an input / output device, a one-time programmable device, an electrostatic discharge device, a passive device, and an analog device.

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