Parylene coating and film removing method for micro device with internal channel and special-shaped surface

Abstract

The invention provides a parylene coating and film removing method for a micro device with an internal channel and a special-shaped surface. The parylene coating and film removing method comprises the following steps: forming a mask layer and coating a parylene film layer on the micro device; cutting the side edges of the top surface and the bottom surface of the micro device by adopting laser, and removing the mask layer and the parylene film layer; the micro device is completely wrapped in the jig, and the top of the special-shaped surface with the mask layer and the parylene film layer extends out of the top of the jig; oxygen and argon are adopted to conduct plasma etching on the top of the special-shaped surface so as to remove the mask layer and the parylene film layer, the etching power ranges from 1000 w to 2000 w, the gas flow of the oxygen ranges from 60 sccm to 200 sccm, and the gas flow of the argon ranges from 5 sccm to 20 sccm. The laser cutting and plasma etching technology is adopted, parylene film coating and film removing can be effectively carried out on the micro device with an internal channel and a special-shaped surface, the fracture interface of the film is made to be neat and smooth, the film removing efficiency and precision are improved, and meanwhile the potential damage risk to the device is greatly reduced.

Description

Technical Field

[0001] The invention relates to the technical field of coating removal, and in particular to a method for coating and removing parylene from a micro device with an internal channel and a special-shaped surface. Background Art

[0002] The unique structure and stable properties of the Parylene film give it excellent protective performance, and it is usually used to protect electronic products, semiconductor devices and other products. Usually, due to the subsequent processing requirements of the device, some areas do not need the Parylene film, and only some areas need to be coated with the Parylene film.

[0003] In view of this situation, since it is impossible to coat a certain area with the parylene film layer alone, the prior art usually achieves the purpose of partially coating the parylene film layer by coating first and then removing the film layer.

[0004] There are two common methods for forming partially coated parylene layers. The first method is to directly coat all areas with parylene layers, and then remove the layers from areas where parylene layers are not needed. However, due to the high chemical stability and high adhesion of parylene, direct removal is extremely difficult.

[0005] The second method is to first mask the area where the parylene film is not needed with a mask layer, coat the parylene film on all areas, and then remove the parylene film and the mask layer together. Although this method increases the process cost to a certain extent, because the parylene film is not directly deposited on the surface, it greatly reduces the difficulty of removing the parylene film.

[0006] However, even if the second method is adopted, there are still technical difficulties in coating and removing the parylene film layer on the surface of current semiconductor devices.

[0007] First, semiconductor devices are small in size. With the development of the semiconductor industry, the integration of devices has been continuously improved. Today, centimeter-level and millimeter-level components are already quite common. Miniaturization means that the chemicals or physical methods used in the film removal process need to be more refined and controllable, and film removal must be very precise, which greatly increases the difficulty of film removal.

[0008] Second, the structure of semiconductor devices is complex. There are some channel structures inside the semiconductor devices, and there are often some special-shaped structures such as solder pillars and bumps on their surfaces. The particularity of these structures must be taken into account when removing the film. However, traditional film removal methods cannot accurately and effectively remove the film layer in a specific area. During the removal process, the film layer that does not need to be removed or even the structures themselves may be damaged. At the same time, the structure of the semiconductor device will also affect the setting of the mask layer in the coating method. The matching between the film removal method and the coating method is also an issue that needs to be considered.

[0009] Third, the Parylene film has very good ductility, and the elongation at break can generally reach 100%-200%. Therefore, after removing the film, the film fracture will be pulled, resulting in burrs, whitening, film shedding, etc., which will affect the implementation of the next process of the product or affect the appearance of the product. Therefore, before removing the film, the film should be disconnected at the boundary between the area that needs to be protected by the film and the area that does not need to be protected by the film. In this way, after removing the film, the fracture interface of the film will be neat and smooth.

[0010] Common methods for disconnecting film layers include mechanical cutting and laser cutting, but these methods can only be used to process devices with regular shapes or relatively large sizes. Based on the above situation, some irregular shaped devices, tiny devices, and devices with mutually shielded areas, such as micro devices with internal channels and shaped surfaces, cannot be cut by knives or lasers in traditional methods.

[0011] Therefore, how to coat and remove the parylene film on micro devices with internal channels and irregular surfaces, and make the fracture interface of the film neat and smooth, is a problem that researchers and technicians are eager to solve.

[0012] Plasma etching technology is an important process technology for removing material from the surface of a device. It uses plasma to bombard the surface of a semiconductor device to generate volatile gases for etching. However, there is no research in the prior art on removing the parylene film layer on micro devices with internal channels and special-shaped surfaces by plasma etching technology.

[0013] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0014] In view of this, the purpose of the present invention is to provide a method for coating and removing parylene for micro devices with internal channels and irregular surfaces, so as to at least solve the problem that the prior art cannot coat and remove parylene films on micro devices with internal channels and irregular surfaces, and cannot make the fracture interface of the film neat and smooth. The present invention adopts a solution combining laser cutting and plasma etching technology, uses laser cutting to remove the film on the plane, and uses the non-directionality and batch processing characteristics of plasma etching technology to process the irregular surface, so that the film layer in the area that cannot be cut by the traditional method can be disconnected, thereby achieving the purpose of cutting the film layer. The present invention makes the fracture interface of the film layer neat and smooth by reasonably selecting the coating and removal methods of the parylene film layer, which can effectively improve the efficiency and accuracy of removing the mask layer and the parylene film layer on the irregular surface of the micro device, while greatly reducing the potential risk of damage to the device.

[0015] The present invention provides a method for coating and removing parylene from a micro device having an internal channel and a profiled surface, comprising the following steps: S101, forming a mask layer on the top surface of the micro device, the bottom surface of the micro device and the top of the special-shaped surface; S102, coating the inner and outer surfaces of the micro device with a parylene film layer by a vapor deposition method; S103, cutting the sides of the top surface and the bottom surface of the micro device by laser, and then removing the mask layer and the parylene film layer on the top surface and the bottom surface of the micro device; S104, completely wrapping the micro device and placing it inside the jig, with the top of the special-shaped surface having the mask layer and the parylene film layer extending out of the top of the jig; S105, plasma etching is performed on the top of the irregular surface using oxygen and argon to remove the mask layer and the parylene film layer, wherein the etching power is 1000-2000w, the gas flow rate of oxygen is 60-200sccm, and the gas flow rate of argon is 5-20sccm.

[0016] In some embodiments, in S105 , the mixing ratio of oxygen to argon is 3:1-40:1.

[0017] In some embodiments, in S105 , the etching pressure is 30-60 Pa.

[0018] In some embodiments, in S105 , the etching time is 6-10 hours.

[0019] In some embodiments, in S101 , a mask layer is formed on the top surface and the bottom surface of the micro device using glue or tape material.

[0020] In some embodiments, in S101 , a mask layer is formed on the top of the profiled surface using an acrylic adhesive.

[0021] In some embodiments, in S101, a mask layer is formed on the top of the profiled surface by using a Czochralski method, and the specific steps are as follows: Completely immerse the top of the profiled surface into the acrylic adhesive, the thickness of the acrylic adhesive is 0.1-0.3mm; The micro-device is pulled up so that the top of the irregular surface leaves the acrylic adhesive, and the acrylic adhesive uniformly wraps the top of the irregular surface; The acrylate adhesive is cured to form a mask layer.

[0022] In some embodiments, in S102 , the thickness of the parylene film layer is 10-25 μm.

[0023] In some embodiments, in S103, the laser is a pulse laser with a wavelength of 355-1064 nm, a pulse width of femtosecond or picosecond, a cutting power of 1-10 W, and a cutting time of 30-120 seconds.

[0024] In some embodiments, in S104, the jig includes a substrate and a sealing plate; at least one blind hole matching the shape of the micro device is opened on the substrate; a through hole corresponding to the blind hole is opened on the sealing plate; when the micro device is placed in the blind hole, the sealing plate cover is arranged on the top of the substrate to close the blind hole, and the top of the profiled surface having the mask layer and the parylene film layer extends out of the through hole.

[0025] In some embodiments, in S104, the jig is made of silicone with a Shore A hardness of 50-70 degrees.

[0026] The beneficial effects that can be achieved by the present invention are: The present invention adopts plasma etching technology to remove the mask layer and the parylene film layer from the irregular surface of the micro device. The non-directionality and batch processing characteristics of the plasma etching technology are used to process the irregular surface, so that the film layer in the area that cannot be cut by the traditional method can be disconnected, so as to achieve the purpose of cutting the film layer, and the fracture interface of the film layer is neat and smooth. Compared with the traditional plasma etching, the stripping of the present invention has the special requirement of stripping the mask layer and the parylene film layer loaded thereon at the same time. In order to solve the above problems, the plasma etching technology of the present invention adopts a gas combination of oxygen and argon. On the one hand, the oxygen ions formed after the oxygen is ionized have high oxidizing properties, and can react chemically with the organic molecules of the film layer to generate gaseous carbon-containing molecules, which are then drawn away by the vacuum system of the equipment to achieve the purpose of etching. On the other hand, under the acceleration of the electrode, the argon plasma has high energy to hit the surface film layer, activate the molecules on the surface of the film layer, and promote the oxygen ions to enter the mask layer for etching. The two gases complement each other and can effectively increase the etching speed. The present invention reasonably controls the flow rates of the two gases, as well as the etching power and etching time of plasma etching, so that the impact action and the oxidation action can be carried out in coordination. Plasma etching can completely remove the mask layer and the parylene film layer on the profiled surface without any film residue, while avoiding the occurrence of over-etching. Reasonable parameter settings can ensure that the film layer is completely removed, prevent the film layer from being pulled and deformed, and ultimately make the fracture interface of the film layer neat and smooth. The present invention can effectively improve the efficiency and accuracy of removing the mask layer and the parylene film layer on the profiled surface of the microdevice, while greatly reducing the potential risk of damage to the device.

[0027] Furthermore, the present invention uses acrylic adhesive as the material for forming the mask layer, and the speed of the acrylic adhesive being etched by oxygen and argon in plasma is moderate, which is beneficial to improving the integrity of film layer removal.

[0028] Furthermore, the present invention creatively adopts the Czochralski method to form a mask layer on the profiled surface, which can ensure that the profiled surface is evenly wrapped by the mask layer and that the thickness of the mask layer in each region is consistent. The present invention reasonably selects the coating and stripping methods of the parylene film layer, and through the reasonable mask layer setting, the combination between the stripping method and the coating method has good consistency and matching, and successfully achieves the purpose of partially coating the parylene film layer on the micro device with internal channels and profiled surfaces.

[0029] Furthermore, the present invention adopts a solution combining laser cutting and plasma etching technologies, using laser cutting to remove the film on the plane that is relatively easy to process, which can minimize the use of plasma etching. Plasma etching is only used on the difficult-to-process special-shaped surfaces. Through the synergistic cooperation of the two technologies, the potential risk of damage to the device is further reduced.

[0030] Furthermore, the present invention adopts a special fixture design to prevent plasma from entering the internal channel of the micro device during the plasma etching process, thereby avoiding damage to the parylene film layer of the internal channel and ensuring that the internal coating still has good protective performance after etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A schematic diagram of a TEC in an embodiment of the present invention is shown; Figure 2 A schematic diagram showing a TEC disposed on a fixture in an embodiment of the present invention is shown; Figure 3 The top view microscopic image of the TEC surface after film removal obtained in Example 1 of the present invention is shown; Figure 4 The side view microscope image of the TEC surface after the film is removed obtained in Example 1 of the present invention is shown; Figure 5 The top view microscopic image of the TEC surface after film removal obtained in Example 2 of the present invention is shown; Figure 6 The top view microscopic image of the TEC surface after film removal obtained in Comparative Example 1 of the present invention is shown; Figure 7 The top view microscopic image of the TEC surface after film removal obtained in Comparative Example 2 of the present invention is shown; Figure 8The TEC surface after film removal obtained in Comparative Example 2 of the present invention is shown in an orthographic microscope image; Fig. 9 The top view microscopic image of the TEC surface after film removal obtained in Comparative Example 4 of the present invention is shown; Fig.10 A top-down microscope image of various positions of the internal channel of the TEC after the film is removed and the top cover plate is removed obtained in Comparative Example 6 of the present invention is shown.

[0033] Description of reference numerals: 11. Semiconductor; 12. Top cover plate; 13. Bottom cover plate; 14. Solder column; 20. Fixture; 21. Substrate; 22. Sealing plate. DETAILED DESCRIPTION

[0034] The term "comprising" in the specification and claims of the present invention and the drawings is synonymous with "including", "containing" or "characterized by", and is inclusive or open-ended, and does not exclude additional undescribed elements or method steps. "Comprising" is a technical term used in the claim language, meaning that the elements are present, but other elements may also be added and still form a structure or method within the scope of the claim.

[0035] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. The term "about" in the present invention means to include a small change (up to + / -10%) from the stated value.

[0036] It should be noted that the micro-devices with internal channels and irregular surfaces mentioned in the present invention are not particularly limited. TEC (thermoelectric cooler) will be used as an example to illustrate the technical solution of the present invention, but the following description does not constitute a limitation on the scope of protection of the present invention. The micro-devices mentioned in the present invention are preferably TEC but are not limited to this. They can also be other micro-devices with internal channels and irregular structures such as IC (integrated circuit), sensor, optoelectronic device, etc. More specifically, the surfaces of various array-packaged semiconductor devices have irregular structures such as solder joints, bumps, solder columns, pins, and pins, and also have array channels inside.

[0037] The parylene coating and film removal method provided by the present invention has no special restrictions on micro devices with internal channels and special-shaped surfaces. As long as the micro devices have internal array channels and special-shaped structures such as solder joints, bumps, solder columns, pins, and tube pins, the method of the present invention can be used to partially coat the parylene film layer.

[0038] like Figure 1 As shown, TEC includes an internal semiconductor 11, a conductive metal, a top cover plate 12, a bottom cover plate 13 and two solder pillars 14 spaced apart at one end of the TEC. The bottom cover plate 13 of the TEC is longer than the top cover plate 12. The two solder pillars 14 are spaced apart at the portion of the bottom cover plate 13 that exceeds the top cover plate 12. A gold layer is plated on the surface of the solder pillars 14. The height of the two solder pillars 14 is higher than the top cover plate 12.

[0039] Based on the above structure, the finished TEC needs to be welded with wires to connect to the power supply, so the welding column is the area where the parylene film layer is not needed. The top and bottom cover plates are the heat transfer areas, and in order to reduce thermal resistance, they are also the areas where the parylene film layer is not needed. How to achieve the purpose of partially coating the parylene film layer on the TEC is at least one of the technical problems solved by the embodiments of the present invention.

[0040] Based on the above structure, the irregular surface of TEC specifically refers to the irregular surface formed on the surface of the solder column. How to effectively remove the mask layer and the parylene film layer on the surface of the cover plate and the top of the solder column without damaging the cover plate and the solder column, while making the fracture interface of the film layer neat and smooth, is at least one of the technical problems solved by the embodiments of the present invention.

[0041] Based on the above structure, the internal channel of TEC specifically refers to the gap between the semiconductors between the upper and lower cover plates of TEC. How to remove the mask layer and the parylene film layer on the surface of the cover plate and the top of the solder column without damaging the thickness of the parylene film layer in the gap is at least one of the technical problems solved by the embodiments of the present invention.

[0042] It should be noted that since the TEC itself is very small, the distance between the two solder pillars is less than 1 mm. Since the two solder pillars block each other, laser or mechanical cutting methods cannot reach this area.

[0043] Furthermore, in the prior art, the cutting depth is usually only 10-20 μm, so the general cutting method cannot completely remove the mask layer and the parylene film layer.

[0044] Furthermore, the solder column substrate is a gold-plated material, and the gold layer on its surface is thin and soft. Contact cutting can easily damage the gold layer. Loss of the gold layer will cause the solder column to be corroded during the use of the TEC.

[0045] The plasma etching used in the present invention has the characteristics of diffusion, and can penetrate into the area where the two welding pillars shield each other, and etch away the surface film layer. At the same time, the preferred etching process and gas composition have the effects of physical and chemical dual etching, which can effectively speed up the etching speed.

[0046] The present invention provides a method for coating and removing parylene from a micro device having an internal channel and a profiled surface, comprising the following steps: S101, forming a mask layer on the top surface of the micro device, the bottom surface of the micro device and the top of the special-shaped surface; S102, coating the inner and outer surfaces of the micro device with a parylene film layer by a vapor deposition method; S103, cutting the sides of the top surface and the bottom surface of the micro device by laser, and then removing the mask layer and the parylene film layer on the top surface and the bottom surface of the micro device; S104, completely wrapping the micro device and placing it inside the jig, with the top of the special-shaped surface having the mask layer and the parylene film layer extending out of the top of the jig; S105, plasma etching is performed on the top of the irregular surface using oxygen and argon to remove the mask layer and the parylene film layer, wherein the etching power is 1000-2000w, the gas flow rate of oxygen is 60-200sccm, and the gas flow rate of argon is 5-20sccm.

[0047] In some embodiments, in S105, the mixing ratio of oxygen and argon is 3:1-40:1, which can be 3:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, 40:1 and any value therebetween. Preferably, the mixing ratio of oxygen and argon is 19:1. The advantage of the reasonable setting of the mixing ratio of oxygen and argon in the present invention is that the etching speed can be increased. Under the same film thickness, the processing time can be shortened, thereby improving production efficiency. Furthermore, under the condition of high etching efficiency, the etching time can be reduced to avoid excessive heat accumulation at the etching interface during etching, and to prevent the device surface from having different colors and other conditions that affect the appearance quality.

[0048] In some embodiments, in S105, the gas flow rate of oxygen is 60-200sccm, which can be 60sccm, 100sccm, 150sccm, 200sccm and any value therebetween. Preferably, the gas flow rate of oxygen is 95sccm. The advantage of the present invention in reasonably setting the gas flow rate of oxygen in plasma etching is that the etching rate can be increased. The oxygen of the present invention is a gas source for ionization. The greater the flow rate, the more ionizable gas molecules are provided, the higher the concentration of plasma, and the faster the etching rate. However, when the ionization capacity limit of the electrode is exceeded, continuing to increase the gas flow rate of oxygen will not increase the ionized ions, but will block the plasma from reaching the film layer that needs to be etched. The present invention optimizes the above situation by reasonably setting the gas flow rate of oxygen.

[0049] In some embodiments, in S105, the gas flow rate of argon is 5-20sccm, which can be 5sccm, 10sccm, 15sccm, 20sccm and any value therebetween. Preferably, the gas flow rate of argon is 5sccm. The advantage of the present invention in reasonably setting the gas flow rate of argon in plasma etching is that it can activate the surface of the film layer. Argon plays a physical bombardment role in plasma etching, so argon is not consumed during etching. The loss of argon is mainly pumped away by the vacuum system, so only this part of the loss needs to be replenished. If the gas flow rate is too small, the consumed argon will not be replenished, and the concentration of argon will become less and less, so the effect of physical activation will gradually weaken. If there is too much argon, it will block the plasma, shorten the free path of the plasma, and reduce the etching rate. The present invention optimizes the above situation by reasonably setting the gas flow rate of argon.

[0050] The first reason for selecting oxygen in the present invention is that the film layer to be etched in the present invention is a parylene film layer, which is an organic polymer material and a substance composed of carbon chains. Active oxygen can react chemically with it to generate gas and be sucked away by the vacuum system. The second reason is that oxygen is a common gas commonly used in industry, does not require special containers and equipment, and the tail gas generated by etching is non-toxic and harmless, highly economical and environmentally friendly.

[0051] The reason why the present invention selects argon is that argon is an inert gas with a large molecular weight and has a high kinetic energy after ionization, which is beneficial to physically activate the surface of the film layer.

[0052] Compared with the CF4 gas commonly used in the prior art plasma etching, the etching gas of the technical solution of the present invention has significant economic benefits, and the use of argon and oxygen has low equipment requirements and low equipment costs. Furthermore, the use of argon and oxygen will not produce toxic and harmful tail gas, which is more advantageous in terms of environmental sustainability.

[0053] In some embodiments, in S105, the etching time is 6-10 hours, which can be 6 hours, 7 hours, 8 hours, 9 hours, 10 hours and any value therebetween. Plasma etching is a way to remove a film layer on a molecular scale. As the etching proceeds, the film layer will gradually react from the outer surface to the inside, and the generated gas will be pumped away by the vacuum system. The film layer sealed and protected by the fixture will not be etched, and a neat and smooth cross-sectional step will be formed at the interface. If the etching time is not enough, the film layer is not completely removed, and the film layer will be pulled when the mask is removed, causing the interface to deform. If the etching time is too long, the etching gas will etch the film layer in the cross-section of the film layer, thereby rendering the fixture protection ineffective. The present invention reasonably controls the etching time of plasma etching, so that plasma etching can completely remove the mask layer and the parylene film layer on the profiled surface, without any film layer residue, and at the same time makes the fracture interface of the film layer neat and smooth.

[0054] It should be noted that the etching time of the present invention depends on the thickness of the parylene film layer, and the etching time is positively correlated with the thickness of the parylene film layer.

[0055] In some embodiments, the etching power is 1000-2000w, which can be 1000w, 1200w, 1400w, 1600w, 1800w, 2000w and any value therebetween. Preferably, the etching power is 1800w. The advantage of the present invention in setting the etching power in plasma etching reasonably is that it can ensure a high etching rate while making the fracture interface of the film layer neat and smooth. The etching power not only provides ionization energy for gas molecules, but also accelerates the ionized ions. Therefore, the appropriate power can maintain a sufficient plasma concentration and is also suitable for plasma acceleration. Because too high ion energy will cause the bombardment energy of ions on the film layer to be too high, resulting in too high a temperature at the etching interface, causing the film layer to turn yellow and discolor or even carbonize and blacken, causing black dust to pollute the product. In addition, too high a plasma concentration or too high an ion energy will cause the chemical etching effect to weaken and the physical bombardment effect to increase, then the cross section of the film layer will become rough and frosted. The present invention optimizes the above situation by reasonably setting the etching power.

[0056] In some embodiments, the etching pressure is 30-60Pa, which can be 30Pa, 40Pa, 50Pa, 60Pa and any value therebetween. Preferably, the etching pressure is 45Pa. The advantage of the present invention in rationally setting the etching pressure in plasma etching is that the etching rate and etching results can be optimized. Suitable pressure can increase the mean free path of gas molecules and reduce the probability of plasma collision before reaching the etched surface, thereby improving the directionality and anisotropy of etching and enhancing the etching rate. At the same time, appropriate pressure settings help reduce physical damage during the etching process and reduce the potential risk of damage to the device.

[0057] It should be noted that in S101, the present invention has no particular restrictions on the material and specific method of forming the mask layer on the top surface and the bottom surface of the micro device, and can be formed by techniques well known to those skilled in the art or commercially available products. Preferably, the mask layer is formed by UV glue on the top surface and the bottom surface of the micro device.

[0058] In some embodiments, in S101, a mask layer is formed on the top of the irregular surface using an acrylic adhesive. Preferably, the mask layer is composed of the following components in percentage by mass: 15-30% isobornyl acrylate, 45-65% polyurethane modified methacrylic resin, 5-15% hexanediol diacrylate, 5-10% acrylic acid, and 0-1% adhesion promoter.

[0059] In some embodiments, in S101, a mask layer is formed on the top of the profiled surface by using a Czochralski method, and the specific steps are as follows: Completely immerse the top of the profiled surface into the acrylic adhesive, the thickness of the acrylic adhesive is 0.1-0.3mm; The micro-device is pulled up so that the top of the irregular surface leaves the acrylic adhesive, and the acrylic adhesive uniformly wraps the top of the irregular surface; The acrylate adhesive is cured to form a mask layer.

[0060] The present invention creatively adopts the pulling method to form a mask layer on the irregular surface, which can ensure that the irregular surface is evenly wrapped by the mask layer and the thickness of the mask layer in each area is consistent. If the thickness of the mask layer is inconsistent, during the plasma etching process, the thin position of the mask layer will be etched away by the plasma first, and then further etched to the gold layer of the solder column, causing the gold layer to appear different colors.

[0061] In some embodiments, in S102, the thickness of the parylene film layer is 10-25 μm. Preferably, the thickness of the parylene film layer is 15 μm. The present invention reasonably sets the thickness of the parylene film layer, and reasonably reduces the difficulty of removing the parylene film layer on the basis of ensuring the protective performance of the parylene.

[0062] In some embodiments, in S103, the laser is a pulsed laser with a wavelength of 355-1064nm, a pulse width of femtoseconds or picoseconds, a cutting power of 1-10W, and a cutting time of 30-120 seconds. Preferably, the laser is an ultraviolet laser with a wavelength of 355nm, a pulse width of 100 femtoseconds-20 picoseconds, a cutting power of 2W, and a cutting time of 120 seconds.

[0063] It should be noted that the cutting time of the present invention depends on the thickness of the parylene film layer, and the cutting time is positively correlated with the thickness of the parylene film layer.

[0064] In some embodiments, in S104, as Figure 2 As shown, the fixture 20 includes a substrate 21 and a sealing plate 22; the substrate 21 is provided with at least one blind hole matching the shape of the micro device; the sealing plate 22 is provided with a through hole corresponding to the blind hole; when the micro device is placed in the blind hole, the sealing plate 22 is covered on the top of the substrate 21 to close the blind hole, and the top of the profiled surface with the mask layer and the parylene film layer extends out of the through hole. Figure 2 As shown, the entire TEC is sealed in the fixture 20, with only the tops of the two solder pillars extending out of the through holes. The present invention adopts a special fixture design to prevent plasma from entering the gap between the semiconductors between the upper and lower cover plates of the TEC during the plasma etching process, thereby avoiding damage to the parylene film layer and ensuring that the internal coating still has good protective performance after etching.

[0065] In some embodiments, in S104, the jig is made of silicone material with a Shore A hardness of 50-70 degrees. The reason for this design of the present invention is that the silicone material has certain elasticity and toughness, and can completely fit the TEC to prevent plasma from entering through the gap of the jig to damage the parylene layer.

[0066] Furthermore, silicone is a soft material that can effectively protect TEC from being damaged by hard materials. If the jig itself is made of hard material, because TEC itself is small and difficult to operate, when the surface of TEC is covered with the parylene film, the film is easily damaged by the jig made of hard material, thus losing its protective effect.

[0067] Furthermore, although the molecular bond energy of the silicone jig is greater, it rarely undergoes chemical reactions and therefore will not be etched, thus protecting the area of ​​the TEC that requires the parylene film layer.

[0068] In some embodiments, the size of the micro device is 4×2×0.6-7×5×1.5 mm. The present invention can effectively coat and remove the parylene film on the micro device with internal channels and special-shaped surfaces, and make the fracture interface of the film layer neat and smooth, improve the efficiency and accuracy of film removal, and greatly reduce the potential risk of damage to the device.

[0069] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0070] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0071] The following will take TEC (thermoelectric cooler) as an example to illustrate the technical solution of the present invention, but the following description does not constitute a limitation on the protection scope of the present invention. The mask layer in the embodiment and the comparative example is composed of the following components in percentage by mass: 20% isobornyl acrylate, 60% polyurethane modified methacrylic resin, 12% hexanediol diacrylate, 7% acrylic acid, and 1% adhesion promoter.

[0072] Example 1 S101, forming a mask layer on the top of the TEC top cover plate, the TEC bottom cover plate, and the top of the TEC welding column; The mask layer is formed on the top of the TEC solder column by using the Czochralski method.

[0073] S102, coating the inner and outer surfaces of the TEC with a parylene film layer by a vapor deposition method; The thickness of the parylene film layer is 15 μm.

[0074] S103, cutting the sides of the TEC top cover plate and the TEC bottom cover plate by laser, and then removing the mask layer and the parylene film layer on the TEC top cover plate and the TEC bottom cover plate; The laser is an ultraviolet laser with a wavelength of 355nm, a pulse width of 15 picoseconds, a cutting power of 2W, and a cutting time of 120 seconds.

[0075] S104, completely encapsulating the TEC and placing it inside the jig, with the top of the solder column having the mask layer and the parylene film layer extending out of the top of the jig; The fixture is made of silicone with a Shore A hardness of 60 degrees.

[0076] S105, plasma etching the top of the welding column using oxygen and argon to remove the mask layer and the parylene film layer; Among them, the etching power is 1800w, the etching pressure is 45Pa, the gas flow rate of oxygen is 95sccm, the gas flow rate of argon is 5sccm, the mixing ratio of oxygen and argon is 19:1, and the etching time is 8 hours.

[0077] Example 2 S101, forming a mask layer on the top of the TEC top cover plate, the TEC bottom cover plate, and the top of the TEC welding column; The mask layer is formed on the top of the TEC solder column by using the Czochralski method.

[0078] S102, coating the inner and outer surfaces of the TEC with a parylene film layer by a vapor deposition method; The thickness of the parylene film layer is 15 μm.

[0079] S103, cutting the sides of the TEC top cover plate and the TEC bottom cover plate by laser, and then removing the mask layer and the parylene film layer on the TEC top cover plate and the TEC bottom cover plate; The laser is an ultraviolet laser with a wavelength of 355nm, a pulse width of 15 picoseconds, a cutting power of 2W, and a cutting time of 120 seconds.

[0080] S104, completely encapsulating the TEC and placing it inside the jig, with the top of the solder column having the mask layer and the parylene film layer extending out of the top of the jig; The fixture is made of silicone with a Shore A hardness of 60 degrees.

[0081] S105, plasma etching the top of the welding column using oxygen and argon to remove the mask layer and the parylene film layer; Among them, the etching power is 1200w, the etching pressure is 45Pa, the gas flow rate of oxygen is 95sccm, the gas flow rate of argon is 5sccm, the mixing ratio of oxygen and argon is 19:1, and the etching time is 8 hours.

[0082] Example 3 S101, forming a mask layer on the top of the TEC top cover plate, the TEC bottom cover plate, and the top of the TEC welding column; The mask layer is formed on the top of the TEC solder column by using the Czochralski method.

[0083] S102, coating the inner and outer surfaces of the TEC with a parylene film layer by a vapor deposition method; The thickness of the parylene film layer is 15 μm.

[0084] S103, cutting the sides of the TEC top cover plate and the TEC bottom cover plate by laser, and then removing the mask layer and the parylene film layer on the TEC top cover plate and the TEC bottom cover plate; The laser is an ultraviolet laser with a wavelength of 355nm, a pulse width of 15 picoseconds, a cutting power of 2W, and a cutting time of 120 seconds.

[0085] S104, completely encapsulating the TEC and placing it inside the jig, with the top of the solder column having the mask layer and the parylene film layer extending out of the top of the jig; The fixture is made of silicone with a Shore A hardness of 60 degrees.

[0086] S105, plasma etching the top of the welding column using oxygen and argon to remove the mask layer and the parylene film layer; Among them, the etching power is 1800w, the etching pressure is 30Pa, the gas flow rate of oxygen is 60sccm, the gas flow rate of argon is 5sccm, the mixing ratio of oxygen and argon is 12:1, and the etching time is 8 hours.

[0087] Comparative Example 1 The method of Example 1 is referred to, except that, in S101, a mask layer is formed on the top of the TEC solder column by a dispensing method, and the specific operations of the dispensing method are: 1. Place the product into a fixture of an automatic dispensing device; 2. Run the automatic dispensing program to seal the area that needs to be masked with glue; 3. Use 365nm UV light for curing; 4. Remove the product.

[0088] Comparative Example 2 The method of Example 1 is referred to, except that in S105, the etching power is 2500w.

[0089] Comparative Example 3 The method of Example 1 is referred to, except that in S105, the etching power is 500w.

[0090] Comparative Example 4 The method of Example 1 is referred to, except that in S105, the etching pressure is 80 Pa, the gas flow rate of oxygen is 250 sccm, the gas flow rate of argon is 5 sccm, and the mixing ratio of oxygen to argon is 50:1.

[0091] Comparative Example 5 The method of Example 1 is referred to, except that in S105, the etching pressure is 45 Pa, the gas flow rate of oxygen is 50 sccm, the gas flow rate of argon is 50 sccm, and the mixing ratio of oxygen to argon is 1:1.

[0092] Test Case The TEC after film removal obtained in the above embodiments and comparative examples was subjected to appearance inspection, and the results of the appearance inspection are shown in Table 1. The appearance inspection method is to fully inspect whether the fracture interface of the film layer on the top of the solder column is neat and smooth, whether there is any film layer remaining on the top of the solder column, and whether the gold layer on the top of the solder column is different in color under a 10x microscope.

[0093] It should be noted that the film residues of the TEC structure in Table 1 are divided into none, a small amount and a large amount. None means that there is no film residue at this position or only film residues that are difficult to observe; a small amount means that there is a small area of ​​observable film residues at this position, but it will not affect the subsequent use of TEC and no further treatment is required; a large amount means that there is a large area of ​​observable film residues at this position, which has affected the subsequent use of TEC and needs further treatment to remove the residual film or be eliminated as a defective product.

[0094] In the fracture interface appearance of the TEC structure film layer in Table 1, the film layer is slightly warped and stretched, corresponding to a small amount of film residue. The fracture interface of the film layer has only a small amount of burrs and warping, which will not affect the subsequent use of TEC and does not require further treatment; the film layer is severely warped and stretched, corresponding to a large amount of film residue. The fracture interface of the film layer has severe burrs and warping, which can even exceed the height of the weld column, which has affected the subsequent use of TEC and needs further treatment to remove the residual film or eliminate it as a defective product.

[0095] In the heterochromatic appearance of the TEC structure in Table 1, obvious heterochromatic refers to that the heterochromatic area on the surface of the solder column is not large, but there are clear heterochromatic points, which has a certain impact on the subsequent use of the TEC; severe heterochromatic refers to that the surface of the solder column is basically completely covered by the heterochromatic, and the TEC is basically unusable in the future.

[0096] Table 1

[0097] The following are microscopic images of the TEC surfaces after film removal obtained in some examples and comparative examples.

[0098] Figure 3 and Figure 4 This is a microscopic image of the TEC surface after film removal obtained in Example 1. Under a 10x microscope, the fracture interface of the film layer on the top of the TEC solder column is neat and smooth, there is no film layer remaining on the top of the solder column, and there is no discoloration on the top of the solder column.

[0099] Figure 5 This is a microscopic image of the TEC surface after film removal obtained in Example 2. Under a 10x microscope, the fracture interface of the film layer at the top of the TEC solder column has a slight film layer warping and stretching, a small amount of film layer remains on the top of the solder column, and there is no discoloration on the top of the solder column. It can be seen from the figure that there is a small amount of film layer remaining on both the left and right solder columns, and the film layer on the right solder column has a slight warping and stretching.

[0100] Figure 6 This is the apparent microscope image of the TEC after the film is removed using Comparative Example 1. Under a 10x microscope, the fracture interface of the film layer on the top of the TEC solder column is neat and smooth, there is no film layer remaining on the top of the solder column, and the top of the solder column has a different color. Since the mask layer is formed by the dispensing method, the thickness of the mask layer is inconsistent in some areas, especially in the corner areas. During the plasma etching process, the thin part of the mask layer will be etched away by plasma, and then further etched to the gold layer of the solder column, causing the gold layer to have a significant different color.

[0101] Figure 7 and Figure 8 This is a microscopic image of the TEC surface after film removal obtained in Comparative Example 2. Under a 10x microscope, the fracture interface of the film layer at the top of the TEC solder column is rough and frosted, and the film layer is discolored and yellowed. There is no film layer remaining on the top of the solder column, and the top of the solder column has serious discoloration. It can be seen that when the technical solution of the present invention is not adopted, for example, when the etching power is significantly higher than the scope protected by the present invention, the corresponding technical effect cannot be achieved, and the technical problem to be solved by the present invention cannot be solved.

[0102] Fig. 9 This is a microscopic image of the TEC surface after film removal obtained in Comparative Example 4. Under a 10x microscope, the fracture interface of the film layer at the top of the TEC solder column has serious film warping and stretching, a large amount of film layer remains on the top of the solder column, and there is no discoloration on the top of the solder column. It can be seen that when the technical solution of the present invention is not adopted, for example, when the etching pressure and the gas flow rate of the etching gas are significantly higher than the scope protected by the present invention, the corresponding technical effect cannot be achieved, and the technical problem to be solved by the present invention cannot be solved.

[0103] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present invention can effectively coat and remove the parylene film on a micro device with internal channels and irregular surfaces, and make the fracture interface of the film layer neat and smooth, thereby improving the efficiency and accuracy of film removal and reducing the potential risk of damage to the device.

[0104] Furthermore, according to Example 1 and Examples 2-3, it can be known that by adopting the preferred etching process of the present invention, using the etching power, etching pressure and the mixing ratio of oxygen and argon under the preferred values, through the synergistic effect of the three, the fracture interface of the film layer can be made more neat and smooth, and the film removal efficiency and accuracy can be more effectively improved, while the potential risk of damage to the device can be greatly reduced.

[0105] Furthermore, in order to specifically verify the technical effect of the fixture design of the present invention, the present invention conducted a performance test on the TEC after film removal obtained in Example 1, and the fixture material at this time was silica gel.

[0106] Comparative Example 6 was designed again. Comparative Example 6 was carried out with reference to Example 1, except that the material of the fixture was aluminum with anodized surface. The performance of the TEC obtained in Comparative Example 6 after film removal was tested.

[0107] The test results of the protective performance of TEC after film removal with different fixture designs are shown in Table 2. The tested protective performance includes salt spray resistance and insulation withstand voltage performance.

[0108] Among them, the test method for salt spray resistance refers to GB / T10125. After 48 hours of salt spray resistance test, check the appearance of the internal channel. If there is no rust or corrosion, it is qualified. If there is rust or corrosion, it is unqualified.

[0109] The test method for insulation withstand voltage performance includes connecting a welding column through the negative pole of the withstand voltage tester, and the positive pole of the withstand voltage tester contacts the film layer. For details, please refer to GB / T1408.1-2016. After the insulation withstand voltage performance test, the film layer can reach the plane, and the breakdown voltage is 2500v, DC, which is qualified, and it is unqualified if it is lower than this value.

[0110] Table 2

[0111] It can be seen that the fixture design using the technical solution of the present invention can prevent plasma from entering the internal channels of the microdevice during the plasma etching process, avoid damaging the parylene film layer of the internal channel, and ensure that the internal coating still has good protective performance after etching.

[0112] After the top cover of the TEC was removed by different fixture designs, the thickness of the parylene film at each position of the internal channel was measured, and the specific results are shown in Table 3. The thickness of the parylene film at each position in Table 3 was measured by micro-sectioning, which specifically includes embedding, grinding, polishing, and observing and measuring the film thickness under a microscope. For details, see IPC TM-650 2.1.1.F.

[0113] Table 3

[0114] like Fig.10 As shown, Fig.10 This is a schematic diagram of various positions of the internal channel of the TEC after the top cover plate is removed after the film is removed in Example 6. Positions 1-4 are the outer ring positions of the TEC, and the thickness of the parylene film should be consistent or close. Because the fixture is made of aluminum with anodized surface, the four positions are not completely sealed and there are gaps. During the plasma etching process, the plasma enters the four positions and etches away part of the film layer. The film thickness of the four positions is damaged to varying degrees, affecting the protective performance of the film layer. Among them, the film thickness of positions 3 and 4 is more significantly reduced.

[0115] The above results show that when the jig material is aluminum with anodized surface, it cannot be closely attached to TEC, resulting in a gap between the jig and TEC. Plasma enters the internal channel through the gap and corrodes part of the film layer. However, the silicone jig has good sealing performance and the film layer of the internal channel is not corroded. The special jig design of the present invention can prevent plasma from entering the internal channel of the micro device during plasma etching, avoid damaging the parylene film layer of the internal channel, and ensure that the internal coating still has good protective performance after etching.

[0116] The embodiments of the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for coating and removing parylene from a micro device having an internal channel and a profiled surface, characterized in that: The following steps are involved: S101, forming a mask layer on the top surface of the micro device, the bottom surface of the micro device and the top of the special-shaped surface; S102, coating the inner and outer surfaces of the micro-device with a parylene film layer by a vapor deposition method; S103, cutting the sides of the top surface of the micro device and the bottom surface of the micro device by laser, and then removing the mask layer and the parylene film layer on the top surface of the micro device and the bottom surface of the micro device; S104, completely wrapping the micro device and placing it inside a jig, with the top of the special-shaped surface having the mask layer and the parylene film layer extending out of the top of the jig; S105, plasma etching the top of the irregular surface with oxygen and argon to remove the mask layer and the parylene film layer, wherein the etching power is 1000-2000w, the gas flow rate of oxygen is 60-200sccm, and the gas flow rate of argon is 5-20sccm.

2. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S105, the mixing ratio of oxygen to argon is 3:1-40:

1.

3. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to any one of claims 1 or 2, characterized in that: In S105, the etching pressure is 30-60Pa.

4. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S105 , the etching time is 6-10 hours.

5. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S101 , a mask layer is formed on the top surface of the micro device and the bottom surface of the micro device using glue or tape material.

6. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S101, an acrylic adhesive is used to form a mask layer on the top of the irregular surface.

7. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 6, characterized in that: In S101, a mask layer is formed on the top of the irregular surface by using a Czochralski method, and the specific steps are as follows: The top of the special-shaped surface is completely immersed in the acrylic adhesive, the thickness of the acrylic adhesive is 0.1-0.3 mm; Pulling up the micro-device so that the top of the irregular surface leaves the acrylic adhesive, and the acrylic adhesive uniformly wraps the top of the irregular surface; The acrylate adhesive is cured to form a mask layer.

8. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S102, the thickness of the parylene film layer is 10-25 μm.

9. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S103, the laser is a pulse laser with a wavelength of 355-1064 nm, a pulse width of femtosecond or picosecond level, a cutting power of 1-10 W, and a cutting time of 30-120 seconds.

10. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S104, the fixture includes: A substrate, wherein at least one blind hole matching the shape of the micro-device is formed on the substrate; A sealing plate, wherein the sealing plate is provided with through holes corresponding to the blind holes; Wherein, after the micro device is placed in the blind hole, the sealing plate cover is arranged on the top of the substrate to close the blind hole, and the top of the special-shaped surface with the mask layer and the parylene film layer protrudes out of the through hole.

11. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to any one of claims 1 or 10, characterized in that: In S104, the fixture is made of silicone with a Shore A hardness of 50-70 degrees.

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