Josephson junction preparation method and quantum chip
By treating the wafer surface twice by buffering the oxide etching solution, the loss problem of the two-level system caused by plasma beam etching is solved, and the more efficient Josephson junction preparation is achieved, and the performance of the quantum chip is improved.
Patent Information
- Application Number
- CN202411959080.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-03-25
AI Technical Summary
In the prior art, when making the Josephson junction of superconducting quantum chips, the oxide layer is removed by plasma beam etching, resulting in intensification of the loss of the underlying line and substrate surface, increasing the loss of the two-level system and limiting the chip performance.
The wafer surface was treated twice with buffer oxide etching liquid, and the oxide layer of the underlying line was removed for the first time. After development, the oxide layer generated by the photolithography process was removed again to ensure that there was no oxide layer on the underlying line surface when the Josephson junction was grown.
It effectively avoids the loss of plasma beam etching on the underlying circuit and substrate, reduces the loss of the two-level system, and improves the performance of the quantum chip.
Smart Images
Figure CN119698232A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of quantum technology, and in particular to a method for preparing a Josephson junction and a quantum chip. Background Art
[0002] The current mainstream superconducting quantum chip Josephson junction production does not perform corresponding treatment on the oxide layer on the underlying circuit before the lithography pattern is defined. Instead, after the lithography pattern is defined, the junction area is plasma-beam etched before the Josephson junction is grown in the junction area. For example, Ar plasma beam etching is used to remove the surface oxide layer. However, because this process itself does not have directional selectivity, not only may the underlying circuit be over-etched, that is, the exposed underlying circuit metal continues to be etched after the oxide layer is etched, but also the non-bottom-layer circuit part of the junction area, that is, the substrate part, will also be partially etched by the ion beam, which will cause surface roughness, thereby exacerbating the two-level system (TLS) loss and limiting the chip performance.
[0003] Therefore, how to provide a method for preparing a Josephson junction that will not aggravate the loss of the two-level system when removing the oxide layer is an urgent problem to be solved by those skilled in the art. Summary of the invention
[0004] The purpose of the present invention is to provide a method for preparing a Josephson junction without increasing the loss of a two-level system.
[0005] In order to solve the above technical problems, the present invention provides a method for preparing a Josephson junction, comprising:
[0006] Putting the wafer with the bottom circuit prepared thereon into the buffered oxide etching solution for the first time to remove the oxide layer on the surface of the bottom circuit;
[0007] Disposing a photoresist on the surface of the wafer that has been treated with the buffered oxide etching solution for the first time, and exposing and developing the photoresist to perform patterning, so as to expose a preset area on the surface of the wafer where a Josephson junction is disposed;
[0008] placing the developed wafer into a buffered oxide etching solution for a second time to remove the oxide layer generated again on the surface of the bottom circuit;
[0009] Based on the patterned photoresist disposed on the surface of the wafer after being treated with the buffered oxide etching solution for the second time, a Josephson junction connected to the bottom circuit is disposed.
[0010] Optionally, after placing the wafer with the bottom layer circuit prepared thereon into the buffered oxide etching solution for the first time, the method further comprises:
[0011] The wafer that has been treated with the buffered oxide etching solution for the first time is placed in ultrapure water for cleaning;
[0012] And / or, after placing the developed wafer into the buffered oxide etching solution for the second time, the method further comprises:
[0013] The wafer that has been treated with the buffered oxide etching solution for the second time is placed in ultrapure water for cleaning.
[0014] Optionally, providing a Josephson junction connected to the bottom circuit based on a patterned photoresist provided on the surface of the wafer after the second treatment with the buffered oxide etching solution includes:
[0015] Putting the wafer which has been treated with the buffered oxide etching solution for the second time into the electron beam evaporation equipment and evacuating the equipment;
[0016] The electron beam evaporation device is used to grow a Josephson junction connected to the bottom circuit based on the patterned photoresist set on the surface of the wafer.
[0017] Optionally, after growing the Josephson junction connected to the bottom circuit, the method further comprises:
[0018] The residual photoresist on the surface of the wafer is stripped off.
[0019] Optionally, stripping the residual photoresist on the surface of the wafer includes:
[0020] The wafer provided with the Josephson junction is placed in an N-methylpyrrolidone solution to strip off the residual photoresist on the surface of the wafer.
[0021] Optionally, after development, at least the surface of the photoresist is provided with a protective layer that is insoluble in the buffered oxide etching solution.
[0022] Optionally, the protective layer is a polymethyl methacrylate layer.
[0023] Optionally, providing a photoresist on the surface of the wafer treated with the buffered oxide etching solution for the first time, and exposing and developing the photoresist to perform patterning includes:
[0024] Spin coating a first layer of electron beam photoresist, a second layer of electron beam photoresist and a conductive adhesive in sequence on the surface of the wafer along the thickness direction, and baking after each layer of electron beam photoresist is spin coated to form a photoresist stacking structure;
[0025] Using an electron beam exposure machine to expose the photoresist stack structure;
[0026] The exposed photoresist stacked structure is developed using a developer.
[0027] Optionally, the coating speed of the first layer of electron beam photoresist is in the range of 1500 rpm to 2000 rpm; the temperature of baking the first layer of electron beam photoresist is in the range of 170° C. to 210° C., and the baking time is 2 min to 4 min;
[0028] The coating speed of the second layer of electron beam photoresist is in the range of 1000 rpm to 2000 rpm; the temperature of baking the second layer of electron beam photoresist is in the range of 170° C. to 210° C., and the baking time is 3 min to 5 min.
[0029] The present invention also provides a quantum chip, comprising a Josephson junction prepared by any of the above-mentioned methods for preparing a Josephson junction.
[0030] The present invention provides a method for preparing a Josephson junction, comprising: placing a wafer prepared with a bottom circuit into a buffered oxide etching solution for the first time to remove an oxide layer on the surface of the bottom circuit; arranging a photoresist on the surface of the wafer treated by the buffered oxide etching solution for the first time, and exposing and developing the photoresist for patterning to expose a preset area on the wafer surface where a Josephson junction is arranged; placing the developed wafer into the buffered oxide etching solution for the second time to remove an oxide layer generated again on the surface of the bottom circuit; and arranging a Josephson junction connected to the bottom circuit based on the patterned photoresist arranged on the surface of the wafer treated by the buffered oxide etching solution for the second time.
[0031] Before the photolithography process, the buffered oxide etchant is used to remove the oxide layer on the wafer surface for the first time. After the development of the photolithography process, the buffered oxide etchant is used for the second time to remove the oxide layer on the wafer surface due to the steps of coating and baking, so as to ensure that there is no oxide layer on the surface of the bottom line when the Josephson junction is grown. Using the buffered oxide etchant to remove the oxide layer can avoid the loss of the bottom line and the substrate surface on the wafer caused by ion beam etching, thereby avoiding the aggravation of the two-level system loss and improving the performance of the quantum chip.
[0032] The present invention also provides a quantum chip, which also has the above-mentioned beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0034] Figure 1 A flowchart of a method for preparing a Josephson junction provided by an embodiment of the present invention;
[0035] Figure 2 The present invention provides a flowchart of a specific method for preparing a Josephson junction. DETAILED DESCRIPTION
[0036] The core of the present invention is to provide a method for preparing a Josephson junction. In the prior art, the method for preparing a Josephson junction includes: setting a photoresist on the surface of a wafer with a bottom layer circuit and baking it, and then using an electron beam exposure machine to define the Josephson junction pattern on the wafer; then using a developer to develop the exposed wafer, and then placing the wafer in an Ar plasma beam etching device to perform plasma beam etching to remove the oxide layer; finally, placing the wafer in an electron beam evaporation device to grow the metal of the Josephson junction. Since the oxide layer is etched using a plasma beam, the process itself does not have directional selectivity. Not only may the bottom layer circuit be over-etched, that is, the exposed bottom layer circuit metal continues to be etched after the oxide layer is etched, but also the non-bottom layer circuit part of the junction area, that is, the substrate part, will also be partially etched by the ion beam, which will cause the surface to be rough, thereby exacerbating the TLS loss of the two-level system, resulting in the chip performance being limited.
[0037] In superconducting quantum chips, the impact of TLS (Two-Level Systems) loss is an important research area. TLS loss refers to certain defects or impurities in the material, which can cause energy level transitions, thereby affecting the coherence and decoherence process of superconducting quantum bits. These defects may cause energy loss and noise in superconducting quantum chips, thereby affecting the performance of quantum bits. The impact of TLS loss in superconducting quantum chips is mainly manifested in the following aspects:
[0038] 1. Shortening of coherence time: The existence of TLS loss will shorten the coherence time of quantum bits because they can interact with quantum bits and cause energy level transitions, resulting in the loss of quantum information.
[0039] 2. Decoherence noise: TLS loss can cause decoherence noise, which interferes with the quantum state of quantum bits and affects the accuracy of quantum computing.
[0040] 3. Optimization of materials and processes: In order to reduce the impact of TLS losses, researchers need to optimize the materials and manufacturing processes of superconducting quantum chips to reduce the introduction of defects and impurities.
[0041] 4. Temperature dependence: The impact of TLS loss may be different at different temperatures. For example, studies have shown that TLS loss is still significant at liquid helium temperature (about 4 K) and has obvious power and temperature dependence.
[0042] 5. Multi-layer stacking technology: In the multi-layer stacking technology of superconducting quantum chips, the through silicon via (TSV) filling process is the key, and TLS loss may affect the conduction performance of TSV.
[0043] 6. Challenges of quantum computing: Although superconducting quantum computing chips have advantages in expanding the number of bits, how to simultaneously improve the quality and quantity of quantum bits, thereby truly improving chip performance, is a challenge currently facing the field of quantum computing.
[0044] In summary, the impact of TLS loss in superconducting quantum chips is multifaceted, and its negative impact on quantum computing performance needs to be reduced through comprehensive optimization of material science, process technology, chip design and quantum control technology.
[0045] The present invention provides a method for preparing a Josephson junction, which includes: placing a wafer prepared with a bottom circuit in a buffered oxide etching solution for the first time to remove an oxide layer on the surface of the bottom circuit; setting a photoresist on the surface of the wafer that has been treated with the buffered oxide etching solution for the first time, and exposing and developing the photoresist for patterning to expose a preset area on the wafer surface where a Josephson junction is set; placing the developed wafer in the buffered oxide etching solution for the second time to remove an oxide layer generated again on the surface of the bottom circuit; and setting a Josephson junction connected to the bottom circuit based on the patterned photoresist set on the surface of the wafer that has been treated with the buffered oxide etching solution for the second time.
[0046] Before the photolithography process, the buffered oxide etchant is used to remove the oxide layer on the wafer surface for the first time. After the development of the photolithography process, the buffered oxide etchant is used for the second time to remove the oxide layer on the wafer surface due to the steps of coating and baking, so as to ensure that there is no oxide layer on the surface of the bottom line when the Josephson junction is grown. Using the buffered oxide etchant to remove the oxide layer can avoid the loss of the bottom line and the substrate surface on the wafer caused by ion beam etching, thereby avoiding the aggravation of the two-level system loss and improving the performance of the quantum chip.
[0047] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0048] Embodiment 1
[0049] Please refer to Figure 1 , Figure 1 The present invention provides a flow chart of a method for preparing a Josephson junction.
[0050] See also Figure 1 In an embodiment of the present invention, a method for preparing a Josephson junction includes:
[0051] S101: placing the wafer with the bottom circuit prepared thereon into a buffered oxide etching solution for the first time to remove the oxide layer on the surface of the bottom circuit.
[0052] In this embodiment, the wafer surface is pre-set with an underlying circuit, which is usually part of the circuit in the quantum chip. The specific content of the underlying circuit can be set according to actual conditions and is not specifically limited here.
[0053] In this step, the wafer prepared with the bottom line will be placed in a buffered oxide etching solution, i.e., a BOE solution, for the first time, and the oxide layer on the surface of the bottom line will be removed by immersion using the BOE solution. Generally speaking, the oxide layer on the entire surface of the wafer can be removed by immersion in the BOE solution, and the BOE solution usually does not react with the substrate and the metal of the bottom line, so it will not damage the bottom line and the substrate, and therefore will not aggravate the loss of the two-level system. For the specific components of the BOE solution, please refer to the prior art, and will not be repeated here.
[0054] S102: a photoresist is disposed on the surface of the wafer that has been treated with the buffered oxide etching solution for the first time, and the photoresist is exposed and developed to perform patterning to expose a preset area on the wafer surface where a Josephson junction is disposed.
[0055] In this step, a photoresist is arranged on the surface of the wafer, and the arrangement of the photoresist usually requires steps such as spin coating and baking. Then, in this step, the photoresist is first exposed, and after exposure, it is developed to pattern the photoresist. The specific content of this step will be described in detail in the following invention embodiments, and will not be repeated here. In the process of arranging the photoresist, for example, it is very easy to cause re-oxidation of the wafer surface during baking, and the oxide layer that may be generated in this step is specifically a subsidiary product generated after removing the oxide layer in S101, so its thickness is usually low.
[0056] After the photoresist is patterned in this step, a preset area on the wafer surface where a Josephson junction is to be arranged will be exposed, so that in a subsequent step, a Josephson junction can be arranged in the preset area.
[0057] S103: placing the developed wafer into a buffered oxide etching solution for a second time to remove the oxide layer generated again on the surface of the bottom circuit.
[0058] In this step, the wafer with patterned photoresist after development needs to be placed in a buffered oxide etchant, that is, placed in the buffered oxide etchant for the second time, to remove the oxide layer generated on the surface of the wafer when the patterned photoresist is set. When using the buffered oxide etchant to remove the oxide layer, damage to the underlying circuit and substrate can be avoided, so the two-level system loss will not be aggravated.
[0059] Preferably, in this embodiment, after development, at least the surface of the photoresist is provided with a protective layer insoluble in the buffered oxide etchant. In this step, since the patterned photoresist needs to be immersed in the buffered oxide etchant, in order to ensure that the patterned photoresist can still maintain a good morphology after the oxide layer is removed for the second time, a protective layer insoluble in the buffered oxide etchant is formed on at least the surface of the above-mentioned photoresist, and the protective layer protects the photoresist from deformation after being immersed in the buffered oxide etchant. Generally speaking, the entire body of the photoresist can be formed of a material insoluble in the buffered oxide etchant, rather than just forming a protective layer of the above-mentioned material on the surface of the photoresist, so as to avoid deformation of the photoresist after being immersed in the buffered oxide etchant.
[0060] Specifically, in the present embodiment, the protective layer is a polymethyl methacrylate (PMMA) layer, that is, the material of the protective layer can be PMMA, and then the main material of the entire photoresist can be PMMA. Buffered oxide etching solution is a commonly used hydrofluoric acid buffer solution, and its components mainly include hydrofluoric acid (HF) and ammonium fluoride (NH4F). Methyl methacrylate (MMA) is an organic chemical raw material, mainly used in the production of organic glass. MMA can form PMMA during the polymerization process, which is a polymer with excellent transparency and weather resistance. The reaction of BOE solution with PMMA is very slow, and PMMA can be considered insoluble in BOE solution within a limited time. Therefore, when polymethyl methacrylate is used as a protective layer, the damage of BOE solution to the pattern defined by the photoresist is very limited, and the impact can be ignored.
[0061] PMMA is the main material of the electron beam photoresist after curing, so when the electron beam photoresist is used to define the photolithography pattern in S102, the BOE solution has almost no effect on the pattern defined by the electron beam photoresist. That is, in this embodiment, the photoresist can specifically use an electron beam photoresist made of polymethyl methacrylate, and the PMMA electron beam photoresist is specifically methyl methacrylate (MMA) spin-coated on the surface of the wafer, and then heated and cured to form a polymethyl methacrylate photoresist layer.
[0062] S104: Based on the patterned photoresist formed on the surface of the wafer after the second treatment with the buffered oxide etching solution, a Josephson junction connected to the underlying circuit is formed.
[0063] In this step, based on the patterned photoresist with the oxide layer removed, functional materials connected to the underlying circuit, including superconducting materials, are grown on the surface of the wafer to set up a Josephson junction connected to the underlying circuit. The specific content of this step will be described in detail in the following invention embodiments, and will not be repeated here.
[0064] A method for preparing a Josephson junction provided by an embodiment of the present invention uses a buffered oxide etchant to remove the oxide layer on the surface of a wafer for the first time before the photolithography process, and uses a buffered oxide etchant to remove the oxide layer on the surface of the wafer for the second time after the development of the photolithography process due to the steps of coating, baking, etc., so as to ensure that there is no oxide layer on the surface of the bottom line when the Josephson junction is grown. Using a buffered oxide etchant to remove the oxide layer can avoid the loss of the bottom line and the substrate surface on the wafer caused by ion beam etching, thereby avoiding the aggravation of the two-level system loss and improving the performance of the quantum chip.
[0065] The specific contents of the method for preparing a Josephson junction provided by the present invention will be described in detail in the following invention examples.
[0066] Embodiment 2
[0067] Please refer to Figure 2 , Figure 2 The present invention provides a flowchart of a specific method for preparing a Josephson junction.
[0068] See also Figure 2 In an embodiment of the present invention, a method for preparing a Josephson junction includes:
[0069] S201: placing the wafer with the bottom circuit prepared thereon into a buffered oxide etching solution for the first time to remove the oxide layer on the surface of the bottom circuit.
[0070] This step is basically the same as S101 in the above embodiment. Please refer to the above embodiment for details, which will not be described again. In this step, the wafer is usually immersed in a buffered oxide etching solution for about 5 minutes to remove the oxide layer on its surface.
[0071] S202: The wafer that has been treated with the buffered oxide etching solution for the first time is placed in ultrapure water for cleaning.
[0072] After the wafer is treated with BOE solution for the first time, the wafer will be immersed in ultrapure water for about 5 minutes in this step to clean the BOE solution remaining on the surface of the wafer. Of course, the specific length of the above immersion time can be set according to actual conditions and is not specifically limited here.
[0073] S203: Spin-coating a first layer of electron beam photoresist, a second layer of electron beam photoresist and a conductive adhesive in sequence on the surface of the wafer along the thickness direction, and baking after each layer of electron beam photoresist is spin-coated to form a photoresist stacked structure.
[0074] The above-mentioned stacked structure of two layers of electron beam photoresist and conductive glue is an electron beam etching process, that is, setting two layers of electron beam photoresist + conductive glue is a common electron beam exposure process, which will not be described in detail here.
[0075] In this embodiment, the coating speed of the first layer of electron beam photoresist is in the range of 1500rpm to 2000rpm; the temperature of the first layer of electron beam photoresist is in the range of 170℃ to 210℃, and the baking time is 2min to 4min; the coating speed of the second layer of electron beam photoresist is in the range of 1000rpm to 2000rpm; the temperature of the second layer of electron beam photoresist is in the range of 170℃ to 210℃, and the baking time is 3min to 5min. That is, the steps of setting two layers of electron beam photoresist in this step usually specifically include: spin coating electron beam photoresist on the wafer, the coating speed is 1500 rpm-2000rpm, and the coating is about 60 seconds. After coating, bake on a hot plate and bake at 170℃ to 210℃ for 2 minutes to 4 minutes. Then spin coat the electron beam photoresist on the wafer again, the coating speed is 1000 rpm-2000rpm, and the coating is about 60 seconds. After the coating, the photoresist is baked on a hot plate at 170° C. to 210° C. for 3 to 5 minutes. After baking, the electron beam photoresist may be a photoresist made of PMMA.
[0076] S204: Expose the photoresist stack structure using an electron beam exposure machine.
[0077] In this step, the exposure process is to define the pattern of the above-mentioned photoresist stack structure.
[0078] S205: using a developer to develop the exposed photoresist stack structure.
[0079] In this step, a specific developer can be used to develop the exposed wafer. Specifically, a developer of MIBK (methyl isobutyl ketone): IPA (isopropyl alcohol) = 1:3 can be used for development. The development temperature is room temperature, and the development time is usually 60 seconds to 90 seconds to obtain a patterned photoresist, that is, the above-mentioned photoresist definition pattern.
[0080] S206: placing the developed wafer into a buffered oxide etching solution for a second time to remove the oxide layer generated again on the surface of the bottom circuit.
[0081] This step is basically the same as S103 in the above embodiment. Please refer to the above embodiment for details, which will not be described again. In this step, the wafer is usually immersed in the buffered oxide etchant for about 5 minutes to remove the oxide layer generated again on the surface.
[0082] S207: The wafer that has been treated with the buffered oxide etching solution for the second time is placed in ultrapure water for cleaning.
[0083] After the wafer is treated with BOE solution for the second time, the wafer is immersed in ultrapure water for about 5 minutes in this step to clean the BOE solution remaining on the surface of the wafer. Of course, the specific length of the above immersion time can be set according to actual conditions and is not specifically limited here.
[0084] S208: placing the wafer that has been treated with the buffered oxide etching solution for the second time into an electron beam evaporation device and evacuating the device.
[0085] In this step, the processed wafer needs to be immediately placed in the electron beam evaporation equipment and evacuated to avoid the re-generation of the oxide layer during the transfer process. The vacuumization is not only the environment required for the growth of the Josephson structure component materials, but also can prevent the re-generation of the oxide layer on the wafer surface.
[0086] S209: A Josephson junction connected to the underlying circuit is grown based on the patterned photoresist set on the surface of the wafer through an electron beam evaporation device.
[0087] In this step, the material of the Josephson junction is grown by electron beam evaporation equipment. The evaporation rate of the corresponding material in this step is usually 3 Å / s to 10 Å / s.
[0088] S210: Stripping the photoresist remaining on the wafer surface.
[0089] In this step, the grown wafer can be placed in a debonding agent such as NMP (N-methylpyrrolidone) solution for a lift-off operation. That is, this step usually specifically includes: placing the wafer provided with the Josephson junction in an N-methylpyrrolidone solution, and stripping off the photoresist remaining on the surface of the wafer. It usually needs to be soaked in an NMP solution for 3 to 5 hours to complete the debonding, and finally complete the preparation of the Josephson junction.
[0090] A method for preparing a Josephson junction provided by an embodiment of the present invention uses a buffered oxide etchant to remove the oxide layer on the surface of a wafer for the first time before the photolithography process, and uses a buffered oxide etchant to remove the oxide layer on the surface of the wafer for the second time after the development of the photolithography process due to the steps of coating, baking, etc., so as to ensure that there is no oxide layer on the surface of the bottom line when the Josephson junction is grown. Using a buffered oxide etchant to remove the oxide layer can avoid the loss of the bottom line and the substrate surface on the wafer caused by ion beam etching, thereby avoiding the aggravation of the two-level system loss and improving the performance of the quantum chip.
[0091] Embodiment 3
[0092] A quantum chip provided by an embodiment of the present invention is introduced below. The quantum chip described below and the Josephson junction preparation method described above can be referenced to each other.
[0093] In this embodiment, the quantum chip includes a Josephson junction, and the Josephson junction is a Josephson junction prepared by a Josephson junction preparation method provided by any of the above embodiments. The specific content of the Josephson junction preparation method has been described in detail in the above invention embodiments, and will not be repeated here.
[0094] Since the quantum chip of this embodiment includes a Josephson junction prepared by a Josephson junction preparation method provided by any of the above embodiments, the quantum chip can have lower TLS loss and thus have higher performance.
[0095] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0096] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0097] The above is a detailed introduction to a method for preparing a Josephson junction and a quantum chip provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims
1. A method for preparing a Josephson junction, characterized in that: include: Putting the wafer with the bottom circuit prepared thereon into the buffered oxide etching solution for the first time to remove the oxide layer on the surface of the bottom circuit; Disposing a photoresist on the surface of the wafer that has been treated with the buffered oxide etching solution for the first time, and exposing and developing the photoresist to perform patterning, so as to expose a preset area on the surface of the wafer where a Josephson junction is disposed; placing the developed wafer into a buffered oxide etching solution for a second time to remove the oxide layer generated again on the surface of the bottom circuit; Based on the patterned photoresist disposed on the surface of the wafer after being treated with the buffered oxide etching solution for the second time, a Josephson junction connected to the bottom circuit is disposed.
2. The method according to claim 1, characterized in that After the wafer prepared with the bottom layer circuit is placed in the buffered oxide etching solution for the first time, the method further includes: The wafer that has been treated with the buffered oxide etching solution for the first time is placed in ultrapure water for cleaning; And / or, after placing the developed wafer into the buffered oxide etching solution for the second time, the method further comprises: The wafer that has been treated with the buffered oxide etching solution for the second time is placed in ultrapure water for cleaning.
3. The method according to claim 1, characterized in that Based on the patterned photoresist disposed on the surface of the wafer after the second treatment with the buffered oxide etching solution, the Josephson junction connected to the bottom circuit is disposed, including: Putting the wafer which has been treated with the buffered oxide etching solution for the second time into the electron beam evaporation equipment and evacuating the equipment; The electron beam evaporation device is used to grow a Josephson junction connected to the bottom circuit based on the patterned photoresist set on the surface of the wafer.
4. The method according to claim 3, characterized in that After growing the Josephson junction connected to the underlying circuit, it also includes: The residual photoresist on the surface of the wafer is stripped off.
5. The method according to claim 4, characterized in that Stripping the residual photoresist from the wafer surface includes: The wafer provided with the Josephson junction is placed in an N-methylpyrrolidone solution to strip off the residual photoresist on the surface of the wafer.
6. The method according to claim 1, characterized in that After development, at least the surface of the photoresist is provided with a protective layer which is insoluble in the buffered oxide etching solution.
7. The method according to claim 6, characterized in that The protective layer is a polymethyl methacrylate layer.
8. The method according to claim 1, characterized in that Providing a photoresist on the surface of the wafer that has been treated with the buffered oxide etching solution for the first time, and exposing and developing the photoresist to perform patterning includes: Spin coating a first layer of electron beam photoresist, a second layer of electron beam photoresist and a conductive adhesive in sequence on the surface of the wafer along the thickness direction, and baking after each layer of electron beam photoresist is spin coated to form a photoresist stacking structure; Using an electron beam exposure machine to expose the photoresist stack structure; The exposed photoresist stacked structure is developed using a developer.
9. The method according to claim 8, characterized in that The coating speed of the first layer of electron beam photoresist is in the range of 1500 rpm to 2000 rpm; the temperature of the first layer of electron beam photoresist is in the range of 170° C. to 210° C., and the baking time is 2 min to 4 min; The coating speed of the second layer of electron beam photoresist is in the range of 1000 rpm to 2000 rpm; the temperature of baking the second layer of electron beam photoresist is in the range of 170° C. to 210° C., and the baking time is 3 min to 5 min.
10. A quantum chip, characterized in that: It comprises a Josephson junction prepared by the method for preparing a Josephson junction according to any one of claims 1 to 9.