Display method and device

Abstract

The invention provides a display method and device. The display method comprises the following steps: determining that the refresh rate of the electronic equipment is switched from a first refresh rate to a second refresh rate, wherein the first refresh rate is greater than the second refresh rate; responding to switching of the refresh rate from the first refresh rate to a second refresh rate, and generating a second image frame after the electronic equipment completes display of the first image frame; and displaying the second image frame, so that the problem of frame loss caused by switching from a high refresh rate to a low refresh rate is solved, the lagging feeling of the electronic equipment is reduced, and the user experience is improved.

Description

Display method and device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on September 30, 2022, with application number 202211230396.X and invention name “Display Method and Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of image processing technology, and in particular to a display method and device. Background Art

[0003] Electronic devices can have multiple applications (APPs) installed. When running an APP, the display of image frames is controlled by the APP's corresponding refresh rate. Some APPs have different refresh rates, and when switching APPs, the refresh rate also switches synchronously. However, when switching from a high refresh rate to a low refresh rate, frame drops can occur, causing noticeable lag and degrading the user experience.

[0004] Summary of the Invention

[0005] This application provides a display method and device, the purpose of which is to solve the frame drop problem caused by switching from a high refresh rate to a low refresh rate, thereby reducing the lag of electronic devices and improving user experience. To achieve the above purpose, this application provides the following technical solutions:

[0006] In a first aspect, the present application provides a display method, which is applied to an electronic device, and the method includes: determining that the refresh rate of the electronic device switches from a first refresh rate to a second refresh rate, the first refresh rate is greater than the second refresh rate; in response to the refresh rate switching from the first refresh rate to the second refresh rate, after the electronic device completes the display of the first image frame, generating a second image frame; and displaying the second image frame.

[0007] Normally, an electronic device generates an image frame if two conditions are met: one condition is that the level change of the first signal (i.e., Vsync-sf) meets a preset condition, which is that the level of the first signal changes from a low level to a high level (corresponding to a rising edge), or the level of the first signal changes from a high level to a low level (corresponding to a falling edge); the other condition is that the electronic device completes the display of the previous image frame. However, when the electronic device switches from the first refresh rate to the second refresh rate, the time consumption of the second signal (i.e., Vsync-hw) increases (i.e., the period increases). The time-consuming second signal can cover at least one first signal. Under the covered first signal, the electronic device cannot determine whether the display of the image frame is completed, so that the electronic device cannot process other image frames, resulting in the loss of image frames. At the end position of the second signal, the electronic device can determine that the display of an image frame is completed, but the electronic device still has to wait for the rising edge or falling edge of the first signal, which may also cause the electronic device to lose image frames during the waiting process. The display method provided in the present application determines that the refresh rate switches from the first refresh rate to the second refresh rate, and after the electronic device completes the display of the first image frame, the electronic device can immediately generate and display the second image frame. Therefore, after the electronic device determines that the display of one image frame is completed, the electronic device does not need to wait for the rising edge or falling edge of the first signal to immediately generate and display another image frame, thereby reducing the loss of image frames, reducing the lag of the electronic device, and improving the user experience.

[0008] Optionally, the method further includes: after the refresh rate is switched to the second refresh rate, controlling the alignment of the first signal and the second signal, wherein the first signal is used to indicate the generation of an image frame, and the second signal is used to indicate the display of an image frame; after the electronic device completes the display of the second image frame and the level change of the first signal satisfies a preset condition, generating a third image frame, wherein the preset condition is that the level of the first signal changes from a low level to a high level, or the level of the first signal changes from a high level to a low level; and displaying the third image frame under the action of the second signal. Alignment means that the periods of the first signal and the second signal are the same, and the rising edges of the first signal and the second signal are aligned, and the falling edges of the first signal and the second signal are also aligned, that is, the waveforms of the first signal and the second signal are the same, and the signal amplitudes can be the same or different.

[0009] Typically, during the process of switching the refresh rate to the second refresh rate, the period of the second signal generated by the electronic device increases, so that the first signal and the second signal that can be aligned before the switch cannot remain aligned after the refresh rate is switched. In this case, the image frame can be generated once every first signal, so that the electronic device synthesizes one frame and loses one frame. Synthesizing one frame can refer to generating an image frame and further displaying the image frame. In the display method provided by the present application, after the refresh rate is switched, the electronic device can control the alignment of the first signal and the second signal, so that the electronic device can generate one image frame under each first signal, preventing the phenomenon of synthesizing one frame and losing one frame, reducing the loss of image frames, thereby reducing the sense of freeze of the electronic device and improving the user experience.

[0010] Optionally, before determining that the refresh rate of the electronic device switches from the first refresh rate to the second refresh rate, the method further includes: in response to the refresh rate being the first refresh rate, generating the (i+n)th first signal according to the i-th second signal, the duration of the interval between the (i+n)th first signal and the i-th second signal being the sum of the periods of the n first signals, where n is a natural number greater than 1; after the refresh rate is switched to the second refresh rate, controlling the alignment of the first signal with the second signal includes: after the refresh rate is switched to the second refresh rate, sampling the first second signal after the refresh rate is switched, generating the first signal using the sampling result of the first second signal, the duration of the interval between the first signal and the first second signal being the sum of the periods of the (n-1) second signals. The reason why the first signal and the second signal are not aligned after the refresh rate is switched is that a second signal with an increasing period is used in the process of generating the first signal. Therefore, in the present application, after determining that the refresh rate is switched, the electronic device adjusts the generation mechanism of the first signal after the switch, and uses the first first signal after the refresh rate is switched to generate the second signal, so that the first signal and the second signal can be aligned after the refresh rate is switched. The sampling results of the second signal can be stored in a result sequence, and when the first signal is generated, the sampling results of the second signal are read from the result sequence. The sampling results of the second signal can be multiple timestamps of the second signal, and the result sequence can be a timestamp sequence storing the multiple timestamps of the second signal.

[0011] Optionally, the method also includes: discarding a special signal, where the special signal is a second signal generated during the process of switching the refresh rate from a first refresh rate to a second refresh rate, and the special signal is the previous signal of the first second signal, thereby reducing the amount of data processed by the electronic device.

[0012] Optionally, discarding the special signal includes: prohibiting sampling of the special signal; or sampling the special signal, but not storing the sampling result of the special signal in the result sequence.

[0013] Optionally, the second image frame is an image frame lost during the process of switching the refresh rate from the first refresh rate to the second refresh rate. In some examples, after determining that the display of the first image frame is complete, the electronic device can immediately generate the first image frame of the lost multiple image frames to ensure image continuity; in some examples, after determining that the display of the first image frame is complete, the electronic device can immediately synthesize the last image frame of the lost multiple image frames to shorten the delay time of the last image frame. The image frame displayed next by the electronic device is the next image frame of the lost last image frame. Immediately generating and displaying the lost last image frame can make the image frame displayed next and the lost last image frame continuous, thereby ensuring continuity.

[0014] Optionally, the electronic device completing display of the first image frame includes: after the electronic device calls the kernel thread crtc_commit to release the fence resource, determining that the electronic device completes display of the first image frame.

[0015] Optionally, determining that the refresh rate of the electronic device switches from the first refresh rate to the second refresh rate includes: determining the end time of the first signal and the start time of the first signal when the refresh rate of the electronic device is the first refresh rate; determining the difference between the end time and the start time; if the difference satisfies a preset switching condition, determining that the refresh rate of the electronic device switches from the first refresh rate to the second refresh rate. The preset switching condition can be used to indicate that the period of the first signal increases, such as the preset switching condition can be a preset threshold or a preset value range, and the values ​​of the preset threshold and the preset value range are determined according to the refresh rate. For example, when switching from 90Hz to 60Hz, the preset threshold can be a value less than 19.4ms, and the preset value range can be (11.1, 19.4].

[0016] Optionally, the application framework layer of the electronic device includes: a refresh rate processing unit and a data reading unit; the hardware abstraction layer of the electronic device includes a hardware hybrid renderer; the kernel layer of the electronic device includes a display driver; a refresh rate processing unit, used to determine that the refresh rate of the electronic device switches from a first refresh rate to a second refresh rate; a data reading unit, used to respond to the refresh rate switching from the first refresh rate to the second refresh rate, and read the first image data after the electronic device completes the display of the first image frame; the hardware hybrid renderer, used to synthesize the first image data to generate a second image frame; and the display driver, used to display the second image frame.

[0017] Optionally, the application framework layer also includes: a signal generating unit, which is used to control the alignment of the first signal and the second signal after the refresh rate is switched to the second refresh rate, the first signal is used to indicate the generation of an image frame, and the second signal is used to indicate the display of an image frame; a data reading unit, which is also used to complete the display of the second image frame on the electronic device, and the level change of the first signal meets the preset condition, and read the second image data, wherein the preset condition is that the level of the first signal changes from a low level to a high level, or the level of the first signal changes from a high level to a low level; a hardware hybrid renderer, which is also used to synthesize the second image data to generate a third image frame; and a display driver, which is also used to display the third image frame under the action of the second signal.

[0018] In a second aspect, the present application provides an electronic device, which includes: one or more processors; one or more memories; the memories store one or more programs, and when one or more programs are executed by the processor, the electronic device executes the above-mentioned display method.

[0019] In a third aspect, the present application provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the processor executes the above-mentioned display method.

[0020] Based on the implementation methods provided in the above aspects, this application can also be further combined to provide more implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1 is a schematic diagram of rendering and displaying an image frame using Vsync-app, Vsync-sf, and Vsync-hw provided by the present application;

[0022] FIG2 is a schematic diagram of a display driver generating Vsync-hw provided by the present application;

[0023] FIG3 is a schematic diagram of tracking the frame loss problem provided by this application;

[0024] FIG4 is an enlarged schematic diagram of the frame loss problem provided by this application;

[0025] FIG5 is a schematic diagram of software / hardware Vsync after the refresh rate is switched provided by the present application;

[0026] FIG6 is a schematic diagram of rendering an image frame to a display using Vsync-app, Vsync-sf, and Vsync-hw after a refresh rate switch provided by the present application;

[0027] FIG7 is a schematic diagram of tracking for optimizing frame loss problem provided by the present application;

[0028] FIG8 is an enlarged schematic diagram of the optimization of the frame loss problem provided by the present application;

[0029] FIG9 is a schematic diagram of optimizing software / hardware Vsync after the refresh rate is switched provided by the present application;

[0030] FIG10 is a schematic diagram of rendering and displaying an image frame using optimized Vsync-app, Vsync-sf, and Vsync-hw provided by the present application;

[0031] FIG11 is a hardware architecture diagram of the electronic device provided in this application;

[0032] FIG12 is a diagram of the software architecture of the electronic device provided by this application;

[0033] FIG13 is a signaling diagram of the display method provided by the present application;

[0034] FIG14 and FIG15 are schematic diagrams of the timestamp sequence and the predicted Vsync-sf provided by this application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to be limiting of the present application. As used in the specification and appended claims of the present application, the singular expressions "one", "a kind of", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the embodiments of the present application, "one or more" refers to one, two or more; "and / or" describes the association relationship of associated objects, indicating that three relationships may exist; for example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship.

[0036] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0037] The "multiple" involved in the embodiments of the present application means greater than or equal to two. It should be noted that in the description of the embodiments of the present application, the words "first" and "second" are only used for the purpose of distinguishing the description and cannot be understood as indicating or implying relative importance or order.

[0038] First, let’s introduce the technical terms involved in this application:

[0039] Vertical synchronization (Vsync) signals are divided into hardware Vsync signals and software Vsync signals. The hardware Vsync signal is abbreviated as Vsync-hw signal, which can be understood as a tearing effect (TE) signal. Software Vsync signals include Vsync-app signal and Vsync-sf signal. For ease of description, Vsync-hw signal, Vsync-app signal, and Vsync-sf signal are abbreviated as Vsync-hw, Vsync-app signal, and Vsync-sf signal.

[0040] Vsync-app and Vsync-sf are generated based on Vsync-hw. Specifically, DispSyncSource.cpp in SF (surfaceflinger) virtualizes Vsync-hw into Vsync-app and Vsync-sf. DispSyncSource.cpp samples Vsync-hw and inputs the sampling results into the software Vsync model. DispSyncSource.cpp runs the software Vsync model to output Vsync-app and Vsync-sf through the software Vsync model. Vsync-hw can be generated by the display driver based on the refresh rate.

[0041] Figure 1 shows how an electronic device uses Vsync-app, Vsync-sf, and Vsync-hw to render image frames to the display. Under Vsync-app, the app generates image data (this process is called app rendering, with "render" in Figure 1 representing image data) and stores it in a buffer. Under Vsync-sf, the SF reads the image data from the buffer and sends it to the hardware compositing renderer (HWChwcomposer, HWC), which synthesizes the image data to generate a single image frame (this process is called SF synthesis). The HWC sends the image frame to the display driver, which, under Vsync-hw, sends the image frame to the screen for display (this process is called HWC display delivery). After the screen displays the image frame, the display driver calls the kernel thread crtc_commit, which releases the fence resource. Releasing the fence resource indicates that the electronic device has completed displaying the image frame.

[0042] However, the display of a frame is not completely independent of the previous one. Only after the previous frame is displayed and crtc_commit releases the fence resource can the SF read the image data of the next frame under the action of Vsync-sf. The HWC and display driver then complete the display of the next frame. In Figure 1, a frame goes through three cycles from rendering to display. The first cycle completes the APP rendering, the second cycle completes the SF synthesis, and the third cycle completes the HWC display.

[0043] The periods of the three signals, Vsync-app, Vsync-sf, and Vsync-hw, can be determined according to the refresh rate corresponding to the APP. For example, if the refresh rate corresponding to the APP is 90Hz, the periods of the three signals, Vsync-app, Vsync-sf, and Vsync-hw, are 11.1 milliseconds (ms); if the refresh rate corresponding to the APP is 60Hz, the periods of the three signals, Vsync-app, Vsync-sf, and Vsync-hw, are 16.6ms. When the electronic device switches APP, the refresh rate also switches synchronously. However, when the electronic device switches from a high refresh rate to a low refresh rate, the period of Vsync-hw is too long, resulting in frame loss during the APP switching process. In addition, after the switching is completed, Vsync-app and Vsync-sf are not aligned with Vsync-hw, resulting in the electronic device alternating between synthesizing a frame and dropping a frame after the switching is completed, causing the electronic device to have a noticeable sense of freeze, reducing the user experience. The synthesized frame can be image data synthesized into a frame of image frames by SF. Dropping a frame may mean delaying SF synthesis, such as performing SF synthesis at the rising edge or falling edge of the next Vsync-sf to synthesize image data of the image frame at the next Vsync-sf, or dropping a frame may mean dropping image data of one image frame.

[0044] For example, consider switching the refresh rate of an electronic device from 90Hz to 60Hz. The display driver in the electronic device can generate Vsync-hw. During the refresh rate switch, the display driver can simulate the refresh rate switch and adjust the Vsync-hw based on the switched refresh rate. As shown in Figure 2, when the refresh rate is 90Hz, the display driver generates a Vsync-hw with a duration of 11.1ms, consisting of a low-level duration of 8.3ms and a high-level duration of 2.8ms. The display driver determines that the refresh rate switch occurs on the rising edge of Vsync-hw, and the refresh rate switches from 90Hz to 60Hz. The display driver uses the rising edge as the start of a Vsync-hw. The Vsync-hw includes a high level with a duration of 2.8ms and a low level with a duration of 16.6ms. The Vsync-hw takes 19.4ms. Therefore, the display driver simulates the mechanism of Vsync-hw at 90Hz, resulting in a Vsync-hw with a duration of 19.4ms when the refresh chip switches from 90Hz to 60Hz. This phenomenon not only causes SF to lose 1 to 2 frames of image frames due to the lack of fence resources, but also causes Vsync-sf and Vsync-hw rising and falling edges to be continuously misaligned, resulting in the alternation of synthesizing one frame and dropping one frame, which brings a noticeable sense of stuttering.

[0045] The frame drop trace is shown in Figure 3. When switching from 90Hz to 60Hz, there is a Vsync-hw time of up to 19.4ms, represented by TE = 19.4ms in Figure 3. During this 19.4ms duration, the SF did not wait for crtc_commit to release the fence resources, and the SF synthesis process could not be executed, resulting in the loss of two frames during the 19.4ms duration, as shown in 1 and 2 in Figure 3. The enlarged schematic diagram of 1 and 2 in Figure 3 is shown in Figure 4. From onMessageReceived to HwcPresentOrValidateDisplay, it indicates that the SF synthesis is executed normally. If the SF is still waiting (wait), it means that the SF did not wait for crtc_commit to release the fence resources, which may cause frame drop. In Figure 4, crtc_commit released the fence resources only after the SF lost two frames.

[0046] At the rising and falling edges of Vsync-sf, if SF waits until crtc_commit releases the fence resources, SF can read the image data. If SF does not wait until crtc_commit releases the fence resources, SF cannot read the image data. After 19.4ms, SF waits for the fence resources once every Vsync-sf, which means that SF can read the image data once every Vsync-sf, resulting in a situation where synthesizing a frame and dropping a frame alternately occur. As shown in 3 in Figure 3, the large box pointed to by 3 shows that synthesizing a frame and dropping a frame alternately occur, and the small squares in the large box indicate that a frame is dropped. For the first small box pointed to by 3 in the large box, because SF did not wait for crtc_commit to release the fence resources at the rising edge of Vsync-sf, SF did not read the image data, so a frame of image frame was lost. Then, on the falling edge of Vsync-sf, SF waits until crtc_commit releases the fence resource. SF can then read the image data and synthesize the image data by HWC. Therefore, on the falling edge of Vsync-sf, one frame of image data is synthesized. After SF loses five frames of image data, the electronic device begins to synthesize the image data at 60Hz normally.

[0047] For example, when exiting an app by swiping sideways on an electronic device, the refresh rate switches from 90Hz to 60Hz. During this switching process, the electronic device first loses two frames of image frames. After the switching is completed, one frame is refreshed and one frame is lost, causing a sense of lag throughout the process, which degrades the user experience.

[0048] After the refresh rate is switched, the schematic diagram of software / hardware Vsync is shown in Figure 5, which shows a schematic diagram of software / hardware Vsync when switching from 90Hz to 60Hz. In Figure 5, the vertical line can be used as the benchmark of software / hardware Vsync, pointing to the start time of software / hardware Vsync.

[0049] At a refresh rate of 90Hz, the three signals, Vsync-app, Vsync-sf, and Vsync-hw, have the same period, and at least the references of Vsync-sf and Vsync-hw are the same within each period. That is, Vsync-sf and Vsync-hw are aligned within each period. This alignment can mean that the periods are the same, the rising edges of Vsync-sf and Vsync-hw are aligned, and the falling edges of Vsync-sf and Vsync-hw are aligned. For Vsync-app, the period is the same as that of Vsync-sf and Vsync-hw, but the rising and falling edges can differ from those of Vsync-sf and Vsync-hw. In Figure 5, Vsync-app is aligned with Vsync-sf and Vsync-hw. However, when the refresh rate switches from 90Hz to 60Hz, a longer Vsync-hw appears. For example, in the fourth cycle in Figure 5, the Vsync-hw takes 19.4ms, that is, a longer Vsync-hw appears in the fourth cycle, and the cycle of Vsync-hw increases from 11.1ms to 19.4ms, but the cycle of Vsync-app and Vsync-sf in the fourth cycle is still 11.1ms. Therefore, the cycle of Vsync-hw in the fourth cycle is different from the cycle of Vsync-app and Vsync-sf in the fourth cycle, resulting in the benchmark of Vsync-hw in the fifth cycle being different from the benchmark of Vsync-app and Vsync-sf in the fourth cycle. Starting from the fifth cycle, Vsync-app, Vsync-sf and Vsync-hw are not aligned.

[0050] As shown in Figure 5, although the cycle of Vsync-app, Vsync-sf and Vsync-hw is 16.6ms when the refresh rate is switched to 60Hz, because Vsync-hw takes a long time in the fourth cycle, Vsync-hw, which originally ends at (1), ends at (2), resulting in the cycle of Vsync-hw in the fourth cycle being different from the cycle of Vsync-app and Vsync-sf in the fourth cycle, and the end of Vsync-hw in the fourth cycle being different from the end of Vsync-app and Vsync-sf in the fourth cycle, which leads to the fact that starting from the fifth cycle, Vsync-app, Vsync-sf and Vsync-hw in actual situation continue to be misaligned up and down.

[0051] Because Vsync-hw ends at (2) in the fourth cycle, crtc_commit, which was originally scheduled to release the fence resource at (1), is now delayed to (2). Because (2) is not a rising or falling edge of Vsync-sf, SF synthesis is delayed by one Vsync-sf. As shown in Figure 5, at (3), a frame is lost because the SF misses the fence resource. The SF synthesis originally scheduled for (3) is actually executed at (4).

[0052] Under the influence of software / hardware Vsync as shown in Figure 5, the process of rendering an image frame to the display using Vsync-app, Vsync-sf, and Vsync-hw is shown in Figure 6. As can be seen from Figure 6, before the refresh rate switches from 90Hz to 60Hz, the APP completes rendering in one cycle, and crtc_commit can release fence resources in this cycle, which means that SF can wait for fence resources in the next cycle and perform SF synthesis in the next cycle. After SF synthesis, the display driver sends it to the display in the next cycle, allowing the screen to display the image frame in the next cycle, thus completing the rendering of the image frame to the display within three cycles. However, when the refresh rate switches from 90Hz to 60Hz, the time consumed by crtc_commit to release the fence resources increases. As shown in (1) in Figure 6, the fence resources that should have been released at the end of the fourth cycle are released after the start of the fifth cycle, causing the SF synthesis of the fifth cycle to be delayed to the sixth cycle, that is, the fence resources are missed at (1), and the SF synthesis that should have been executed at (1) is actually executed at (2). The delay in SF synthesis causes a frame to be lost; similarly, the fence resources are missed at (3), and the SF synthesis that should have been executed at (3) is actually executed at (4), resulting in a frame loss. That is, compared to generating one image frame under each Vsync-app, after the refresh rate is switched, one image frame is generated every Vsync-app.

[0053] As shown in Figures 3 to 6, when an electronic device switches from a high-refresh-rate app to a low-refresh-rate app, the long Vsync-hw cycle causes frame dropout during the app switch. After the switch is complete, Vsync-app, Vsync-sf, and Vsync-hw are misaligned, resulting in alternating frames being synthesized and dropped after the switch is complete. This causes noticeable lag in the electronic device and degrades the user experience.

[0054] To address this issue, the present application provides a display method that, in response to switching from a high refresh rate to a low refresh rate, synthesizes image data for one image frame upon receiving an instruction from crtc_commit to release fence resources but without receiving Vsync-sf. That is, when switching from a high refresh rate to a low refresh rate, although SF is not at the rising edge or falling edge of Vsync-sf, SF determines that crtc_commit has released the fence resources (i.e., the display of one image frame is completed), then SF can read the image data immediately after crtc_commit releases the fence resources to immediately perform SF synthesis. Compared to waiting for Vsync-sf to read the image data, the image data for one image frame can be synthesized in advance, so that when the high refresh rate is switched to the low refresh rate, the image data for one image frame can be quickly synthesized, thereby reducing the number of frame drops.

[0055] In some examples, in response to switching to a low refresh rate, Vsync-app, Vsync-sf, and Vsync-hw are synchronized, that is, after switching to a low refresh rate, Vsync-app, Vsync-sf, and Vsync-hw are aligned to solve the situation where one frame is synthesized and one frame is dropped alternately due to the fact that Vsync-app, Vsync-sf, and Vsync-hw are not aligned after switching.

[0056] As shown in Figure 7, a trace diagram of the optimization of the frame loss problem after the electronic device implements the display method of the present application. In Figure 7, the refresh rate switches from 90Hz to 60Hz. When switching from 90Hz to 60Hz, the time taken for one frame of Vsync-hw is extended from 11.1ms to 19.4ms (as shown in TE=19.4ms in Figure 7). The Vsync-hw that takes 19.4ms covers one Vsync-sf. Generally, crtc_commit completes the release of fence resources at the end position of Vsync-hw. Therefore, under the covered Vsync-sf, SF cannot wait for crtc_commit to release the fence resources, resulting in the loss of two frames under the Vsync-hw that takes 19.4ms. After the Vsync-hw that takes 19.4ms ends, SF determines that crtc_commit has released the fence resources and immediately performs SF synthesis to immediately force the synthesis of image data of one frame. That is, although SF is not at the rising edge or falling edge of Vsync-sf, SF determines that crtc_commit releases the fence resource and immediately performs SF synthesis to forcibly synthesize image data of one frame.

[0057] That is, under normal circumstances, SF synthesis must meet two conditions: one condition is to be at the rising edge or falling edge of Vsync-sf, and the other condition is to determine that crtc_commit has released the fence resources; but when switching from a high refresh rate to a low refresh rate, a time-consuming Vsync-hw occurs, and SF synthesis only needs to meet one condition, which can be to determine that crtc_commit has released the fence resources. In this way, SF does not need to wait for the next rising edge or falling edge of Vsync-sf, and the SF synthesis at the next Vsync-sf will be advanced, so that the image data of one frame can be synthesized in advance.

[0058] The pre-synthesized image data may be image data of any one of the two lost image frames. Although two frames are lost under the 19.4ms Vsync-hw, the image data of any one of the two lost image frames can be immediately synthesized after the 19.4ms Vsync-hw ends, which is equivalent to losing one frame and reducing the number of lost frames. In some examples, the image data of the first frame of the two lost image frames can be immediately synthesized after the 19.4ms Vsync-hw ends to ensure image continuity; in some examples, the image data of the second frame of the two lost image frames can be immediately synthesized after the 19.4ms Vsync-hw ends, shortening the delayed synthesis time of the second image frame.

[0059] Because the Vsync-hw that takes 19.4ms may cause the subsequent Vsync-app, Vsync-sf and Vsync-hw to be misaligned, and the misalignment of Vsync-app, Vsync-sf and Vsync-hw may cause the electronic device to synthesize one frame and lose one frame. To address this problem, after switching to a low refresh rate, the electronic device can align Vsync-app, Vsync-sf and Vsync-hw. After Vsync-app, Vsync-sf and Vsync-hw are aligned, SF can read image data from the buffer on the rising and falling edges of Vsync-sf respectively, and the image data is synthesized by HWC, thereby performing SF synthesis on the rising and falling edges of Vsync-sf respectively, so that the electronic device can perform SF synthesis on the rising and falling edges of Vsync-sf respectively after switching to 60Hz, thereby avoiding the loss of image frames.

[0060] The following is an explanation of the optimization of software / hardware Vsync after the refresh rate switches, as shown in Figure 9. In Figure 9, when the refresh rate is 90Hz, the cycles of the three signals Vsync-app, Vsync-sf, and Vsync-hw are the same, and the benchmarks of Vsync-app, Vsync-sf, and Vsync-hw in each cycle are also the same. However, when the refresh rate switches from 90Hz to 60Hz, a long Vsync-hw occurs. For example, in the fourth cycle in Figure 9, the Vsync-hw duration is 19.4ms, that is, a long Vsync-hw occurs in the fourth cycle. Originally, crtc_commit releases the fence resource before the end of (1), but because the refresh rate switches from 90Hz to 60Hz, crtc_commit releases the fence resource at (2) and completes the release of the fence resource at (5) (i.e., the end of the fourth cycle). As a result, at (3), SF synthesis is not performed because the fence resource is missed, resulting in a frame loss. (4) is the end of Vsync-hw in the fourth cycle. At (4), the circuit waits until crtc_commit releases the fence resource, and then immediately performs SF synthesis at (4) to synthesize the image data of one frame, thereby forcing the refresh of one frame, that is, forcing the display of one frame in the fifth cycle.

[0061] In the fifth cycle, the end time of the three signals Vsync-app, Vsync-sf, and Vsync-hw is the same. Then, in the sixth cycle, the start time of the three signals Vsync-app, Vsync-sf, and Vsync-hw is the same. Because the cycles of the three signals Vsync-app, Vsync-sf, and Vsync-hw are the same, in the sixth cycle, Vsync-app, Vsync-sf, and Vsync-hw are aligned vertically. As shown in Figure 9, starting from the sixth cycle, Vsync-app, Vsync-sf, and Vsync-hw are aligned vertically. Taking Vsync-hw as an example, the sixth cycle can be based on the sixth vertical line in Figure 9 as the start time and the seventh vertical line as the end time, so that the subsequent software / hardware Vsync can be aligned, and the electronic device can stably refresh (display) the image at a refresh rate of 60Hz.

[0062] After software / hardware Vsync optimization, the process of rendering image frames to display using Vsync-app, Vsync-sf, and Vsync-hw is shown in Figure 10. At (1), a frame should be dropped if fence resources are missed, but at (2), the dark gray frame is refreshed immediately when the fence resources are available, instead of waiting for the next Vsync_sf (specifically, waiting for the rising or falling edge of Vsync_sf), thereby avoiding the loss of light gray frames; at (3), the light gray frame is normally refreshed until the fence resources are released, and the SF is synthesized normally and sent to the HWC for display; at (4), the dark gray frame is normally refreshed until the fence resources are released, and the SF is synthesized normally and sent to the HWC for display, and so on. There is no subsequent phenomenon of alternating between synthesizing a frame and dropping a frame, which reduces the sense of stuttering and improves the user experience.

[0063] The above-described display method can be applied to electronic devices. In some embodiments, the electronic devices can be mobile phones, tablet computers, desktop computers, laptop computers, notebook computers, ultra-mobile personal computers (UMPCs), handheld computers, netbooks, personal digital assistants (PDAs), wearable electronic devices, smart watches, and the like. This application does not impose any particular limitation on the specific form of the electronic devices.

[0064] As shown in FIG11 , the electronic device may include: a processor, an external memory interface, an internal memory, a Universal Serial Bus (USB) interface, a charging management module, a power management module, a battery, antenna 1, antenna 2, a mobile communication module, a wireless communication module, a sensor module, buttons, a motor, an indicator, a camera, a display screen (also referred to as a screen), and a Subscriber Identity Module (SIM) card interface, etc. The audio module may include a speaker, a receiver, a microphone, an earphone interface, etc., and the sensor module may include a pressure sensor, a gyroscope sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, etc.

[0065] The processor may include one or more processing units, for example: the processor may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). Among them, different processing units can be independent devices or integrated into one or more processors. The processor is the nerve center and command center of the electronic device. The controller can generate operation control signals based on the instruction opcode and timing signal to complete the control of instruction fetching and execution.

[0066] The display screen is used to display images, videos, a series of graphical user interfaces (GUIs), etc.

[0067] The external memory interface can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device. The external memory card communicates with the processor through the external memory interface to implement data storage functions. For example, files such as music and videos are saved in the external memory card. The internal memory can be used to store computer executable program code, which includes instructions. The processor executes various functional applications and data processing of the electronic device by running the instructions stored in the internal memory. For example, in the present application, the processor executes the instructions stored in the internal memory to enable the electronic device to execute the display method provided in the present application.

[0068] It should be understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device. In other embodiments, the electronic device may include more or fewer components than shown, or may combine or separate certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0069] In addition, operating systems run on the above components, such as the iOS operating system developed by Apple, the Android open source operating system developed by Google, and the Windows operating system developed by Microsoft.

[0070] The operating system of the electronic device can adopt a layered architecture, an event-driven architecture, a microkernel architecture, a microservice architecture, or a cloud architecture. The embodiment of the present application takes the Android system with a layered architecture as an example to illustrate the software structure of the electronic device. Figure 12 is a software architecture diagram of the electronic device. The layered architecture divides the software into several layers, and each layer has a clear role and division of labor. The layers communicate with each other through software interfaces. Taking the Android system as an example, in some embodiments, the Android system is divided into four layers, from top to bottom, namely, the application layer, the application framework layer (Framework), the hardware abstraction layer (HAL) and the kernel layer (Kernel).

[0071] The application layer can include a series of application packages. Application packages may include apps such as camera, gallery, calendar, call, map, navigation, WLAN, Bluetooth, music, video, and short messaging. The application framework layer provides an application programming interface (API) and programming framework for applications in the application layer. The application framework layer includes some predefined functions. For example, the application framework layer may include a window manager, content provider, view system, phone manager, resource manager, notification manager, etc. The application framework layer may also include SF, which includes DispSyncSource.cpp, SF.cpp, and VsyncReactor.cpp. DispSyncSource.cpp, SF.cpp, and VsyncReactor.cpp can be considered three units in SF. For example, DispSyncSource.cpp can be called a signal generation unit, SF.cpp can be called a data reading unit, and VsyncReactor.cpp can be called a refresh rate processing unit. The HAL may include HWC. The kernel layer is the layer between hardware and software. The kernel layer includes at least a display driver, a camera driver, an audio driver, and a sensor driver. HWC can be used to synthesize image data. During the synthesis of image data, functions such as setCallback, registerCallback, and onComposerhalVsync can be called.

[0072] VsyncReactor.cpp samples Vsync-hw, and DispSyncSource.cpp generates Vsync-app and Vsync-sf based on the sampling results. VsyncReactor.cpp calls addResyncSample to sample Vsync-hw and obtain a Vsync-hw timestamp, which is an example of the sampling result. The Vsync-hw timestamp is stored in the timestamp sequence using addHwVsyncTimestamp. VsyncReactor.cpp also calls periodConfirmed for scene recognition. When VsyncReactor.cpp detects a high-to-low refresh rate switch and a prolonged Vsync-hw, it sends a command to SF.cpp, instructing it to perform SF synthesis with the HWC after confirming that crtc_commit has released fence resources. VsyncReactor.cpp then adjusts the timestamp sequence to ensure alignment of Vsync-app, Vsync-sf, and Vsync-hw after the refresh rate switch.

[0073] Taking the refresh rate of an electronic device as 90Hz and the refresh rate switching from 90Hz to 60Hz as an example, the interaction process between the above DispSyncSource.cpp, SF.cpp, VsyncReactor.app and HWC is described. The signaling diagram is shown in Figure 13, which may include the following steps:

[0074] S101. VsyncReactor.cpp calls addResyncSample to sample Vsync-hw(i) and obtain the timestamp of Vsync-hw(i). The timestamp of Vsync-hw(i) is stored in the timestamp sequence. For example, VsyncReactor.cpp calls addHwVsyncTimestamp to store the timestamp of Vsync-hw(i) in the timestamp sequence.

[0075] S102, DispSyncSource.cpp generates Vsync-sf(i+2) according to the timestamp of Vsync-hw(i). Vsync-sf(i+2) is the second Vsync-sf after Vsync-sf(i). Vsync-hw(i) and Vsync-sf(i) correspond to the same cycle. In this embodiment, Vsync-hw(i) and Vsync-sf(i) are Vsync-hw and Vsync-sf in the i-th cycle. SF can also generate Vsync-app(i+2) when generating Vsync-sf(i+2). Under the action of Vsync-app(i+2), APP generates image data, which will not be described in detail here. Among them, generating Vsync-sf(i+2) according to the timestamp of Vsync-hw(i) is only an example and is not limited in this embodiment.

[0076] S103: After SF.cpp determines that crtc_commit has released the fence resource and is at the rising or falling edge of Vsync-sf(i+2), SF.cpp reads the image data. A rising edge of Vsync-sf(i+2) indicates that the level of Vsync-sf(i+2) has changed from a low level to a high level, and a falling edge of Vsync-sf(i+2) indicates that the level of Vsync-sf(i+2) has changed from a high level to a low level.

[0077] S104. HWC synthesizes the image data to complete SF synthesis through SF.cpp and HWC to generate image frames.

[0078] S105. The HWC may send the synthesized image data to a display driver, which drives the screen to display the image frame.

[0079] S106. VsyncReactor.cpp calls periodConfirmed and recognizes that the duration of Vsync-hw(i+1) is 19.4ms, confirming that the refresh rate has switched. VsyncReactor.cpp sends a refresh rate switch instruction to SF.cpp. The instruction not only indicates the refresh rate switch but also carries the duration of Vsync-hw(i+1). Vsync-hw(i+1) is the next Vsync-hw after Vsync-hw(i).

[0080] Ideally, when the next Vsync-hw signal ends at the current time, the difference between the current time and the start time of the Vsync-hw is equal to the period of the Vsync-hw. Therefore, periodConfirmed can identify whether a preset scenario occurs by whether the difference exceeds the preset threshold. The preset scenario is a scenario where the refresh rate switching has a long Vsync-hw time. When switching from 90Hz to 60Hz, the preset threshold can be, but is not limited to, a value less than 19.4ms. For example, a value between 11.1 and 19.4 can be taken. Alternatively, periodConfirmed can identify whether a preset scenario occurs by whether the difference is within a preset value range. The preset value range can be 11.1 to 19.4. The preset value range may not include 11.1, but may include 19.4. In other refresh rate switching scenarios, the preset threshold is not limited to being determined based on 19.4ms. This embodiment does not limit the preset threshold.

[0081] S107 , SF.cpp responds to the instruction and reads the image data immediately after determining that crtc_commit has released the fence resources.

[0082] S108. The HWC synthesizes the image data to generate image frames.

[0083] S109. The HWC may send the synthesized image data to a display driver, which drives the screen to display the image frame.

[0084] That is to say, SF.cpp receives the instruction sent by VsyncReactor.cpp, which indicates the refresh rate switching and the time consumption of Vsync-hw(i) is 19.4ms. Then SF.cpp does not need to wait for the rising and falling edges of Vsync-sf. After determining that crtc_commit releases the fence resources, SF can read the image data, so that SF reads the image data in advance, and similarly HWC synthesizes the image data in advance.

[0085] S110. VsyncReactor.cpp prohibits calling addResyncSample to sample Vsync-hw(i+1), so that the timestamp of Vsync-hw(i+1) is not stored in the timestamp sequence.

[0086] S110', VsyncReactor.cpp calls addResyncSample to sample Vsync-hw(i+1), but prohibits calling addHwVsyncTimestamp to store the timestamp of Vsync-hw(i+1) in the timestamp sequence, thereby also achieving the purpose of not storing the timestamp of Vsync-hw(i+1) in the timestamp sequence.

[0087] S111. VsyncReactor.cpp calls addResyncSample to sample Vsync-hw(i+2) to obtain the timestamp of Vsync-hw(i+2), and calls addHwVsyncTimestamp to store the timestamp of Vsync-hw(i+2) in the timestamp sequence.

[0088] S112. DispSyncSource.cpp generates Vsync-sf(i+3) based on the timestamp of Vsync-hw(i+2). The generated Vsync-sf(i+3) is aligned with Vsync-hw(i+3).

[0089] S113 , after SF.cpp determines that crtc_commit has released the fence resource and is at the rising edge or falling edge of Vsync-sf(i+3), SF.cpp reads the image data.

[0090] S114. HWC synthesizes the image data to complete SF synthesis through SF.cpp and HWC to generate image frames.

[0091] S115. The HWC may send the synthesized image data to a display driver, which drives the screen to display the image frame.

[0092] Vsync-sf(i+3) and Vsync-hw(i+3) are aligned to ensure that Vsync-app, Vsync-sf, and Vsync-hw are aligned after the refresh rate is switched. On subsequent rising or falling edges of Vsync-sf, SF reads image data and HWC synthesizes the image data. SF synthesis is completed through SF and HWC to generate a frame. Starting from Vsync-sf(i+3), the electronic device can generate image frames normally, avoiding the phenomenon of synthesizing one frame and dropping one frame.

[0093] FIG14 shows an example of a timestamp sequence and a predicted Vsync-sf. When sampling Vsync-hw, multiple time points of Vsync-hw can be sampled to obtain multiple timestamps, and Vsync-sf is generated using the multiple timestamps of Vsync-hw. FIG14 takes the example of generating the (i+2)th Vsync-sf using the multiple timestamps of the i-th Vsync-hw. This embodiment does not limit the generation of the Vsync-sf using the Vsync-hw. The multiple timestamps of Vsync-hw can be stored as a timestamp set in a timestamp queue. FIG14 illustrates the example of storing one timestamp (e.g., the first timestamp) of the multiple timestamps of Vsync-hw in the timestamp queue.

[0094] As shown in Figure 14, the first timestamp TS1 of Vsync-hw (abbreviated as Vsync-hw2) in the second cycle is stored in the timestamp queue, and the timestamp of Vsync-hw2 is used to generate Vsync-sf4; the first timestamp TS2 of Vsync-hw3 is stored in the timestamp queue, and Vsync-sf5 can be generated based on the timestamp of Vsync-hw3; the first timestamp TS3 of Vsync-hw4 is stored in the timestamp queue, and Vsync-sf6 can be generated based on the timestamp of Vsync-hw4. Because Vsync-hw3 takes a long time, the sampling time of Vsync-hw3 is increased, causing the generation of Vsync-sf5 to be delayed. Before the refresh rate switch, the Vsync-hw period should be the same as the Vsync-sf period. However, the increased Vsync-hw3 time makes the periods of Vsync-hw3 and Vsync-sf3 different, resulting in the end time of Vsync-sf3 being different from the end time of Vsync-hw3, and the end of Vsync-hw3 being later than the end of Vsync-sf3. After Vsync-sf3 ends, Vsync-sf4 begins, and after Vsync-hw3 ends, Vsync-hw4 begins. Therefore, when the end time of Vsync-sf3 is different from the end time of Vsync-hw3, the start time of Vsync-sf4 and Vsync-hw4 are different. Starting from Vsync-hw4, the software and hardware Vsync are not aligned.

[0095] Figure 15 shows the optimization of the timestamp sequence and predicted Vsync-sf. When the refresh rate is switched and the time taken by Vsync-hw3 before the refresh rate switch is 19.4ms, addHwVsyncTimestamp skips the timestamp of Vsync-hw3 and uses the timestamp of Vsync-hw4 to generate Vsync-sf5, where Vsync-sf5 is separated from Vsync-hw3 by a Vsync-hw cycle, and Vsync-hw5 is separated from Vsync-hw3 by a Vsync cycle. The cycle of c-hw indicates that the start time of Vsync-hw5 and Vsync-sf5 is one Vsync-hw cycle (i.e., one Vsync-hw4) away from the end time of Vsync-hw3. Vsync-hw5 and Vsync-sf5 have the same refresh rate, which means that the cycle of Vsync-hw5 is the same as that of Vsync-sf5. Therefore, Vsync-hw5 and Vsync-sf5 have the same cycle and the same reference, that is, Vsync-hw5 and Vsync-sf5 are aligned.

[0096] Because addHwVsyncTimestamp skips the timestamp of Vsync-hw3 and uses the timestamp of Vsync-hw4 to generate Vsync-sf5, and Vsync-hw4 is the next Vsync-hw after Vsync-hw3, using the timestamp of Vsync-hw4 to generate Vsync-sf5 means that the generation of Vsync-sf5 is delayed, and the end time of Vsync-sf4 is also delayed, which increases the period of Vsync-sf4. As shown in Figure 15, the period of Vsync-sf4 is 19.4ms. The dotted line indicates that when Vsync-sf5 is generated from Vsync-hw3, the period of Vsync-sf4 increases from 16.6ms to 19.4ms when the timestamp of Vsync-hw4 is used to generate Vsync-sf5. Although the period of Vsync-sf4 increases, Vsync-hw5 and Vsync-sf5 are aligned. In this way, starting from Vsync-sf5, the electronic device can generate image frames normally, avoiding the phenomenon of synthesizing one frame and dropping one frame.

[0097] In addition, the present application provides an electronic device, which includes: one or more processors; one or more memories; the memories store one or more programs, and when one or more programs are executed by the processor, the electronic device performs the above-mentioned display method.

[0098] The present application provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the processor executes the above-mentioned display method.

Claims

1. A display method, characterized in that: Applied to electronic equipment, the method includes: Determining that a refresh rate of the electronic device switches from a first refresh rate to a second refresh rate, the first refresh rate being greater than the second refresh rate; In response to the refresh rate switching from the first refresh rate to the second refresh rate, generating a second image frame after the electronic device completes displaying the first image frame; The second image frame is displayed.

2. The method according to claim 1, characterized in that The method further comprises: After the refresh rate is switched to the second refresh rate, controlling the alignment of a first signal and a second signal, wherein the first signal is used to instruct generation of an image frame and the second signal is used to instruct display of an image frame; generating a third image frame when the electronic device completes display of the second image frame and the level change of the first signal satisfies a preset condition, wherein the preset condition is that the level of the first signal changes from a low level to a high level, or the level of the first signal changes from the high level to the low level; Under the action of the second signal, the third image frame is displayed.

3. The method according to claim 2, characterized in that Before determining that the refresh rate of the electronic device is switched from the first refresh rate to the second refresh rate, the method further includes: in response to the refresh rate being the first refresh rate, generating an (i+n)th first signal according to the i-th second signal, wherein the duration of the interval between the (i+n)th first signal and the i-th second signal is the sum of the periods of n first signals, where n is a natural number greater than 1; After the refresh rate is switched to the second refresh rate, controlling the alignment of the first signal and the second signal includes: after the refresh rate is switched to the second refresh rate, sampling the first second signal after the refresh rate is switched, and using the sampling result of the first second signal to generate the first signal, and the interval between the first signal and the first second signal is the sum of the periods of (n-1) second signals.

4. The method according to claim 3, characterized in that The method further includes discarding a special signal, where the special signal is the second signal generated during the process of switching the refresh rate from the first refresh rate to the second refresh rate, and the special signal is a previous signal of the first second signal.

5. The method according to claim 4, characterized in that The discarding of the special signal includes: prohibiting sampling of the special signal; or, The special signal is sampled, and the sampling result of the special signal is not stored in the result sequence.

6. The method according to any one of claims 1 to 5, characterized in that The second image frame is an image frame lost during the process of switching the refresh rate from the first refresh rate to the second refresh rate.

7. The method according to any one of claims 1 to 6, characterized in that The electronic device completing the display of the first image frame includes: after the electronic device calls the kernel thread crtc_commit to release the fence resource, determining that the electronic device completes the display of the first image frame.

8. The method according to any one of claims 1 to 7, characterized in that Determining that the refresh rate of the electronic device switches from the first refresh rate to the second refresh rate includes: determining an end time of the first signal and a start time of the first signal when the refresh rate of the electronic device is the first refresh rate; determining a difference between the end time and the start time; If the difference satisfies a preset switching condition, it is determined that the refresh rate of the electronic device is switched from the first refresh rate to the second refresh rate.

9. The method according to any one of claims 1 to 8, characterized in that The application framework layer of the electronic device includes: a refresh rate processing unit and a data reading unit; the hardware abstraction layer of the electronic device includes a hardware hybrid renderer; the kernel layer of the electronic device includes a display driver; The refresh rate processing unit is configured to determine whether the refresh rate of the electronic device is switched from the first refresh rate to the second refresh rate; The data reading unit is configured to read the first image data after the electronic device completes displaying the first image frame in response to the refresh rate switching from the first refresh rate to the second refresh rate; The hardware hybrid renderer is configured to synthesize the first image data to generate a second image frame; The display driver is used to display the second image frame.

10. The method according to claim 9, characterized in that The application framework layer further includes: a signal generating unit, the signal generating unit being configured to control, after the refresh rate is switched to the second refresh rate, alignment of a first signal with a second signal, the first signal being configured to instruct generation of an image frame, and the second signal being configured to instruct display of an image frame; The data reading unit is further configured to read the second image data when the electronic device completes display of the second image frame and the level change of the first signal satisfies a preset condition, wherein the preset condition is that the level of the first signal changes from a low level to a high level, or the level of the first signal changes from the high level to the low level; The hardware hybrid renderer is further configured to synthesize the second image data to generate a third image frame; The display driver is further configured to display the third image frame under the action of the second signal.

11. An electronic device, characterized in that: The electronic device comprises: one or more processors; one or more memories; The memory stores one or more programs, and when the one or more programs are executed by the processor, the electronic device executes the display method according to any one of claims 1 to 10.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor is caused to execute the display method according to any one of claims 1 to 10.

Images