Repeater mixed crosstalk detection

Abstract

In some examples, an apparatus includes circuitry configured to receive communications (602) on a first bus. The circuitry is further configured to provide the communication on a second bus for a first time period (604). The circuitry is further configured to monitor a duration of time (606) during which the communication is provided on the second bus. The circuitry is also configured to stop providing the communication on the second bus for a second period of time (608) in response to the duration exceeding a threshold amount.

Description

Background Art

[0001] Universal Serial Bus (USB) is a standard that establishes specifications for interconnect wiring, connectors, and communication protocols between peripheral devices. Embedded USB (eUSB) extends at least some of the USB protocols to interconnect wiring, connectors, and communication protocols between various subsystems or circuits (e.g., such as a system on a chip (SoC)). Summary of the invention

[0002] In some examples, an apparatus includes a circuit that includes a repeater circuit system, a processing circuit, a first logic circuit, a second logic circuit, a timer circuit, and a third logic circuit. The repeater circuit system has first and second inputs and first and second outputs. The processing circuit has first and second outputs. The first logic circuit has an output and first and second inputs, wherein the first input of the first logic circuit is coupled to the second output of the processing circuit, and the second input of the first logic circuit is coupled to the second output of the repeater circuit system. The second logic circuit has an output and first and second inputs, wherein the first input of the second logic circuit is coupled to the output of the first logic circuit. The timer circuit has an output and first and second inputs, wherein the first input of the timer circuit is coupled to the output of the first logic circuit, the second input of the timer circuit is coupled to the output of the second logic circuit, and the output of the timer circuit is coupled to the second input of the second logic circuit. The third logic circuit has an output and first and second inputs, wherein the first input of the third logic circuit is coupled to the first output of the processing circuit, the second input of the third logic circuit is coupled to the output of the timer circuit, and the output of the third logic circuit is coupled to the second input of the repeater circuit system.

[0003] In some examples, a device includes circuitry configured to receive communications on a first bus. The circuitry is further configured to provide communications on a second bus for a first time period. The circuitry is further configured to monitor a duration of providing communications on the second bus. The circuitry is further configured to stop providing communications on the second bus for a second time period in response to the duration exceeding a threshold amount.

[0004] In some examples, a method includes receiving data at a repeater via a first bus for consecutive first and second time periods. The method also includes providing data at a second bus of the repeater for the first time period. The method also includes monitoring the duration of the first time period. The method also includes deactivating the repeater for a second time period in response to the duration exceeding a threshold amount. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of the example system.

[0006] Figure 2is a block diagram of an example high speed (HS) component of a host-side repeater.

[0007] Figure 3 is a block diagram of an example HS component of a peripheral side repeater.

[0008] Figure 4 is a block diagram of an example repeater.

[0009] Figure 5 is a timing diagram of the example signals.

[0010] Figure 6 is a flowchart of the instance method.

[0011] Figure 7 is a flowchart of the instance method.

[0012] Figure 8 is a flowchart of the instance method. DETAILED DESCRIPTION

[0013] As described above, USB is a standard that establishes specifications for interconnect wiring, connectors, and communication protocols. As referred to herein, USB refers to any version of the USB specification, including any amendments or supplements certified by the USB Implementers Forum (USB IF) or any suitable body that replaces and / or assists the USB IF in the role of overseeing the USB specification, whether currently existing or developed later. In at least one instance, USB as referred to herein covers any one or more of the USB 1.0 specification, the USB 2.0 specification, the USB 3.0 specification, the USB 4.0 specification, or any derivative thereof (e.g., amendments or ".x" variants of the above specifications). In addition, as referred to herein, traditional USB refers to USB 2.x and / or USB 1.x. In at least some instances, embedded USB (eUSB) refers to eUSB2.0 or eUSB2. Although eUSB2 is mentioned herein, in various instances, the teachings of this specification further apply to other versions of eUSB2 that are extensions, replacements, derivatives of eUSB2, or otherwise share at least some commonality or similarity with eUSB2. Thus, although eUSB2 is referred to herein in an exemplary manner, in some examples, the present description is not limited to implementation in an eUSB 2.0 environment, in an eUSB2 environment, or in a USB environment.

[0014] When USB was born, it was primarily envisioned to be implemented when defining standards for connection and communication between personal computers and peripheral devices. However, as the adoption of the USB standard has expanded and implementation in computing devices that support the USB standard has become popular, efforts have been made to expand and expand the applicability of USB. For example, although specifications were initially established for communication between personal computers and peripheral devices, USB has expanded to communication between peripheral devices, between personal computers, and other use cases. Due to this widespread implementation and use of USB, further efforts are being made to utilize USB as a communication protocol between various subsystems or circuits (e.g., systems on a chip (SoC)). Such implementations are sometimes referred to as eUSB2.0, or more simply as eUSB2. New challenges arise when implementing eUSB2. For example, at the circuit level, computing devices typically operate at voltage levels different from those of traditional USB, thereby creating obstacles between direct communication between eUSB2 and traditional USB systems. To alleviate this obstacle, the eUSB2 repeater acts as a bridge or non-linear redriver between the eUSB2 and legacy USB systems, and vice versa, to convert between legacy USB signaling voltage levels, which are conventionally approximately 3.3 volts (V), and eUSB2 signaling voltage levels, which are circuit levels (e.g., silicon appropriate voltages) of, for example, approximately 1.0 V, 1.2 V, 1.4 V, or any other suitable value less than 3.3 V.

[0015] In some cases, a device continues to signal beyond the maximum packet duration specified in the communication standard (e.g., USB or eUSB2) according to which the device communicates. For example, the maximum packet duration according to some communication standards or protocols may be about 20 microseconds (μs). A device that continues to signal beyond this maximum packet duration is called a mixed string. In an example of a communication system comprising a first device, an eUSB2 repeater, and a second device, wherein the first device sends data to a repeater with a signal, and the repeater relays the data to the second device, the second device is able to detect the mixed string of the first device. However, when the repeater relays the data to the second device, since the signaling line between the repeater and the second device is occupied by the relayed data, the signal from the second device notifying the repeater of the mixed string of the first device may not be detected by the repeater. To alleviate this situation, some repeaters may include a separate or dedicated reset pin or port outside the pin or port specified according to USB or eUSB2. However, this method is not standardized and requires additional pins, thereby increasing the space and cost of such implementations.

[0016] Examples of the present specification provide a repeater capable of detecting a mixed-talk condition and initiating a connection reset. For example, the repeater may monitor the amount of time that the repeater relays data from a first device to a second device (or conversely, does not relay data from the first device to the second device). In response to the amount of time exceeding a threshold amount, the repeater may be internally deactivated to reset the repeater and / or prevent the repeater from relaying data received from the first device, thereby resolving the mixed-talk condition seen at the second device. In some examples, the first device detects the deactivation of the repeater and stops transmitting in response to the deactivation and disconnection of the repeater.

[0017] Figure 1 1 is a block diagram of an example system 100. In the example, the system 100 includes a host system 104 having a host device 116 and a repeater (e.g., an eUSB2 repeater) 118, and a peripheral system 108 having a peripheral device 122 and a repeater (e.g., an eUSB2 repeater) 124. The host system 104 is coupled to the peripheral system 108 via a bus 112, such as a USB 2.0 bus. The host device 116 is coupled to the eUSB2 repeater 118 (which may also be referred to as a host-side repeater 118) via an eUSB2 bus 120. The peripheral device 122 is coupled to the eUSB2 repeater 124 (which may also be referred to as a peripheral-side repeater 124) via an eUSB2 bus 126. In various examples, the host device 116 may be an application processor unit (APU), a microcontroller unit (MCU), a general purpose processor, logic circuitry, memory, analog circuitry, and / or a state machine. Peripheral systems 108 may include, for example, an external hard drive, a mouse, a printer, a keyboard, a display, logic circuitry, analog circuitry, and / or a processor.

[0018] In the example, bus 112 is an external connection between host system 104 and peripheral system 108 , eUSB2 bus 120 is an interconnection between eUSB2 repeater 118 and host device 116 , and eUSB2 bus 126 is an interconnection between eUSB2 repeater 124 and peripheral device 122 .

[0019] In some examples, peripheral system 108 may include repeater 124, and host system 104 may not include repeater 118. In other examples, host system 104 may include repeater 118, and peripheral system 108 may not include repeater 124.

[0020] In operation, the host device 116 transmits downstream packets via the eUSB2 bus 120. The repeater 118 converts the downstream packets from the eUSB2 signaling voltage level (e.g., about 1.0V to 1.2V) to the USB 2.0 signaling voltage level (e.g., about 3.3V), and transmits the downstream packets via the bus 112. The repeater 124 receives the downstream packets and converts the downstream packets from the USB 2.0 signaling voltage level (e.g., about 3.3V) to the eUSB2 signaling level (e.g., about 1.0V to 1.2V), and transmits the downstream packets to the peripheral device 122 via the eUSB2 bus 126.

[0021] The peripheral device 122 may respond to the host device 116 with an upstream packet transmitted to the repeater 124 via the eUSB2 bus 126. The repeater 124 converts the upstream packet from the eUSB2 signaling voltage level to the USB 2.0 signaling voltage level and transmits the upstream packet via the bus 112. The repeater 118 receives the upstream packet and converts the upstream packet from the USB 2.0 signaling voltage level to the eUSB2 signaling voltage level and transmits the upstream packet to the host device 116 via the eUSB2 bus 120.

[0022] As described above, in some examples, the eUSB2 bus 126 may be busy (e.g., occupied), for example, via a downstream packet. In such an example, the peripheral device 122 is unable to transmit an upstream packet to the repeater 124 via the eUSB2 bus 126. Therefore, in an example where the host system 104 is pinging, the peripheral device 122 cannot notify the repeater 124 of the pinging. To mitigate this, in some examples, the repeater 124 includes circuitry (not shown), programming, or a combination thereof to detect the pinging of the host system 104. For example, in response to the repeater 124 receiving a continuous data stream (e.g., a data packet) from the host system 104 without interruption for greater than a programmed amount of time, the repeater 124 determines that the host system 104 is pinging. In response to determining that the host system 104 is pinging, the repeater 124 disables the relaying of the received communication to the peripheral device 122. In some examples, repeater 124 disables relaying of received communications until the babble condition is resolved (eg, host system 104 stops sending data) or peripheral device 122 resets repeater 124 .

[0023] Although the present specification contemplates an example in which repeater 124 detects mixed chatter of host system 104, in various other examples, other configurations are possible. For example, repeater 124 may detect mixed chatter of peripheral device 122, repeater 118 may detect mixed chatter of peripheral device 122, repeater 118 may detect mixed chatter of host device 110, or any combination thereof.

[0024] Figure 21 is a block diagram of a high-speed (HS) component 200 of a repeater 118 in various embodiments. The repeater 118 includes an eUSB2 port 204 configured to interface with an eUSB2 bus 120. The eUSB2 bus 120 provides a connection to a host device 116, such as Figure 1 As shown in . The eUSB2 port 204 includes an eUSB2 transmitter 208 and an eUSB2 receiver 210. The eUSB2 transmitter 208 transmits upstream packets to the host device 116 via the eUSB2 bus 120. The eUSB2 receiver 210 receives downstream packets from the host device 116 via the eUSB2 bus 120. In an example, the eUSB2 transmitter 208 and the eUSB2 receiver 210 are implemented with or as buffers.

[0025] The eUSB2 port 204 includes a high speed squelch circuit (eHSSQ) 212 that detects downstream packets on the eUSB2 bus 120. The eHSSQ 212 can detect a start of packet (SOP) of a downstream packet transmitted by the host device 116 via the eUSB2 bus 120, and in response thereto assert a squelch signal SQL1 indicating a downstream packet on the eUSB2 bus 120. In an example, to detect the SOP, the eHSSQ 212 detects the presence of a differential voltage on the data lines (e.g., D+ and D- data lines) of the eUSB2 bus 120, and in response thereto asserts a squelch signal SQL1 to indicate that the host device 116 has placed a downstream packet on the eUSB2 bus 120. The eUSB2 port 204 also includes a loss of signal (LOS) circuit 214 that detects an end of packet (EOP) on the eUSB2 bus 120, and in response thereto asserts a LOS1 signal.

[0026] Repeater 118 also includes a USB 2.0 port 220 configured to interface with bus 112. Bus 112 provides connections to peripheral systems 108, such as Figure 1 . The USB 2.0 port 220 includes a USB 2.0 transmitter 224 and a USB 2.0 receiver 226. The USB 2.0 receiver 226 receives upstream packets from the peripheral system 108 via the bus 112. The USB 2.0 transmitter 224 transmits downstream packets to the peripheral system 108 via the bus 112. In an example, the USB 2.0 transmitter 224 and the USB 2.0 receiver 226 are implemented with or as buffers. In some examples, the eUSB2 port 204 operates at a different voltage (e.g., about 1V to 1.2V) than the USB2 port 220 (e.g., about 3V). In these examples, the repeater 118 may include isolation (e.g., galvanic isolation) between the eUSB2 port 204 and the USB2 port 220 so that these ports can operate at different voltages.

[0027] The USB 2.0 port 220 includes a high-speed squelch circuit (HSSQ) 228 that detects an upstream packet on the bus 112. The HSSQ 228 can detect the SOP of an upstream packet transmitted by the peripheral system 108 via the bus 112, and in response thereto assert a squelch signal SQL2 indicating an upstream packet. In an example, to detect the SOP, the HSSQ 228 detects the presence of a differential voltage on the data lines (e.g., D+ and D- data lines) of the bus 112, and in response thereto asserts a squelch signal SQL2 to indicate that the peripheral system 108 has placed an upstream packet on the bus 112. The USB 2.0 port 220 also includes a high-speed disconnect detection circuit (HSDSC) 232 that monitors the removal of a peripheral HS terminal from the bus 112. The HSDSC 232 asserts a DSC1 signal in response to a disconnection of a peripheral device from the bus 112.

[0028] Figure 3 1 is a block diagram of a HS component 300 of a repeater 124 in various embodiments. The repeater 124 includes an eUSB2 port 304 configured to interface with an eUSB2 bus 126. The eUSB2 bus 126 provides connections to peripheral devices 122, such as Figure 1 As shown in FIG. 1 , the eUSB2 port 304 includes an eUSB2 receiver 308 and an eUSB2 transmitter 310. The eUSB2 receiver 308 receives upstream packets from the peripheral device 122 via the eUSB2 bus 126. The eUSB2 transmitter 310 transmits downstream packets to the peripheral device 122 via the eUSB2 bus 126. In an example, the eUSB2 receiver 308 and the eUSB2 transmitter 310 are implemented with or as buffers.

[0029] The eUSB2 port 304 includes a high speed squelch circuit (eHSSQ) 312 that detects an upstream packet on the eUSB2 bus 126. The eHSSQ 312 can detect the SOP of an upstream packet transmitted by the peripheral device 122 via the eUSB2 bus 126, and in response thereto assert a squelch signal SQL3 indicating an upstream packet on the eUSB2 bus 126. In an example, to detect the SOP, the eHSSQ 312 detects the presence of a differential voltage on the data lines of the eUSB2 bus 126, and in response thereto provides a squelch signal SQL3 indicating that the peripheral device 122 has placed an upstream packet on the eUSB2 bus 126. The eUSB2 port 304 also includes a LOS circuit 314 that detects an end of packet (EOP) on the eUSB2 bus 126 and in response thereto provides a LOS2 signal.

[0030] Repeater 124 also includes a USB 2.0 port 320 coupled to bus 112. Bus 112 provides a connection to host device 116, such as Figure 1. The USB 2.0 port 320 includes a USB 2.0 receiver 324 and a USB 2.0 transmitter 326. The USB 2.0 receiver 324 receives downstream packets from the host device 116 via the bus 112. The USB 2.0 transmitter 326 transmits upstream packets to the host device 116 via the bus 112. In an example, the USB 2.0 receiver 324 and the USB 2.0 transmitter 326 are implemented with or as buffers. In some examples, the eUSB2 port 304 operates at a different voltage (e.g., about 1V to 1.2V) than the USB2 port 320 (e.g., about 3V). In these examples, the repeater 124 may include isolation (e.g., galvanic isolation) between the eUSB2 port 304 and the USB2 port 320 to isolate the ports so that the ports can operate at different voltages.

[0031] The USB 2.0 port 320 includes a high-speed squelch circuit HSSQ 328 that detects downstream packets on the bus 112. The HSSQ 328 can detect the SOP of the downstream packets transmitted by the host device 116, and in response thereto assert a squelch signal SQL4 indicating the downstream packets. In an example, to detect the SOP, the HSSQ 328 detects the presence of a differential voltage on the data lines of the bus 112, and in response thereto provides SQL4, which indicates that the host system 104 has placed a downstream packet on the bus 112.

[0032] In some instances, USB 2.0 port 320 also includes high speed disconnect HSDSC 332, while in other instances HSDSC 332 is omitted, such as in instances where the peripheral device does not detect disconnection via the data lines of bus 112. HSDSC 332 asserts the DSC2 signal in response to the host system disconnecting from bus 112.

[0033] In an example, the USB 2.0 receiver 324 and the eUSB2 transmitter 310 each include an enable input. In response to receiving a signal (Enable) having a value of logic 1 at its enable input, the USB 2.0 receiver 324 and the eUSB2 transmitter 310 are enabled and configured to forward received signals. In response to receiving Enable having a value of logic 0 at its enable input, the USB 2.0 receiver 324 and the eUSB2 transmitter 310 are disabled and configured not to forward received signals. For example, in response to determining a mixed sound condition, as described herein, Enable having a value of logic 0 may be provided to disable signal forwarding by the USB 2.0 receiver 324 and the eUSB2 transmitter 310. In some examples, the eUSB2 receiver 210 and the USB 2.0 transmitter 224 may additionally or alternatively have an enable input.

[0034] Figure 4 4 is a block diagram of an example repeater 124 in various examples. In some examples, the repeater 124 includes the HS component 300, the state machine 402, the logic circuit 404, the logic circuit 406, the timer 408, and the logic circuit 410. In the example architecture, the HS component 300 is coupled to the bus 112 and the eUSB2 bus 126, as described above with respect to Figure 3 HS component 300 also has an enable input (to which Enable is provided) and a status output (at which SQL4 is provided). In some examples, the enable input belongs to USB 2.0 receiver 324 and eUSB2 transmitter 310, as described above with respect to Figure 3 As described above, Enable is provided to USB 2.0 receiver 324 and eUSB2 transmitter 310. In some examples, the status output of HS component 300 is the output of HSSQ 328, as described above with respect to Figure 3 As described, the status signal provided at the status output is SQL4.

[0035] State machine 402 has a first output and a second output. Logic circuit 404 has a first input coupled to the second output of state machine 402, a second input coupled to the state output of high-speed component 300, and an output. In some examples, the second input of logic circuit 404 is an inverting input. The second input of logic circuit 404 can be inverted by coupling an inverter (not shown) between the second input of logic circuit 404 and the state output of high-speed component 300 or by incorporating inverter circuitry into the circuitry of logic circuit 404. Logic circuit 406 has a first input coupled to the output of logic circuit 404, a second input, and an output. Timer 408 has a reset input coupled to the output of logic circuit 404, an increment input coupled to the output of logic circuit 406, and an output coupled to the second input of logic circuit 406. In some examples, the second input of logic circuit 406 is an inverting input. The second input of logic circuit 406 can be inverted by coupling an inverter (not shown) between the second input of logic circuit 406 and the output of timer 408 or by incorporating inverter circuitry into the circuitry of logic circuit 406. In some examples, the reset input of timer 408 is an inverting input. The reset input of timer 408 can be inverted by coupling an inverter (not shown) between the reset input of timer 408 and the output of logic circuit 404 or by incorporating inverter circuitry into the circuitry of timer 408. Logic circuit 410 has a first input coupled to the first output of state machine 402, a second input coupled to the output of timer 408, and an output coupled to the enable input of high speed component 300. The second input of logic circuit 410 can be inverted by coupling an inverter (not shown) between the second input of logic circuit 410 and the output of timer 408 or by incorporating inverter circuitry into the circuitry of logic circuit 410.

[0036] exist Figure 4 In an example of operation of the repeater 124 of the HS component 300, the HS component 300 provides an idle signal indicating that the repeater 124 is inactive (not repeating), for example, so that the host system 104 has not yet placed data on the bus 112 for the repeater 124 to repeat. In some examples, the idle signal is an active high signal (e.g., having a value of logic 1 in response to the absence of data on the bus 112), while in other examples, the idle signal is an active low signal (e.g., having a value of logic 0 in response to the absence of data on the bus 112). In an example, the idle signal is SQL4, as described above.

[0037] State machine 402 provides a status signal at its second output indicating the state of the repeater. The operation of state machine 402 may be performed according to actions specified by the standard. For example, state machine 402 may provide a status signal (HS L0) having a value determined based on the USB or eUSB standard, as described above. In an example, state machine 402 determines the value of the status signal based on the value of any one or more of the signals provided on bus 112, the signals provided on bus 120, and / or the signals provided on bus 126, the signals provided on the bus being represented, for example, by SQL4, SQL3, DSC2, and LOS2, as defined in the standard applicable to the operation of state machine 402. Although Figure 4 4. Although not shown in FIG. 4, in some examples, state machine 402 receives any one or more of SQL4, SQL3, DSC2, and / or LOS2 as input. State machine 402 may generally be referred to as a processing circuit, or may be implemented by a processing circuit. The processing circuit may be a processor, a microprocessor, a controller, an integrated circuit, a field programmable gate array (FPGA), or any other combination of analog, digital, or logic circuits or components coupled to provide functionality including an implementation of state machine 402. In some examples, logic circuit 404 performs an AND logic operation such that in response to the state signal having a value of logic 1 (e.g., indicating that repeater 124 is in a normal functional mode in which high-speed data transmission is available) and the idle signal having a value of logic 0, logic circuit 404 provides a reset signal having a value of logic 1 at its output. In response to the idle signal having a value of logic 1 or the state signal having a value of logic 0 (e.g., indicating that repeater 124 is in a low-power mode in which high-speed data transmission is not available), logic circuit 404 provides a reset signal having a value of logic 0.

[0038] In some examples, logic circuit 406 performs an AND logic operation such that in response to the reset signal having a value of logic 1 and the timer signal provided at the output of timer 408 having a value of logic 0, logic circuit 406 provides an increment signal having a value of logic 1. In response to the timer signal having a value of logic 1 or the reset signal having a value of logic 0, logic circuit 406 provides an increment signal having a value of logic 0. Timer 408 includes any suitable circuitry for maintaining and incrementing a count and providing a timer signal in response to the count exceeding a programmed value. In some examples, the timer signal has a value of logic 0 in response to the count maintained by timer 408 being less than the programmed value, and has a value of logic 1 in response to the count maintained by timer 408 being greater than the programmed value. In some examples, the programmed value represents a maximum packet duration specified in the communication standard under which repeater 124 operates, as described above. In some examples, timer 408 is clocked by a clock signal (not shown) such that in response to the reset signal having a value of logic 1 and the increment signal having a value of logic 0, the count maintained by timer 408 is incremented at an edge of the clock signal. In an example, the clock signal is provided by an internal free running oscillator (not shown) of timer 408 that clocks timer 408. In some examples, the edge is a rising edge of the clock signal, while in other examples, the edge is a falling edge of the clock signal.

[0039] The state machine 402 also provides a repeater enable signal at its first output. The state machine 402 determines the value of the repeater enable signal. In some examples, the logic circuit 410 performs an AND logic operation such that in response to the repeater enable signal having a value of logic 1 and the timer signal having a value of logic 0, the logic circuit 410 provides Enable having a value of logic 1. In response to the repeater enable signal having a value of logic 0 or the timer signal having a value of logic 1, the logic circuit 410 provides Enable having a value of logic 0. In response to Enable having a value of logic 1, the HS component 300 relays data received on the bus 112 to the eUSB2 bus 126. In response to Enable having a value of logic 0 indicating a shuffle condition of the device providing data on the bus 112, the HS component 300 is disabled and does not relay data received on the bus 112 to the eUSB2 bus 126. For example, Enable has a value of logic 0 causing the USB 2.0 receiver 324 and the eUSB2 transmitter 310 to be disabled and configured to not forward received signals, as described above with respect to Figure 3 described.

[0040] Figure 55 is a timing diagram 500 of signals in various examples. In an example, the signals may be present in and / or represent the operation of a system such as the system 100, the peripheral system 108, and / or the repeater 124. The diagram 500 includes DP and DM representing the positive and negative components of a differential signal provided on the bus 112 (e.g., an input to the repeater 124), eDP and eDM representing the positive and negative components of a differential signal provided on the bus 126 (e.g., an output of the repeater 124), SQL4, an output signal of the timer 408 indicating that a mixed sound condition has been detected, Enable, a state of the state machine 402, a state of the timer 408, and a bus reset signal (XeSE1).

[0041] In some examples, at time t1, data (e.g., DP / DM) is detected on bus 112. In response to detecting the data, SQL4 is set to a value of logic 0, and the data is forwarded to bus 126 as eDP / eDM. In response to SQL4 being set to a value of logic 0, timer 408 begins to increment. At time t2, the count maintained by timer 408 reaches a programmed value, which indicates a maximum duration of DP / DM according to the communication standard based on which DP / DM is provided. In response to the count reaching this maximum duration, timer 408 provides an output signal having a value of logic 1 to indicate that a mixed sound condition on bus 112 has been detected. In response to the output signal of timer 408 having a value of logic 1, Enable having a value of logic 0 is provided. Enable having a value of logic 0 disables DP / DM as a relay for eDP / eDM, as described above. At time t3, data is no longer provided on bus 112, and SQL4 having a value of logic 1 is provided. In response to SQL4 having a value of logic 1, timer 408 is reset to count 0, the output signal of timer 408 is set to logic 0, and Enable having a value of logic 1 is provided. Enable having a value of logic 1 enables DP / DM as a relay for eDP / eDM, as described above.

[0042] At time t4, DP / DM is detected on bus 112. In response to detecting DP / DM, SQL4 is set to a value of logic 0, and DP / DM is forwarded to bus 126 as eDP / eDM. In response to SQL4 being set to a value of logic 0, timer 408 begins to increment. At time t5, peripheral device 122 provides XeSE1 with a value of logic 1. In some instances, XeSE1 is a bus or port reset signal. Repeater 124 may be configured to reset, enter an unconnected state, or perform other actions in response to receiving XeSE1 with a value of logic 1. However, eDP / eDM relayed by repeater 124 on bus 126 may cause contention on bus 126, thereby preventing repeater 124 from receiving XeSE1 from peripheral device 122. At time t6, the count maintained by timer 408 reaches a programmed value, which indicates the maximum duration of DP / DM according to the communication standard on which DP / DM is provided. In response to the count reaching this maximum duration, timer 408 provides an output signal having a value of logic 1 to indicate that a mixed-talk condition has been detected on bus 112. In response to the output signal of timer 408 having a value of logic 1, Enable having a value of logic 0 is provided. Enable having a value of logic 0 causes DP / DM on bus 126 to be disabled as a relay for eDP / eDM, as described above.

[0043] Disabling the repeating on bus 126 may resolve contention with peripheral device 122 transmitting XeSE1 having a value of logic 1. Thus, at time t7, repeater 124 detects the logic 1 value of XeSE1 and asserts the reset signal to reset, enter an unconnected state, or perform other actions.

[0044] Figure 6 6 is a flow chart of a method 600 in various examples. In some examples, the method 600 is implemented by a repeater (e.g., repeater 124), as described above. The method 600 is implemented, for example, to detect a mixed sound condition of a device providing data to the repeater, and to stop the relaying of the data in response to detecting the mixed sound condition.

[0045] At operation 602, a repeater receives communications on a first bus. In some instances, the first bus is a USB 2.0 bus, such as USB 2.0 bus 112, and the communications are received from a USB 2.0 device. In other instances, the first bus is an eUSB2 bus, such as eUSB2 bus 126, and the communications are received from an eUSB2 device. In some instances, the communications are arranged as packets subject to maximum packet length or maximum duration restrictions to conform to a particular communication protocol or standard.

[0046] At operation 604, the repeater provides communications on the second bus for a first period of time. Providing communications on the second bus may be referred to as relaying communications received at operation 602 on the first bus. In some examples, the second bus is an eUSB2 bus and the communications are provided to an eUSB2 device. In other examples, the second bus is a USB 2.0 bus and the communications are provided to a USB 2.0 device.

[0047] At operation 606, the repeater monitors the duration of providing communications on the second bus. In another example, the repeater monitors the duration of receiving communications on the first bus. In some examples, the repeater monitors the duration by incrementing a count of a timer for the monitored time period.

[0048] At operation 608, in response to the duration exceeding the threshold amount, the repeater stops providing communication on the second bus for a second time period. For example, in response to the duration exceeding the threshold or programmed amount, the repeater determines that there is a mixed string condition. The threshold or programmed amount is, for example, a maximum packet length or duration of communication. The maximum packet length or duration can be, for example, a duration specified in the communication protocol, standard, or specification described above. In some instances, the repeater stops relaying or providing communication on the second bus by de-asserting the repeater enable signal.

[0049] Figure 7 700 in various examples. In some examples, the method 700 is implemented by a repeater (e.g., repeater 124), as described above. The method 700 is implemented, for example, to detect a mixed sound condition of a device providing data to the repeater, and to stop the relaying of the data in response to detecting the mixed sound condition.

[0050] At operation 702, a repeater receives data via a first bus for first and second consecutive amounts of time. In some instances, the first bus is a USB 2.0 bus and the data is received from a USB 2.0 device. In other instances, the first bus is an eUSB2 bus and the data is received from an eUSB2 device. In some instances, the data is arranged into packets subject to maximum packet length or maximum duration restrictions to conform to a particular communication protocol or standard.

[0051] At operation 704, the repeater provides data at the second bus for a first amount of time. Providing data on the second bus may be referred to as repeating the data received at operation 702 on the first bus. In some examples, the second bus is an eUSB2 bus and the data is provided to an eUSB2 device. In other examples, the second bus is a USB 2.0 bus and the data is provided to a USB 2.0 device.

[0052] At operation 706, the repeater monitors a duration of the first amount of time. In some examples, the repeater monitors the duration by incrementing a count of a timer for the monitored time period.

[0053] At operation 708, in response to the duration exceeding the threshold amount, the repeater disables relaying for a second amount of time. For example, in response to the duration (e.g., the first amount of time) meeting or exceeding a threshold or programming amount, the repeater determines that there is a mixed sound condition of the device that provides data or data. The threshold or programming amount is, for example, a maximum packet length or duration of data. The maximum packet length or duration can be, for example, a duration specified in a communication protocol, standard, or specification described above. In some examples, the repeater stops relaying or providing data on the second bus by de-asserting the repeater enable signal.

[0054] Figure 8 8 is a flow chart of a method 800 in various examples. In some examples, the method 800 is implemented by a repeater (eg, repeater 124), as described above. The method 800 is implemented, for example, to control the operation of the repeater 124.

[0055] At operation 802, repeater 124 enters high speed operation (e.g., HS LO=1). Repeater 124 entering high speed operation may be determined by state machine 402, for example, based on the value of any one or more of SQL2, SQL4, a signal provided on bus 112, a signal provided on bus 120, and / or a signal provided on bus 126, as defined in a standard applicable to the operation of state machine 402.

[0056] At operation 804, the repeater 124 determines whether SQL4 has a value of logic 1. In response to SQL4 having a value of logic 1, the method 800 remains at operation 802. In response to SQL4 not having a value of logic 1, the method 800 proceeds to operation 806. Figure 8 Not explicitly shown in , operation 804 may be responsive to receiving data for relaying by repeater 124, such as DP / DM on bus 112 for relaying on bus 126 as eDP / eDM, as described above.

[0057] At operation 806 , the repeater 124 sets Enable to a value of logic 1 and relays DP / DM as eDP / eDM, thereby proceeding to operation 808 .

[0058] At operation 808, the timer 408 determines whether the increment count (e.g., the mixed sound timer) has exceeded a programmed value (e.g., tmax). In an example, tmax is determined based on the communication standard or protocol according to which DP / DM is provided as described above. In response to the mixed sound timer not exceeding tmax, the method proceeds to operation 810.

[0059] At operation 810, the repeater 124 determines whether SQL4 has a value of logic 1. In response to SQL4 not having a value of logic 1, the method 800 returns to operation 808. In response to SQL4 having a value of logic 1, the method 800 proceeds to operation 812.

[0060] At operation 812 , the repeater 124 sets Enable to a value of logic 0, thereby disabling the DP / DM on the bus 126 as a relay for eDP / eDM. Subsequently, the method 800 returns to operation 804 .

[0061] Returning to operation 808, in response to the crosstalk timer exceeding tmax, the method proceeds to operation 814. At operation 814, the repeater 124 sets Enable to a value of logic 0, thereby disabling the DP / DM on the bus 126 as a relay for eDP / eDM. Subsequently, the method 800 proceeds to operation 816.

[0062] At operation 816, the repeater 124 determines whether SQL4 has a value of logic 1. In response to SQL4 having a value of logic 1, the method 800 returns to operation 804. In response to SQL4 not having a value of logic 1, the method 800 proceeds to operation 818.

[0063] At operation 818, the repeater 124 determines whether XeSE1 having a logic 1 value is received. In response to not receiving XeSE1 having a logic 1 value, the method 800 returns to operation 816. In response to receiving XeSE1 having a logic 1 value, the method 800 proceeds to operation 820.

[0064] At operation 820, the repeater 124 resets or enters an unconnected / disconnected state in response to the logic 1 value of XeSE1. In some examples, in response to the repeater 124 entering the unconnected / disconnected state, the status signal is set to a logic 0 value.

[0065] Although the operations of methods 600, 700, 800 have been described and labeled with reference numerals, in various examples, methods 600, 700, 800 include additional operations not described herein (e.g., intermediate comparisons, logic operations, output selections such as via multiplexers, etc.). In some examples, any one or more of the operations described herein include one or more sub-operations (e.g., intermediate comparisons, logic operations, output selections such as via multiplexers, etc.), in some examples, any one or more of the operations described herein are omitted, and / or in some examples, any one or more of the operations described herein are performed in an order different from that presented herein (e.g., in reverse order, substantially simultaneously, overlapping, etc.).

[0066] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0067] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or through a combination thereof.

[0068] Circuits or devices described herein as including certain components may alternatively be coupled to those components to form the described circuit systems or devices. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0069] Although some components may be described herein as belonging to a specific process technology, these components may be exchanged with components of other process technologies. The circuits described herein may be reconfigured to include replaced components to provide functionality that is at least partially similar to the functionality available before component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements that are coupled in series and / or in parallel to provide the impedance amount represented by the resistors shown. For example, a resistor or capacitor shown and described as a single component in this article may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described as a single component in this article may alternatively be a plurality of resistors or capacitors coupled in series between two nodes identical to a single resistor or capacitor.

[0070] The use of the phrase "ground voltage potential" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "approximately" or "substantially" before a parameter means within + / -10% of the parameter.

[0071] Modifications may be made in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A device comprising: A circuit comprising: repeater circuitry having first and second inputs and first and second outputs; a processing circuit having first and second outputs; a first logic circuit having an output and first and second inputs, wherein the first input of the first logic circuit is coupled to the second output of the processing circuit and the second input of the first logic circuit is coupled to the second output of the repeater circuitry; a second logic circuit having an output and first and second inputs, wherein the first input of the second logic circuit is coupled to the output of the first logic circuit; a timer circuit having an output and first and second inputs, wherein the first input of the timer circuit is coupled to the output of the first logic circuit, the second input of the timer circuit is coupled to the output of the second logic circuit, and the output of the timer circuit is coupled to the second input of the second logic circuit; as well as a third logic circuit having an output and first and second inputs, wherein the first input of the third logic circuit is coupled to the first output of the processing circuit, the second input of the third logic circuit is coupled to the output of the timer circuit, and the output of the third logic circuit is coupled to the second input of the repeater circuit system.

2. The apparatus of claim 1, wherein the processing circuit implements a finite state machine.

3. The device of claim 1 , wherein the first, second, and third logic circuits are AND logic circuits, wherein the second input of the first logic circuit, the second input of the second logic circuit, and the second input of the third logic circuit are inverting inputs, and the first input of the timer circuit is an inverting input.

4. The device of claim 1, wherein the circuit is an embedded universal serial bus (eUSB) repeater.

5. The apparatus of claim 4, further comprising a Universal Serial Bus device coupled to the first input of the repeater circuitry and an eUSB device coupled to the first output of the repeater circuitry.

6. A device comprising: A circuit configured to: receiving communications on a first bus; providing said communication over the second bus for a first period of time; monitoring a duration of providing said communication on said second bus; as well as In response to the duration exceeding a threshold amount, providing the communication on the second bus is stopped for a second time period.

7. The device of claim 6, wherein the first bus is a Universal Serial Bus bus and the second bus is an eUSB bus.

8. The device of claim 6, wherein the circuit is configured to determine that a crosstalk condition exists in response to the duration exceeding the threshold amount.

9. The apparatus of claim 6, wherein the threshold amount is a maximum packet length of the communication.

10. The apparatus of claim 9, wherein the maximum packet length is a duration specified in a Universal Serial Bus specification.

11. The apparatus of claim 6, wherein the circuit comprises: repeater circuitry having first and second inputs and first and second outputs; a processing circuit having first and second outputs; a first logic circuit having an output and first and second inputs, wherein the first input of the first logic circuit is coupled to the second output of the processing circuit and the second input of the first logic circuit is coupled to the second output of the repeater circuitry; a second logic circuit having an output and first and second inputs, wherein the first input of the second logic circuit is coupled to the output of the first logic circuit; A timer circuit having an output and first and second inputs, wherein the first input of the timer circuit is coupled to the output of the first logic circuit, the second input of the timer circuit is coupled to the output of the second logic circuit, and the output of the timer circuit is coupled to the the second input of the second logic circuit; as well as a third logic circuit having an output and first and second inputs, wherein the first input of the third logic circuit is coupled to the first output of the processing circuit, the second input of the third logic circuit is coupled to the output of the timer circuit, and the output of the third logic circuit is coupled to the second input of the repeater circuit system.

12. The apparatus of claim 11, wherein to stop providing the communication on the second bus, the third logic circuit is configured to provide a repeater enable signal having a de-asserted value at the second input of the repeater circuitry.

13. The device of claim 11, wherein the timer circuit is configured to monitor the duration of the communication on the first bus.

14. A method comprising: receiving data at the repeater via the first bus for consecutive first and second time periods; providing the data at a second bus of the repeater for the first period of time; monitoring a duration of the first time period; as well as In response to the duration exceeding a threshold amount, the repeater is deactivated for the second time period. The method of claim 14 , wherein the threshold amount is a maximum packet length of the data.

16. The method of claim 15, wherein the maximum packet length is a duration specified in a Universal Serial Bus specification.

17. The method of claim 14, wherein deactivating the repeater prevents the repeater from providing the data at the second bus.

18. The method of claim 14, wherein the duration exceeding the threshold amount indicates a crosstalk condition of the data.

19. The method of claim 14, further comprising detecting a bus reset signal at the second bus during the second time period.

20. The method of claim 19, further comprising controlling the repeater to enter a disconnected state in response to the bus reset signal.

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