Synchronized alignment of multiple high-speed frequency dividers

Abstract

A timing alignment circuit (108) includes detection circuitry (138, 142) to receive a first output signal and a second output signal, and to output an error flag signal and a dividing ratio slip signal indicating whether the second output signal leads or lags behind the first output signal. The timing alignment circuit (108) also includes control circuitry and alignment circuitry (162, 164). The control circuitry (162) receives a first local synchronization state signal and outputs a first control signal to the first component (102). The alignment circuitry (164) receives the error flag signal and the divider ratio slip signal from the detection circuitry (138, 142), and also receives a second local synchronization state signal indicating when the first output signal and the second output signal are synchronized. The alignment circuitry (164) outputs a second control signal to the second component (104).

Description

[0001] The present description relates to synchronously aligning output signals of multiple high speed dividers, and more particularly to controlling multiple high speed dividers to align their respective output signals at specific edges at set points in time during operation without performing a reset or other stop / start sequence on the dividers. Background Art

[0002] Many electronic systems are designed so that their multiple integrated circuits operate synchronously. The respective clock signals of such circuits to be synchronized may be based on a common reference clock signal. Accurate high-speed clock distribution is important in various system applications, including serial interfaces between data converters (e.g., analog-to-digital converters (ADCs) or digital-to-analog converters (DACs)) on one side and logic devices (e.g., field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs)) on the other side.

[0003] The electronics industry has generally adopted high-speed serial interface standards, each of which is incorporated herein by reference in its entirety as identified below. One such standard is the low voltage differential signal (LVDS) standard TIA / EIA-644 promulgated by the Telecommunications Industry Association (TIA) and the Electronics Industries Alliance (EIA). Another serial interface standard that is particularly useful for interfaces between data converters and logic devices has been promulgated by the Joint Electron Devices Engineering Council (JEDEC) as a JEDEC standard (JESD), which includes the JESD204A, JESD204B, and JESD204C standards (collectively referred to as the JESD204 standards). The JESD204 standard provides a serial data rate of up to 12.5 gigabits per second (Gbps) while achieving deterministic latency on the serial link. The data octets are encoded into ten-bit symbols ("8b / 10b" encoding) for synchronization, clock recovery, and direct current (DC) balancing of the serializer / deserializer (SerDes). Common JESD204B / C implementations include clock generator circuits, such as digital phase-locked loops (DPLLs), from which device clock signals and system reference clock signals are generated for each device having a serial interface. For example, eight devices in a system may reside in a single clock or DPLL domain, where the device clock and system reference clock are based on one reference clock (e.g., a clock output by one PLL).

[0004] Within a given clock domain, such as in a JESD204B / C system, it may be necessary to dynamically or on-the-fly adjust the phase of one of the generated device clocks or the system reference clock during operation. In some JESD204B / C systems, such dynamic phase adjustment of one device clock in a clock domain requires all other clocks in the clock domain to be reset (e.g., stopped and restarted) and then resynchronized. If the phase adjustment is to be applied to the system reference clock, then the system reference modules throughout the clock domain must be reset and resynchronized after the phase offset is applied. In either case, dynamic clock phase adjustment of one device involves resetting all devices and clocks in the clock domain, which results in reduced system performance, utilization, and efficiency.

[0005] In instances where multiple high-speed flip-flops of a system are to be synchronized, a reset may be employed. The disadvantage of this approach is that the additional circuit overhead required to implement the reset function reduces the speed of each flip-flop. This speed loss can be significant and limits the speed of operation. One environment where this speed loss is particularly problematic is in a PLL, where the voltage-controlled oscillator (VCO) operates in the highest frequency region of the process node.

[0006] It is in this context that examples of the present specification appear. Summary of the invention

[0007] In an example, the timing alignment circuit includes a detection circuit system having an input terminal configured to receive a first output signal and a second output signal, respectively. The detection circuit system has an error flag output terminal and a division ratio output terminal, wherein the error flag output terminal is configured to output an error flag signal indicating whether the second output signal leads or lags the first output signal, and the division ratio slip output terminal is configured to output a division ratio slip signal. The timing alignment circuit further includes a control circuit system configured to receive a first local synchronization state signal, and the control circuit system has a first control output terminal configured to output a first control signal to the first component. The alignment circuit system of the timing alignment circuit is configured to receive the error flag signal and the division ratio slip signal from the detection circuit system, and is further configured to receive a second local synchronization state signal indicating when the first output signal and the second output signal are synchronized. The alignment circuit system has a second control output terminal configured to output a second control signal to the second component.

[0008] In an example, a system includes n frequency dividers, including a reference frequency divider and n-1 non-reference frequency dividers, each of the n frequency dividers being configured to output a data signal, where n is an integer of 2 or greater. The system further includes n-1 instances of detection circuit systems respectively associated with the n-1 non-reference frequency dividers. Each instance of the detection circuit system is configured to determine whether the data signal of the corresponding non-reference frequency divider leads or lags the data signal of the reference frequency divider, and to issue a corresponding error signal based on the determination. The system also includes a control circuit system coupled to the reference frequency divider; and n-1 instances of alignment circuit systems, each of which is configured to align a corresponding one of the n-1 data signals of the n-1 non-reference frequency dividers with the data signal of the reference frequency divider. The system further includes a synchronization completion circuit system, which is configured to output a global synchronization status signal when each of the data signals of the n-1 non-reference frequency dividers is aligned with the data signal of the reference frequency divider.

[0009] In an example, a method includes: applying a root clock signal to a reference divider and a non-reference divider; outputting a first output signal by the reference divider at a first initial division ratio; outputting a second output signal by the non-reference divider at a second initial division ratio; comparing the phases of the first output signal and the second output signal using a phase detection circuit system; outputting an error flag signal indicating whether the second output signal leads or lags behind the first output signal by the phase detection circuit system, and also outputting a division ratio slip signal; and adjusting the second output signal based on the error flag signal and the division ratio slip signal so that a specific edge of the second output signal is aligned with a specific edge of the first output signal.

[0010] In an example, a system includes: m output channels, where m is an integer of 3 or greater; a ring bus clock line that couples the m output channels; and m instances of a component timing circuit system that are respectively coupled to the m output channels. Each instance of the component timing circuit system includes components such as a frequency divider, a detection circuit system, a control circuit system, and an alignment circuit system. The component outputs a component output signal to be aligned with a reference output signal, and the reference output signal may originate from another component of another of the m instances of the component timing circuit system. The detection circuit system is configured to receive the component output signal and the reference output signal, and determine whether the component output signal leads or lags behind the reference output signal. The control circuit system is configured to receive a timing clock signal from the component and receive a first alignment status signal from the detection circuit system. The alignment circuit system is configured to align the component output signal with the reference output signal based on a signal received from the detection circuit system and a second alignment status signal received from the control circuit system. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1is a schematic diagram of an example system including a plurality of frequency dividers and an example timing alignment circuit.

[0012] Figure 2 is Figure 1 Example timing diagrams of various signals generated in an example system.

[0013] Figure 3 is a schematic diagram of an example multi-channel semiconductor chip in which one or more of the channel output signals may be synchronized with another channel output signal used as a reference.

[0014] Figure 4 is a schematic diagram of an example frequency division timing synchronization circuit, which can be used for Figure 3 An example multi-channel semiconductor chip is shown.

[0015] Figure 5 is the operation timing alignment circuit (e.g. Figure 1 Flowchart of an example method of a timing alignment circuit (shown in FIG. 1 ).

[0016] The same reference numerals are used in the drawings to designate the same or similar (structurally and / or functionally) features. DETAILED DESCRIPTION

[0017] Specific but non-limiting examples are described in detail below with reference to the accompanying drawings. In the drawings, corresponding numerals and symbols generally refer to corresponding parts unless otherwise indicated. Objects depicted in the drawings are not necessarily drawn to scale.

[0018] In an example arrangement, the output signals of multiple frequency dividers are synchronized during operation without resetting the frequency divider. The frequency divider can be started with the same frequency division ratio, but its output signal can be out of phase. Using phase detection, alignment and control circuit system, the output signal of the frequency divider is aligned, and then the frequency divider can be synchronously switched to its final frequency division ratio. At a specific time point, the specific edges (e.g., rising edges) of multiple output signals are aligned, and then each frequency divider can operate with its final frequency division ratio. In an example, the final frequency division ratio is selected so that the output signal of the frequency divider is aligned at the least common multiple of the final frequency division ratio. A frequency divider is used as a reference frequency divider, and one or more output signals of one or more non-reference frequency dividers are adjusted so that the rising / falling edge of each frequency divider is aligned with the corresponding rising / falling edge of the output signal of the reference frequency divider. In an example, when the edge alignment is achieved, the signal is asserted. The phase detection and alignment scheme described herein can be applied to a single or multiple clock domain environments.

[0019] Figure 11 is a schematic diagram of a system 100 that includes a plurality of frequency dividers 102, 104, and 106, and an example timing alignment circuit generally indicated by reference numeral 108. System 100 or portions thereof may be implemented as a single integrated circuit. Frequency divider 102 is a reference frequency divider, and frequency dividers 104 and 106 are each non-reference frequency dividers. Although Figure 1 Two non-reference dividers are shown, but system 100 may include from one to n-1 non-reference dividers, where n represents the total number of dividers including reference divider 102, and may be any suitable integer of 2 or greater. The dividers 102, 104, 106, etc. of system 100 may reside in a single clock domain, where all dividers are based on a root or reference clock signal (HS_CLK). In some applications (e.g., JESD204B / C applications), the root clock signal HS_CLK may have a relatively high frequency, such as on the order of several GHz. The root clock signal is distributed to dividers 102, 104, 106, etc.

[0020] The reference divider 102 has a clock input 112, a clock output 114, and a data output 116. Based on the root clock signal HS_CLK input to the clock input 112, the reference divider 102 generates a first output signal (DIV B OUT) at the data output 116. The reference divider 102 also outputs a first timing clock signal (DIV B TIMING CLK) for alignment at the clock output 114. The non-reference dividers 104 and 106 are similarly constructed. The non-reference divider 104 has a clock input 122, which is configured to receive the root clock signal, a clock output 124, at which a second timing clock signal (DIV A TIMING CLK) for alignment is output, and a data output 126, at which a second output signal (DIV A OUT) is output. The non-reference divider 106 has a clock input 132 for the root clock signal, a clock output 134 at which a third timing clock signal (DIV C TIMING CLK) for alignment is output, and a data output 136 at which a third output signal (DIV C OUT) is output. Each additional non-reference divider that may be added to the system 100 may be similarly constructed. Each of the first output signal, the second output signal, and the third output signal may be considered or used as a clock signal for one or more other components, such as one or more integrated circuits and / or one or more electronic devices.

[0021] The example timing alignment circuit 108 includes two instances of detection circuitry: detection circuitry 138 for comparing the phase of the first output signal and the second output signal, and detection circuitry 142 for comparing the phase of the first output signal and the third output signal. More generally, the number of instances of detection circuitry depends on the number of frequency dividers in the system 100. For n frequency dividers, there are n-1 instances of detection circuitry, each configured to compare the phase of the data signal of a corresponding one of the n-1 non-reference frequency dividers with the phase of the data signal of the reference frequency divider 102.

[0022] The detection circuit system 138 includes a phase detector 144 having input terminals 146 and 148 coupled to the data output terminals 116 and 126, respectively, to receive the first output signal and the second output signal. The phase detector 144 is configured to compare the phases of the first output signal and the second output signal and output the comparison signal to the filter 150, which filters the comparison signal. The filter 150 then outputs a first error flag signal indicating whether the phase of the second output signal leads or lags the phase of the first output signal. The filter 150 also outputs a first frequency division ratio slip signal.

[0023] The detection circuit system 142 includes a phase detector 154 having input terminals 156 and 158 coupled to the data output terminals 116 and 136, respectively, to receive the first output signal and the third output signal. The phase detector 154 is configured to compare the phases of the first output signal and the third output signal, and output the comparison signal to the filter 160, which filters the comparison signal. The filter 160 then outputs a second error flag signal indicating whether the phase of the third output signal leads or lags the phase of the first output signal, and also outputs a second frequency division ratio slip signal.

[0024] Each of the phase detectors 144 and 154 may be a linear phase detector, a nonlinear phase detector (e.g., a switch-mode phase detector), a time-to-digital converter (TDC), or any other detector capable of performing phase detection within one cycle of the root clock signal. Each of the filters 150 and 160 may be configured to ensure the accuracy of the lead or lag determination made by the filter by waiting a set number of cycles before outputting the error flag signal and the division ratio slip signal.

[0025] The first and second error flag signals and the first and second division ratio slip signals are used in the alignment process. A negative error flag in the error flag signal may indicate that the phase of the data signal from the corresponding non-reference frequency divider lags behind the phase of the reference frequency divider data signal, while a positive error flag signal indicates the opposite. Each additional instance of the detection circuit system may be included and is configured to output an error flag signal and a division ratio slip signal in response to a comparison of the phase of the data signal of the corresponding additional frequency divider with the first output signal.

[0026] The example timing alignment circuit 108 further includes a control circuit system 162 coupled to the reference divider 102, and two instances of alignment circuit systems 164 and 166 in the illustrated example for aligning the second output signal of the non-reference divider 104 with the first output signal of the reference divider 102 and aligning the third output signal of the non-reference divider 106 with the first output signal, respectively. More generally, the timing alignment circuit 108 includes n-1 instances of alignment circuit systems, each configured to align a corresponding one of the n-1 data signals of the n-1 non-reference dividers with the first output signal.

[0027] The example timing alignment circuit 108 further includes n control flip-flops, where in the illustrated example, n is 3. A control flip-flop 168 is associated with the reference divider 102 and the control circuitry 162. A control flip-flop 172 is associated with the non-reference divider 104 and the alignment circuitry 164. A control flip-flop 174 is associated with the non-reference divider 106 and the alignment circuitry 166.

[0028] In an example, the control circuit system 162 is a multiplexer that selects one of two division ratio signals, namely, a signal (DIV X) indicating an initial division ratio of the reference divider 102 or a signal (DIV B) indicating a final division ratio of the reference divider 102. Which signal is selected by the multiplexer 162 and output to the reference divider 102 is controlled by a first local synchronization status signal (SYNC_DONE) received from the control flip-flop 168, a first timing clock signal received from the reference divider 102, and a global synchronization status signal (SYNC_DONE_FSM).

[0029] In an example, alignment circuitry 164 includes three multiplexers: 164a, 164b, and 164c. Multiplexer 164a selects a division ratio signal indicating an incremented or decremented final division ratio of reference divider 102, i.e., DIV X+1 or DIV X-1, based on the first error flag signal. If the first error flag signal indicates that the second output signal (from non-reference divider 104) leads the first output signal (from reference divider 102), multiplexer 164a selects DIV X-1, and if the first error flag signal indicates that the second output signal lags the first output signal, multiplexer 164a selects DIV X+1. Multiplexer 164b receives the signal output by multiplexer 164a (i.e., DIV X+1 or DIV X-1) and also receives DIV X. Multiplexer 164b selects one of DIV X±1 and DIV X based on the first division ratio slip signal and outputs the selected signal to multiplexer 164c, which also receives as input a signal (DIV A) indicating the final division ratio of non-reference frequency divider 104. Which signal is selected by multiplexer 164c and output to non-reference frequency divider 104 is controlled by a second local synchronization state signal (SYNC_DONE) received from control flip-flop 172, a second timing clock signal received from non-reference frequency divider 104, and a global synchronization state signal (SYNC_DONE_FSM).

[0030] In an example, alignment circuitry 166 includes three multiplexers: 166a, 166b, and 166c. Multiplexer 166a selects DIV X+1 or DIV X-1 based on the second error flag signal. If the second error flag signal indicates that the third output signal (from non-reference divider 106) leads the first output signal (from reference divider 102), multiplexer 166a selects DIV X-1, and if the second error flag signal indicates that the third output signal lags the first output signal, multiplexer 166a selects DIV X+1. Multiplexer 166b receives the signal output by multiplexer 166a (i.e., DIV X+1 or DIV X-1) and also receives DIV X. Multiplexer 166b selects one of DIV X±1 and DIV X based on the second division ratio slip signal and outputs the selected signal to multiplexer 166c, which also receives as input a signal (DIV C) indicating the final division ratio of non-reference frequency divider 106. Which signal is selected by multiplexer 166c and output to non-reference frequency divider 106 is controlled by a third local synchronization state signal (SYNC_DONE) received from control flip-flop 174, a third timing clock signal received from non-reference frequency divider 106, and a global synchronization state signal.

[0031] The example timing alignment circuit 108 further includes a synchronization completion circuit system 176, which is an AND gate in the illustrated example. The AND gate 176 has n-1 inputs that are respectively coupled to the n-1 instances of the detection circuit system. In the illustrated example, the AND gate 176 has two inputs: one input is coupled to the filter 150 of the detection circuit system 138, and the other input is coupled to the filter 160 of the detection circuit system 142. When the second output signal is aligned with the first output signal, the filter 150 outputs a signal indicating such alignment (e.g., a logic high signal) to the AND gate 176, and when the third output signal is aligned with the first output signal, the filter 160 outputs a signal indicating such alignment (e.g., also a logic high signal) to the AND gate 176. When a logic high signal is received from each of the filter 150 and the filter 160, the AND gate 176 outputs a global synchronization state signal to the control flip-flops 168, 172, and 174.

[0032] The example timing alignment circuit 108 further includes n instances of output circuitry, one for each divider in the system 100. In the illustrated example, a first output circuitry 178 is associated with the reference divider 102, a second output circuitry 182 is associated with the non-reference divider 104, and a third output circuitry 184 is associated with the non-reference divider 106.

[0033] The first output circuit system 178 includes an output flip-flop 178a, which is coupled to receive the first output signal and the root clock signal and output the first intermediate output signal. The output flip-flop 178b is coupled to receive the first local synchronization state signal and the first intermediate output signal, and outputs the second intermediate output signal. The AND gate 178c receives the first intermediate output signal and the second intermediate output signal. The output flip-flop 178d is disposed downstream of the AND gate 178c to receive the third intermediate output signal from the AND gate 178c when the first intermediate output signal and the second intermediate output signal are both logic high.

[0034] The second output circuit system 182 is similarly configured, except that the output flip-flop 182a at the front end receives the second output signal, and the output flip-flop 182b receives the second local synchronization state signal. The fourth intermediate output signal and the fifth intermediate output signal are output from the flip-flops 182a and 182b, respectively, and input to the AND gate 182c, which outputs the sixth intermediate output signal when both the fourth intermediate output signal and the fifth intermediate output signal are logic high.

[0035] The third output circuit system 184 is also configured similarly. However, in this case, the output flip-flop 184a receives the third output signal, and the output flip-flop 184b receives the third local synchronization state signal. The seventh intermediate output signal and the eighth intermediate output signal are output from the flip-flops 184a and 184b, respectively, and are input to the AND gate 184c, which outputs the ninth intermediate output signal when both the sixth intermediate output signal and the seventh intermediate output signal are logic high.

[0036] The output signal of flip-flop 178d is at the final division ratio (e.g., DIV B) of reference divider 102. The output signal of flip-flop 182d is at the final division ratio (e.g., DIV A) of non-reference divider 104, and the output signal of flip-flop 184d is at the final division ratio (e.g., DIV C) of non-reference divider 106.

[0037] In an example, the initial division ratio of all dividers in system 100 (e.g., dividers 102, 104, and 106) is the same, namely, DIV X. Using the initial common division ratio, at each iteration, each instance of alignment circuitry 164 and 166 provides a division ratio signal to its corresponding divider 104 or 106, namely, DIV X, DIV X-1, DIV X+1, or its corresponding final division ratio.

[0038] Figure 2 The adjustment of the output signals 202, 204 and 206 of the frequency dividers 102, 104 and 106, respectively, is depicted. The frequency dividers 102, 104 and 106 are started with the same common division ratio and therefore have the same frequency but are out of phase. In the case of normal operation of the frequency dividers 102, 104 and 106, the timing alignment circuit 108 adjusts the phase of the signals 204 and 206 relative to the signal 202. After the rising edges of the output signals 202, 204 and 206 are first aligned, the corresponding Figure 1The SYNC_DONE signal of the global synchronization status signal (SYNC_DONE_FSM) output by AND gate 176 in the clock signal register 106 is asserted as logic high, but the system 100 can be configured to wait one cycle until the next time point when the rising edges are aligned again to switch to the final division ratio. In response to the global synchronization status signal, each of the control flip-flops 168, 172 and 174 outputs its local synchronization status signal to its corresponding divider 102, 104 and 106, and to its corresponding output circuit system 178, 182 and 186. The signals 202, 204 and 206 can then be switched to their final division ratios: DIV B, DIV A and DIV C, respectively. The timing alignment circuit system 108 and the output circuit systems 178, 182 and 186 can be implemented as synchronization logic so that each divider 102, 104 and 106 can deterministically "jump" from one division ratio to another without causing timing glitches and with a fixed delay.

[0039] As described above, timing alignment circuitry 108 may be configured to align all dividers of a system, or may be configured to align only selected dividers within the system. Furthermore, a system to which timing alignment 108 is applied may be a single domain or multiple independent domains, each with multiple dividers.

[0040] Another application of the timing alignment circuitry 108 is the channel environment. Figure 3 A semiconductor chip 300 with m output channels is shown, where m can be 20 (e.g., OUT0 to OUT19). The m channels can be coupled via a tri-state transmit / receive ring bus clock line 302. Different subsets of the m channels can operate under different clock domains. M instances of a frequency divider timing synchronization circuit 304 are placed on the semiconductor chip 300, one instance for each output channel. Each frequency divider timing synchronization circuit 304 is a part of the timing alignment circuit 108. Each frequency divider timing synchronization circuit 304 can be used to align its associated channel output with another channel output used as a reference.

[0041] Figure 4 3 is a schematic diagram of an example frequency division timing synchronization circuit 304, multiple instances of which may be incorporated into semiconductor chip 300. Frequency division timing synchronization circuit 304 includes frequency divider 306. Similar to Figure 1 Each non-reference divider 104, 106 in the frequency divider 306 is associated with a detection circuit system 308, an alignment circuit system 310, a control trigger 312 and an output circuit system 314. The functions of these components are similar to Figure 1 The corresponding counterparts are basically the same.

[0042] The divider 306 has a clock input 316 for a root clock signal (HS_CLK), a clock output 318 at which a timing clock signal (DIV TIMING CLK) for alignment is output, and a data output 320 at which an output signal (DIV OUT) is output. The detection circuit system 308 includes a phase detector 322 having inputs 324 and 326 coupled to the data output 320 and the tri-state ring bus clock line 302, respectively, to receive DIV OUT and a reference divider output signal (DIV REF OUT) received from the tri-state ring bus clock line 302. The phase detector 322 is configured to compare the phases of DIV OUT and DIV REF OUT and output a comparison signal to a filter 328 of the detection circuit system 308. After filtering the comparison signal, the filter 328 outputs an error flag signal indicating whether the phase of DIV OUT leads or lags the phase of DIV REF OUT. Filter 328 also outputs a division ratio slip signal. The error flag signal and the division ratio slip signal are used in the alignment process by alignment circuitry 310, which includes three multiplexers: 310a, 310b, and 310c. The error flag signal controls multiplexer 310a to output one or the other of its two input signals: DIV X+1 and DIV X-1. The division ratio slip signal controls multiplexer 310b to output one or the other of its input signals: the output of multiplexer 310a and DIV X. Multiplexer 310c is controlled by a synchronization state signal (SYNC_DONE) of a control flip-flop 312 to output one or the other of its input signals: the output of multiplexer 310b and DIV A (the final division ratio of divider 306). The control flip-flop 312 receives as input the timing clock signal (DIV TIMING CLK) from the divider 306 and another synchronization status signal (SYNC_DONE_FSM) from the buffer 330 of the divider timing synchronization circuit 304. The buffer 330 receives (SYNC_DONE_FSM) from the filter 328 when it determines that the two divider output signals are aligned and issues SYNC_DONE_FSM after a delay to control the flip-flop 312.

[0043] The output circuit system 314 is configured to be substantially the same as any of the output circuit systems 178, 182, and 184. To this end, the output circuit system 314 includes three flip-flops 314a, 314b, and 314d and an AND gate 314c. The output signal (DIV OUT) of the frequency divider 306 is input to the flip-flop 314a at the front end, and the flip-flop 314d outputs a signal (CHANNEL_OUT) at the final frequency division ratio of the frequency divider 306.

[0044] Figure 5 5 is a flow chart of an example method 500 for aligning the output signals of multiple frequency dividers without resetting any frequency divider. In operation 502, a root (or reference) clock signal is applied to a reference frequency divider and one or more non-reference frequency dividers to allow the frequency dividers to operate normally. In response, each frequency divider outputs an output signal (operation 504). Initially, each frequency divider may have the same frequency division ratio, so each output signal has the same frequency. However, the output signals are out of phase. In order to synchronize the frequency divider output signals, in operation 506, the phase of each non-reference frequency divider output signal is compared with the reference frequency divider output signal. In operation 508, for each comparison, an error flag signal and a frequency division ratio slip signal are generated and output. In operation 510, the error flag signal and the frequency division ratio slip signal generated by a given comparison are used to align a specific edge (e.g., a rising edge) of the non-reference frequency divider output signal of the comparison with a specific edge of the reference frequency divider output signal. In operation 512, the frequency divider is synchronously switched to its final frequency division ratio, thereby ensuring phase alignment. Thus, the dividers are phase aligned, but a synchronous reset does not have to be performed.

[0045] Figure 5 A possible order of operations for aligning the output signals of multiple frequency dividers is depicted. All operations need not be performed in the order described. Two or more operations may be combined into a single operation. Some operations may be performed substantially simultaneously. Additional operations and / or alternative operations may be performed according to the execution herein.

[0046] Provide an example of an adjustable timing alignment circuit that can be used in any of a plurality of clock generation environments to synchronize the output signals of a plurality of frequency dividers or other clock generation components. In some instances, at a specific time, a plurality of frequency divider output signals that are initially operated with the same frequency division ratio are synchronized using one of the frequency dividers as a reference, after which the plurality of frequency dividers are synchronously switched to their final frequency division ratios. Since the delay through the frequency divider is predictable, the timing alignment circuit and the underlying algorithm ensure phase alignment when the frequency divider is changed to its final frequency division ratio. The example timing alignment circuit has the ability to predictably, synchronously, and without glitches update the frequency divider to any final frequency division ratio. The trigger in the system does not need to be reset to achieve synchronization, so that the trigger can operate at the highest speed allowed by the process. The frequency divider can be powered on in any state and then synchronized. The alignment process is relatively fast and can be used multiple times during operation without disconnecting or resetting any component in the system.

[0047] The term "coupled" is used throughout this specification. The term and its derivatives may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then in the first instance, device A is coupled to device B, or in the second instance, if the intermediate component C does not substantially change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal provided by device A, then device A is coupled to device B through the intermediate component C.

[0048] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by the manufacturer at the time of manufacture to perform the function, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through construction and / or layout of the device's hardware components and interconnects, or a combination thereof.

[0049] An "output" identified as part of a component may be a terminal, pin, interconnect, lead, or node of the component to couple the component to another component. Any such component may be a device element, circuit element, integrated circuit, device, or other electronic or semiconductor component.

[0050] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, certain components of the circuit or device may be formed within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to other components to form the described structure at or after manufacture, such as by an end user and / or a third party.

[0051] The circuits described herein may be reconfigured to include replaced components to provide functionality at least partially similar to functionality available prior to component replacement.Components shown as logic gates may be configured in any suitable manner to provide a particular logic function.

[0052] As used herein, the term "divider" includes any component that produces an output signal at a specific division ratio that is switchable to another division ratio. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value.

[0053] Modifications of the described examples are possible, as are other examples, within the scope of the claims.

Claims

1. A timing alignment circuit, comprising: a detection circuit system having input terminals configured to receive a first output signal and a second output signal, respectively, the detection circuit system having an error flag output terminal and a division ratio output terminal, the error flag output terminal being configured to output an error flag signal indicating whether the second output signal leads or lags the first output signal, and the division ratio slip output terminal being configured to output a division ratio slip signal; a control circuit system configured to receive the first local synchronization status signal, the control circuit system having a first control output configured to output a first control signal to the first component; and an alignment circuit system configured to receive the error flag signal and the division ratio slip signal from the detection circuit system, the alignment circuit system further configured to receive a second local synchronization status signal indicating when the first output signal and the second output signal are synchronized, the alignment circuit system having a second control output terminal configured to output a second control signal to a second component.

2. The timing alignment circuit of claim 1 , wherein the detection circuit system comprises: a phase detector having the input terminals configured to receive the first output signal and the second output signal, respectively, the phase detector having a phase comparison output terminal configured to output a phase comparison signal indicating a phase difference between the first output signal and the second output signal; and A filter has an input terminal coupled to the phase comparison output terminal, the filter having the error flag output terminal and the division ratio output terminal.

3. The timing alignment circuit according to claim 1, wherein the control circuit system includes a first multiplexer configured to receive the first local synchronization state signal and having the first control output terminal, the first multiplexer having a first division ratio input terminal configured to receive a first division ratio signal and a second division ratio input terminal configured to receive a second division ratio signal, and the first multiplexer is configured to output the first division ratio signal or the second division ratio signal as the first control signal based on the first local synchronization state signal.

4. The timing alignment circuit of claim 3, wherein the alignment circuit system comprises: a second multiplexer configured to receive the error flag signal from the detection circuitry; a third multiplexer configured to receive the division ratio slip signal from the detection circuitry; and A fourth multiplexer is configured to receive the second local synchronization state signal, the fourth multiplexer having the second control output terminal.

5. The timing alignment circuit of claim 4, wherein: The second multiplexer is configured to increment or decrement the first frequency division ratio signal based on the error flag signal and output an adjusted first frequency division ratio signal; The third multiplexer is configured to output one of the adjusted first division ratio signal and the first division ratio signal based on the division ratio slip signal; and The fourth multiplexer is configured to output one of the output of the second multiplexer and a third division ratio signal as the second control output signal at the second control output terminal based on the second local synchronization state signal.

6. The timing alignment circuit of claim 1, further comprising: a first control flip-flop configured to output the first local synchronization state signal based on a first timing clock signal and a global synchronization state signal; and A second control flip-flop is configured to output the second local synchronization state signal based on a second timing clock signal and the global synchronization state signal.

7. The timing alignment circuit system of claim 1 further comprising: A first output circuit system comprising: a first output flip-flop configured to receive the first output signal and a root clock signal, the first output flip-flop configured to output a first intermediate output signal, and a second output flip-flop configured to receive the first local synchronization state signal and the first intermediate output signal, the second output flip-flop configured to output a second intermediate output signal; and The second output circuit system comprises: a third output flip-flop configured to receive the second output signal and the root clock signal, the third output flip-flop configured to output a third intermediate output signal, and A fourth output flip-flop is configured to receive the second local synchronous state signal and the third intermediate output signal, wherein the fourth flip-flop is configured to output a fourth intermediate output signal.

8. The timing alignment circuit system of claim 7, wherein: The first output circuitry further includes a first logic circuitry configured to receive the first intermediate output signal and the second intermediate output signal and output a fifth intermediate output signal; and The second output circuitry further includes a second logic circuitry configured to receive the third intermediate output signal and the fourth intermediate output signal and to output a sixth intermediate output signal.

9. The timing alignment circuit system of claim 8, wherein: The first output circuit system further includes a fifth output flip-flop configured to receive the root clock signal and output a final output signal of the first frequency divider; and The second output circuit system further includes a sixth output flip-flop configured to receive the root clock signal and output a final output signal of the second frequency divider.

10. The timing alignment circuit system of claim 9, wherein at a set time, a specific edge of the second final output signal of the second component is aligned with a specific edge of the first final output signal of the first component.

11. A system comprising: n frequency dividers, including a reference frequency divider and n-1 non-reference frequency dividers, each of the n frequency dividers being configured to output a data signal, wherein n is an integer of 2 or greater; n-1 instances of detection circuitry, each associated with the n-1 non-reference frequency dividers, each instance of the detection circuitry being configured to determine whether the data signal of the corresponding non-reference frequency divider leads or lags the data signal of the reference frequency divider and to issue a corresponding error signal based on the determination; control circuitry coupled to the reference divider; n-1 instances of alignment circuitry, each configured to align a respective one of the n-1 data signals of the n-1 non-reference dividers with the data signal of the reference divider; and A synchronization completion circuit system is configured to output a global synchronization status signal when each of the data signals of the n-1 non-reference frequency dividers is aligned with the data signal of the reference frequency divider.

12. The system of claim 11, further comprising: n control triggers, including: a reference control flip-flop coupled to the reference divider and the control circuitry, and n-1 non-reference flip-flops each coupled to a respective one of the n-1 non-reference dividers and a respective one of the n-1 instances of the alignment circuitry.

13. The system of claim 12, wherein each of the n-1 instances of the detection circuitry comprises: a phase detector configured to receive the data signal output by the corresponding non-reference frequency divider and the data signal output by the reference frequency divider, and further configured to output a phase comparison signal; and A filter is configured to receive the phase comparison signal output by the associated phase detector and is further configured to output an error flag signal and a division ratio slip signal to the corresponding alignment circuit system.

14. The system of claim 13, further comprising: n instances of output circuitry comprising: reference output circuitry configured to receive the data signal of the reference divider, and n-1 instances of non-reference output circuitry each configured to receive the data signal of a corresponding one of the non-reference dividers.

15. A method comprising: applying a root clock signal to a reference divider and a non-reference divider; The reference frequency divider outputs a first output signal with a first initial frequency division ratio; Outputting a second output signal by the non-reference frequency divider with a second initial frequency division ratio; comparing the phases of the first output signal and the second output signal using phase detection circuitry; The phase detection circuit system outputs an error flag signal indicating whether the second output signal leads or lags behind the first output signal, and also outputs a frequency division ratio slip signal; and The second output signal is adjusted based on the error flag signal and the division ratio slip signal to align a specific edge of the second output signal with a specific edge of the first output signal. 16 . The method of claim 15 , wherein each of the first initial frequency division ratio and the second initial frequency division ratio are the same.

17. The method of claim 16, further comprising: After the adjustment is completed, the first initial frequency division ratio of the first output signal is switched to a first final frequency division ratio, and the second initial frequency division ratio of the second output signal is switched to a second final frequency division ratio.

18. The method of claim 17, wherein the adjusting comprises: performing a first selection operation of selecting one of an increasing first initial frequency division ratio or a decreasing first initial frequency division ratio as a first intermediate frequency division ratio based on the error flag signal; performing a second selection operation of selecting one of the first intermediate frequency division ratio and the first initial frequency division ratio as a second intermediate frequency division ratio based on the frequency division ratio slip signal; performing a third selection operation of selecting one of the second intermediate frequency division ratio and the second final frequency division ratio as a non-reference frequency divider control signal based on a non-reference frequency divider local synchronization state signal; and The non-reference divider control signal is input to the non-reference divider.

19. The method of claim 18, further comprising: performing a fourth selection process of selecting one of the first initial frequency division ratio and the first final ratio as a reference frequency divider control signal based on a reference frequency divider local synchronization state signal; and The reference divider control signal is input to the reference divider.

20. The method of claim 19, wherein: The non-reference divider local synchronization status signal is based on the global synchronization status signal and a timing signal from the non-reference divider, and The reference divider local synchronization status signal is based on the global synchronization status signal and a timing signal from the reference divider.

21. A system comprising: m output channels, where m is an integer of 3 or greater; a ring bus clock line coupling the m output channels; and m instances of component timing circuitry, respectively coupled to the m output channels; Each of the m instances of the component timing circuitry comprises: a component configured to output a component output signal; A detection circuit system is configured to: receiving the component output signal and a reference output signal, and determining whether the component output signal leads or lags the reference output signal; A control circuit system configured to: receiving a timing clock signal from said component, and receiving a first alignment status signal from the detection circuitry; and Alignment circuitry is configured to align the component output signal with the reference output signal based on a signal received from the detection circuitry and a second alignment status signal received from the control circuitry.

22. The system of claim 21, wherein each of the m instances of the component timing circuitry comprises output circuitry coupled to the component.

23. The system of claim 21, wherein each of the m instances of the component timing circuitry comprises a buffer coupled between the detection circuitry and the control circuitry to communicate the first alignment status signal to the control circuitry.

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