Managing conductive connections for semiconductor devices

Abstract

Systems, apparatuses, and methods for managing electrically conductive connections of semiconductor devices are provided. In one aspect, a method includes providing an integrated structure including an array structure in a first region and a conductive connection structure in a second region adjacent to the first region, at least a portion of at least one polysilicon layer over the conductive connection structure; etching at least a portion of the at least one polysilicon layer to expose one or more conductive connections in the conductive connection structure; depositing an isolation material on the array structure and the conductive connection structure; and forming a conductive vertical interconnect via (via) through the isolation material to contact the one or more conductive connections and the conductive layer in the array structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. Background Art

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because they can increase array density by stacking more layers within a similar footprint. However, as more layers are stacked in the same area, managing conductive connections between different components and / or with external devices or components can be challenging. Summary of the invention

[0003] The present disclosure describes methods, apparatus, systems, and techniques for managing conductive connections of semiconductor devices (eg, 3D memory devices).

[0004] One aspect of the present disclosure is characterized by a method comprising: providing an integrated structure comprising an array structure in a first region and a conductive connection structure in a second region adjacent to the first region, at least a portion of at least one polysilicon layer being above the conductive connection structure; etching at least a portion of at least one polysilicon layer to expose one or more conductive connections in the conductive connection structure; depositing an isolation material over the array structure and the conductive connection structure; and forming a conductive vertical interconnect path (via) through the isolation material to contact the one or more conductive connections and the conductive layer in the array structure.

[0005] In some embodiments, forming a conductive via includes: etching an isolation material to expose one or more conductive connections in a conductive connection structure and a portion of a conductive layer in an array structure; and depositing a conductive material on one or more conductive connections in the conductive connection structure and a portion of a conductive layer in the array structure to form the conductive via, wherein each conductive via is coupled to a corresponding one of the one or more conductive connections and the portion of the conductive layer.

[0006] In some embodiments, one or more conductive connections in the conductive connection structure and a portion of the conductive layer in the array structure are exposed together during etching of the isolation material.

[0007] In some embodiments, the method further includes: depositing a conductive pad layer on the conductive via; depositing at least one covering layer above the conductive pad layer; and forming one or more pad openings through the at least one covering layer to expose one or more corresponding portions of the conductive pad layer.

[0008] In some embodiments, the method further comprises depositing a dielectric layer on the conductive pad layer, the dielectric layer being between the conductive pad layer and the at least one cover layer. Forming one or more pad openings may comprise etching through the at least one cover layer and the dielectric layer to form corresponding pad openings.

[0009] In some embodiments, the conductive pad layer includes a first conductive material, and the conductive via includes a second conductive material different from the first conductive material.

[0010] In some embodiments, the conductive via and the conductive pad layer are formed in the same process by depositing the same conductive material.

[0011] In some embodiments, at least one polysilicon layer includes a plurality of portions, and at least one portion of the at least one polysilicon layer is a first portion of the at least one polysilicon layer, and a second portion of the at least one polysilicon layer is above the array structure. Providing the integrated structure may include: etching the second portion of the at least one polysilicon layer to expose a plurality of memory cell strings in the array structure and gate lines between adjacent string groups; and forming a conductive layer across the first region, wherein the conductive layer contacts end surfaces of the plurality of memory cell strings and the gate lines.

[0012] In some embodiments, end surfaces of the plurality of memory cell strings and the gate lines form a flat surface. In some embodiments, end surfaces of the plurality of memory cell strings and the gate lines form an uneven surface.

[0013] In some embodiments, forming the conductive via includes forming a conductive via through the isolation material to contact a portion of the conductive layer above the gate line.

[0014] In some embodiments, etching at least a portion of at least one polysilicon layer includes: etching all of at least a portion of at least one polysilicon layer within the etching region. The first region and the second region may be arranged along a first direction, and one or more conductive connections may extend along a second direction perpendicular to the first direction. The etching region may have a first edge and a second edge opposite to each other along the first direction, the first edge being able to extend to an edge of a plane of the integrated structure, and the second edge being able to extend to an edge of the second region. The etching region may have an etching depth from a top surface to a bottom surface along the second direction, and a distance between a top surface of the etching region and an end surface of each of one or more conductive connections in the conductive connection structure is not greater than the etching depth. The etching depth may be determined based on an etching time.

[0015] In some embodiments, depositing the isolation material on the array structure and the conductive connection structure includes: depositing the isolation material between adjacent conductive connections in the conductive connection structure and on the conductive layer in the array structure. The method may also include: after depositing the isolation material on the array structure and the conductive connection structure, polishing the surface of the deposited isolation material.

[0016] In some embodiments, the isolation material includes tetraethyl orthosilicate (TEOS), and depositing the isolation material may include performing boundary field oxide (BFOX) isolation.

[0017] Another aspect of the disclosure features a semiconductor device that includes: an array structure including a conductive layer coupled to a plurality of memory cell strings; a conductive connection structure disposed separately from the array structure, the conductive connection structure including a plurality of conductive connections; and a conductive pad layer disposed above the array structure and the conductive connection structure, the conductive pad layer including a plurality of conductive pads coupled to portions of the conductive layer and each of the plurality of conductive connections through corresponding conductive vias. The plurality of conductive connections are separated by an isolation material filled in the conductive connection structure.

[0018] In some embodiments, the corresponding conductive vias are separated and isolated by an isolation material filled between the conductive pad layer, the array structure, and the conductive connection structure.

[0019] In some embodiments, there is no conductive material between the conductive connection structure and the array structure. In some embodiments, there is no conductive material between the plurality of conductive connections in the conductive connection structure.

[0020] In some embodiments, a connection angle between the conductive pad layer and at least one of the corresponding conductive vias is about 90 degrees.

[0021] In some embodiments, the array structure and the conductive connection structure are integrated in a first die. The semiconductor device may also include a second die integrated with the first die, and at least one of the plurality of conductive connections may be coupled to a control circuit in the second die.

[0022] In some embodiments, the semiconductor device further comprises a cover layer on top of the conductive pad layer. The cover layer may include a plurality of pad openings on top of a plurality of conductive pads in the conductive pad layer, and each of the plurality of conductive pads may be coupled to at least one of the corresponding conductive vias.

[0023] Another aspect of the present disclosure is characterized by a system including a memory device and a controller coupled to the memory device and configured to control the memory device. The memory device includes: an array structure including a conductive layer coupled to a plurality of memory cell strings; a conductive connection structure disposed separately from the array structure, the conductive connection structure including a plurality of conductive connections, the plurality of conductive connections being separated by an isolation material filled in the conductive connection structure; and a conductive pad layer disposed above the array structure and the conductive connection structure, the conductive pad layer including a plurality of conductive pads, the plurality of conductive pads being coupled to a portion of the conductive layer and each of the plurality of conductive connections through corresponding conductive vias.

[0024] In some embodiments, the memory device further comprises: a plurality of conductive interconnects passing through the cover layer on top of the conductive pad layer to contact a plurality of conductive pads in the conductive pad layer, and each of the plurality of conductive pads is coupled to at least one of the corresponding conductive vias. The controller may be coupled to the memory device through at least one of the plurality of conductive interconnects.

[0025] Implementations of the present disclosure may provide one or more of the following technical advantages and / or benefits. For example, in some implementations, as one or more final steps in forming a 3D memory device, a 3D memory array and peripheral circuits are conductively coupled to conductive pads for external coupling to external components or devices. The techniques implemented herein can manage the conductive connections of a 3D memory device to simplify processing steps, improve etching calibration accuracy, reduce the number of machines to be used, and reduce manufacturing costs. For example, compared to conventional methods, the technology can omit multiple process steps (e.g., atomic layer deposition (ALD), oxide deposition, metal removal, etching of through-surface contacts (TSC)), which can speed up the manufacturing process, save manufacturing costs, and improve manufacturing accuracy and yield.

[0026] In some embodiments, for example, the bottom polysilicon is pre-removed from the top of the conductive connection structure and the array structure, so that the conductive connection structure and the array structure can be processed using the same mask for patterning and / or deposition to form conductive vias and conductive pads together. In addition, when the bottom polysilicon is removed, there can be no leakage between the conductive connection and silicon (Si) in the conductive connection structure, which can eliminate through-substrate contact (TSC)-Si leakage and burnout problems. In addition, processing the conductive connection structure and the array structure together increases the processing window. Therefore, the technology can increase reliability, simplify manufacturing processes, improve pad coupling input / output (I / O), reduce manufacturing costs, and improve the performance of semiconductor devices and systems.

[0027] In some embodiments, for example, after the gate-induced drain leakage (GIDL) loop process is completed, the bottom polysilicon is directly removed using a buried shallow trench isolation (BSTI) etching process to open the conductive connection, which has low requirements for exposure accuracy in patterning and / or etching, and does not require the backside deep trench ring (BDTI) to be performed for isolation. Therefore, this technology can greatly release or increase the processing window and improve pad coupling input / output. Since the process does not require BDTI isolation, there is no tungsten (W) residual problem, which can reduce W depression.

[0028] In some embodiments, due to the small aspect ratio of BSTI, TEOS can be used to fill the open area and replace the ALD process, and no etching back and removal of Ti residues are required, which can significantly reduce costs and cycle time. In some embodiments, a metal such as tungsten W can be filled in the trench to form a conductive via, and aluminum (Al) can be easily deposited on the conductive via to form a conductive pad.

[0029] The details of one or more embodiments of the subject matter of the present disclosure are set forth in the accompanying drawings and the detailed description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings, which are incorporated herein and form a part of the present disclosure, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable one of ordinary skill in the relevant art to make and use the present disclosure.

[0031] Figure 1 A cross-sectional view of a semiconductor device according to one or more embodiments of the present disclosure is shown.

[0032] Figure 2 is a flow chart of an example process for forming a semiconductor device according to one or more embodiments of the present disclosure.

[0033] Figures 3A-3G Cross-sectional views of the structure of a semiconductor device at various stages of a manufacturing process are shown according to one or more embodiments of the present disclosure.

[0034] Figure 4 A block diagram of an example system having one or more semiconductor devices according to one or more embodiments of the present disclosure is shown.

[0035] Like reference numbers and designations in the various drawings indicate like elements.It should also be understood that the various exemplary embodiments shown in the drawings are merely illustrative representations and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0036] Figure 1 A cross-sectional view of a semiconductor device 100 according to one or more embodiments of the present disclosure is shown. In some embodiments, the semiconductor device 100 is a 3D memory device (e.g., a NAND flash memory device). In some embodiments, the semiconductor device 100 is an intermediate structure, and one or more post-processing steps can be performed on the intermediate structure to form a 3D memory device. The semiconductor device 100 can be formed, for example, as in Figure 2 and Figures 3A-3G Note that for illustration purposes, Figure 1 The present invention includes two cross-sectional views of a semiconductor device 100 in FIG. (a) and FIG. (b), respectively. FIG. (a) shows a cross-sectional view of the semiconductor device 100 in an XZ plane, and FIG. (b) shows a cross-sectional view of the semiconductor device 100 in a YZ plane. Figure 1 Separated by a dotted line.

[0037] In some embodiments, Figure 1 As shown in , the semiconductor device 100 includes two dies 110 and 120, which are bonded face-to-face, for example, with a bonding layer 102 therebetween. In the semiconductor device 100, the die 120 includes an array structure 130 having an array of memory cells, which may be referred to as the array die 120, and the die 110 includes a peripheral circuit (or control circuit) 114, which may be referred to as the peripheral die 110. The array structure 130 may be formed on the front side of the array die 120, and the peripheral circuit 114 may be formed on the front side of the die 110. The array structure 130 and the peripheral circuit 114 may be conductively coupled to each other through a conductive bonding pad 104 (e.g., made of a conductive material such as a metal) in the bonding layer 102. In some examples, the peripheral circuit 114 is formed using complementary metal oxide semiconductor (CMOS) technology, and the peripheral die 110 is also referred to as a CMOS die 110.

[0038] In some embodiments, the semiconductor device may include a plurality of array dies (e.g., array die 120) and a CMOS die (e.g., CMOS die 110). The plurality of array dies and CMOS die may be stacked and bonded together. The CMOS die may be coupled to each of the plurality of array dies, respectively, and each of the plurality of array dies may be driven to operate in a manner similar to the semiconductor device 100, respectively. The semiconductor device 100 may be any suitable device. In some examples, the semiconductor device 100 includes at least a first wafer and a second wafer bonded face to face. The array die 120 may be disposed on a first wafer together with other array dies, and the CMOS die 110 may be disposed on a second wafer together with other CMOS dies. The first wafer and the second wafer may be bonded together, so that the array die on the first wafer may be bonded to the corresponding CMOS die on the second wafer. In some examples, the semiconductor device 100 is a chip having at least the array die 120 and the CMOS die 110 bonded together. In an example, the chip is cut from the bonded wafers. In another example, the semiconductor device 100 is a semiconductor package including one or more semiconductor chips assembled on a package substrate.

[0039] In some embodiments, the CMOS die 110 includes a substrate 112, and the peripheral circuit 114 is formed on the substrate 112. The substrate 112 can be any suitable semiconductor substrate having any suitable semiconductor material (e.g., a single crystal, a polycrystalline, or a single crystal semiconductor). For example, the substrate 112 can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon on insulator (SOI), germanium on insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. The substrate 112 can be a bulk wafer or an epitaxial layer. For simplicity, the main surface of the substrate 112 is referred to as the XY plane, and the direction perpendicular to the main surface is referred to as the Z direction. The peripheral circuit 114 can include one or more logic and / or circuits, including address decoding circuits, page buffer circuits or sense amplifiers, data buffers, data I / O circuits, voltage generators, control logic, etc.

[0040] In some embodiments, the array die 120 includes: a) an array structure 130 and a connection structure 140 in a first region 101; and b) a conductive connection structure 150 in a second region 103. The second region 103 may also be referred to as a connection region, where one or more conductive connections are arranged to connect the array structure 130 and / or the connection structure 140 to the peripheral circuit 114 and / or external components, circuits, and / or devices. The array structure 130 is adjacent to the connection structure 140 in the first region 101. For example, the connection structure 140 may be an extension of the array structure 130. The first region 101 and the second region 103 may be adjacent to each other, for example, Figure 1 The boundary 141 of the connection structure 140 may be considered as the boundary of the first region 101 and / or the boundary of the second region 103 .

[0041] The array structure 130, the connection structure 140 and the conductive connection structure 150 may be formed in a substrate, for example, as Figure 3A The substrate may be a semiconductor substrate, for example, similar or identical to substrate 112. During the formation of semiconductor device 100, the substrate may be thinned and at least partially removed. For example, connection structure 140 may include remaining portion 144 of the substrate.

[0042] like Figure 1 As shown in , the array structure 130 may include a plurality of vertical memory cell strings 136 along the Z direction, such as 3D NAND memory cell strings. The array structure 130 may also include a plurality of alternating pairs of conductive layers (or word lines) 132 and isolation layers 134. The conductive layer 132 may include a metal material, such as tungsten W, and the isolation layer 134 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The vertical memory cell string 136 passes through the conductive layer 132 and the isolation layer 134 to connect to the corresponding bit line 131. The vertical memory cell string 136 may include any one of an insulator / trap or a trap / insulator combination or only polysilicon or any one of a polysilicon / insulator combination in a vertical channel along the Z direction. In some examples, the vertical memory cell string 136 includes a multilayer OX / SIN / OX(ONO) 136a that may be formed on the inner surface of the vertical channel and a polysilicon 136b that may be filled in the middle of the vertical channel. The outer surface of the vertical channel contacts a conductive layer 132 , which acts as the gates of the memory cells of a vertical string of memory cells 136 .

[0043] In some embodiments, the array structure 130 includes a gate line 133 among a plurality of vertical memory cell strings 136. The gate line 133 is configured to separate adjacent memory blocks. During the formation of the array structure 130, the gate line 133 can be used as a channel for etching a sacrificial layer and for filling a conductive material to form a conductive layer 132. In some embodiments, for example, Figure 1 As shown, the gate line 133 has a size (e.g., diameter or width) that is larger than the size (e.g., diameter or width) of the memory cell string 136. The array structure 130 may also include a conductive layer 135 formed on top of the end surfaces of the plurality of vertical memory cell strings 136 and the gate line 133, for example as a common source line (CSL). The common source line may be conductively coupled to an external device (e.g., an external power supply or an external control signal), for example, through corresponding conductive vias 154c and corresponding conductive pads 164c. The conductive layer 135 may be made of polysilicon or metal. A protective layer 137 may be formed on the conductive layer 135. The protective layer 137 may include an isolation material, such as a dielectric material (e.g., silicon nitride or oxide).

[0044] In some embodiments, for example, Figure 1 As shown in , the end surfaces of the plurality of vertical memory cell strings 136 and the gate line 133 form an uneven surface, for example, the end surface of the gate line 133 may be lower than the end surface of the plurality of vertical memory cell strings 136. Since the gate line 133 may have a larger size than the vertical memory cell string 136, the end surface of the gate line 133 may have a larger area than the end surface of the vertical memory cell string 136. Therefore, the conductive via 154c may be formed on a portion of the conductive layer 135 on top of the end surface of the gate line 133, which is easier to pattern and deposit to form the conductive via 154c, for example, as described with respect to Figure 3E-3F In some embodiments, the end surfaces of the plurality of vertical memory cell strings 136 and the gate line 133 form a flat surface. For example, a conductive material layer may be deposited on the end surfaces of the plurality of vertical memory cell strings 136 and the end surfaces of the gate line 133, and then, for example, Figure 1 The conductive material layer is polished to become a flat surface on the uneven surface shown in FIG. The polished conductive material layer forms the conductive layer 135. In this case, the conductive via 154c may be formed on any portion of the conductive layer 135 on the flat surface.

[0045] The connection structure 140 is used to facilitate conductive connections to, for example, the gates of the memory cells in the vertical memory cell string 136, the gates of the selected transistors, etc. The gates of the memory cells in the vertical memory cell string 136 correspond to the word lines of the NAND memory architecture. The connection structure 140 is configured to conductively connect the conductive layer 132 (or word lines) to corresponding contact pads (e.g., on the bottom of the connection structure), for example, through array contacts (TACs) and / or step contacts (SCTs), and further connect to control circuits (e.g., peripheral circuits 114 in the CMOS die 110), for example, through conductive bonding pads 104.

[0046] In some embodiments, the connection structure 140 includes a channel structure 142. The channel structure 142 may be in the shape of a cylinder or a column. The channel structure 142 may have the same structure as the vertical memory cell string 136, and the channel structure 142 and the vertical memory cell string 136 may be formed in the same process. In some examples, the channel structure 142 includes a multilayer OX / SIN / OX (ONO) that may be formed on the inner surface of the vertical channel and polysilicon that may be filled in the middle of the vertical channel. The channel structure 142 may be a stop line, and no metal layer is connected to the channel structure 142.

[0047] In some embodiments, the array die 120 is configured to include one or more back metal layers on the back side of the array die 120. The back metal layer can be used to provide pad structures and / or routing paths. Figure 1 As shown in , the array die 120 includes a pad layer 160 having a plurality of conductive pads 164a, 164b, 164c (collectively referred to as conductive pads 164 and individually referred to as conductive pads 164). The conductive pads 164 may be separated by an isolation material 122 (e.g., oxide) in the pad layer 160. The conductive pads 164 may be formed to facilitate the attachment of a bonding wire that may conductively couple the conductive pads 164 to an external component or device (e.g., a power source, a ground, other semiconductor devices, a metal line on a printed circuit board (PCB), etc.).

[0048] In some embodiments, for example, Figure 1 As shown in , the array die 120 includes one or more cover layers, such as an isolation layer 162, a dielectric layer 170 (e.g., made of silicon nitride), and a protective layer 172 on top of a pad layer 160. A plurality of pad openings 174 may be formed through the one or more cover layers so that the conductive pads 164 may be coupled to external components through the pad openings 174 via bonding wires.

[0049] As mentioned above, in the second region 103 of the array die 120, the conductive connection structure 150 includes a plurality of conductive connections 152a, 152b (collectively referred to as conductive connections 152 and individually referred to as conductive connections 152) configured to be conductively coupled to the peripheral circuit 114 (e.g., via the bonding conductive pads 104) and / or to the conductive layer 132 in the array structure 130 (e.g., via the connection structure 140). Figure 1 As shown in , the conductive connection 152 may be through a substrate contact (TSC). The conductive connections 152a, 152b may be coupled to corresponding conductive pads 164a, 164b through corresponding conductive vias 154a, 154b in the second region 103. The conductive vias 154a, 154b, 154c may be collectively referred to as conductive vias 154 and individually referred to as conductive vias 154. The conductive vias 154a, 154b in the second region 103 and the conductive via 154c in the first region 101 may be formed using the same process steps, for example, as shown in FIG. Figure 3D-3F As discussed in further detail below, the bottom polysilicon can be removed from the second region 103, and a large process window can be obtained for forming the conductive via 154. In some embodiments, the connection angle between the conductive pad 164 and the conductive via 154 is about 90 degrees.

[0050] In some embodiments, the conductive via 154 and the conductive pad 164 are made of different materials, for example, the conductive via 154 can be made of tungsten (W), and the conductive pad 164 can be made of aluminum (Al). The conductive via 154 and the conductive pad 164 can be formed in different process steps. In some embodiments, the conductive via 154 and the conductive pad 164 are made of the same material, such as W, Al, or any suitable conductive material, and the conductive via 154 and the conductive pad 164 can be formed in the same process step.

[0051] The array die 120 includes an isolation material 122 filled in different components. For example, the conductive vias 154 are separated and isolated by the isolation material 122 filled between the conductive pad layer 160, the array structure 130, and the conductive connection structure 150. There may be no conductive material between the conductive connection structure 150 and the array structure 130. There may be no conductive material between the conductive connections 152 in the conductive connection structure 150.

[0052] Figure 2 A semiconductor device (eg, Figure 1 Flowchart of an example process 200 of a semiconductor device 100). Figures 3A-3G The following diagram shows a process (e.g., Figure 2The process 200 includes steps of: Figure 1 100) is a cross-sectional view of the structure of a semiconductor device 100). Figures 3A-3G The structure shown in FIG. 200 describes the process. Note that similar to Figure 1 , for illustration purposes, Figures 3A-3G Each of the diagrams includes two cross-sectional views of the corresponding structure in diagrams (a) and (b), respectively. Diagram (a) shows a cross-sectional view of the corresponding structure in the XZ plane, while diagram (b) shows a cross-sectional view of the corresponding structure in the YZ plane. Figures 3A-3G In each of , the two figures (a) and (b) are separated by a dotted line.

[0053] At step 202, an integrated structure is provided. The integrated structure may include an array structure in a first region and a conductive connection structure in a second region adjacent to the first region.

[0054] For example, Figure 3A As shown in FIG. , the peripheral die 310 (eg, Figure 1 The peripheral die 110) and the array die 320 (eg, Figure 1 The bonding layer 302 (eg, Figure 1 The peripheral die 310 and the array die 320 are bonded to form an integrated structure 300a by bonding the peripheral die 310 with the array die 320 using the bonding layer 102 of the substrate 302. The bonding layer 302 may include a plurality of conductive bonding pads 304. The peripheral die 310 may be a CMOS die and may include a substrate 312 (eg, Figure 1 The peripheral circuit 314 (eg, Figure 1 Peripheral circuit 114).

[0055] Similar to Figure 1 The array die 120, the array die 320 may include: a) a first region 301 (eg, Figure 1 The array structure 330 (eg, Figure 1 Array structure 130) and connection structure 340 (e.g., Figure 1 and b) a second region 303 (eg, Figure 1 The conductive connection structure 350 (eg, Figure 1 The connection structure 340 is adjacent to the array structure 330 and may be an extension of the array structure 330. The second region 303 utilizes a boundary 341 (eg, Figure 1 The boundary 141) is adjacent to the first area 303.

[0056] Array structure 330, connection structure 340 and conductive connection structure 350 can be formed in a substrate similar to substrate 312, for example. The substrate can be any suitable semiconductor substrate having any suitable semiconductor material (such as a single crystal, polycrystalline or single crystal semiconductor). For example, the substrate can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon on insulator (SOI), germanium on insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some examples, the substrate includes polycrystalline silicon. The substrate can be thinned from the back of the substrate. The thinned substrate can include a bottom polycrystalline silicon layer 324. One or more layers, such as an isolation layer 326 (e.g., made of a dielectric material such as an oxide) and a protective layer 328 can be formed on top of the bottom polycrystalline silicon layer 324.

[0057] Similar to Figure 1 The array structure 130 includes a plurality of alternating conductive layers 332 (eg, Figure 1 Conductive layer 132) and isolation layer 334 (eg, Figure 1 The array structure 330 also includes a pair of conductive layers 332 and isolation layers 334 extending through the conductive layer 332 and isolation layer 334 to couple to the bit line 331 (eg, Figure 1 A plurality of vertical memory cell strings 336 (eg, Figure 1 Each vertical memory cell string 336 may include a multi-layer OX / SIN / OX(ONO) 336a (eg, Figure 1 ONO 136a) and polysilicon 336b (e.g., Figure 1 The array structure 330 may further include a gate line 333 (eg, Figure 1 The connection structure 340 may include a conductive connection coupled to the conductive layer 332, for example, through an array contact (TAC) and a conductive pad. The connection structure 340 may include a channel structure 342 (e.g., Figure 1 Channel structure 142).

[0058] The conductive connection structure 350 is located in the second region 303, which may also be referred to as a connection region or a peripheral region. The conductive connection structure 350 includes a plurality of conductive connections 352a, 352b (collectively referred to as conductive connections 352 and individually referred to as conductive connections 352). The conductive connections 352 may be, for example, Figure 1Conductive connections 352 of the embodiment of the present invention. Conductive connections 352 may be separated and isolated by isolation material 322 (e.g., oxide). Conductive connections 352 may be conductively coupled to conductive layer 332 in array structure 340 and / or connection structure 340, and coupled to peripheral circuit 314 in peripheral die 310.

[0059] In some embodiments, at step 202, an integrated structure 300a is provided, and a bottom polysilicon layer 324 is located above both the conductive connection structure 350 and the array structure 330. To form a common source line on the array structure 330, the protective layer 328 is first removed, and then a first portion of the bottom polysilicon layer 324 and the isolation layer 326 on the top of the array structure 330 is etched away to expose, for example, a plurality of vertical memory cell strings 336 on one side of the stop line 342 along the X direction. On the other side of the stop line 342, a second portion of the bottom polysilicon layer 324 and the isolation layer 326 on the conductive connection structure 350 in the second region 303 and on at least a portion of the connection structure 340 remains unchanged or is not etched. Figure 3B As shown in FIG. 3 , a conductive layer (eg, a source polysilicon layer) 335 may be deposited across the first region 301 and / or the second region 303 to form an integrated structure 300 b. The conductive layer 335 may be Figure 1 The conductive layer 135 of the vertical memory cell string 336 may contact the end surfaces of the plurality of vertical memory cell strings 336 and the gate line 333. In some embodiments, the end portions of the vertical memory cell strings 336 (e.g., on the back side of the array die 320 away from the peripheral die 310) are etched to expose the polysilicon layer 336b of the vertical memory cell string 336 so that the conductive layer 335 contacts the polysilicon layer 336 in the vertical memory string 336. The end portions of the vertical memory cell string 336 may include an ONO layer 336a.

[0060] In some embodiments, at step 202, providing Figure 3B The integrated structure 300 b shown in FIG. 1 , wherein a first portion of the bottom polysilicon layer 324 is above the conductive connection structure 350 but not above the array structure 330 .

[0061] At step 204 , at least a portion of at least one polysilicon layer (eg, a first portion of bottom polysilicon layer 324 ) is etched to expose one or more conductive connections (eg, conductive connection 352 ) in conductive connection structures (eg, conductive connection structures 350 ).

[0062] In order to protect the array structure 330 and the connection structure 340 from being etched, a protection layer 337 (eg, a protective film 337) is first deposited on top of the array structure 330 and the connection structure 340 in the first region 301 (eg, on top of the conductive layer 335). Figure 1protective layer 137). Figure 3C As shown in the structure 300c of FIG. 300c, all of the first portion of the polysilicon layer 324 within the etched region 327 is etched away to expose the end surfaces of the conductive connections 352a, 352b. The etched region 327 may have first and second opposite edges X1, X2 along the x-direction. The first edge X1 may extend to the edge of the plane of the semiconductor device, and the second edge X2 may extend to the edge of the second region 303, such as the boundary 341. The etched region 327 may have an etch depth from the top surface Y1 to the bottom surface Y2 along the z-direction. The top surface Y1 may be at the same level as the top surface of the connection structure 340 having the conductive layer 335 and the protective layer 337. The bottom surface Y2 may be at the same level as the end surfaces of the conductive connections 352a, 352b or lower than the end surfaces of the conductive connections 352a, 352b, so that the conductive connections 352s, 352b may be exposed for connection. The distance between the top surface Y1 of the etched region 303 and the end surface of each of the conductive connections 352a, 352b in the conductive connection structure 350 is not greater than the etching depth. The etching depth may be determined based on the etching time.

[0063] The etching process at step 204 may be performed using a buried shallow trench isolation (BSTI) process to remove the bottom polysilicon layer 324 and the conductive layer 335 (e.g., a source polysilicon layer) in the second region 303. The etching process may be performed by dry etching (e.g., vapor phase etching, reactive ion etching (RIE), or plasma etching). The etching process has low requirements for exposure accuracy in patterning and / or etching, and does not require the performance of a backside deep trench ring (BDTI) for isolation, which may greatly free up or increase the process window. This may also enable the formation of conductive vias for coupling to conductive pads for input / output, such as Figure 3D-3G As shown in detail in .

[0064] At step 206, an insulating spacer is deposited on the array structure (eg, array structure 330) and the conductive connection structure (eg, conductive connection structure 350). Figure 3D As shown in FIG. 3 , an isolation material 327 is formed on the structure 300 c to obtain a structure 300 d , wherein the isolation material 327 may be filled between adjacent conductive connections 352 a , 352 b in the conductive connection structure 350 and over the conductive layer 335 on the array structure 330 .

[0065] In some embodiments, isolation material 327 includes an oxide, which can be deposited by any suitable deposition method, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). In some embodiments, since BSTI has a small depth-to-width ratio, isolation material 327 can include tetraethyl orthosilicate (TEOS). TEOS can be deposited by a boundary field oxide (BFOX) isolation process, which can replace other deposition methods such as ALD without the need for etch-back and removal of residues (e.g., Ti), thereby reducing manufacturing costs and cycle time.

[0066] After depositing the isolation material 327 over the array structure 330 and the conductive connection structure 350 , the surface of the deposited isolation material 327 or the surface of the structure 300 d may be polished, for example, using chemical mechanical polishing (CMP) or planarization to smooth the surface of the structure 300 d .

[0067] At step 208, conductive vias are formed through the isolation material to contact one or more conductive connections and conductive layers in the array structure.

[0068] When the bottom polysilicon layer 324 on the conductive connection structure 350 and the array structure 330 is removed, the isolation material 327 is deposited on the array structure 330 and the conductive connection structure 350 (eg, Figure 3D ), the materials to be etched (e.g., isolation material 327) in the conductive connection structure 350 and the array structure 330 are the same. Therefore, the conductive connection structure 350 and the array structure 330 can be processed together in the same process for patterning using the same mask to form conductive vias, which can greatly increase the processing window. In addition, there is no leakage between the conductive connection 352 and the silicon.

[0069] For example, Figure 3EAs shown in the structure 300e of , the deposited isolation material 327 can be patterned and removed using the same mask to form trenches 329a, 329b, 329c (collectively referred to as trenches 329 and individually referred to as trenches 329) in the same etching process to expose the conductive connections 352a, 352b in the conductive connection structure 350 and a portion of the conductive layer 335 together, for example, in the same etching step. This portion of the conductive layer 335 can be on top of the gate line 333 or any other suitable position in the array structure 330. The size of the trench 329c can be smaller than, equal to, or larger than the size of the end surface of the gate line 333. The size of the trench 329c is controlled to be smaller than the spacing between adjacent vertical memory cell strings 336 so that the vertical memory cell strings 336 are not exposed. Note that a portion of the protective layer 337 on the portion of the conductive layer 335 is also etched away to expose the portion of the conductive layer 335. The etching step can be performed, for example, by wet etching. The etching depth can be controlled, for example, by time, to expose the conductive connections 352a, 352b. Figure 3E As shown in , the bottom surfaces of grooves 329a, 329b can be at the same level or lower than the end surfaces of conductive connections 352a, 352b, and the bottom surface of groove 329c can be, for example, the top surface of conductive layer 335 on gate line 333.

[0070] Then, conductive material is deposited in the trench 329 and on the conductive connections 352a, 352b in the conductive connection structure 350 and on the portion of the conductive layer 335 in the array structure 330 on the gate line 333 to form conductive vias 354a, 354b, 354c (collectively referred to as conductive vias 354 and individually referred to as conductive vias 354). The conductive vias 354 may be, for example, Figure 1 Each of the conductive vias 354a, 354b, 354c is coupled to a corresponding one of the conductive connections 352a, 352b and a portion of the conductive layer 335 on the gate line 333. The conductive material may include a metal such as tungsten W. When the components and / or structures (e.g., such as tungsten W) between the conductive connection 352 and the connection structure 340 are removed by an etching process at step 204, Figure 3C ) and fill the isolation material 327 (eg, as shown in FIG. 1 ) in the first region 301 and the second region 303 (eg, between the conductive connection 352, the connection structure 340 and the array structure 330). Figure 3D), components and / or structures (e.g., conductive connection 352, connection structure 340, and array structure 330) in first region 301 and second region 303 can be conductively isolated by filled isolation material 327. Therefore, process 200 does not require one or more additional processes to form BDTI isolation to isolate components and / or structures in first region 301 and second region 303, such as conductive connection 352, connection structure 340, and array structure 330. Thus, there is no tungsten residue problem, which can reduce tungsten recesses. In some embodiments, the conductive material includes aluminum (Al).

[0071] In some embodiments, process 200 further includes depositing a conductive pad layer 360 on conductive via 354. For example, Figure 3F As shown in structure 300f, a conductive pad layer 360 is formed on a surface of structure 300e, for example, on top of conductive via 354, and in contact with conductive via 354. Conductive pad layer 360 may include a conductive material, for example, a metal such as aluminum (Al).

[0072] In some embodiments, the conductive via 354 and the conductive pad layer 360 are made of different materials, for example, the conductive via 354 can be made of tungsten W, and the conductive pad layer 360 can be made of aluminum (Al). The conductive via 354 and the conductive pad layer 360 can be formed in different process steps. In some embodiments, the conductive via 354 and the conductive pad layer 360 are made of the same material (for example, tungsten W, aluminum (Al) or any suitable conductive material). The conductive via 354 and the conductive pad layer 360 can be formed in the same process step, for example, the same material is deposited on the structure 300e to fill the trench 329 until the conductive pad layer 360 is formed. In this way, the process 200 can be simplified.

[0073] In some embodiments, the isolation layer 362 (eg, Figure 1 An isolation layer 162) is further formed on the conductive pad layer 360, for example, as Figure 3F The structure is shown in 300f.

[0074] In some embodiments, process 200 further includes forming individual conductive pads 364a, 364b, 364c (collectively referred to as conductive pads 364 and individually referred to as conductive pads 364) by patterning conductive pad layer 360. Conductive pads 364 may be, for example Figure 1Conductive pads 364a, 364b, 364c can each be coupled to a corresponding conductive via 354, which is coupled to a portion of conductive layer 335 on gate line 333 and a corresponding one of conductive connections 352. In some embodiments, process 200 also includes filling isolation material (e.g., oxide) between adjacent conductive pads 364. The surface of the deposited isolation material can be polished, for example, by using CMP.

[0075] In some embodiments, process 200 further includes depositing one or more layers (eg, dielectric layer 370 and protective layer 372) over conductive pad layer 360. Dielectric layer 370 (eg, Figure 1 The dielectric layer 170) and the protective layer 372 (eg, Figure 1 A protective layer 172 may be sequentially formed on the structure 300f, for example, after an isolation material is filled between adjacent conductive pads 364.

[0076] In some embodiments, Figure 3G As shown, one or more pad openings 374 (eg, Figure 1 The pad openings 174 are formed to expose one or more corresponding conductive pads 364, so that the one or more conductive pads 364 can be coupled to one or more external components, such as power, ground, other semiconductor devices, metal lines on a printed circuit board (PCB), etc., through bonding wires passing through the one or more pad openings 174. Therefore, the peripheral circuit 314 in the peripheral die 310 and / or the conductive layer 332 in the array die 320 can be conductively coupled to one or more external components. Figure 3G The structure 300g can be used with Figure 1 The semiconductor devices 100 are the same or similar.

[0077] Figure 4 A block diagram of a system 400 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. The system 400 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 4As shown in , system 400 may include a host device 408 and a memory system 402 having one or more 3D memory devices 404 and a memory controller 406. The host device 408 may include a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), such as an application processor (AP). The host device 408 may be configured to send data to or receive data from the one or more 3D memory devices 404.

[0078] The 3D memory device 404 may be any 3D memory device disclosed herein, such as Figure 1-3G . In some embodiments, the 3D memory device 404 includes a NAND flash memory. A memory controller 406 (also referred to as a controller circuit) is coupled to the 3D memory device 404 and a host device 408. Consistent with embodiments of the present disclosure, the 3D memory device 404 may include a plurality of conductive interconnects that contact a conductive pad in a conductive pad layer through a cover layer, and the memory controller 406 may be coupled to the 3D memory device 404 through at least one of the plurality of conductive interconnects. The memory controller 406 is configured to control the 3D memory device 404. For example, the memory controller 406 may be configured to operate a plurality of channel structures via word lines. The memory controller 406 may manage data stored in the 3D memory device 404 and communicate with the host device 408.

[0079] In some embodiments, the memory controller 406 is designed / configured to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 406 is designed / configured to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which can be used as a data storage device and enterprise storage array for mobile devices such as smart phones, tablet computers, laptop computers, etc. The memory controller 406 can be configured to control the operation of the 3D memory device 404, such as read, erase and program (or write) operations. The memory controller 406 can also be configured to manage various functions related to data stored or to be stored in the 3D memory device 404, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 406 is also configured to process error correction code (ECC) related to data read from or written to the 3D memory device 404. Any other suitable functions may also be performed by the memory controller 406 , such as formatting the 3D memory device 404 .

[0080] The memory controller 406 may communicate with an external device (e.g., the host device 408) according to a specific communication protocol. For example, the memory controller 406 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced mini disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0081] The memory controller 406 and the one or more 3D memory devices 404 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 402 can be implemented and packaged into different types of terminal electronic products. Figure 4 In one example shown, a memory controller 406 and a single 3D memory device 404 may be integrated into a memory card 402. The memory card 402 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0082] The subject matter described in the present disclosure and the embodiments of the actions and operations can be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware, including the structures disclosed in the present disclosure and their structural equivalents, or a combination of one or more thereof. The embodiments of the subject matter described in the present disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier, for execution by a data processing device or for controlling the operation of the data processing device. The carrier can be a tangible non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to an appropriate receiver device for execution by a data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them, or a part of a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. The computer storage medium is not a propagation signal.

[0083] Note that references in this disclosure to "one embodiment," "an embodiment," "exemplary embodiments," "some embodiments," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a person skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0084] Typically, a term can be understood at least in part from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one," "an," or "the" can also be understood to convey singular usage or to convey plural usage. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0085] It should be readily understood that the meaning of "on", "over", and "on" in the present disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween. Furthermore, "over" or "on" not only means "over something" or "on something", but also may include the meaning of "over something" or "on something" with no intervening features or layers therebetween (i.e., directly on something).

[0086] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or some) elements or features as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation shown in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0087] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is usually where the semiconductor devices are formed, so unless otherwise specified, the semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, so the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0088] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes at or at the layer. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, wherein one or more layers can be included, and / or one or more layers can be provided on, above and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductors and contact layers (wherein contacts, interconnect lines and / or vertical interconnect paths (vias) are formed) and one or more dielectric layers.

[0089] As used herein, the term "nominal / nominal" refers to an expected or target value for a characteristic or parameter of a component or process step set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. As used herein, a range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" refers to a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device in question. Based on a particular technology node, the term "approximately" may refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0090] In the present disclosure, the terms “horizontal / horizontally / lateral / laterally” mean nominally parallel to a lateral surface of a substrate, and the terms “vertical” or “vertically” mean nominally perpendicular to a lateral surface of a substrate.

[0091] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string", such as a NAND string) on ​​a laterally oriented substrate such that the memory string extends in a vertical direction relative to the substrate.

[0092] The present disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature may be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0093] The foregoing description of specific embodiments can be readily modified and / or adapted for use in a variety of applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0094] Although the present disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope of the claimed protection as defined by the claims themselves, but rather as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described in the present disclosure in the context of different embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any appropriate sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and claims may be directed to sub-combinations or variations of sub-combinations.

[0095] Similarly, although operations are shown in the drawings and described in a particular order in the claims, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order, or that all of the operations shown be performed, to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0096] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes shown in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0097] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method comprising: Providing an integrated structure comprising an array structure in a first region and a conductive connection structure in a second region adjacent to the first region, wherein at least a portion of at least one polysilicon layer is above the conductive connection structure; etching the at least a portion of the at least one polysilicon layer to expose one or more conductive connections in the conductive connection structure; depositing an isolation material over the array structure and the conductive connection structure; and Conductive vertical interconnect vias (vias) are formed through the isolation material to contact the one or more conductive connections and conductive layers in the array structure.

2. The method according to claim 1, wherein: Forming the conductive via comprises: etching the isolation material to expose the one or more conductive connections in the conductive connection structure and portions of the conductive layer in the array structure; and Conductive material is deposited on the one or more conductive connections in the conductive connection structure and the portion of the conductive layer in the array structure to form the conductive vias, wherein each of the conductive vias is coupled to a corresponding one of the one or more conductive connections and the portion of the conductive layer.

3. The method according to claim 1 or 2, further comprising: depositing a conductive pad layer on the conductive via; depositing at least one capping layer over the conductive pad layer; as well as One or more pad openings are formed through the at least one cover layer to expose one or more corresponding portions of the conductive pad layer.

4. The method of claim 3 , further comprising depositing a dielectric layer on the conductive pad layer, the dielectric layer being between the conductive pad layer and the at least one cover layer, in, Forming the one or more pad openings includes: Etching through the at least one capping layer and the dielectric layer to form corresponding pad openings.

5. The method according to claim 3 or 4, wherein: The conductive pad layer includes a first conductive material, and the conductive via includes a second conductive material different from the first conductive material.

6. A method according to any preceding claim, wherein: The at least one polysilicon layer comprises a plurality of portions, and wherein the at least one portion of the at least one polysilicon layer is a first portion of the at least one polysilicon layer, and a second portion of the at least one polysilicon layer is above the array structure, and Wherein, providing the integrated structure comprises: etching the second portion of the at least one polysilicon layer to expose a plurality of memory cell strings and gate lines between adjacent groups of strings in the array structure; and The conductive layer is formed across the first region, wherein the conductive layer is in contact with end surfaces of the plurality of memory cell strings and the gate line.

7. The method according to claim 6, wherein: The plurality of memory cell strings and the end surfaces of the gate lines form a flat surface.

8. The method according to claim 6, wherein: The plurality of memory cell strings and the end surfaces of the gate lines form uneven surfaces.

9. The method according to any one of claims 6 to 8, wherein: Forming the conductive via comprises: A conductive via is formed through the isolation material to contact a portion of the conductive layer over the gate line.

10. A method according to any preceding claim, wherein: Etching the at least a portion of the at least one polysilicon layer comprises: etching all of the at least a portion of the at least one polysilicon layer within the etch region, wherein the first region and the second region are arranged along a first direction, and the one or more conductive connections extend along a second direction perpendicular to the first direction, The etching region has a first edge and a second edge opposite to each other along the first direction, the first edge can extend to the edge of the plane of the integrated structure, and the second edge can extend to the edge of the second region, and Wherein, the etching area has an etching depth from the top surface to the bottom surface along the second direction, and the distance between the top surface of the etching area and the end surface of each of the one or more conductive connections in the conductive connection structure is not greater than the etching depth.

11. A method according to any preceding claim, wherein: Depositing the isolation material on the array structure and the conductive connection structure comprises: depositing the isolation material between adjacent conductive connections in the conductive connection structure and over the conductive layer in the array structure, and Wherein, the method further comprises: After depositing the isolation material on the array structure and the conductive connection structure, the surface of the deposited isolation material is polished.

12. A semiconductor device comprising: an array structure including a conductive layer coupled to a plurality of memory cell strings; A conductive connection structure is disposed separately from the array structure, the conductive connection structure comprising a plurality of conductive connections; as well as a conductive pad layer disposed above the array structure and the conductive connection structure, the conductive pad layer comprising a plurality of conductive pads coupled to portions of the conductive layer and each of the plurality of conductive connections through corresponding conductive vias, Wherein, the plurality of conductive connections are separated by an isolation material filled in the conductive connection structure.

13. The semiconductor device according to claim 12, wherein: The corresponding conductive vias are separated and isolated by the isolation material filled between the conductive pad layer, the array structure and the conductive connection structure.

14. The semiconductor device according to claim 12 or 13, wherein: There is no conductive material between the conductive connection structure and the array structure.

15. The semiconductor device according to any one of claims 12 to 14, wherein: There is no conductive material between the plurality of conductive connections in the conductive connection structure.

16. The semiconductor device according to any one of claims 12 to 15, wherein: A connection angle between the conductive pad layer and at least one of the corresponding conductive vias is about 90 degrees.

17. The semiconductor device according to any one of claims 12 to 16, wherein: The array structure and the conductive connection structure are integrated in a first die, and Wherein the semiconductor device further comprises a second die integrated with the first die, and wherein at least one of the plurality of conductive connections is coupled to a control circuit in the second die.

18. The semiconductor device according to any one of claims 12 to 17, further comprising a cover layer on top of the conductive pad layer, in, The cover layer includes a plurality of pad openings on top of the plurality of conductive pads in the conductive pad layer, and wherein each of the plurality of conductive pads is coupled to at least one of the corresponding conductive vias.

19. A system comprising: A memory device, the memory device comprising: an array structure including a conductive layer coupled to a plurality of memory cell strings; a conductive connection structure, disposed separately from the array structure, the conductive connection structure comprising a plurality of conductive connections, the plurality of conductive connections being separated by an isolation material filled in the conductive connection structure; and a conductive pad layer disposed above the array structure and the conductive connection structure, the conductive pad layer comprising a plurality of conductive pads coupled to portions of the conductive layer and each of the plurality of conductive connections through corresponding conductive vias; and A controller is coupled to the memory device and is configured to control the memory device.

20. The system of claim 19, wherein: The memory device further comprises: a plurality of conductive interconnects passing through a cover layer on top of the conductive pad layer to contact the plurality of conductive pads in the conductive pad layer, and each of the plurality of conductive pads is coupled to at least one of the corresponding conductive vias, Wherein, the controller is coupled to the memory device via at least one conductive interconnect among the plurality of conductive interconnects.

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