Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor substrate has: transistor sections and diode sections that are alternately arranged in a first direction and have long sides in a second direction; and a current sensing section disposed so as to face the transistor section in the second direction, the transistor section, the diode section, and the current sensing section having a drift region of the first conductivity type, and a base region of the second conductivity type provided between the drift region and the upper surface of the semiconductor substrate. In a plan view, the current sensing portion is surrounded by a sensing well region of a second conductivity type provided so that the concentration is higher than that of the base region and deeper from the upper surface than the base region, and the width of the sensing well region is larger in the first direction than the width of the transistor portion facing the current sensing portion.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Conventionally, there is known a semiconductor device including a current sensing portion (see, for example, Patent Document 1).

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Publication No. 2021-192447 Summary of the invention

[0004] Technical issues In the current sensing portion, it is preferable to suppress the influence of holes bypassing from the active portion.

[0005] Technical Solution In a first embodiment of the present invention, a semiconductor device having a semiconductor substrate is provided. The semiconductor substrate may have a transistor portion and a diode portion, which are alternately arranged along a first direction and have a long side in a second direction. The semiconductor substrate may have a current sensing portion, which is arranged opposite to the transistor portion in the second direction. In any of the above-mentioned semiconductor devices, the transistor portion, the diode portion, and the current sensing portion may have a drift region of a first conductivity type. In any of the above-mentioned semiconductor devices, the transistor portion, the diode portion, and the current sensing portion may have a base region of a second conductivity type disposed between the drift region and the upper surface of the semiconductor substrate. When looking down at any of the semiconductor devices, the current sensing portion may be surrounded by a sensing well region of a second conductivity type, which is set to have a concentration higher than that of the base region and deeper from the upper surface than the base region. In the first direction of any of the semiconductor devices, the width of the sensing well region may be larger than the width of the transistor portion opposite to the current sensing portion.

[0006] In any of the semiconductor devices described above, the semiconductor substrate may include an active well region surrounding the transistor portion and the diode portion in a plan view. In any of the semiconductor devices described above, the sensing well region may be provided inside the active well region in a plan view.

[0007] In any of the semiconductor devices described above, a plurality of pad portions may be provided above the active well region. In any of the semiconductor devices described above, the current sensing portion may be disposed between two pad portions in the first direction.

[0008] In any of the above-described semiconductor devices, at least a portion of the transistor portion that faces the current sensing portion may be located between the pad portions.

[0009] In any of the above-mentioned semiconductor devices, the transistor portion may have an emitter region of a first conductivity type disposed on the upper surface. In any of the above-mentioned semiconductor devices, the transistor portion may have a collector region of a second conductivity type disposed on the lower surface of the semiconductor substrate. In any of the above-mentioned semiconductor devices, the diode portion may not have an emitter region on the upper surface. In any of the above-mentioned semiconductor devices, the diode portion may have a cathode region of the first conductivity type disposed on the lower surface. In any of the above-mentioned semiconductor devices, the semiconductor substrate may also have a boundary region, which is disposed between the transistor portion and the diode portion, has no emitter region on the upper surface, and has a collector region on the lower surface. In any of the above-mentioned semiconductor devices, the peripheral end position of the sensing well region in the first direction may be opposite to the boundary region in the second direction.

[0010] In any of the semiconductor devices described above, the transistor portion and the current sensing portion may have a plurality of groove portions arranged from the upper surface of the semiconductor substrate toward the inside, the plurality of groove portions being arranged along the first direction and having a length in the second direction. In any of the semiconductor devices described above, the distance between the groove portion arranged at the endmost portion of the current sensing portion in the first direction and the sensing well region in the first direction may be smaller than the distance between the groove portion arranged at the endmost portion of the transistor portion in the first direction and the active well region in the first direction.

[0011] In any of the semiconductor devices described above, the sensing well region may have an inner peripheral end opposite to the current sensing portion in a plan view, and an outer peripheral end opposite to the inner peripheral end. In any of the semiconductor devices described above, the width between the inner peripheral end and the outer peripheral end of the sensing well region may be larger than the distance between the active well region and the sensing well region.

[0012] In any of the semiconductor devices described above, the transistor portion and the current sensing portion may have a plurality of groove portions arranged from the upper surface of the semiconductor substrate toward the inside. In any of the semiconductor devices described above, the transistor portion and the current sensing portion may have a mesa portion as an area between the groove portions. In any of the semiconductor devices described above, the transistor portion and the current sensing portion may have a contact region of the second conductivity type, which is arranged between the base region and the upper surface of the semiconductor substrate and has a higher concentration than the base region. In any of the semiconductor devices described above, the area ratio of the contact region to the area of ​​one mesa portion of the current sensing portion may be greater than the area ratio of the transistor portion.

[0013] In any of the above semiconductor devices, a length of the contact region of the current sensing portion in the second direction may be greater than a length of the contact region of the transistor portion in the second direction.

[0014] In any of the above semiconductor devices, the transistor portion and the current sensing portion may have a plurality of groove portions arranged from the upper surface of the semiconductor substrate toward the inside, the plurality of groove portions are arranged along the first direction and have long sides in the second direction. In any of the above semiconductor devices, the intervals of the groove portions of the current sensing portion in the first direction may be greater than the intervals of the groove portions of the transistor portion in the first direction.

[0015] In any of the above semiconductor devices, a distance between the transistor portion opposite to the current sensing portion in the second direction and the current sensing portion may be greater than a distance between the diode portion and the current sensing portion in the second direction.

[0016] In any of the above semiconductor devices, the semiconductor substrate may have a boundary region disposed between the transistor portion and the diode portion. In any of the above semiconductor devices, a distance between the transistor portion and the current sensing portion opposite to the current sensing portion in the second direction may be greater than a width of the boundary region in the first direction.

[0017] In the second direction of any of the semiconductor devices, a region of the first conductivity type may be provided on the lower surface of the semiconductor substrate between the transistor portion and the current sensing portion.

[0018] In any of the above semiconductor devices, a distance between the transistor portion and the current sensing portion in the second direction may be 500 μm or more.

[0019] In any of the semiconductor devices described above, the current sensing portion may have a plurality of groove portions arranged from the upper surface of the semiconductor substrate toward the inside. In any of the semiconductor devices described above, the current sensing portion may have a mesa portion as a region between the groove portions. In any of the semiconductor devices described above, an emitter region of a first conductivity type may be arranged in at least one mesa portion, and the emitter region of the first conductivity type is arranged between the drift region and the upper surface of the semiconductor substrate. In any of the semiconductor devices described above, a base region may be arranged in at least one mesa portion. In any of the semiconductor devices described above, a trench contact portion arranged from the upper surface of the semiconductor substrate toward the inside may be arranged in at least one mesa portion.

[0020] In any of the semiconductor devices described above, the transistor portion may include a plurality of trench portions. In any of the semiconductor devices described above, the transistor portion may include a mesa portion. In any of the semiconductor devices described above, the mesa portion of the transistor portion may not include a trench contact portion.

[0021] In any of the above semiconductor devices, a width of the current sensing portion in the first direction may be smaller than a width of the transistor portion opposite to the current sensing portion in the first direction.

[0022] In any of the above-described semiconductor devices, an inner peripheral end portion of the sensing well region in the first direction may be located opposite to the transistor portion in the second direction.

[0023] Any of the semiconductor devices described above may include an interlayer insulating film disposed on the upper surface of the semiconductor substrate. Any of the semiconductor devices described above may include a sensing emitter electrode disposed above the interlayer insulating film. In any of the semiconductor devices described above, the interlayer insulating film may have a contact hole between the transistor portion and the current sensing portion in the second direction. In any of the semiconductor devices described above, the sensing emitter electrode and the sensing well region may be connected via the contact hole.

[0024] Any of the semiconductor devices described above may include an interlayer insulating film disposed on the upper surface of the semiconductor substrate. Any of the semiconductor devices described above may include an upper surface electrode disposed above the interlayer insulating film. Any of the semiconductor devices described above may include a well region of a second conductivity type, the well region of the second conductivity type being disposed between the transistor portion and the sensing well region in the second direction. In any of the semiconductor devices described above, the interlayer insulating film may have a contact hole between the transistor portion and the sensing well region in the second direction. In any of the semiconductor devices described above, the upper surface electrode and the well region may be connected via the contact hole.

[0025] In any of the semiconductor devices described above, the well region may be an active well region surrounding the transistor portion and the diode portion in a plan view. In any of the semiconductor devices described above, the upper surface electrode may be an emitter electrode provided above the transistor portion.

[0026] In the first direction of any of the above semiconductor devices, a length of the contact hole may be greater than at least one of a width of the transistor portion opposite to the current sensing portion and a width of the current sensing portion.

[0027] In any of the above-mentioned semiconductor devices, a lead-out trench contact portion formed inward from the upper surface of the semiconductor substrate may be provided at a lower end of the contact hole.

[0028] It should be noted that the above-described invention does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups may also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 1 is a diagram showing an equivalent circuit of a semiconductor device 100 according to an embodiment of the present invention.

[0030] Figure 2 1 is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0031] Figure 3 yes Figure 2Magnified view of area A in FIG.

[0032] Figure 4 It is shown Figure 3 A diagram showing an example of the AA' section in FIG.

[0033] Figure 5 It is shown Figure 3 A diagram showing an example of the BB' section in FIG.

[0034] Figure 6 It is shown Figure 2 A diagram showing an example of the CC' cross section in FIG.

[0035] Figure 7 It is a plan view of the mesa portion 60 of the transistor portion 70 and the mesa portion 63 of the current sensing portion 26 .

[0036] Figure 8 This is a diagram showing the arrangement of the periphery of the current sensing unit 26 of a sample having a large chip size.

[0037] Fig. 9 This is a diagram showing the arrangement of the periphery of the current sensing unit 26 of a measurement sample having a small chip size.

[0038] Fig.10 It is a graph showing the measurement results of the active area dependency of the short-circuit withstand capability.

[0039] Fig.11 It is shown Figure 3 FIG. 1 is a diagram of another example of region A in FIG.

[0040] Fig.12 It is shown Figure 3 A diagram showing an example of the AB section in FIG.

[0041] Fig.13 It is shown Figure 3 FIG. 2 is a diagram of another example of the BB' cross section.

[0042] Fig.14 It is shown Figure 2 FIG. 1 is another example of an enlarged view of region A in FIG.

[0043] Fig.15 It is shown Fig.14 A diagram showing an example of the AB section in FIG.

[0044] Explanation of symbols 10…semiconductor substrate, 12…emitter region, 14…base region, 15…contact region, 16…accumulation region, 17…P+ contact region, 18…drift region, 19…bottom P region, 21…upper surface, 22…collector region, 23…lower surface, 24…collector electrode, 26…current sensing portion, 28…sensing well region, 29…active well region, 34…inner peripheral end, 36…outer peripheral end, 38…interlayer insulating film, 40…groove portion, 42…gate insulating film, 44…gate conductive portion, 48…second gate flow channel, 50…first gate flow channel, 51…gate flow channel for current sensing, 52…emitter electrode, 54…contact hole, 56…sensing emitter electrode, 58…groove contact portion, 60… mesa portion, 61… mesa portion, 62… mesa portion, 63… mesa portion, 70… transistor portion, 72… boundary region, 80… diode portion, 82… cathode region, 90… edge termination structure portion, 92… guard ring, 94… field plate, 100… semiconductor device, 110… pad portion, 111… temperature sensing portion, 112… temperature sensing wiring, 114… current control pad, 115… auxiliary emitter electrode pad, 116… gate pad, 117… cathode pad, 118… anode pad, 120… active portion, 140… outer peripheral end, 142… first end side, 154… contact hole, 156… extraction trench contact, 202… high concentration region DETAILED DESCRIPTION

[0045] The present invention is described below by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of the features described in the embodiments are not necessarily required for the solution of the invention. In this specification, the same parts in the figures are sometimes marked with the same reference numerals and the description is omitted. In addition, for the convenience of description, a part of the structure is sometimes not shown.

[0046] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is installed.

[0047] In this specification, sometimes an orthogonal coordinate system of the X-axis, Y-axis, and Z-axis is used to explain technical matters. The orthogonal coordinate system only determines the relative positions of the components and does not limit specific directions. For example, the Z-axis direction does not limit the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the Z-axis direction is recorded without recording the positive or negative, it refers to the direction parallel to the +Z-axis and the -Z-axis.

[0048] In this specification, the orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are referred to as the X-axis and the Y-axis. In addition, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. In addition, in this specification, the direction parallel to the upper surface and the lower surface of the semiconductor substrate, including the X-axis and the Y-axis, is sometimes referred to as the horizontal direction.

[0049] In this specification, when it is said that they are “same” or “equal”, it may include the case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0050] In this specification, the conductivity type of the doped region doped with impurities is set to P type or N type for description. In this specification, impurities sometimes specifically refer to one of N type donors or P type acceptors, and sometimes are described as dopants. In this specification, doping refers to the introduction of donors or acceptors into a semiconductor substrate, and setting it to a semiconductor exhibiting N type conductivity or a semiconductor exhibiting P type conductivity. In this specification, the doping concentration of the N type region is sometimes referred to as the donor concentration, and the doping concentration of the P type region is sometimes referred to as the acceptor concentration.

[0051] Figure 1 1 is a diagram showing an equivalent circuit of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a transistor unit 70 and a current sensing unit 26. The current sensing unit 26 has the same structure as the transistor unit 70 and measures the current flowing through the transistor unit 70. The transistor unit 70 and the current sensing unit 26 may be IGBTs.

[0052] The collector of the transistor unit 70 and the collector of the current sensing unit 26 are connected to each other and to a common collector terminal (C). The gate conductive portion of the transistor unit 70 and the gate conductive portion of the current sensing unit 26 are connected to a common gate drive circuit. On the other hand, the emitter electrode 52 of the transistor unit 70 and the sensing emitter electrode of the current sensing unit 26 are electrically separated inside the semiconductor device 100. The emitter electrode 52 of the transistor unit 70 is connected to the emitter electrode terminal (E) and is supplied with an emitter electrode potential. Although the sensing emitter electrode of the current sensing unit 26 is also connected to the emitter electrode terminal, it is supplied with an emitter electrode potential via the sensing resistor Rs branched from the emitter electrode 52.

[0053] When the semiconductor device 100 is operating, a predetermined current flows through the transistor unit 70, and a current corresponding to the current value of the transistor unit 70 flows through the current sensing unit 26. The current value flowing through the current sensing unit 26 is measured based on the voltage drop at the sense resistor Rs at this time. The current value of the transistor unit 70 is estimated based on the measurement result in the current sensing unit 26. In this way, an overcurrent of the transistor unit 70 can be detected and the device can be stopped. It should be noted that L represents the inductance component of the wire.

[0054] Figure 2 FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Figure 2 , the positions of the components projected onto the upper surface of the semiconductor substrate 10 are shown. Figure 2 In FIG. 1 , only some components of the semiconductor device 100 are shown, and some components are omitted.

[0055] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. In this specification, the end of the periphery of the semiconductor substrate 10 when viewed from above is referred to as the peripheral end 140. The view from above refers to the situation of observing from the upper surface side of the semiconductor substrate 10 parallel to the Z axis. In addition, any end edge of the peripheral end 140 of the semiconductor substrate 10 when viewed from above is referred to as the first end edge 142. The direction parallel to the first end edge 142 when viewed from above is referred to as the X-axis direction, and the direction perpendicular to the first end edge 142 is referred to as the Y-axis direction.

[0056] The semiconductor substrate 10 is provided with an active portion 120. The active portion 120 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode 52 is provided above the active portion 120, but Figure 2 Omitted in .

[0057] The active portion 120 is provided with at least one of a transistor portion 70 including a transistor element such as an IGBT and a diode portion 80 including a diode element such as a freewheeling diode (FWD). Figure 2 In the example of , the transistor section 70 and the diode section 80 are alternately arranged along the first direction. That is, the first direction is the arrangement direction of the transistor section 70 and the diode section 80. The first direction may also be the arrangement direction of the groove section described later. In this example, the transistor section is provided at the end of the active section in the first direction. In other examples, only one of the transistor section 70 and the diode section 80 may be provided in the active section 120.

[0058] The transistor portion 70 and the diode portion 80 may each have a long side in the second direction. That is, the second direction is the extension direction of the transistor portion 70 and the diode portion 80. In this specification, the first direction is set as the X-axis direction and the second direction is set as the Y-axis direction for description. The length of the transistor portion 70 in the Y-axis direction is greater than the width of the transistor portion 70 in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than the width of the diode portion 80 in the X-axis direction. The extension direction of the transistor portion 70 and the diode portion 80 may be the same as the long side direction of each groove portion described later.

[0059] The diode portion 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is a region that overlaps with the cathode region when viewed from above. On the lower surface of the semiconductor substrate 10, a P+ type collector region may be provided in a region other than the cathode region. In this specification, the region in which the diode portion 80 is extended in the Y-axis direction to the active well region 29 described later is sometimes also included in the diode portion 80. A collector region is provided on the lower surface of the extended region.

[0060] The transistor portion 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor portion 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, and the gate structure has an N+ type emitter region, a P- type base region, a gate conductive portion, and a gate insulating film.

[0061] A plurality of pad portions 110 are provided above the upper surface of the semiconductor substrate 10 ( Figure 2In the example of the embodiment, the current control pad 114, the auxiliary emitter electrode pad 115, the gate pad 116, the cathode pad 117, and the anode pad 118 are provided. The current control pad 114 is connected to the current sensing portion 26. The current sensing portion 26 has the same structure as the transistor portion 70, and its area (corresponding to the area of ​​the channel) when viewed from above is smaller than that of the transistor portion 70. By detecting the current flowing through the current sensing portion 26, the current flowing through the entire semiconductor device 100 can be estimated. When the output from the current sensing portion 26 is wired to the emitter electrode 52, the wiring can be extended from the current control pad 114. The auxiliary emitter electrode pad 115 is connected to the emitter electrode 52 arranged above the upper surface of the semiconductor substrate 10. In order to make the wiring extending from the current control pad 114 the same potential as the emitter electrode 52, it can be connected to the emitter electrode 52 by wire bonding in the auxiliary emitter electrode pad 115. The gate pad 116 is connected to the gate conductive portion of the transistor portion 70 and the gate conductive portion of the current sensing portion 26. The gate pad 116 of this example is connected to each gate conductive portion via a gate flow path described later. The cathode pad 117 and the anode pad 118 are connected to the temperature sensing portion 111 described later. It should be noted that the number and type of pad portions 110 provided on the semiconductor substrate 10 are not limited to Figure 2 Example shown.

[0062] Each pad is formed of a metal material such as aluminum. The plurality of pad portions 110 are arranged along a predetermined direction between the active portion 120 and the first end edge 142 of the upper surface of the semiconductor substrate 10. The plurality of pad portions 110 of this example are arranged to be sandwiched between the active portion 120 and the first end edge 142 in the Y-axis direction. The plurality of pad portions 110 of this example are arranged above the active well region 29 described later.

[0063] In the arrangement direction of the plurality of pads 110, the current sensing unit 26 can be disposed between any two pads 110. In this example, the current sensing unit 26 is disposed between two pads 110 in the first direction. The first direction in this example is the same as the arrangement direction of the pads 110.

[0064] The semiconductor device 100 includes a gate flow path for transmitting a gate voltage to the transistor portion 70. The semiconductor device 100 of this example includes a first gate flow path and a second gate flow path 48 as gate flow paths. In this example, each gate flow path is provided above the upper surface of the semiconductor substrate 10 and is insulated from the upper surface of the semiconductor substrate 10 by an interlayer insulating film.

[0065] exist Figure 2, the first gate flow channel is omitted. The first gate flow channel is provided between the first end side 142 of the semiconductor substrate 10 and at least one pad portion 110 when viewed from above. The first gate flow channel of this example is provided parallel to the first end side 142 by passing between the current control pad 114, the auxiliary emission electrode pad 115, the gate pad 116, the cathode pad 117 and the anode pad 118, respectively, and the first end side 142. The first gate flow channel is connected to the gate pad 116.

[0066] In addition, the first gate flow channel is provided between the other end sides of the semiconductor substrate 10 and the active portion 120 in a manner of surrounding the active portion 120. That is, the first gate flow channel of this example is provided in a ring shape along each end side of the semiconductor substrate 10. The first gate flow channel can be a metal wiring such as aluminum, or a semiconductor wiring such as polysilicon doped with impurities. The first gate flow channel can also be a structure in which the metal wiring and the semiconductor wiring are provided overlappingly through an insulating film. The insulating film is provided with a contact hole for connecting the metal wiring and the semiconductor wiring.

[0067] The second gate channel 48 may be provided in a manner to cross the active portion 120. The second gate channel 48 may be a semiconductor wiring. The second gate channel 48 of this example crosses the active portion 120 in the X-axis direction. The second gate channel 48 is electrically connected to the first gate channel. The gate voltage is transmitted from the gate pad 116 to the transistor portion 70 and the current sensing portion 26 via the first gate channel and the second gate channel 48. By providing the second gate channel 48 in the active portion 120, the deviation of the wiring length from the gate pad 116 can be reduced in each region of the semiconductor substrate 10. The first gate channel or the second gate channel 48 may also be provided around the pad portion 110 and between the active portion 120 and any pad portion 110.

[0068] The semiconductor substrate 10 has an active well region 29. The active well region 29 surrounds the transistor portion 70 and the diode portion 80 in a plan view. The active well region 29 surrounds the active portion 120 in a plan view. The active well region 29 is a region of the second conductivity type having a higher doping concentration than the base region. The active well region 29 in this example is a P+ type. The active well region 29 can surround the active portion 120 along the gate flow path. The active well region 29 is also provided around the pad portion 110, but Figure 2 Omitted in .

[0069] The edge termination structure portion 90 is provided between the active well region 29 and the outer peripheral end 140 of the semiconductor substrate 10 on the upper surface of the semiconductor substrate 10. The edge termination structure portion 90 can be arranged in a ring shape on the upper surface of the semiconductor substrate 10 so as to surround the active well region 29. The edge termination structure portion 90 of this example is arranged along the outer peripheral end 140 of the semiconductor substrate 10. The edge termination structure portion 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 includes, for example, a guard ring, a field plate, a surface electric field reduction portion, and a structure formed by combining them.

[0070] The temperature sensing wiring 112 is provided above the active portion 120. The temperature sensing wiring 112 may be a semiconductor wiring. The temperature sensing wiring 112 is connected to the temperature sensing portion 111. The temperature sensing wiring 112 extends to the region between the active portion 120 and the peripheral end 140 on the upper surface of the semiconductor substrate 10, and is connected to the cathode pad 117 and the anode pad 118. It should be noted that the semiconductor device 100 may not include the temperature sensing portion 111 and the temperature sensing wiring 112.

[0071] Figure 3 yes Figure 2 1 is an enlarged view of region A in FIG. Region A is a region around the current sensing portion 26. In a plan view, the current sensing portion 26 is surrounded by a second conductivity type sensing well region 28. The sensing well region 28 is set to have a higher concentration than the base region and deeper from the upper surface of the semiconductor substrate 10 than the base region. The current sensing portion 26 of this example is arranged opposite to the transistor portion 70 in the second direction.

[0072] When the transistor section 70 and the current sensing section 26 are opposite to each other, holes easily flow from the transistor section 70 to the current sensing section 26. The holes flowing to the current sensing section 26 are accumulated in the current sensing section 26, causing voltage oscillation. Since the capacitance of the current sensing section 26 is smaller than the capacitance of the transistor section 70, the groove of the current sensing section 26 is destroyed by the oscillation. Therefore, it is preferable to suppress the influence of the holes flowing to the current sensing section 26.

[0073] By providing the sensing well region 28, holes flowing around the current sensing portion 26 can be extracted, and the accumulation of holes in the current sensing portion 26 can be suppressed. In the semiconductor device 100 of this example, in the first direction, the width Wsu of the sensing well region 28 is larger than the width Wt of the transistor portion 70 opposite to the current sensing portion 26. The width Wt of the transistor portion 70 can be the distance from one groove portion provided at the boundary between the transistor portion 70 and the boundary region 72 described later to another groove portion. In this way, the holes flowing around can be further extracted, and since the holes are difficult to accumulate as carriers, the oscillation of the current sensing portion 26 can be suppressed. At this time, a P+ contact region 17 (see Figure 5 ). For example, the P+ contact region 17 is provided in such a manner as to be in contact with the inner periphery of the sensing well region 28 and surround the current sensing portion 26. Thus, holes flowing into the sensing well region 28 can be easily extracted.

[0074] The width Ws of the current sensing portion 26 in the first direction may be smaller than the width Wt of the transistor portion 70 in the first direction opposite to the current sensing portion 26. Thus, the area of ​​the sensing well region 28 in a plan view can be increased, and the holes that flow around can be further extracted.

[0075] The sensing well region 28 can be provided inside the active well region 29 when viewed from above. The potential of the current sensing portion 26 is different from that of the active well region 29 because the voltage is reduced by the sensing resistor. Therefore, the sensing well region 28 of this example is separated from the active well region 29. The active well region 29 and the sensing well region 28 can be provided with a distance that can withstand the potential difference caused by the voltage reduction at the sensing resistor. The distance D1 between the active well region 29 and the sensing well region 28 can be greater than 1 μm and less than 10 μm.

[0076] The sensing well region 28 has an inner peripheral end 34 opposite to the current sensing portion 26 in a plan view, and an outer peripheral end 36 opposite to the inner peripheral end 34. The width Wu between the inner peripheral end 34 and the outer peripheral end 36 of the sensing well region 28 can be larger than the distance D1 between the active well region 29 and the sensing well region 28. Thus, the area of ​​the sensing well region 28 in a plan view can be enlarged, and the holes around which the current flows can be further extracted.

[0077] At least a portion of the transistor portion 70 opposite to the current sensing portion 26 may be located between the pad portions 110. Being located between the pad portions 110 means that the transistor portion 70 has a long side in the second direction until it reaches a position overlapping with the pad portion 110 in the first direction. In this example, a portion of the transistor portion 70 is disposed between the current control pad 114 and the auxiliary emitter electrode pad 115. Thus, the area of ​​the active portion 120 can be enlarged. Accordingly, the inner peripheral end of the active well region 29 may also be disposed between the pad portions 110. The transistor portion 70 may extend to a position closer to the first end side 142 than the diode portion 80.

[0078] Two well regions, namely, the active well region 29 and the sensing well region 28, are provided between the transistor portion 70 and the current sensing portion 26. In addition, the current sensing portion 26 can be provided between the pad portions 110 close to the first end side 142. When the region between the pad portions 110 is divided into two equal parts, namely, the region on the active portion 120 side and the region on the first end side 142 side, the area of ​​the current sensing portion 26 provided on the region on the first end side 142 side can be larger than the area of ​​the region provided on the active portion 120 side. Thus, the region of the transistor portion 70 provided between the pad portions 110 can be ensured.

[0079] The semiconductor substrate 10 may have a boundary region 72 disposed between the transistor portion 70 and the diode portion 80. The boundary region 72 of this example is disposed between the transistor portion 70 and the diode portion 80 in the first direction. The boundary region 72 may not have an emitter region on the upper surface of the semiconductor substrate 10, and may have a collector region on the lower surface of the semiconductor substrate 10. By providing the boundary region 72, it is possible to suppress the flow of holes from the transistor portion 70 to the diode portion 80, thereby suppressing the switching loss of the diode portion 80.

[0080] The outer peripheral end position of the sensing well region 28 in the first direction of this example is opposite to the boundary region 72 in the second direction. The holes in the active portion 120 that flow toward the current sensing portion 26 flow only from the transistor portion 70, and do not flow from the diode portion 80. Therefore, the sensing well region 28 that extracts the flowing holes does not need to be provided at a position opposite to the diode portion 80.

[0081] The inner peripheral end position of the sensing well region 28 in the first direction may be opposite to the transistor portion 70 in the second direction. This can increase the area of ​​the sensing well region 28 in a plan view, and further extract the holes that flow around.

[0082] Figure 4 It is shown Figure 31 is a diagram of an example of an A-A' cross section in FIG. The A-A' cross section is an XZ cross section passing through the emitter region 12 of the transistor portion 70, the boundary region 72, and the diode portion 80. In the A-A' cross section, the semiconductor device 100 includes a semiconductor substrate 10, a collector electrode 24, an interlayer insulating film 38, and an emitter electrode 52. The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The upper surface 21 and the lower surface 23 are two main surfaces of the semiconductor substrate 10.

[0083] Interlayer insulating film 38 is provided on upper surface 21 of semiconductor substrate 10. Interlayer insulating film 38 is a film including at least one of an insulating film such as silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. Contact hole 54 is provided in interlayer insulating film 38.

[0084] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0085] The transistor portion 70 and the diode portion 80 have a drift region 18 of a first conductivity type and a base region 14 of a second conductivity type disposed between the drift region 18 and the upper surface 21 of the semiconductor substrate 10. The boundary region 72 also has a drift region 18 of a first conductivity type and a base region 14 of a second conductivity type disposed between the drift region 18 and the upper surface 21 of the semiconductor substrate 10. In this example, the drift region 18 is of N-type, and the base region 14 is of P-type.

[0086] The transistor portion 70 has a plurality of groove portions 40 arranged from the upper surface 21 of the semiconductor substrate 10 toward the inside. The groove portions 40 of this example are arranged along the first direction and have long sides in the second direction. The interval between the groove portions 40 of the transistor portion 70 in the first direction is set to D2. The groove portion 40 has a groove, a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is arranged in a manner covering the inner wall of the groove. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the groove. The gate conductive portion 44 is arranged inside the groove at a position closer to the inside than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The diode portion 80 and the boundary region 72 can also have a groove portion 40 in the same manner. The trench portion 40 may function as a gate trench or as a dummy trench, and a plurality of trench portions 40 may have both functions mixed therein.

[0087] In the arrangement direction, a mesa portion 60 is provided between each groove portion 40 of the transistor portion 70. The mesa portion 60 refers to a region between the groove portions 40 inside the semiconductor substrate 10. As an example, the upper end of the mesa portion 60 is the upper surface 21 of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the groove portion 40. The mesa portion 60 of this example is provided on the upper surface 21 of the semiconductor substrate 10 in a manner extending along the groove portion 40 in the second direction. Similarly, a mesa portion 61 is provided in the boundary region 72, and a mesa portion 62 is provided in the diode portion 80. In this specification, when referred to as a mesa portion, they refer to the mesa portion 60, the mesa portion 61, and the mesa portion 62, respectively. A base region 14 is provided in each mesa portion.

[0088] The transistor portion 70 has an emitter region 12 of the first conductivity type disposed on the upper surface 21. The emitter region 12 is disposed to be exposed on the upper surface 21 of the semiconductor substrate 10 and to be in contact with the groove portion 40. The emitter region 12 may be in contact with the groove portions 40 on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. The emitter region 12 in this example is of N+ type.

[0089] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided to be in contact with the emitter region 12. The base region 14 may be in contact with the groove portions 40 on both sides of the mesa portion 60.

[0090] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. The semiconductor substrate 10 of this example is provided with the accumulation region 16-1 and the accumulation region 16-2, but the number of the accumulation regions 16 is not limited thereto. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be improved and the on-voltage can be reduced. The accumulation region 16 can be provided in a manner covering the entire lower surface of the base region 14 in each mesa portion 60.

[0091] In the mesa portion 62 of the diode portion 80, a P-type base region 14 is provided in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. The diode portion 80 does not have an emitter region 12 on the upper surface 21 of the semiconductor substrate 10.

[0092] The semiconductor substrate 10 has a boundary region 72 provided between the transistor portion 70 and the diode portion 80. In the mesa portion 61 of the boundary region 72, a P-type base region 14 is provided in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. The boundary region 72 does not have an emitter region 12 on the upper surface 21 of the semiconductor substrate 10.

[0093] The transistor portion 70 has a collector region 22 of the second conductivity type provided on the lower surface 23 of the semiconductor substrate 10. The collector region 22 in this example is of the P+ type. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron. The boundary region 72 also has a collector region 22 of the P+ type on the lower surface 23 of the semiconductor substrate 10.

[0094] The diode portion 80 has a cathode region 82 of a first conductivity type provided on the lower surface 23 of the semiconductor substrate 10. The cathode region 82 in this example is of N+ type. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. It should be noted that the elements that become the donors and acceptors of each region are not limited to the above examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 can be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0095] In a cross section different from the AA' cross section, a second conductivity type contact region may be provided in the transistor portion 70, the boundary region 72, and the diode portion 80. The contact region may be provided between the base region 14 and the upper surface 21. The contact region may be a P+ type region having a higher doping concentration than the base region 14.

[0096] The boundary between the transistor portion 70 and the boundary region 72 may be the center of the trench portion 40 whose lower surface 23 is the collector region 22 and is located between the mesa portion 60 provided with the emitter region 12 and the mesa portion 61 not provided with the emitter region 12. The boundary between the boundary region 72 and the diode portion 80 may be the boundary between the cathode region 82 and the collector region 22.

[0097] Each groove portion 40 penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 to reach the drift region 18. In the region where at least any one of the emitter region 12, the contact region, and the accumulation region 16 is provided, each groove portion 40 also penetrates these doped regions to reach the drift region 18. The groove portion 40 penetrating the doped region is not limited to the structure manufactured in the order of forming the groove portion 40 after forming the doped region. The structure in which the groove portion 40 penetrates the doped region after forming the groove portion 40 is also included in the structure in which the groove portion 40 penetrates the doped region. It should be noted that the bottom of the groove portion 40 may be a curved surface convex to the lower side (curved in the cross section).

[0098] The gate conductive portion 44 can be set longer than the base region 14 in the depth direction. The groove portion 40 at the cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. At least one gate conductive portion 44 of the transistor portion 70 among the gate conductive portions 44 of the plurality of groove portions 40 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel obtained by an inversion layer of electrons is formed in the surface layer of the interface in the base region 14 that is in contact with the gate groove portion 40. As a result, in the transistor portion 70, the main current flows between the emitter electrode 52 and the collector electrode 24.

[0099] Figure 5 It is shown Figure 3 BB' cross section is an XZ cross section passing through the emitter region 12, the sensing well region 28 and the active well region 29 of the current sensing portion 26. In the BB' cross section, the semiconductor device 100 includes a semiconductor substrate 10, a collector electrode 24, an interlayer insulating film 38, a gate insulating film 42, a current sensing gate channel 51, an emitter electrode 52, a sensing emitter electrode 56 and a first gate channel 50.

[0100] The interlayer insulating film 38 is disposed on the upper surface 21 of the semiconductor substrate 10. The emitter electrode 52, the sensing emitter electrode 56 and the first gate runner 50 are disposed above the interlayer insulating film 38. The sensing emitter electrode 56 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The sensing emitter electrode 56 is formed of a metal material such as aluminum. The collector electrode 24 is disposed on the lower surface 23 of the semiconductor substrate 10.

[0101] On the upper surface 21 of the semiconductor substrate 10 , the sensing emitter electrode 56 is separated from the emitter electrode 52 . The sensing emitter electrode 56 is connected to the emitter electrode 52 via a sensing resistor. The first gate runner 50 is disposed between the sensing emitter electrode 56 and the emitter electrode 52 .

[0102] In the depth direction, a current sensing gate channel 51 is provided between the sensing emitter electrode 56, the first gate channel 50, and the emitter electrode 52 and the upper surface 21 of the semiconductor substrate 10. The current sensing gate channel 51 is electrically insulated from the semiconductor substrate 10 by the gate insulating film 42 extended from the upper surface 21 of the semiconductor substrate 10. In the BB' cross section, the current sensing gate channel 51 is insulated from the sensing emitter electrode 56, the first gate channel 50, and the emitter electrode 52 by the interlayer insulating film 38. In other cross sections, the current sensing gate channel 51 can be connected to the first gate channel 50. In other cross sections, the current sensing gate channel 51 can be connected to the gate conductive portion 44 of the current sensing portion 26. The first gate channel 50 and the current sensing gate channel 51 can apply a gate voltage to the gate conductive portion 44 of the current sensing portion 26.

[0103] The sensing emitter electrode 56 is electrically connected to the sensing well region 28 via the contact hole 54 provided in the interlayer insulating film 38 and the P+ contact region 17 or the base region 14. The first gate runner 50 is electrically insulated from the active well region 29 by the interlayer insulating film 38. The sensing well region 28 and the active well region 29 are P+ type regions connected to the upper surface 21 of the semiconductor substrate 10. In the depth direction, the sensing well region 28 and the active well region 29 can be provided deeper than the base region 14, or deeper than the groove portion 40.

[0104] The current sensing portion 26 includes a drift region 18 of a first conductivity type and a base region 14 of a second conductivity type disposed between the drift region 18 and the upper surface 21 of the semiconductor substrate 10. The current sensing portion 26 includes a plurality of groove portions 40 disposed inward from the upper surface 21 of the semiconductor substrate 10. The groove portions 40 of this example are arranged along the first direction and have long sides in the second direction.

[0105] The current sensing portion 26 has a mesa portion 63 which is a region between the groove portions 40. In this example, the mesa portion 63 is provided between the groove portions 40 in the first direction and extends in the second direction. In the mesa portion 63, an emitter region 12, a base region 14, and an accumulation region 16 are provided from the upper surface 21 in the same manner as the transistor portion 70. The current sensing portion 26 has a P+ type collector region 22 on the lower surface 23. The configuration of the current sensing portion 26 and the function of each component may be the same as those of the transistor portion 70.

[0106] The emitter region 12 and the accumulation region 16 may not be provided in the mesa portion 63 provided at the end of the current sensing portion 26 in the first direction. The emitter region 12 and the accumulation region 16 may not be provided in the region between the groove portion 40 and the sensing well region 28 provided at the end of the current sensing portion 26 in the first direction.

[0107] The distance between the trench portion 40 disposed at the end of the current sensing portion 26 in the first direction and the sensing well region 28 in the first direction is set to D4. The distance D4 may be smaller than the distance D5 between the trench portion 40 disposed at the end of the transistor portion 70 in the first direction and the active well region 29 in the first direction (see Figure 6 ). As a result, the distance between the current sensing portion 26 and the sensing well region 28 becomes smaller, so that holes flowing from the transistor portion 70 can be further extracted through the sensing well region 28, and the accumulation of carriers can be suppressed. At this time, a P+ contact region 17 can also be provided on the surface side of the base region 14 adjacent to the sensing well region 28. For example, the P+ contact region 17 is provided in a manner that is in contact with the inner periphery of the sensing well region 28 and surrounds the current sensing portion 26. As a result, holes flowing into the sensing well region 28 can be easily extracted.

[0108] In a cross section different from the BB' cross section, a contact region of the second conductivity type may be provided in the current sensing portion 26. The contact region may be provided between the base region 14 and the upper surface 21. The contact region may be a P+ type region having a higher doping concentration than the base region 14. By providing the contact region in the current sensing portion 26, holes flowing from the transistor portion 70 can be extracted through the contact region.

[0109] The interval between the groove portions 40 of the current sensing portion 26 in the first direction is set to D3. The interval D3 may be larger than the interval D2 (refer to Figure 4 ). As a result, the area of ​​the contact region of the current sensing unit 26 is increased, and holes can be further extracted.

[0110] Figure 6 It is shown Figure 2 FIG. 1 is a diagram showing an example of a CC' cross section in FIG. The CC' cross section is an XZ cross section passing through the emitter region 12, the active well region 29 and a portion of the edge termination structure 90 of the transistor portion 70. In the CC' cross section, the semiconductor device 100 includes a semiconductor substrate 10, a collector electrode 24, an interlayer insulating film 38, an emitter electrode 52, a first gate flow channel 50 and a field plate 94. The configuration of the transistor portion 70 can be the same as Figure 4 The transistor portion 70 described in is the same.

[0111] In the semiconductor substrate 10, an active well region 29 is provided between the edge termination structure portion 90 and the transistor portion 70. The active well region 29 is a P+ type region in contact with the upper surface 21 of the semiconductor substrate 10. A portion of the trench portion 40 may be arranged at a position overlapping with the active well region 29.

[0112] An interlayer insulating film 38 covering the source well region 29 may be provided on the upper surface 21 of the semiconductor substrate 10. Electrodes and wiring such as an emitter electrode 52 and a first gate runner 50 are provided above the interlayer insulating film 38. The emitter electrode 52 is provided so as to extend from above the active portion 120 to above the active well region 29. The emitter electrode 52 may be connected to the active well region 29 via a contact hole 54 provided in the interlayer insulating film 38.

[0113] The first gate runner 50 is disposed between the emitter electrode 52 and the edge termination structure portion 90. The emitter electrode 52 and the first gate runner 50 are disposed apart from each other. The first gate runner 50 is electrically insulated from the active well region 29 by the interlayer insulating film 38.

[0114] The edge termination structure 90 is provided with a plurality of guard rings 92, a plurality of high concentration regions 202, and a plurality of field plates 94. The guard ring 92 in this example is a P+ type semiconductor region formed by ion implantation near the upper surface 21. The guard ring 92 can be formed by selectively implanting a P type dopant such as boron from the upper surface 21 of the semiconductor substrate 10 and performing a heat treatment. The depth of the bottom of the guard ring 92 can be the same as the depth of the bottom of the active well region 29, or the depth of the bottom of the guard ring 92 can be different from the depth of the bottom of the active well region 29.

[0115] The upper surface of the guard ring 92 is covered by the interlayer insulating film 38. The field plate 94 is formed of a metal such as aluminum or a conductive material such as polysilicon. The field plate 94 can be formed of an aluminum-silicon alloy, such as a metal alloy such as AlSi, AlSiCu, etc. The field plate 94 can be formed of the same material as the first gate flow channel 50 or the emitter electrode 52. The field plate 94 is disposed on the interlayer insulating film 38. The field plate 94 of this example is connected to the guard ring 92 through a contact hole 54 disposed in the interlayer insulating film 38.

[0116] In the edge termination structure portion 90, a collector region 22 may be provided in a region in contact with the lower surface 23. Each guard ring 92 may be provided on the upper surface 21 in a manner of surrounding the active portion 120. The plurality of guard rings 92 may have a function of extending the depletion layer generated in the active portion 120 to the outside of the semiconductor substrate 10. Thus, the electric field concentration inside the semiconductor substrate 10 may be prevented, and the withstand voltage of the semiconductor device 100 may be improved.

[0117] The distance in the first direction between the groove portion 40 provided at the end of the transistor portion 70 in the first direction and the active well region 29 is set to D5. The emitter region 12 and the accumulation region 16 may not be provided between the groove portion 40 provided at the end of the transistor portion 70 in the first direction and the active well region 29. The P+ contact region 17 may be provided on the surface side of the base region 14 between the groove portion 40 provided at the end of the transistor portion 70 in the first direction and the active well region 29.

[0118] Figure 7 is a top view of the mesa portion 60 of the transistor portion 70 and the mesa portion 63 of the current sensing portion 26. Figure 7 The transistor portion 70 and the current sensing portion 26 have an emitter region 12 and a contact region 15. The contact region 15 is a second conductivity type region provided between the base region 14 and the upper surface 21 of the semiconductor substrate 10 and having a higher concentration than the base region 14.

[0119] The area ratio of the contact region 15 to the area of ​​one mesa portion 63 of the current sensing portion 26 is greater than the area ratio of the contact region 15 to the area of ​​one mesa portion 60 of the transistor portion 70. Thus, the area ratio of the contact region 15 of the current sensing portion 26 is increased compared to the transistor portion 70, and holes can be further extracted through the contact region 15.

[0120] In this example, the emitter regions 12 and the contact regions 15 are alternately arranged along the second direction (Y-axis direction). The length W2 of the contact region 15 of the current sensing unit 26 in the second direction may be greater than the length W1 of the contact region 15 of the transistor unit 70 in the second direction. Thus, the area ratio of the contact region 15 of the current sensing unit 26 can be made higher than that of the transistor unit 70, and holes can be further extracted through the contact region 15.

[0121] Figure 8 This is a diagram showing the arrangement of the periphery of the current sensing unit 26 of a measurement sample having a large chip size. Fig. 9 2 is a diagram showing the arrangement of the current sensing unit 26 and its surroundings of a measurement sample having a small chip size. The inventors conducted a study to investigate the active area dependency of the short-circuit withstand capability. Figure 8 as well as Fig. 9 Measurement of the sample shown. A large chip size means that the area of ​​the active portion 120 is large. The area ratio of the area of ​​the active portion 120 to the area of ​​the current sensing portion 26 is set to a predetermined ratio independently of the chip size. In addition, the area obtained by adding the current sensing portion 26 and the sensing well region 28 is constant independently of the chip size. Therefore, when the chip size is large, the area of ​​the current sensing portion 26 also increases accordingly. Along with this, the distance between the transistor portion 70 and the current sensing portion 26 in the second direction decreases. On the other hand, when the chip size is small, the area of ​​the current sensing portion 26 also decreases accordingly. Along with this, the distance between the transistor portion 70 and the current sensing portion 26 in the second direction increases.

[0122] Fig.10 It is a graph showing the measurement results of the active area dependency of the short-circuit withstand capability. Fig.10 The horizontal axis represents the area of ​​the transistor section 70, and the vertical axis represents the current density of the current sensing section 26. It can be seen that the smaller the chip size, that is, the larger the distance between the transistor section 70 and the current sensing section 26, the greater the tolerance. It is believed that this is because the larger the distance between the transistor section 70 and the current sensing section 26, the less the hole flow from the transistor section 70 to the current sensing section 26.

[0123] Fig.11 It is shown Figure 3FIG. 7 is a diagram of another example of region A in FIG. The transistor portion 70 may not be provided between the pad portions 110. The distance Dts between the transistor portion 70 and the current sensing portion 26 in the second direction opposite to the current sensing portion 26 may be greater than the distance Dds between the diode portion 80 and the current sensing portion 26 in the second direction. Thus, the distance between the transistor portion 70 and the current sensing portion 26 can be ensured, and the flow of holes from the transistor portion 70 to the current sensing portion 26 can be suppressed. The distance Dts between the transistor portion 70 and the current sensing portion 26 in the second direction may be greater than 500 μm.

[0124] Although the switching loss increases when holes bypass from the transistor portion 70 to the diode portion 80, some bypass is allowed. On the other hand, if holes bypass from the transistor portion 70 to the current sensing portion 26, the current sensing portion 26 is destroyed due to oscillation. Therefore, the distance Dts between the transistor portion 70 and the current sensing portion 26 relative to the current sensing portion 26 in the second direction may be greater than the width Wi of the boundary area 72 in the first direction. Thus, compared with the bypass of holes from the transistor portion 70 to the diode portion 80, the bypass of holes from the transistor portion 70 to the current sensing portion 26 can be more reliably suppressed. It should be noted that the relationship between the above distance and width is Figure 3 It can also be established in .

[0125] Fig.12 It is shown Figure 3 FIG. 2 is a diagram showing an example of an AB cross section in FIG. The AB cross section is a YZ cross section passing through the transistor section 70 and the current sensing section 26. The configuration of the transistor section 70 and the current sensing section 26 can be different from Figures 1 to 11 The same as any of the structures described in .

[0126] In the second direction, a region of the first conductivity type may be provided on the lower surface 23 of the semiconductor substrate 10 between the transistor section 70 and the current sensing section 26. In this example, an N+ type cathode region 82 is provided on the lower surface 23 of the semiconductor substrate 10 between the transistor section 70 and the current sensing section 26. Thus, the flow of holes from the transistor section 70 to the current sensing section 26 can be suppressed.

[0127] In the AB cross section, the upper surfaces of the active well region 29 and the sensing well region 28 are covered by the interlayer insulating film 38. In the AB cross section, a P+ contact region 17 may be provided at the end of the transistor portion 70 connected to the active well region 29. In addition, a P+ contact region 17 may be provided at the end of the current sensing portion 26 connected to the sensing well region 28. The interlayer insulating film 38 may cover a portion of the P+ contact region 17.

[0128] Fig.13 It is shown Figure 3Figures of other examples of the BB' cross section in . In at least one mesa portion 63 of the current sensing portion 26 of this example, there are provided an emitter region 12 of the first conductivity type or a P+ contact region 17 of the second conductivity type disposed between the drift region 18 and the upper surface 21 of the semiconductor substrate 10, a base region 14 of the second conductivity type disposed between the drift region 18 and the upper surface 21 of the semiconductor substrate 10, a trench contact portion 58 disposed from the upper surface 21 of the semiconductor substrate 10 toward the inside, and a bottom P region 19 disposed at the bottom of the trench contact portion 58 in the depth direction. By providing the trench contact portion 58 and the bottom P region 19, the holes flowing around can be extracted and the accumulation of carriers can be suppressed. The trench contact portion 58 may penetrate the emitter region 12 or the P+ contact region 17, or may not penetrate the emitter region 12 or the P+ contact region 17. The bottom P region 19 may be connected to the base region 14. The mesa portion 63 provided at the end of the current sensing portion 26 in the first direction and not provided with the emitter region 12 and the accumulation region 16 may also be provided with the trench contact portion 58 and the bottom P region 19 . Fig.13 The components other than the table portion 63 can be Figure 5 The mesa portion 60 of the transistor portion 70 may not have the trench contact portion 58 and the bottom P region 19 .

[0129] Fig.14 It is shown Figure 2 FIG. 1 is another example of an enlarged view of region A in FIG. Figure 2 The difference between the region A shown in FIG. 1 and FIG. 2 is that a contact hole 154 is provided when viewed from above. Figure 2 The same, so the description is omitted.

[0130] A contact hole 154 may be provided between the transistor section 70 and the current sensing section 26 in the second direction. In this example, a contact hole 154-1 and a contact hole 154-2 are provided. The contact hole 154-1 connects the active well region 29 to the electrode. The contact hole 154-2 connects the sensing well region 28 to the electrode.

[0131] Only one of the contact hole 154 - 1 and the contact hole 154 - 2 may be provided, or both may be provided. A plurality of contact holes 154 - 1 may be provided in the X-axis direction.

[0132] Fig.15 It is shown Fig.14 The AB section in this example is the same as Fig.12 The AB cross section shown is different in that the contact hole 154 and the extraction trench contact portion 156 are provided, and the boundary between the emitter electrode 52 and the sensing emitter electrode 56 is located on the negative side in the Y-axis direction. Figure 2 The same, so the description is appropriately omitted.

[0133] The semiconductor device 100 of this example also includes an interlayer insulating film 38 provided on the upper surface 21 of the semiconductor substrate 10. A sense emitter electrode 56 is provided above the interlayer insulating film 38. The interlayer insulating film 38 has a contact hole 154-2 between the transistor portion 70 and the current sensing portion in the second direction. The contact hole 154-2 of this example is provided above the sense well region 28.

[0134] The sensing emitter electrode 56 and the sensing well region 28 are connected via the contact hole 154 - 2 , thereby further extracting holes flowing around the current sensing unit 26 .

[0135] An upper surface electrode may be provided above the interlayer insulating film 38. The upper surface electrode may be the emitter electrode 52 provided above the transistor portion 70, or may be the sensing emitter electrode 56. The semiconductor device 100 may include a well region of the second conductivity type provided between the transistor portion 70 and the sensing well region 28 in the second direction. The well region may be an active well region 29 surrounding the transistor portion 70 and the diode portion 80 in a plan view, or may be an active well region 29 not surrounding the transistor portion 70 and the diode portion 80, or may be another region of the second conductivity type.

[0136] The interlayer insulating film 38 may have a contact hole 154-1 between the transistor portion 70 and the sensing well region 28 in the second direction. The upper surface electrode and the well region may be connected via the contact hole 154-1. Thus, holes flowing around the current sensing portion 26 can be further extracted.

[0137] In this example, the emitter electrode 52 is connected to the active well region 29 via the contact hole 154-1. In other examples, the emitter electrode 52 can be connected to the active well region 29 that does not surround the transistor portion 70 and the diode portion 80, and the sensing emitter electrode 56 can be connected to other second conductivity type regions via the contact hole 154-1. The position of the contact hole 154-1 in the second direction can be appropriately adjusted within the range between the transistor portion 70 and the sensing well region 28 according to the connected upper surface electrode.

[0138] At the lower ends of the contact holes 154-1 and 154-2, there are provided extraction trench contacts 156-1 and 156-2 formed from the upper surface 21 of the semiconductor substrate 10 toward the inside. Thus, the effect of extracting holes is further improved. The extraction trench contact 156 may have the same depth as the trench contact provided in the active part 120, or may have a different depth from the trench contact provided in the active part 120. The extraction trench contact 156 may be the same depth as the trench contact 58 provided in the current sensing part 26 (see FIG. 2 ). Fig.13), or a different depth from the trench contact portion 58 provided in the current sensing portion 26. The width of the extraction trench contact portion 156 may be wider than the width of the trench contact portion provided in the active portion 120, or the same as the width of the trench contact portion provided in the active portion 120. The width of the extraction trench contact portion 156 may be wider than the width of the trench contact portion 58 provided in the current sensing portion 26, or the same as the width of the trench contact portion 58 provided in the current sensing portion 26.

[0139] The length of the contact hole 154-1 in the first direction is L1 (refer to Fig.14 ). In addition, the length of the contact hole 154-2 in the first direction is set to L2 (refer to Fig.14 ). The length L1 and the length L2 may be greater than at least one of the width Wt of the transistor section 70 opposite to the current sensing section 26 and the width Ws of the current sensing section 26. Thus, the holes flowing from the transistor section 70 can be extracted before reaching the current sensing section 26. The length L1 and the length L2 may be greater than any one of the width Wt of the transistor section 70 opposite to the current sensing section 26 and the width Ws of the current sensing section 26. In addition, the length L1 may be greater than the length L2.

[0140] The contact hole 154-1 may be provided to surround the current sensing portion 26. Similarly, the contact hole 154-2 may be provided to surround the current sensing portion 26. Thus, the holes flowing around the current sensing portion 26 can be further extracted. The contact hole 154-1 and the contact hole 154-2 may also be provided in discrete point shapes.

[0141] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

Claims

1. A semiconductor device, characterized in that: A semiconductor substrate is provided, The semiconductor substrate has: transistor portions and diode portions which are alternately arranged along the first direction and have long sides in the second direction; and a current sensing portion arranged opposite to the transistor portion in the second direction, The transistor section, the diode section and the current sensing section have: A drift region of a first conductivity type; and A base region of a second conductivity type is disposed between the drift region and the upper surface of the semiconductor substrate, In a plan view, the current sensing portion is surrounded by a second conductive type sensing well region, and the second conductive type sensing well region is set to have a concentration higher than that of the base region and deeper from the upper surface than the base region. In the first direction, the sensing well region has a width greater than a width of the transistor portion opposite to the current sensing portion.

2. The semiconductor device according to claim 1, wherein: The semiconductor substrate has an active well region, and the active well region surrounds the transistor portion and the diode portion in a plan view. The sensing well region is disposed inside the active well region in a plan view.

3. The semiconductor device according to claim 2, wherein: A plurality of pad portions are disposed above the active well region, The current sensing portion is disposed between the two pad portions in the first direction.

4. The semiconductor device according to claim 3, wherein: At least a portion of the transistor portion that is opposed to the current sensing portion is located between the pad portions.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The transistor unit has: An emitter region of the first conductivity type, which is disposed on the upper surface; as well as A collector region of the second conductivity type is disposed on the lower surface of the semiconductor substrate, The diode portion does not have the emitter region on the upper surface, but has a cathode region of the first conductivity type provided on the lower surface. The semiconductor substrate further comprises a boundary region, which is disposed between the transistor portion and the diode portion, has no emitter region on the upper surface, and has the collector region on the lower surface. An outer peripheral end position of the sensing well region in the first direction is opposite to the boundary region in the second direction.

6. The semiconductor device according to any one of claims 2 to 4, characterized in that The transistor section and the current sensing section have a plurality of groove sections provided from the upper surface of the semiconductor substrate toward the inside, the plurality of groove sections are arranged along the first direction and have long sides in the second direction, A distance between the trench portion disposed at the endmost portion of the current sensing portion in the first direction and the sensing well region in the first direction is smaller than a distance between the trench portion disposed at the endmost portion of the transistor portion in the first direction and the active well region in the first direction.

7. The semiconductor device according to any one of claims 2 to 4, characterized in that The sensing well region has an inner peripheral end facing the current sensing portion in a plan view and an outer peripheral end opposite to the inner peripheral end. Compared with the distance between the active well region and the sensing well region, the width between the inner peripheral end and the outer peripheral end of the sensing well region is larger.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that The transistor section and the current sensing section have: a plurality of groove portions disposed inwardly from the upper surface of the semiconductor substrate; and a land portion, which is a region between the groove portions; as well as a contact region of a second conductivity type, which is disposed between the base region and the upper surface of the semiconductor substrate and has a concentration higher than that of the base region, An area ratio of the contact region with respect to an area of ​​one of the mesa portions of the current sensing portion is larger than the area ratio of the transistor portion.

9. The semiconductor device according to claim 8, wherein: The length of the contact region of the current sensing portion in the second direction is greater than the length of the contact region of the transistor portion in the second direction.

10. The semiconductor device according to any one of claims 1 to 4, characterized in that The transistor section and the current sensing section have a plurality of groove sections arranged from the upper surface of the semiconductor substrate toward the inside, the plurality of groove sections are arranged along a first direction and have long sides in a second direction, An interval between the trench portions of the current sensing portion in the first direction is greater than an interval between the trench portions of the transistor portion in the first direction.

11. The semiconductor device according to any one of claims 1 to 3, characterized in that A distance between the transistor portion and the current sensing portion in the second direction relative to the current sensing portion is greater than a distance between the diode portion and the current sensing portion in the second direction.

12. The semiconductor device according to any one of claims 1 to 4, characterized in that The semiconductor substrate has a boundary region disposed between the transistor portion and the diode portion, A distance between the transistor portion opposite to the current sensing portion in the second direction and the current sensing portion is greater than a width of the boundary region in the first direction.

13. The semiconductor device according to any one of claims 1 to 4, characterized in that In the second direction, a region of the first conductivity type is provided on the lower surface of the semiconductor substrate between the transistor portion and the current sensing portion.

14. The semiconductor device according to any one of claims 1 to 3, characterized in that A distance between the transistor portion and the current sensing portion in the second direction is 500 μm or more.

15. The semiconductor device according to any one of claims 1 to 4, characterized in that The current sensing unit has: a plurality of groove portions disposed inwardly from the upper surface of the semiconductor substrate; and a land portion, which is a region between the groove portions, At least one of the table sections is provided with: an emitter region of a first conductivity type, disposed between the drift region and the upper surface of the semiconductor substrate; the base region; as well as A trench contact portion is provided from the upper surface of the semiconductor substrate toward the inside.

16. The semiconductor device according to claim 15, wherein: The transistor unit has: a plurality of said groove portions; and The countertop portion, The mesa portion of the transistor portion does not have the trench contact portion.

17. The semiconductor device according to any one of claims 1 to 4, characterized in that The width of the current sensing portion in the first direction is smaller than the width of the transistor portion opposite to the current sensing portion in the first direction.

18. The semiconductor device according to any one of claims 1 to 4, characterized in that An inner peripheral end portion of the sensing well region in the first direction is located opposite to the transistor portion in the second direction.

19. The semiconductor device according to claim 1, wherein: The semiconductor device comprises: an interlayer insulating film disposed on the upper surface of the semiconductor substrate; and a sensing emitter electrode disposed above the interlayer insulating film, The interlayer insulating film has a contact hole between the transistor section and the current sensing section in the second direction, The sensing emitter electrode is connected to the sensing well region via the contact hole.

20. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: an interlayer insulating film disposed on the upper surface of the semiconductor substrate; an upper surface electrode disposed above the interlayer insulating film; as well as a well region of a second conductivity type, which is disposed between the transistor portion and the sensing well region in the second direction, The interlayer insulating film has a contact hole between the transistor portion and the sensing well region in the second direction, The upper surface electrode and the well region are connected via the contact hole.

21. The semiconductor device according to claim 20, wherein: The well region is an active well region surrounding the transistor portion and the diode portion in a plan view, The upper surface electrode is an emitter electrode provided above the transistor portion.

22. The semiconductor device according to any one of claims 19 to 21, characterized in that In the first direction, the length of the contact hole is greater than at least one of a width of the transistor portion opposite to the current sensing portion and a width of the current sensing portion.

23. The semiconductor device according to any one of claims 19 to 21, characterized in that A lead-out trench contact portion formed from the upper surface of the semiconductor substrate toward the inside is provided at the lower end of the contact hole.

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