Wafer cutting method and device and bare chip

Abstract

The invention relates to the technical field of semiconductor manufacturing, and discloses a wafer cutting method and device and a bare die, a wafer comprises a metal layer and a substrate layer, the wafer cutting method comprises the steps that picosecond laser is used for forming two protection grooves in each cutting channel in the wafer, and the depth of the protection grooves is larger than the thickness of the metal layer in the cutting channels; a wide groove is formed in the area between the two protection grooves of each cutting channel through wide laser, and the wide groove and the protection groove in the same cutting channel are connected; a picosecond laser is used for conducting fine trimming on the edge area of the protection groove of each cutting channel, and slag in the edge areas of the protection grooves is removed; and carrying out implicit cutting on the substrate layer part corresponding to the wide groove of each cutting channel by using implicit cutting laser. By adopting a combined process of picosecond laser grooving, wide-beam laser cutting and implicit cutting laser cutting, the problems of large heat affected zone, rough surface, internal stress accumulation and back collapse are solved, and the stress resistance and the overall reliability of the bare chip are remarkably improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, for example, to a wafer cutting method and equipment, and a bare chip. Background Art

[0002] With the development of the semiconductor industry, the market demand for high-performance, low-cost chips is growing. In order to meet this demand, the wafer manufacturing process is constantly optimized to reduce costs while improving the performance and reliability of bare chips. Especially for wafers made of Low-K materials, the wafer cutting process of related technologies faces many challenges.

[0003] In the related art, the common wafer cutting process mainly relies on nanosecond laser grooving combined with blade or water jet cutting. However, due to its long pulse width, nanosecond laser will produce significant thermal effects during the cutting process, causing local melting and recasting of the material, forming a large heat-affected zone. This not only increases the surface roughness, but may also store additional stress inside the chip, reducing the stress resistance of the die. In addition, blade or water jet cutting methods are prone to back collapse, that is, leaving microcracks or other forms of mechanical damage on the back of the wafer, seriously affecting the quality and reliability of the chip.

[0004] In summary, the wafer cutting process of nanosecond laser grooving combined with blade or water jet cutting in the related art leads to a larger heat-affected zone, increased surface roughness, internal stress accumulation and back collapse due to thermal effects and mechanical damage, thereby reducing the stress resistance and overall reliability of the bare chip.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The embodiments of the present disclosure provide a wafer cutting method and equipment, and a bare chip. By adopting a combined process of picosecond laser grooving, wide-beam laser cutting, and hidden laser cutting, the problems of large heat-affected zone, rough surface, internal stress accumulation, and back collapse are solved, thereby significantly improving the stress resistance and overall reliability of the bare chip.

[0008] According to a first aspect of the present disclosure, a wafer cutting method is provided, wherein the wafer includes a metal layer and a substrate layer, and the wafer cutting method includes:

[0009] Using a picosecond laser to open two protection grooves in each cutting path in the wafer, wherein the depth of the protection groove is greater than the thickness of the metal layer in the cutting path;

[0010] A wide groove is opened in the area between two protection grooves in each cutting path by using a wide beam laser, wherein the wide groove in the same cutting path is connected to the protection groove;

[0011] Use picosecond laser to fine-tune the edge area of ​​the protection groove of each cutting path to remove the slag in the edge area of ​​the protection groove;

[0012] Use a hidden cutting laser to perform hidden cutting on the substrate layer portion corresponding to the wide groove of each cutting street.

[0013] In some embodiments, using a picosecond laser to open two protection grooves in each scribe line in a wafer includes: using two picosecond lasers to simultaneously scan each scribe line in the wafer to form two protection grooves.

[0014] In some embodiments, using a wide beam laser to open a wide groove in the area between two protection grooves of each cutting street includes: using a wide beam laser to scan the area between the two protection grooves of each cutting street multiple times to form a wide groove between the two protection grooves.

[0015] In some embodiments, a picosecond laser is used to fine-tune the edge area of ​​the protection groove of each cutting road, including: using a picosecond laser to fine-tune the first edge area of ​​the protection groove of each cutting road, wherein the first edge area is a transition area between the top surface of the cutting road and the side wall of the protection groove.

[0016] In some embodiments, a picosecond laser is used to fine-tune the first edge region of the protective groove of each cutting lane, including: using a single picosecond laser to sequentially scan along the first edge of each protective groove of each cutting lane to sequentially fine-tune each first edge region.

[0017] In some embodiments, the slot width of each scribe line is 15 micrometers to 50 micrometers, wherein the slot width is the sum of the widths of two protection slots and one wide slot in the same scribe line.

[0018] In some embodiments, the distance between two protection grooves in the same scribe line is 10 micrometers to 42 micrometers.

[0019] In some embodiments, the diameter of the protrusions on the wide groove surface does not exceed 1.5 microns.

[0020] According to a second aspect of the present disclosure, there is provided a wafer cutting device, comprising a controller, and a picosecond laser, a wide beam laser, and a stealth cutting laser communicatively connected to the controller;

[0021] The controller is configured to execute the wafer cutting method provided by the first aspect of the present disclosure based on a picosecond laser, a wide beam laser and a stealth cutting laser.

[0022] According to a third aspect of the present disclosure, a bare chip is provided, characterized in that it is separated from a wafer using the wafer cutting method provided by the first aspect of the present disclosure.

[0023] The wafer cutting method, equipment, and bare chip provided by the embodiments of the present disclosure can achieve the following technical effects: two protective grooves are opened in each cutting path using a picosecond laser. The cold processing characteristics of the picosecond laser hardly generate heat, thereby avoiding local melting and recasting of the material and significantly reducing the heat-affected zone. A wide groove is then opened in the area between the two protective grooves so that the portion of the substrate layer corresponding to the wide groove of each cutting path can be hidden cut using a hidden cutting laser. Since the hidden cutting laser is a non-contact cutting method, the cutting operation can be completed without damaging the back of the wafer, and basically no back collapse phenomenon will occur, which maximizes the protection of the back of the chip from damage, thereby improving the stress resistance and overall reliability of the bare chip. In summary, by adopting a combination of picosecond laser grooving, wide-beam laser cutting, and hidden laser cutting processes, the problems of large heat-affected zone, rough surface, internal stress accumulation, and back collapse are solved, significantly improving the stress resistance and overall reliability of the bare chip.

[0024] The foregoing general description and the following description are exemplary and explanatory only and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0026] Figure 1 is a schematic diagram of a partial structure of a wafer provided by an embodiment of the present disclosure;

[0027] Figure 2 is a schematic diagram of a portion of a scribe line in a wafer provided by an embodiment of the present disclosure;

[0028] Figure 3 is a schematic diagram of a wafer cutting device provided by an embodiment of the present disclosure;

[0029] Figure 4 It is a schematic diagram of a process of a wafer cutting method provided by an embodiment of the present disclosure;

[0030] Figure 5 is a schematic diagram of providing a protection groove in a cutting path according to an embodiment of the present disclosure;

[0031] Figure 6 This is a schematic diagram comparing nanosecond laser grooved particles and picosecond laser grooved particles;

[0032] Figure 7 This is a schematic diagram comparing the damage caused by nanosecond laser grooving and picosecond laser grooving;

[0033] Figure 8 is a schematic diagram of opening a wide groove in a cutting path provided by an embodiment of the present disclosure;

[0034] Fig. 9 The embodiment of the present disclosure provides Figure 8 A main view of

[0035] Fig.10 The embodiment of the present disclosure provides Fig. 9 A magnified image of point A before refinement;

[0036] Fig.11 The embodiment of the present disclosure provides Fig. 9 The enlarged image of point A after refinement;

[0037] Fig.12 The embodiment of the present disclosure provides Figure 8 Another main view of ;

[0038] Fig.13 is a schematic diagram of a bare chip provided by an embodiment of the present disclosure;

[0039] Fig.14 is a schematic diagram of a bare chip in the related art;

[0040] Fig.15 It is a structural diagram of a controller provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0042] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0043] Unless otherwise stated, the term "plurality" means two or more.

[0044] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0045] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0046] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0047] Combination Figure 1 As shown, the embodiment of the present disclosure shows a partial structure of a wafer, wherein the wafer includes a plurality of dies 100 to be divided, each of which is an independent functional unit. A scribeline 200 is provided between adjacent dies 100, for dividing the wafer into separate dies 100 in a subsequent dicing process.

[0048] Each die 100 on the wafer represents a complete integrated circuit, including all circuit elements and interconnection structures. These die 100 will be cut and separated after manufacturing and packaged into final chip dies. The dicing lane 200 is a non-functional area located between adjacent dies 100, and the width is usually tens of microns to hundreds of microns. The dicing lane 200 not only provides operating space for the cutting tool, but also is used to accommodate defects or damage that may occur during the process to ensure the integrity and functionality of each die 100.

[0049] Figure 2 is a schematic diagram of a portion of a scribe line 200 in a wafer, combined with Figure 2 As shown, the wafer includes a metal layer 201 and a substrate layer 202. The metal layer 201 is a conductive material layer formed on the wafer by processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating. The substrate is the basic structure of the wafer, usually made of semiconductor materials such as single crystal silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), etc. It is the basis of all subsequent processing steps and determines the basic electrical properties and mechanical support of the final chip.

[0050] Combination Figure 3 As shown, the embodiment of the present disclosure provides a wafer cutting device, which includes a controller 1, a picosecond laser 2, a wide beam laser 3 and a hidden cutting laser 4, and the picosecond laser 2, the wide beam laser and the hidden cutting laser 4 are all connected to the controller 1 in communication. The controller 1 can perform a wafer cutting method based on the picosecond laser 2, the wide beam laser and the hidden cutting laser 4, so as to obtain a bare die 100 on the wafer.

[0051] In combination with the wafer cutting device provided by the embodiment of the present disclosure, the embodiment of the present disclosure provides a wafer cutting method, which is executed by a controller 1 based on a picosecond laser 2, a wide beam laser and a hidden cutting laser 4, such as Figure 4 As shown, the wafer dicing method includes:

[0052] S401 , the controller 1 uses a picosecond laser to open two protection grooves 203 in each dicing street 200 in the wafer.

[0053] S402 , the controller 1 uses a wide beam laser to open a wide groove 204 in the area between two protection grooves 203 of each cutting street 200 .

[0054] S403 , the controller 1 uses a picosecond laser to fine-tune the edge region of the protection groove 203 of each cutting path 200 to remove slag from the edge region of the protection groove 203 .

[0055] S404 , the controller 1 uses a hidden cutting laser to perform hidden cutting on a portion of the substrate layer 202 corresponding to the wide groove 204 of each cutting street 200 .

[0056] In the disclosed embodiment, picosecond laser grooving is based on the principle of cold laser grooving. Compared with nanosecond laser grooving, picosecond laser grooving generates less heat, thereby reducing the impact of the grooving process on the die, greatly reducing the stress concentrated inside the die during the die grooving process, thereby improving the die's stress resistance.

[0057] In the embodiment of the present disclosure, Figure 5 As shown, combined Figure 5 As shown, the depth of the protection groove 203 is greater than the thickness of the metal layer 201 to ensure that the metal layer 201 is completely cut off and the electrical connection between the scribe line 200 (non-functional area) and the die 100 (functional area) is disconnected.

[0058] In some embodiments, the controller 1 may control the picosecond laser 2 to emit a picosecond laser to scan the cutting road 200 along a scanning path in the extending direction of the cutting road 200 , thereby forming two protective grooves 203 on the scanning path.

[0059] In some embodiments, using a picosecond laser to open two protection grooves 203 in each cutting street 200 in a wafer includes: using two picosecond laser beams to simultaneously scan each cutting street 200 in the wafer to form two protection grooves 203. Specifically, the controller 1 can control the picosecond laser 2 to emit two picosecond laser beams, and two parallel scanning paths along the extension direction of the cutting street 200 are simultaneously scanned in the cutting street 200, so as to form the protection grooves 203 respectively on the two scanning paths, so as to obtain the two protection grooves 203 at the same time.

[0060] Figure 6 Schematic diagrams showing nanosecond laser grooved particles and picosecond laser grooved particles are shown, Figure 7 Figure 2 shows schematic diagrams of damage caused by nanosecond laser grooving and picosecond laser grooving. Figure 6 It can be seen that the size of the particles produced by using picosecond laser to open the protection groove 203 is significantly smaller than the size of the particles produced by using nano laser. Figure 7 It can be seen that using nanosecond laser to open the protection groove 203 will produce obvious heat-affected zone, surface debris, fine cracks and recast materials, while using nanosecond laser to open the protection groove 203 will not produce obvious heat-affected zone, surface debris, fine cracks and recast materials. Therefore, using picosecond laser to open the protection groove 203 is more delicate. Using picosecond laser to open the protection groove 203 can reduce cracks and damage at the edge of the die 100, thereby reducing the stress effect, which helps to improve the stress resistance of the die 100 in the subsequent three rounds of test layers and improve the yield rate of the die.

[0061] In the disclosed embodiment, a wide beam laser refers to a laser beam that can produce a larger spot size or coverage area on the target surface. The wide beam laser can be a large spot laser, an expanded beam laser, a planar array laser, or a linear laser. Using a wide beam laser to open a wide groove 204 in the area between two protective grooves 203 can improve the groove opening efficiency and shorten the groove opening time.

[0062] In the embodiment of the present disclosure, Figure 8 As shown, the wide groove 204 in the same cutting street 200 is connected to the protection groove 203. In other words, one wide groove 204 and two protection grooves 203 in the same cutting street 200 form a complete recessed area.

[0063] In some embodiments, the controller 1 can control the wide-beam laser 3 to emit a wide-beam laser and scan the cutting road 200 along a scanning path in the extension direction of the cutting road 200. The scanning path is located between two protective grooves 203 of the cutting road 200, thereby realizing the opening of a wide groove 204 in the area between the two protective grooves 203.

[0064] In some embodiments, a wide-beam laser is used to open a wide groove 204 in a region between two protection grooves 203 of each cutting road 200, including: using a wide-beam laser to scan a region between two protection grooves 203 of each cutting road 200 multiple times, so as to form a wide groove 204 between the two protection grooves 203. Specifically, the controller 1 can control the wide-beam laser 3 to emit a wide-beam laser, and scan the cutting road 200 multiple times along a scanning path in the extension direction of the cutting road 200, and the scanning path is located between the two protection grooves 203 of the cutting road 200, so as to realize opening a wide groove 204 in a region between the two protection grooves 203.

[0065] Combination Fig. 9 and Fig.10 As shown, the process of using a wide beam laser to open a wide groove 204 will generate slag, which will adhere to the surface of the cutting path 200, for example, to the edge area of ​​the protection groove 203. In the embodiment of the present disclosure, after the die 100 is separated from the wafer, the edge area of ​​the protection groove 203 will become the edge area of ​​the die 100. If the edge area of ​​the die 100 is attached with slag and forms a protrusion, it will cause edge defects of the die 100 and become a weak point of the die 100 in resisting stress. Therefore, combined with Fig.11 As shown, by using a picosecond laser to fine-tune the edge area of ​​the protection groove 203 of each cutting path 200 to remove the slag in the edge area of ​​the protection groove 203, the edge defects of the die 100 can be reduced, which helps to improve the stress resistance of the die 100 in the subsequent three rounds of test layers and improve the yield rate of the die.

[0066] In the disclosed embodiment, the controller 1 can control the picosecond laser 2 to emit a picosecond laser to scan along the edge area of ​​the protection groove 203 of the cutting path 200 to remove the slag at the edge area of ​​the protection groove 203 .

[0067] In some embodiments, the edge region of the protection groove 203 of each cutting street 200 is finely trimmed using a picosecond laser, including: using a picosecond laser to finely trim the first edge region 205 of the protection groove 203 of each cutting street 200. Specifically, the controller 1 can control the picosecond laser 2 to emit a picosecond laser, scan along the first edge region 205 of the protection groove 203 of the cutting street 200, and remove the slag in the edge region of the protection groove 203.

[0068] Here, the first edge area 205 is the transition area between the top surface of the cutting path 200 and the side wall of the protective groove 203. The top surface of the cutting path 200 and the front surface of the bare chip 100 belong to the same plane. Therefore, the first edge area 205 is the area connected to the bare chip 100. By targetedly fine-tuning the first edge area 205 of the protective groove 203, the slag causing the edge defects of the bare chip 100 can be effectively removed, and the laser usage time during the fine-tuning process can be reduced, thereby improving the overall efficiency.

[0069] In some embodiments, the first edge region 205 of the protection groove 203 of each cutting path 200 is finely trimmed using a picosecond laser, including: using a single-beam picosecond laser to sequentially scan along the first edge of each protection groove 203 of each cutting path 200, so as to sequentially fine-tune each first edge region 205. Specifically, the controller 1 can control the picosecond laser 2 to emit a single-beam picosecond laser to sequentially scan along the first edge region 205 of each protection groove 203 of the cutting path 200 in a preset order, so as to sequentially remove the slag in the first edge region 205 of each protection groove 203.

[0070] In the embodiment of the present disclosure, the controller 1 can control the hidden cutting laser 4 to emit a hidden cutting laser, and scan the wide groove 204 area in the cutting road 200 along a scanning path in the extension direction of the cutting road 200, thereby realizing hidden cutting of the substrate layer 202 portion corresponding to the wide groove 204 of the cutting road 200.

[0071] In the disclosed embodiment, the hidden cutting laser can be a nanosecond infrared laser, and the hidden cutting laser 4 is a laser capable of emitting nanosecond infrared laser. Hidden cutting is a non-contact, internally modified cutting method used in the wafer cutting process. The working principle of hidden cutting technology is to use a nanosecond pulsed infrared laser to focus on a specific depth inside the wafer, where the material is modified (such as forming microcracks) by absorbing the laser energy without causing obvious damage to the surface. Afterwards, after appropriate stress treatment (such as sticking strips and bending wafers), these internal microcracks will expand into complete cutting lines, thereby achieving wafer separation. This method can reduce the edge damage and debris problems that may be caused by traditional cutting methods, reduce back collapse, and improve cutting accuracy and yield.

[0072] The wafer cutting method provided by the embodiment of the present disclosure uses a picosecond laser to open two protective grooves 203 in each cutting path 200. The cold processing characteristics of the picosecond laser hardly generate heat, thereby avoiding local melting and recasting of the material and significantly reducing the heat affected zone. Afterwards, a wide groove 204 is opened in the area between the two protective grooves 203 so that the substrate layer 202 corresponding to the wide groove 204 of each cutting path 200 can be cut by using a hidden cutting laser. Since the hidden cutting laser is a non-contact cutting method, the cutting operation can be completed without damaging the back of the wafer, and basically no back collapse phenomenon will occur, which maximizes the protection of the back of the chip from damage, thereby improving the stress resistance and overall reliability of the die. The above method is suitable for wafer segmentation tasks of Low-K materials. In summary, by adopting a combined process of picosecond laser grooving, wide beam laser cutting and hidden cutting laser cutting, the problems of large heat affected zone, rough surface, internal stress accumulation and back collapse are solved, and the stress resistance and overall reliability of the die are significantly improved.

[0073] Furthermore, since slag is generated during the wide beam laser grooving process, the slag may cause defects in subsequent processes or affect the quality of the die. Therefore, a picosecond laser is used to fine-tune the edge area of ​​the protection groove 203 of each cutting path 200 to remove the slag in the edge area of ​​the protection groove 203. The high precision and non-thermal absorption mechanism of the picosecond laser make this process very delicate, and can effectively remove any residue without damaging the surrounding materials, ensuring the cleanliness and flatness of the cutting path 200, which can reduce the edge defects of the die 100, help improve the stress resistance of the die 100 in the subsequent three rounds of test layers, and improve the yield rate of the die.

[0074] In the embodiment of the present disclosure, the slot width of each cutting path is 15 micrometers to 50 micrometers, wherein the slot width is the sum of the widths of two protection slots and one wide slot in the same cutting path. Fig.12 As shown, the slot width of the cutting path is L1 in the figure. Since the total width of the two protection grooves 203 and the wide groove 204 can be as low as 15 microns, the size of the cutting path 200 can be further reduced, so that the wafer cutting method provided by the embodiment of the present disclosure can be applied to the task of wafer cutting with a cutting path 200 width of 30um to 80um.

[0075] In the embodiment of the present disclosure, the distance between two protection grooves 203 in the same dicing street 200 is 10 micrometers to 42 micrometers. Fig.12 As shown, the distance between two protection grooves 203 in the same cutting street 200 is L2 in the figure.

[0076] In the embodiment of the present disclosure, the diameter of the protrusion on the surface of the wide groove 204 does not exceed 1.5 microns, which can ensure that the surface of the wide groove 204 has a high flatness, creating feasible conditions for the subsequent implementation of hidden cutting in the wide groove 204 area. By implementing hidden cutting in the wide groove 204, the edge damage and debris problems that may be caused by traditional cutting methods can be reduced, the back collapse phenomenon can be reduced, and the cutting accuracy and yield rate can be improved.

[0077] Combination Fig.13 As shown, the embodiment of the present disclosure provides a bare die 100 , which is separated from a wafer using the wafer cutting method provided in the above embodiment. Fig.13 The figure shows a die obtained by using the wafer cutting technology of the related art, and the lower left area of ​​the die has a back collapse phenomenon. Fig.13 and Fig.14 It can be seen that the risk of back collapse of the bare chip 100 obtained by using the wafer cutting method provided by the embodiment of the present disclosure is smaller.

[0078] Combination Fig.15 As shown, an embodiment of the present disclosure provides a controller 1, which includes a processor 11 and a memory 12. Optionally, the controller 1 may also include a communication interface 13 and a bus 14. The processor 11, the communication interface 13, and the memory 12 may communicate with each other through the bus 14. The communication interface 13 may be used for information transmission. The processor 11 may call the logic instructions in the memory 12 to execute the vehicle remote control method of the above embodiment.

[0079] In addition, the logic instructions in the above-mentioned memory 12 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent bare chip.

[0080] The memory 12 is a computer-readable storage medium that can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 11 executes the function application and data processing by running the program instructions / modules stored in the memory 12, that is, the vehicle remote control method in the above embodiment is implemented.

[0081] The memory 12 may include a program storage area and a data storage area, wherein the program storage area may store an application required for operating the device and at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 12 may include a high-speed random access memory and may also include a non-volatile memory.

[0082] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned vehicle remote control method.

[0083] The technical solution of the embodiment of the present disclosure may be embodied in the form of a software bare chip, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0084] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method or device including the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the embodiments may refer to each other. For the methods, bare chips, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0085] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementations should not be considered to reach the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0086] In the embodiments disclosed herein, the disclosed methods and bare chips (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated into a processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

[0087] The flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program bare chips according to the embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different boxes may also occur in an order different from that disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by dedicated hardware-based devices that perform specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A wafer cutting method, wherein the wafer comprises a metal layer and a substrate layer, characterized in that: Wafer dicing methods include: Using a picosecond laser to open two protection grooves in each cutting path in the wafer, wherein the depth of the protection groove is greater than the thickness of the metal layer in the cutting path; A wide groove is opened in the area between two protection grooves in each cutting path by using a wide beam laser, wherein the wide groove in the same cutting path is connected to the protection groove; Use picosecond laser to fine-tune the edge area of ​​the protection groove of each cutting path to remove the slag in the edge area of ​​the protection groove; Use a hidden cutting laser to perform hidden cutting on the substrate layer portion corresponding to the wide groove of each cutting street.

2. The wafer cutting method according to claim 1, characterized in that: Two protection grooves are opened in each cutting path of the wafer using a picosecond laser, including: using two picosecond lasers to scan each cutting path of the wafer at the same time to form two protection grooves.

3. The wafer cutting method according to claim 1, characterized in that: Using a wide beam laser to open a wide groove in the area between two protection grooves of each cutting path includes: using a wide beam laser to scan the area between the two protection grooves of each cutting path for multiple times to form a wide groove between the two protection grooves.

4. The wafer cutting method according to claim 1, characterized in that: Using a picosecond laser to fine-tune the edge area of ​​the protection groove of each cutting path includes: using a picosecond laser to fine-tune the first edge area of ​​the protection groove of each cutting path, wherein the first edge area is the transition area between the top surface of the cutting path and the side wall of the protection groove.

5. The wafer cutting method according to claim 4, characterized in that: The first edge area of ​​the protective groove of each cutting path is refined using a picosecond laser, including: using a single beam of picosecond laser to scan along the first edge of each protective groove of each cutting path in turn to gradually remove the slag in these areas to achieve a refined effect.

6. The wafer cutting method according to any one of claims 1 to 5, characterized in that: The slot width of each cutting street is 15 micrometers to 50 micrometers, wherein the slot width is the sum of the widths of two protection slots and one wide slot in the same cutting street.

7. The wafer cutting method according to any one of claims 1 to 5, characterized in that: The distance between two protection grooves in the same cutting path is 10 microns to 42 microns.

8. The wafer cutting method according to any one of claims 1 to 5, characterized in that: The diameter of the protrusions on the wide groove surface does not exceed 1.5 microns.

9. A wafer cutting device, characterized in that: It includes a controller, and a picosecond laser, a wide beam laser, and a stealth cutting laser that are connected to the controller for communication; The controller is configured to perform the wafer dicing method according to any one of claims 1 to 8 based on a picosecond laser, a wide beam laser, and a stealth cutting laser.

10. A bare chip, characterized in that: It is separated from the wafer using the wafer cutting method described in any one of claims 1 to 8.

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