Micro electro mechanical system device packaging method and structure based on wafer bonding

Abstract

The invention provides a micro electro mechanical system device packaging method and structure based on wafer bonding. The method comprises the following steps: etching the back surface of a device wafer by utilizing a photoetching process to form a first mark, arranging a first dielectric layer on the front surface of the device wafer, arranging a first metal layer on the first dielectric layer to form a wafer device structural layer, and connecting a device to be packaged on the wafer device structural layer; etching the back surface of the cap wafer by utilizing a photoetching process to form a second mark, arranging a second dielectric layer on the front surface of the cap wafer, arranging a second metal layer on the second dielectric layer, and forming a cavity on the cap wafer to form a micro-cap structure layer; and performing photoetching pre-alignment bonding, thinning the back surface of the device wafer, forming a third metal layer according to the etching pattern so as to enable the third metal layer to be connected with the first metal layer, and thinning the back surface of the cap wafer so as to complete packaging of the device to be packaged. According to the method, the wafer-level bonding precision can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of device packaging, and in particular to a micro-electromechanical system device packaging method and structure based on wafer bonding. Background Art

[0002] MEMS (Micro-Electro-Mechanical System) devices such as MEMS inertial devices, oscillators, filters, etc., have a significant impact on their performance during operation due to air damping. Vacuum packaging is a necessary condition to ensure high Q value, low insertion loss, and low energy consumption of the device. According to different processing techniques, MEMS vacuum packaging can be divided into device-level vacuum packaging and wafer-level vacuum packaging. Wafer-level vacuum packaging uses silicon micromachining technology, which can greatly reduce the overall size of the device. At the same time, it can minimize the contamination of water flow and particles in the movable structure of the MEMS device during the dicing process, which is conducive to reducing batch costs and improving product consistency, yield and reliability. At present, there are roughly two technical solutions for realizing wafer-level packaging of MEMS products, one is based on thin film deposition and sacrificial layer corrosion, and the other is based on wafer bonding. Traditional wafer-level bonding lacks a high-precision alignment solution, making it difficult to control the bonding accuracy, which makes it easy to cause displacement during wafer bonding. Summary of the invention

[0003] The object of the present invention is to provide a micro-electromechanical system device packaging method and structure based on wafer bonding, so as to solve the technical problem of low bonding accuracy in the prior art.

[0004] The technical solution of the present invention is as follows: a method for packaging a micro-electromechanical system device based on wafer bonding is provided, comprising:

[0005] Etching on the back side of the device wafer by using a photolithography process to form a first mark, setting a first dielectric layer on the front side of the device wafer, setting a first metal layer on the first dielectric layer, etching the first metal layer to form a wafer device structure layer, and connecting the device to be packaged on the wafer device structure layer through a connector;

[0006] Using a photolithography process to etch on the back side of the cap wafer according to the position of the first mark to form a second mark, setting a second dielectric layer on the front side of the cap wafer, setting a second metal layer on the second dielectric layer, etching the second metal layer, etching the second dielectric layer according to the etched second metal layer, etching the cap wafer using an inductively coupled plasma process, forming a cavity on the cap wafer to form a micro-cap structure layer;

[0007] The wafer device structure layer and the micro-cap structure layer are photolithographically pre-aligned and bonded according to the first mark and the second mark, the back side of the device wafer of the wafer device structure layer is thinned, the thinned device wafer and the first dielectric layer are etched to obtain an etching pattern, a third metal layer is formed according to the etching pattern to connect the third metal layer to the first metal layer, and the back side of the cap wafer of the micro-cap structure layer is thinned to complete the packaging of the device to be packaged.

[0008] Furthermore, the process of etching the back side of the device wafer by photolithography to form a first mark and remove the first photoresist layer includes:

[0009] A first protective layer is set on the front side of the device wafer, and photoresist is coated on the back side of the device wafer to form a first photoresist layer. The back side of the device wafer is etched using a photolithography process to form a first mark, and the first photoresist layer and the first protective layer are removed.

[0010] Furthermore, a first dielectric layer is provided on the front side of the device wafer, a first metal layer is provided on the first dielectric layer, and the first metal layer is etched to form a wafer device structure layer, including:

[0011] A first dielectric layer is arranged on the front side of the device wafer, a first metal layer is arranged on the first dielectric layer, a first photoresist layer with a pattern is arranged on the first metal layer, the first metal layer is etched according to the pattern of the first photoresist layer, the first photoresist layer is removed, and a wafer device structure layer is formed.

[0012] Further, the etching on the back side of the cap wafer according to the position of the first mark by using a photolithography process to form a second mark includes:

[0013] A second protective layer is set on the front side of the cap wafer, and photoresist is coated on the back side of the cap wafer to form a second photoresist layer. A photolithography process is used to etch on the back side of the cap wafer according to the position of the first mark to form a second mark, and the second photoresist layer and the second protective layer are removed, wherein the positions of the second mark and the first mark correspond.

[0014] Further, a second dielectric layer is provided on the front side of the cap wafer, a second metal layer is provided on the second dielectric layer, the second metal layer is etched, and the second dielectric layer is etched according to the etched second metal layer, including:

[0015] A second dielectric layer is arranged on the front side of the cap wafer, a second metal layer is arranged on the second dielectric layer, a second photoresist layer with a pattern is arranged on the second metal layer, the second metal layer is etched according to the pattern of the second photoresist layer, the second photoresist layer is removed, and the second dielectric layer is etched according to the etched second metal layer.

[0016] Further, the back side of the device wafer of the wafer device structure layer is thinned, and the thinned device wafer and the first dielectric layer are etched to obtain an etching pattern, including:

[0017] A first blue film layer is arranged on the back side of the cap wafer of the micro-cap structure layer, the back side of the device wafer of the wafer device structure layer is thinned, the first blue film layer is removed, a third photoresist layer with a pattern is arranged on the back side of the thinned device wafer, the thinned device wafer and the first dielectric layer are etched according to the pattern of the third photoresist layer to obtain an etching pattern, and the third photoresist layer is removed.

[0018] Further, forming a third metal layer according to the etching pattern so that the third metal layer is connected to the first metal layer includes:

[0019] A fourth photoresist layer with a pattern is disposed on the back side of the etched device wafer, and a third metal layer is formed according to the pattern of the fourth photoresist layer and the etching pattern, so that the third metal layer is connected to the first metal layer.

[0020] Further, the back side of the cap wafer of the micro-cap structure layer is thinned to complete the packaging of the device to be packaged, including:

[0021] The fourth photoresist layer is removed, a second blue film layer is set on the back side of the etched device wafer, the back side of the cap wafer of the micro-cap structure layer is thinned, and the second blue film layer is removed to complete the packaging of the device to be packaged.

[0022] Furthermore, the first metal layer, the second metal layer and the third metal layer respectively include one or more of gold, aluminum, tin, silver, copper, chromium, titanium, tungsten and nickel, and the connecting member includes tungsten or copper.

[0023] Another technical solution of the present invention is as follows: a micro-electromechanical system device packaging structure based on wafer bonding is provided, wherein the micro-electromechanical system device packaging structure based on wafer bonding is manufactured by the micro-electromechanical system device packaging method based on wafer bonding described in any one of the above technical solutions, and the micro-electromechanical system device packaging structure based on wafer bonding includes a wafer device structure layer after the back side of the device wafer is thinned, a third metal layer connected to the first metal layer of the wafer device structure layer, and a micro-cap structure layer after the back side of the cap wafer is thinned.

[0024] The beneficial effects of the present invention are as follows: a first mark is formed by etching on the back side of a device wafer using a photolithography process, a first dielectric layer is arranged on the front side of the device wafer, a first metal layer is arranged on the first dielectric layer, the first metal layer is etched to form a wafer device structure layer, and the device to be packaged is connected to the wafer device structure layer through a connector; a second mark is formed by etching on the back side of a cap wafer using a photolithography process according to the position of the first mark, a second dielectric layer is arranged on the front side of the cap wafer, a second metal layer is arranged on the second dielectric layer, the second metal layer is etched, the second dielectric layer is etched according to the etched second metal layer, and the cap wafer is etched using an inductively coupled plasma process. Etching is performed to form a cavity on the cap wafer to form a micro-cap structure layer; the wafer device structure layer and the micro-cap structure layer are pre-aligned and bonded by photolithography according to the first mark and the second mark, the back side of the device wafer of the wafer device structure layer is thinned, the thinned device wafer and the first dielectric layer are etched to obtain an etching pattern, a third metal layer is formed according to the etching pattern to connect the third metal layer with the first metal layer, and the back side of the cap wafer of the micro-cap structure layer is thinned to complete the packaging of the device to be packaged; the above technical solution can realize the packaging of MEMS devices, improve the accuracy of wafer-level bonding, and improve the packaging accuracy of MEMS devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic flow chart of a method for packaging a micro-electromechanical system device based on wafer bonding provided in an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of the state after step S1011 is completed provided in an embodiment of the present invention;

[0027] Figure 3 A schematic diagram of the state after step S1012 is completed provided in an embodiment of the present invention;

[0028] Figure 4 A schematic diagram of the state after step S1013 is completed provided in an embodiment of the present invention;

[0029] Figure 5 A schematic diagram of the state after step S1014 is completed provided in an embodiment of the present invention;

[0030] Figure 6 A schematic diagram of the state after step S1015 is completed provided in an embodiment of the present invention;

[0031] Figure 7 A schematic diagram of the state after step S1016 is completed provided in an embodiment of the present invention;

[0032] Figure 8 A schematic diagram of the state after step S1017 is completed provided in an embodiment of the present invention;

[0033] Fig. 9 A schematic diagram of the state after step S1018 is completed provided in an embodiment of the present invention;

[0034] Fig.10 A schematic diagram of the state after step S1019 is completed provided in an embodiment of the present invention;

[0035] Fig.11 A schematic structural diagram of a wafer device structure layer provided by an embodiment of the present invention;

[0036] Fig.12 A schematic diagram of the state after step S10110 is completed provided in an embodiment of the present invention;

[0037] Fig.13 A schematic diagram of the state after step S1021 is completed provided in an embodiment of the present invention;

[0038] Fig.14 A schematic diagram of the state after step S1022 is completed provided in an embodiment of the present invention;

[0039] Fig.15 A schematic diagram of the state after step S1023 is completed provided in an embodiment of the present invention;

[0040] Fig.16 A schematic diagram of the state after step S1024 is completed provided in an embodiment of the present invention;

[0041] Fig.17 A schematic diagram of the state after step S1025 is completed provided in an embodiment of the present invention;

[0042] Fig.18 A schematic diagram of the state after step S1026 is completed provided in an embodiment of the present invention;

[0043] Fig.19 A schematic diagram of the state after step S1027 is completed provided in an embodiment of the present invention;

[0044] Fig. 20 A schematic diagram of the state after step S1028 is completed provided in an embodiment of the present invention;

[0045] Fig.21 A schematic diagram of the state after step S1029 is completed provided in an embodiment of the present invention;

[0046] Fig. 22 A schematic diagram of the state after step S10210 is completed provided in an embodiment of the present invention;

[0047] Fig.23 A schematic diagram of the state after step S10211 is completed provided in an embodiment of the present invention;

[0048] Fig.24 A schematic diagram of the state after step S10212 is completed provided in an embodiment of the present invention;

[0049] Fig.25 A schematic diagram of the structure of a micro-cap structure layer provided in an embodiment of the present invention;

[0050] Fig.26 A schematic diagram of the state after step S1031 is completed provided in an embodiment of the present invention;

[0051] Fig. 27 A schematic diagram of the state after step S1032 is completed provided in an embodiment of the present invention;

[0052] Fig.28 A schematic diagram of the state after step S1033 is completed provided in an embodiment of the present invention;

[0053] Fig.29 A schematic diagram of the state after step S1034 is completed provided in an embodiment of the present invention;

[0054] Fig.30 A schematic diagram of the state after step S1035 is completed provided in an embodiment of the present invention;

[0055] Fig.31 A schematic diagram of the state after step S1035 is completed provided in an embodiment of the present invention;

[0056] Fig.32 A schematic diagram of the state after step S1036 is completed provided in an embodiment of the present invention;

[0057] Fig.33 A schematic diagram of the state after step S1037 is completed provided in an embodiment of the present invention;

[0058] Fig.34 A schematic diagram of the state after step S1038 is completed provided in an embodiment of the present invention;

[0059] Fig.35 A schematic diagram of the state after step S1039 is completed provided in an embodiment of the present invention;

[0060] Fig.36 A schematic diagram of the state after step S10310 is completed provided in an embodiment of the present invention;

[0061] Fig.37 A schematic diagram of the state after step S10311 is completed provided in an embodiment of the present invention;

[0062] Fig.38 A schematic diagram of a MEMS device packaging structure based on wafer bonding provided in an embodiment of the present invention.

[0063] Figure markings: 10-wafer device structure layer; 11-first protective layer; 12-device wafer; 13-first photoresist layer; 14-first dielectric layer; 15-first mark; 16-first metal layer; 17-first photoresist layer; 18-connector; 19-device to be packaged; 20-microcap structure layer; 21-second protective layer; 22-cap wafer; 23-second photoresist layer; 24-second mark; 25-second dielectric layer; 26-second metal layer; 27-second photoresist layer; 28-cavity; 29-first blue film layer; 30-third photoresist layer; 31-fourth photoresist layer; 32-third metal layer; 33-second blue film layer. DETAILED DESCRIPTION

[0064] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0065] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0066] Figure 1 FIG. 1 is a flow chart of a method for packaging a MEMS device based on wafer bonding according to an embodiment of the present invention. It should be noted that the method for packaging a MEMS device based on wafer bonding according to the present invention is not limited to the method for packaging a MEMS device based on wafer bonding if substantially the same results are achieved. Figure 1 The process sequence shown is limited. Figure 1As shown, the MEMS device packaging method based on wafer bonding includes the following steps:

[0067] S101, etching on the back side of the device wafer 12 by photolithography to form a first mark 15, setting a first dielectric layer 14 on the front side of the device wafer 12, setting a first metal layer 16 on the first dielectric layer 14, etching the first metal layer 16 to form a wafer device structure layer 10, and connecting a device to be packaged 19 on the wafer device structure layer 10 through a connector 18;

[0068] In some embodiments, the etching on the back side of the device wafer 12 by using a photolithography process to form a first mark 15 and remove the first photoresist layer 13 includes:

[0069] A first protective layer 11 is set on the front side of the device wafer 12, and a photoresist is coated on the back side of the device wafer 12 to form a first photoresist layer 13. The back side of the device wafer 12 is etched by a photolithography process to form a first mark 15, and the first photoresist layer 13 and the first protective layer 11 are removed.

[0070] In a specific embodiment, the device wafer 12 may be a thick device wafer, the first mark 15 may be multiple (e.g., 2), the first mark 15 may be a positioning cavity, and the first protective layer 11 may include photoresist. The first photoresist layer 13 may be removed by using a photoresist cleaning agent. The connector 18 and the device to be packaged 19 may include multiple ones.

[0071] In a specific embodiment, the first protective layer 11 is provided on the front surface of the device wafer 12 as step S1011. The state diagram after the step S1011 is completed is as follows: Figure 2 The back side of the device wafer 12 is coated with photoresist to form a first photoresist layer 13, and the back side of the device wafer 12 is etched by photolithography to form a first mark 15 as step S1012. The state diagram after step S1012 is completed is as shown in FIG. Figure 3 As shown in FIG. 1 , the first photoresist layer 13 is removed as step S1013, and a schematic diagram of the state after step S1013 is completed is shown in FIG. Figure 4 Before removing the first protective layer 11, the device wafer 12 may be flipped, and flipping the device wafer 12 is performed as step S1014. The state diagram after step S1014 is completed is as shown in FIG. Figure 5 As shown in FIG. 1 , the first protective layer 11 is removed as step S1015, and the state diagram after step S1015 is completed is as shown in FIG. Figure 6 shown.

[0072] In some embodiments, a first dielectric layer 14 is disposed on the front side of the device wafer 12, a first metal layer 16 is disposed on the first dielectric layer 14, and the first metal layer 16 is etched to form a wafer device structure layer 10, including:

[0073] A first dielectric layer 14 is arranged on the front side of the device wafer 12, a first metal layer 16 is arranged on the first dielectric layer 14, a first photoresist layer 17 with a pattern is arranged on the first metal layer 16, the first metal layer 16 is etched according to the pattern of the first photoresist layer 17, and the first photoresist layer 17 is removed to form a wafer device structure layer 10.

[0074] In a specific embodiment, the wafer device structure layer 10 may include a silicon-based wafer and a bonding material layer, the silicon-based wafer is the device wafer 12, the bonding material layer includes a first dielectric layer 14 and a first metal layer 16, the first dielectric layer 14 may include an inorganic material or an organic material, the inorganic material may include glass paste, silicate, hydroxide mixture, etc., the organic material includes epoxy resin, silicone, etc. When the first metal layer 16 is set on the first dielectric layer 14, the first metal layer 16 may be set on the first dielectric layer 14 in a manner of seed layer sputtering and metal electroplating growth. By setting a first photoresist layer 17 with a pattern, the position of the metal is defined by the pattern, and the first metal layer 16 is etched according to the pattern of the first photoresist layer 17 to remove excess metal and retain the remaining metal to form an electrode, and then the device to be packaged 19 is flip-chip mounted at the corresponding position through the connector 18. Setting the first dielectric layer 14 on the front side of the device wafer 12 is used as step S1016, and the state schematic diagram after the completion of step S1016 is as shown in FIG. Figure 7 As shown in FIG. 1 , the first metal layer 16 is provided on the first dielectric layer 14 as step S1017. The state diagram after step S1017 is completed is shown in FIG. Figure 8 As shown in FIG. 1 , a first photoresist layer 17 having a pattern is provided on the first metal layer 16 as step S1018. A schematic diagram of a state after step S1018 is completed is shown in FIG. Fig. 9 The first metal layer 16 is etched according to the pattern of the first photoresist layer 17 as step S1019. The state diagram after step S1019 is completed is as shown in FIG. Fig.10 The schematic diagram of the structure of the wafer device structure layer 10 is shown in FIG. Fig.11 As shown in FIG. 1 , the device to be packaged 19 is connected to the wafer device structure layer 10 through the connector 18 as step S10110, and the state diagram after the step S10110 is completed is as shown in FIG. Fig.12 shown.

[0075] S102, using a photolithography process to etch on the back side of the cap wafer 22 according to the position of the first mark 15 to form a second mark 24, setting a second dielectric layer 25 on the cap wafer 22, setting a second metal layer 26 on the second dielectric layer 25, etching the second metal layer 26, etching the second dielectric layer 25 according to the etched second metal layer 26, etching the cap wafer 22 using an inductively coupled plasma process, forming a cavity 28 on the cap wafer 22, so as to form a micro-cap structure layer 20;

[0076] In a specific embodiment, the above-mentioned cap wafer 22 can be a thick cap wafer. Through deep hole etching technology of silicon (such as inductively coupled plasma process), a hole is directly punched on the micro-cap bonding surface (cap wafer 22) to produce a cavity 28. The position of the cavity 28 can be determined according to the position of the second mark 24 and the patterned photolithography metal (the second dielectric layer 25 after etching) to doubly ensure the production accuracy of the cavity 28.

[0077] In some embodiments, etching the back side of the cap wafer 22 using a photolithography process to form the second mark 24 includes:

[0078] A second protective layer 21 is set on the front side of the cap wafer 22, and photoresist is coated on the back side of the cap wafer 22 to form a second photoresist layer 23. A photolithography process is used to etch the back side of the cap wafer 22 according to the position of the first mark 15 to form a second mark 24. The second photoresist layer 23 is removed, and the second protective layer 21 is removed, wherein the positions of the second mark 24 and the first mark 15 correspond.

[0079] In a specific embodiment, a photoresist cleaning agent can be used to remove the second photoresist layer 23, and a photolithography process can be used to etch the back of the cap wafer 22 to form a second mark 24, which can be a positioning cavity. The number of second marks 24 is the same as the number of first marks 15, and the position of the second mark 24 corresponds to the position of the first mark 15. The second protective layer 21 is set on the front of the cap wafer 22 as step S1021. The state diagram after step S1021 is completed is as shown in FIG. Fig.13 As shown. The step S1022 is to coat the back side of the cap wafer 22 with photoresist to form a second photoresist layer 23. The state diagram after the step S1022 is completed is as shown in FIG. Fig.14 The second mark 24 is formed by etching the back side of the cap wafer 22 by using a photolithography process as step S1023. The state diagram after step S1023 is completed is as shown in FIG. Fig.15 As shown in FIG. 1 , the second photoresist layer 23 is removed as step S1024, and a schematic diagram of the state after step S1024 is completed is shown in FIG. Fig.16 Before removing the second protective layer 21, the cap wafer 22 may be flipped, and flipping the cap wafer 22 is performed as step S1025. The state diagram after step S1025 is completed is as shown in FIG. Fig.17 As shown in FIG. 1 , removing the second protective layer 21 is taken as step S1026, and a schematic diagram of the state after step S1026 is completed is shown in FIG. Fig.18 shown.

[0080] In some embodiments, a second dielectric layer 25 is disposed on the front surface of the cap wafer 22, a second metal layer 26 is disposed on the second dielectric layer 25, the second metal layer 26 is etched, and the second dielectric layer 25 is etched according to the etched second metal layer 26, including:

[0081] A second dielectric layer 25 is arranged on the front side of the cap wafer 22, a second metal layer 26 is arranged on the second dielectric layer 25, a second photoresist layer 27 with a pattern is arranged on the second metal layer 26, the second metal layer 26 is etched according to the pattern of the second photoresist layer 27, the second photoresist layer 27 is removed, and the second dielectric layer 25 is etched according to the etched second metal layer 26.

[0082] In a specific embodiment, the second dielectric layer 25 is provided on the front surface of the cap wafer 22 as step S1027. The state diagram after the step S1027 is completed is as follows: Fig.19 As shown in FIG. 2 , setting the second metal layer 26 on the second dielectric layer 25 is used as step S1028, and a schematic diagram of the state after step S1028 is completed is shown in FIG. Fig. 20 As shown in FIG. 2 , a second photoresist layer 27 having a pattern is provided on the second metal layer 26 as step S1029. A schematic diagram of the state after step S1029 is completed is shown in FIG. Fig.21 The second metal layer 26 is etched according to the pattern of the second photoresist layer 27 as step S10210, and the state diagram after step S10210 is completed is as shown in FIG. Fig. 22 The second photoresist layer 27 is removed in step S10211, and the state diagram after step S10211 is completed is as shown in FIG. Fig.23 As shown in FIG. 1 , etching the second dielectric layer 25 according to the etched second metal layer 26 is used as step S10212, and a schematic diagram of the state after step S10212 is completed is shown in FIG. Fig.24 The schematic diagram of the structure of the micro-cap structure layer 20 is shown in FIG. Fig.25 shown.

[0083] S103, perform photolithography pre-alignment bonding on the wafer device structure layer 10 and the micro-cap structure layer 20 according to the first mark 15 and the second mark 24, thin the back side of the device wafer 12 of the wafer device structure layer 10, etch the thinned device wafer 12 and the first dielectric layer 14 to obtain an etching pattern, form a third metal layer 32 according to the etching pattern to connect the third metal layer 32 to the first metal layer 16, thin the back side of the cap wafer 22 of the micro-cap structure layer 20 to complete the packaging of the device 19 to be packaged.

[0084] In a specific embodiment, the wafer device structure layer 10 and the micro-cap structure layer 20 are photolithographically pre-aligned and bonded according to the first mark 15 and the second mark 24 to ensure the accuracy of wafer alignment. During bonding, the first mark 15 and the second mark 24 can be aligned, and bonding can be performed using bonding technologies such as metal bonding, eutectic bonding, silicon-silicon direct bonding, and glass paste bonding. Photolithographically pre-aligned and bonded according to the first mark 15 and the second mark 24 are performed on the wafer device structure layer 10 and the micro-cap structure layer 20 as step S1031. The state diagram after step S1031 is completed is as follows: Fig.26 shown.

[0085] In some embodiments, the back side of the device wafer 12 of the wafer device structure layer 10 is thinned, and the thinned device wafer 12 and the first dielectric layer 14 are etched to obtain an etching pattern, including:

[0086] A first blue film layer 29 is arranged on the back side of the cap wafer 22 of the micro-cap structure layer 20, the back side of the device wafer 12 of the wafer device structure layer 10 is thinned, the first blue film layer 29 is removed, and a third photoresist layer 30 with a pattern is arranged on the back side of the thinned device wafer 12, and the thinned device wafer 12 and the first dielectric layer 14 are etched according to the pattern of the third photoresist layer 30 to obtain an etching pattern, and the third photoresist layer 30 is removed.

[0087] In a specific embodiment, the back side of the device wafer 12 of the wafer device structure layer 10 can be thinned by wafer thinning technology to eliminate the first mark 15. After the wafer device structure layer 10 and the micro-cap structure layer 20 are pre-aligned and bonded by photolithography, it is necessary to vertically lead out the electrode, that is, the third metal layer 32. Prior to this, it is necessary to coat a patterned photoresist layer (a third photoresist layer 30 with a pattern) on the back side of the cap wafer 22 to determine the position of deep hole etching, and then etch the thinned device wafer 12 and the first dielectric layer 14 to obtain an etching pattern.

[0088] In a specific embodiment, disposing the first blue film layer 29 on the back side of the cap wafer 22 of the micro-cap structure layer 20 is used as step S1032. The state diagram after the completion of step S1032 is as shown in FIG. Fig. 27 As shown in FIG. 1 , the back side of the device wafer 12 of the wafer device structure layer 10 is thinned as step S1033, and a schematic diagram of the state after step S1033 is completed is shown in FIG. Fig.28 As shown in FIG. 1 , the first blue film layer 29 is removed as step S1034, and the state diagram after step S1034 is completed is as shown in FIG. Fig.29 As shown in FIG. 1 , a third photoresist layer 30 having a pattern is provided on the back of the thinned device wafer 12 as step S1035. A schematic diagram of the state after step S1035 is completed is shown in FIG. Fig.30 The device wafer 12 and the first dielectric layer 14 are etched according to the pattern of the third photoresist layer 30 as step S1035. The state diagram after step S1035 is completed is as shown in FIG. Fig.31 As shown in FIG. 1 , removing the third photoresist layer 30 is performed as step S1036, and a schematic diagram of the state after step S1036 is completed is shown in FIG. Fig.32 shown.

[0089] In some embodiments, forming the third metal layer 32 according to the etching pattern so that the third metal layer 32 is connected to the first metal layer 16 includes:

[0090] A fourth photoresist layer 31 with a pattern is disposed on the back side of the etched device wafer 12 , and a third metal layer 32 is formed according to the pattern of the fourth photoresist layer 31 and the etching pattern, so that the third metal layer 32 is connected to the first metal layer 16 .

[0091] In a specific embodiment, the third metal layer 32 is formed according to the pattern of the fourth photoresist layer 31 and the etching pattern. The third metal layer 32 can be formed by seed layer sputtering and metal electroplating growth, so that the third metal layer 32 is connected to the first metal layer 16 to achieve electrode extraction.

[0092] In a specific embodiment, a fourth photoresist layer 31 having a pattern is provided on the back side of the device wafer 12 after etching as step S1037. A schematic diagram of the state after step S1037 is completed is shown in FIG. Fig.33 A third metal layer 32 is formed according to the pattern of the fourth photoresist layer 31 and the etching pattern so that the third metal layer 32 is connected to the first metal layer 16 as step S1038. A schematic diagram of the state after step S1038 is completed is shown in FIG. Fig.34 shown.

[0093] In some embodiments, the back side of the cap wafer 22 of the micro-cap structure layer 20 is thinned to complete the packaging of the device to be packaged 19, including:

[0094] The fourth photoresist layer 31 is removed, and a second blue film layer 33 is set on the back side of the etched device wafer 12 , the back side of the cap wafer 22 of the micro-cap structure layer 20 is thinned, and the second blue film layer 33 is removed to complete the packaging of the device 19 to be packaged.

[0095] In a specific embodiment, the back side of the cap wafer 22 of the micro-cap structure layer 20 is thinned to remove the second mark 24. Removing the fourth photoresist layer 31 is used as step S1039. The state diagram after step S1039 is completed is as follows: Fig.35 As shown in FIG. 1 , a second blue film layer 33 is provided on the back side of the device wafer 12 after etching as step S10310, and a schematic diagram of the state after step S10310 is completed is shown in FIG. Fig.36 As shown in FIG. 1 , the back side of the cap wafer 22 of the micro-cap structure layer 20 is thinned as step S10311, and a schematic diagram of the state after step S10311 is completed is shown in FIG. Fig.37 The second blue film layer 33 is removed to complete the packaging of the device to be packaged 19, and a MEMS device packaging structure based on wafer bonding is obtained. The schematic diagram of the MEMS device packaging structure based on wafer bonding is shown in FIG. Fig.38 After the packaged device 19 is packaged, the product can be diced and cut into individual products.

[0096] In some embodiments, the first metal layer 16, the second metal layer 26 and the third metal layer 32 respectively include one or more of gold, aluminum, tin, silver, copper, chromium, titanium, tungsten and nickel, and the connector 18 includes tungsten or copper.

[0097] The wafer bonding-based MEMS device packaging method provided in an embodiment of the present invention comprises the following steps: etching on the back side of a device wafer 12 by a photolithography process to form a first mark 15, setting a first dielectric layer 14 on the front side of the device wafer 12, setting a first metal layer 16 on the first dielectric layer 14, etching the first metal layer to form a wafer device structure layer 10, and connecting a device 19 to be packaged on the wafer device structure layer 10 via a connector 18; etching on the back side of a cap wafer 22 by a photolithography process according to the position of the first mark 15 to form a second mark 24, setting a second dielectric layer 25 on the front side of the cap wafer 22, setting a second metal layer 26 on the second dielectric layer 25, etching the second metal layer 26, etching the second dielectric layer 25 according to the etched second metal layer 26, and using inductively coupled plasma to perform etching. The present invention relates to a body process, etching the cap wafer 22, forming a cavity 28 on the cap wafer 22 to form a micro-cap structure layer 20; performing photolithography pre-alignment bonding on the wafer device structure layer 10 and the micro-cap structure layer 20 according to the first mark 15 and the second mark 24, thinning the back side of the device wafer 12 of the wafer device structure layer 10, etching the thinned device wafer 12 and the first dielectric layer 14 to obtain an etching pattern, forming a third metal layer 32 according to the etching pattern to connect the third metal layer 32 with the first metal layer 16, and thinning the back side of the cap wafer 22 of the micro-cap structure layer 20 to complete the packaging of the device 19 to be packaged; the above technical solution can realize the packaging of MEMS devices, improve the accuracy of wafer-level bonding, and improve the packaging accuracy of MEMS devices.

[0098] The MEMS device packaging method based on wafer bonding provided in an embodiment of the present invention can make a positioning cavity on the device wafer of one or more component units, align the pre-made wafer micro-cap through the positioning cavity, and then complete the wafer-level packaging after the package is attached through silicon-silicon direct bonding. Finally, the electrode is led out from the vertical direction through the back hole etching technology. The cap can effectively protect one or more devices in the cavity 28, and can be suitable for multi-device sealing products with extremely high environmental requirements.

[0099] The MEMS device packaging method based on wafer bonding provided by the embodiment of the present invention proposes a design of adding a positioning cavity to assist the wafer-level bonding process, which can improve the bonding accuracy, which is very critical in the application of high-precision packaging. In the end, the positioning cavity can be eliminated through the thinning process to improve the appearance and application scenarios of the product. The MEMS device packaging method based on wafer bonding provided by the embodiment of the present invention can be used for wafer-level mass production. Compared with the traditional glass-based / organic material cap structure products, the number of products is much higher than the products of traditional processes, and the cost of a single product is greatly reduced. The traditional airtight packaging structure involving glass materials usually adopts the chip to wafer packaging method because the glass processing has high requirements on thickness and it is difficult to thin and cut thick slices, resulting in a slow process flow. The MEMS device packaging method based on wafer bonding provided by the embodiment of the present invention directly adopts the wafer to wafer packaging method for packaging, which reduces the process time and saves a lot of time cost. Compared with the traditional organic bonding of glass and organic materials, the moisture resistance of organic materials themselves is relatively poor. The MEMS device packaging method based on wafer bonding provided in the embodiment of the present invention adopts silicon-silicon direct bonding technology, which can effectively increase the sealing and reliability of the product.

[0100] The embodiment of the present invention provides a MEMS device packaging structure based on wafer bonding, the MEMS device packaging structure based on wafer bonding is manufactured by the MEMS device packaging method based on wafer bonding described in any of the above embodiments, the MEMS device packaging structure based on wafer bonding includes a wafer device structure layer 10 after the back side of the device wafer 12 is thinned, a third metal layer 32 connected to the first metal layer 16 of the wafer device structure layer 10, and a micro-cap structure layer 20 after the back side of the cap wafer 22 is thinned. The schematic diagram of the MEMS device packaging structure based on wafer bonding is as follows: Fig.38 shown.

[0101] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for packaging a micro-electromechanical system device based on wafer bonding, characterized in that: include: Etching on the back side of the device wafer by using a photolithography process to form a first mark, setting a first dielectric layer on the front side of the device wafer, setting a first metal layer on the first dielectric layer, etching the first metal layer to form a wafer device structure layer, and connecting the device to be packaged on the wafer device structure layer through a connector; Using a photolithography process to etch on the back side of the cap wafer according to the position of the first mark to form a second mark, setting a second dielectric layer on the front side of the cap wafer, setting a second metal layer on the second dielectric layer, etching the second metal layer, etching the second dielectric layer according to the etched second metal layer, etching the cap wafer using an inductively coupled plasma process, forming a cavity on the cap wafer to form a micro-cap structure layer; The wafer device structure layer and the micro-cap structure layer are photolithographically pre-aligned and bonded according to the first mark and the second mark, the back side of the device wafer of the wafer device structure layer is thinned, the thinned device wafer and the first dielectric layer are etched to obtain an etching pattern, a third metal layer is formed according to the etching pattern to connect the third metal layer to the first metal layer, and the back side of the cap wafer of the micro-cap structure layer is thinned to complete the packaging of the device to be packaged.

2. The method for packaging a MEMS device based on wafer bonding according to claim 1, characterized in that: The method of etching the back side of the device wafer by using a photolithography process to form a first mark and remove the first photoresist layer comprises: A first protective layer is set on the front side of the device wafer, and photoresist is coated on the back side of the device wafer to form a first photoresist layer. The back side of the device wafer is etched using a photolithography process to form a first mark, and the first photoresist layer and the first protective layer are removed.

3. The method for packaging a MEMS device based on wafer bonding according to claim 1, characterized in that: A first dielectric layer is arranged on the front side of the device wafer, a first metal layer is arranged on the first dielectric layer, and the first metal layer is etched to form a wafer device structure layer, including: A first dielectric layer is arranged on the front side of the device wafer, a first metal layer is arranged on the first dielectric layer, a first photoresist layer with a pattern is arranged on the first metal layer, the first metal layer is etched according to the pattern of the first photoresist layer, the first photoresist layer is removed, and a wafer device structure layer is formed.

4. The method for packaging a MEMS device based on wafer bonding according to claim 1, characterized in that: The method of etching the back side of the cap wafer according to the position of the first mark by using a photolithography process to form a second mark includes: A second protective layer is set on the front side of the cap wafer, and photoresist is coated on the back side of the cap wafer to form a second photoresist layer. A photolithography process is used to etch on the back side of the cap wafer according to the position of the first mark to form a second mark, and the second photoresist layer and the second protective layer are removed, wherein the positions of the second mark and the first mark correspond.

5. The method for packaging a MEMS device based on wafer bonding according to claim 1, characterized in that: The method comprises: providing a second dielectric layer on the front side of the cap wafer, providing a second metal layer on the second dielectric layer, etching the second metal layer, and etching the second dielectric layer according to the etched second metal layer, including: A second dielectric layer is arranged on the front side of the cap wafer, a second metal layer is arranged on the second dielectric layer, a second photoresist layer with a pattern is arranged on the second metal layer, the second metal layer is etched according to the pattern of the second photoresist layer, the second photoresist layer is removed, and the second dielectric layer is etched according to the etched second metal layer.

6. The method for packaging a MEMS device based on wafer bonding according to claim 1, characterized in that: The back side of the device wafer of the wafer device structure layer is thinned, and the thinned device wafer and the first dielectric layer are etched to obtain an etching pattern, including: A first blue film layer is arranged on the back side of the cap wafer of the micro-cap structure layer, the back side of the device wafer of the wafer device structure layer is thinned, the first blue film layer is removed, a third photoresist layer with a pattern is arranged on the back side of the thinned device wafer, the thinned device wafer and the first dielectric layer are etched according to the pattern of the third photoresist layer to obtain an etching pattern, and the third photoresist layer is removed.

7. The method for packaging a MEMS device based on wafer bonding according to claim 1, characterized in that: Forming a third metal layer according to the etching pattern so that the third metal layer is connected to the first metal layer, comprising: A fourth photoresist layer with a pattern is disposed on the back side of the etched device wafer, and a third metal layer is formed according to the pattern of the fourth photoresist layer and the etching pattern, so that the third metal layer is connected to the first metal layer.

8. The method for packaging a MEMS device based on wafer bonding according to claim 7, characterized in that: The back side of the cap wafer of the micro-cap structure layer is thinned to complete the packaging of the device to be packaged, including: The fourth photoresist layer is removed, a second blue film layer is set on the back side of the etched device wafer, the back side of the cap wafer of the micro-cap structure layer is thinned, and the second blue film layer is removed to complete the packaging of the device to be packaged.

9. The method for packaging a MEMS device based on wafer bonding according to claim 1, characterized in that: The first metal layer, the second metal layer and the third metal layer respectively include one or more of gold, aluminum, tin, silver, copper, chromium, titanium, tungsten and nickel, and the connecting member includes tungsten or copper.

10. A micro-electromechanical system device packaging structure based on wafer bonding, characterized in that: The MEMS device packaging structure based on wafer bonding is manufactured by the MEMS device packaging method based on wafer bonding according to any one of claims 1 to 9, and the MEMS device packaging structure based on wafer bonding includes a wafer device structure layer after the back side of the device wafer is thinned, a third metal layer connected to the first metal layer of the wafer device structure layer, and a micro-cap structure layer after the back side of the cap wafer is thinned.

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