An acceleration sensor chip with a DLC optimized structure and a method for manufacturing the same

Abstract

The application belongs to the technical field of micro electro mechanical system sensors, and discloses an acceleration sensor chip with a DLC optimized structure and a preparation method thereof; in the piezoresistive acceleration sensor chip, an SOI substrate is bonded to boron glass through a substrate frame, and a center mass is connected to the substrate frame through four embedded micro-beams arranged in a cross shape; four piezoresistance strips are arranged on the four embedded micro-beams, and the four piezoresistance strips are connected into a Wheatstone full bridge through surface metal leads deposited on the SOI substrate and connected with pads deposited on the SOI substrate; wherein, a DLC film is deposited on the SOI substrate, and the DLC film covers the surface metal leads, the four piezoresistance strips and the area of the SOI substrate except the pads. The application can improve the sensitivity of the sensor while ensuring the strength of the sensitive structure; the protection of the piezoresistance strips is realized, and the reliability of the sensor can be improved.

Description

Technical Field

[0001] This invention belongs to the field of micro-electro-mechanical system (MEMS) sensor technology, and specifically relates to an accelerometer chip with a DLC optimized structure and its fabrication method. Background Technology

[0002] With the development of MEMS and microfabrication technologies, MEMS sensors capable of measuring various physical parameters have rapidly developed and are widely used; further, their applications cover all sectors of the national economy and military defense. Among the many parameters measured, acceleration measurement is particularly widely used. As one of the important parameters reflecting the working state of machinery, acceleration needs to be precisely measured in automobiles, aerospace, manufacturing, and military weaponry. Based on different measurement principles, MEMS accelerometers are classified into piezoresistive, piezoelectric, capacitive, resonant, fiber optic, and thermal convection types, among others; piezoresistive accelerometers are widely used due to their advantages such as high sensitivity, fast response, high stability, and low power consumption.

[0003] In existing technologies, piezoresistive accelerometers generally consist of a mass block, a microbeam, and piezoresistive strips distributed over specific areas of the beam. The piezoresistive strips are typically piezoresistors, and measurement is achieved by converting the measured acceleration into a change in the piezoresistive resistivity. Currently, commonly used structures include single cantilever beams, double cantilever beams, four-beam structures, and cross beam structures. Among these, single and double cantilever beam structures have high sensitivity but low natural frequencies and narrow frequency response ranges; while four-beam and cross beam structures have high natural frequencies but lower sensitivity.

[0004] In practical applications, the sensitivity and natural frequency of an accelerometer are crucial performance indicators; therefore, the design aims to achieve the highest possible sensitivity and natural frequency. However, due to the working principle of the spring-mass system in a piezoresistive accelerometer, sensitivity and natural frequency are mutually restrictive parameters that cannot be improved simultaneously. To alleviate this constraint, methods such as improving the sensing mechanism or optimizing the sensitive structure are generally employed. The former aims to increase the strain coefficient of the piezoresistor, thereby improving sensitivity, often requiring new materials or processes, making rapid large-scale application difficult. The latter, using reasonable size configurations and novel structures, can achieve better results, but as structural complexity increases, it poses challenges to the sensor's manufacturing process and structural reliability. Furthermore, considering the complexity of the sensor's operating environment and the randomness of its use, the sensor's sensitive structure also needs to possess sufficient strength and reliability. Summary of the Invention

[0005] The purpose of this invention is to provide an accelerometer chip with an optimized DLC structure and its fabrication method, thereby solving one or more of the aforementioned technical problems. The technical solution provided by this invention employs embedded microbeams and a diamond-like carbon (DLC) film, offering advantages such as simple structure and good compatibility with processing technologies. It can improve sensor sensitivity while ensuring the strength of the sensitive structure; furthermore, it protects the piezoresistive strip, thus improving sensor reliability.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] The present invention provides an accelerometer chip with a DLC optimized structure, comprising: an SOI substrate and borosilicate glass, wherein the SOI substrate includes a substrate frame and a central mass block;

[0008] The SOI substrate is bonded to the borosilicate glass via a substrate frame. The central mass block is connected to the substrate frame via four embedded microbeams arranged in a cross shape. Four varistor strips are arranged on the four embedded microbeams. The four varistor strips are connected to form a Wheatstone bridge via surface metal leads deposited on the SOI substrate and connected to pads deposited on the SOI substrate.

[0009] The center mass block has gaps between itself, the substrate frame, and the borosilicate glass to serve as working spaces. A DLC film is deposited on the SOI substrate, covering the surface metal leads, four varistor strips, and the area of ​​the SOI substrate excluding the pads.

[0010] A further improvement of the present invention is that,

[0011] The thickness of the DLC film is 100nm to 200nm;

[0012] The DLC film uses DLC sp. 3 The bond content is higher than 80%, and the Young's modulus is 300 MPa to 600 MPa.

[0013] A further improvement of the present invention is that,

[0014] The resistivity of the DLC film is greater than or equal to 1×10⁻⁶. 8 Ω·cm.

[0015] A further improvement of the present invention is that,

[0016] The resistivity of the DLC film is less than 1×10⁻⁶. 8 Ω·cm;

[0017] A silicon dioxide isolation layer is deposited between the SOI substrate and the DLC film.

[0018] A further improvement of the present invention is that,

[0019] The thickness of the central mass block is the same as the thickness of the substrate frame, and the borosilicate glass has grooves etched at the positions corresponding to the central mass block.

[0020] A further improvement of the present invention is that,

[0021] The embedded microbeam is fabricated on the device layer of the SOI substrate, and the thickness of the embedded microbeam is 15μm to 50μm.

[0022] A further improvement of the present invention is that,

[0023] The four embedded microbeams are of the same size, and the four varistor strips have the same resistance value. Among the four embedded microbeams, two opposite embedded microbeams form a group. The four varistor strips are respectively set on the four embedded microbeams. In one group, the varistor strips on the two embedded microbeams are close to the center of the central mass block, and in the other group, the varistor strips on the two embedded microbeams are far away from the center of the central mass block. Alternatively, the four varistor strips are respectively set at both ends of the two embedded microbeams in the group.

[0024] A further improvement of the present invention is that,

[0025] The four embedded microbeams are named Embedded Microbeam I, Embedded Microbeam II, Embedded Microbeam III, and Embedded Microbeam IV. Embedded Microbeam I and Embedded Microbeam II are a pair, with identical dimensions. Embedded Microbeam III and Embedded Microbeam IV are another pair, with identical dimensions. The dimensions of Embedded Microbeam I and Embedded Microbeam II are smaller than those of Embedded Microbeam III and Embedded Microbeam IV.

[0026] The four varistor strips are varistor strip I, varistor strip II, varistor strip III, and varistor strip IV;

[0027] Among them, the four varistor strips have the same resistance value; varistor strips III and IV are respectively set at the two ends of the embedded microbeam I near the center of the central mass block, and varistor strips II and I are respectively set at the two ends of the embedded microbeam II near the center of the central mass block.

[0028] A further improvement of the present invention is that,

[0029] The surface metal leads adopt a Pt-Ti-Pt-Au multilayer structure; wherein, the ohmic contact area is made of Pt, and the lead layer adopts a Ti-Pt-Au multilayer metal lead structure; in the lead layer, the Ti layer is used as the adhesive layer, and the Au layer is the topmost metal layer.

[0030] The present invention provides a method for fabricating an accelerometer chip, comprising the following steps:

[0031] Step 1: Clean and thermally oxidize the SOI substrate to prepare an SOI substrate with silicon dioxide layers on the upper and lower surfaces respectively;

[0032] Step 2: Using a varistor mask, the front side of the SOI substrate prepared in Step 1 is photolithographically etched. The photoresist is used as a mask, and a dry etching process is used to remove the silicon dioxide layer of the varistor strip area to create windows in the varistor region. The silicon dioxide layer is then used as a mask for light doping by boron ion implantation to form the varistor strip. After removing the silicon dioxide layer, the SOI substrate is then subjected to high-temperature annealing to promote the redistribution of implanted impurities to remove lattice damage and generate a new silicon dioxide layer.

[0033] Step 3: Using an ohmic contact mask, the front ohmic contact area of ​​the SOI substrate after step 2 is photolithographically etched. The silicon dioxide layer is used as a mask, and boron ion implantation is performed again for heavy doping. After that, the SOI substrate is subjected to diffusion annealing to promote the redistribution of implanted impurities and remove lattice damage, ensuring the uniform distribution and concentration requirements of doped impurities.

[0034] Step 4: Use a cavity deep mask to photolithographically etch the back cavity of the SOI substrate after step 3. Use the photoresist layer as a mask and use dry etching to sequentially etch the silicon dioxide layer and the silicon substrate of the SOI substrate. During the etching process, the buried oxide layer is used as an etching self-stopping layer.

[0035] Step 5: Using anodic bonding technology, the SOI substrate treated in Step 4 is directly bonded to borosilicate glass. A silicon dioxide layer is deposited on the surface of the SOI substrate. Then, lead holes are photolithographically patterned on the front side using a lead hole mask. The photoresist layer is used as a mask, and the silicon dioxide in the lead hole area is removed using a dry etching process. The SOI substrate is then cleaned and dried. Next, surface metal lead and pad patterns are photolithographically patterned using a metal lead and pad mask. Multilayer metal is sputtered using a magnetron sputtering process, and the surface metal lead and pads are obtained through a lift-off process.

[0036] Step 6: Deposit a DLC film on the SOI substrate after the processing in step 5; wherein, a front-side photolithography is performed using a pad mask, and a photoresist layer is used as a mask to protect the pads. A physical vapor deposition process is used to deposit a DLC film on the upper surface of the SOI substrate. Finally, a stripping process is used to expose the pads again, so that the DLC film covers the surface metal leads, varistor strips, and the area of ​​the SOI substrate other than the pads.

[0037] Step 7: Based on the SOI substrate processed in Step 6, release the sensor sensitive structure and dicing it to obtain a single sensor chip.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The accelerometer chip provided by this invention is specifically a high-sensitivity piezoresistive accelerometer chip based on a DLC film strength-reinforced beam. It features a simple structure, good fabrication process compatibility, and improves sensor sensitivity while ensuring the strength of the sensitive structure. Simultaneously, it protects the piezoresistor and surface electrodes, enhancing sensor reliability. Further explanation is provided: by depositing the DLC film and employing an embedded microbeam structure, sensor structural complexity is avoided, reducing fabrication difficulty. The embedded microbeam structure maximizes the mass block weight and microbeam length within the same sensor chip size, thereby improving sensor sensitivity and reducing sensor volume. The strength-reinforced beam is obtained by depositing a DLC film with good insulation and high Young's modulus, significantly improving the strength and stiffness of the accelerometer's sensitive structure while maintaining high sensitivity, increasing the natural frequency to some extent, and enhancing structural reliability.

[0040] In this invention, a high sp2000pF2 ... 3 The DLC film with high content has good chemical stability, corrosion resistance, thermal conductivity, thermal shock resistance and wear resistance. It can play a good role in isolating and protecting the surface metal leads and varistor strips of the sensor chip, which significantly improves the reliability and service life of the sensor.

[0041] In this invention, different solutions are adopted for DLC films with different resistivities. For high resistivity DLC films, a method of directly depositing the DLC film on the surface of the SOI substrate is adopted, which can reduce the preparation steps. For low resistivity DLC films, a solution of depositing a silicon dioxide isolation layer between the SOI substrate and the DLC film is adopted, which achieves electrical isolation, reduces the requirements for the resistivity of the DLC film, and broadens the range of usable DLC films.

[0042] In the fabrication method of this invention, the sensitive structure of the accelerometer chip is fabricated on an SOI substrate, which enables precise control of the structural dimensions. In particular, the buried oxide layer of SOI can be fully utilized as an etching self-stopping layer, thereby ensuring the accuracy of the thickness of the embedded microbeam. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art are briefly introduced below; obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the overall structure of an accelerometer chip with a DLC optimized structure provided in an embodiment of the present invention;

[0045] Figure 2 for Figure 1 A partially enlarged structural diagram at point A in the illustrated embodiment;

[0046] Figure 3 for Figure 1 The embodiment shown is a schematic diagram of the back structure of the SOI substrate;

[0047] Figure 4 This is a schematic diagram of the resistor arrangement scheme for the accelerometer chip in an embodiment of the present invention; wherein, Figure 4 Image (a) is a schematic diagram of resistor arrangement scheme one. Figure 4 Image (b) is a schematic diagram of resistor arrangement scheme two. Figure 4 (c) is a schematic diagram of the Wheatstone bridge;

[0048] Figure 5 This is a cross-sectional view of the fabrication process of the accelerometer chip in an embodiment of the present invention.

[0049] Figure 6 This is a schematic diagram of the preparation process scheme one in the embodiments of the present invention;

[0050] Figure 7 This is a schematic diagram of the preparation process scheme two in this embodiment of the invention;

[0051] Explanation of reference numerals in the attached figures:

[0052] 1. SOI substrate; 2. Pads; 3. Center mass block; 4. Embedded microbeams; 5. Varistor strips; 6. Surface metal leads; 7. Borosilicate glass; 8. DLC film;

[0053] 4-1. Embedded microbeam I; 4-2. Embedded microbeam II; 4-3. Embedded microbeam III; 4-4. Embedded microbeam IV;

[0054] 5-1. Varistor strip I; 5-2. Varistor strip II; 5-3. Varistor strip III; 5-4. Varistor strip IV. Detailed Implementation

[0055] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0057] The present invention will now be described in further detail with reference to the accompanying drawings:

[0058] Please see Figures 1 to 3 An embodiment of the present invention provides an accelerometer chip with a DLC optimized structure, comprising: an SOI substrate 1 and borosilicate glass 7;

[0059] The SOI substrate 1 includes a substrate frame and a central mass block 3; wherein, the SOI substrate 1 is bonded to the borosilicate glass 7 through the substrate frame, and the central mass block 3 is connected to the substrate frame through four embedded microbeams 4 arranged in a cross shape, and gaps are provided between the central mass block 3, the substrate frame, and the borosilicate glass 7 to serve as working space.

[0060] The embedded microbeam 4 is provided with varistor strips 5. The four varistor strips 5 are connected to form a Wheatstone bridge through surface metal leads 6 deposited on the SOI substrate 1 and connected to the pads 2 deposited on the SOI substrate 1.

[0061] A DLC film 8 is deposited on the SOI substrate 1, and the DLC film 8 covers the surface metal leads 6, four varistor strips 5, and the area of ​​the SOI substrate 1 except for the pads 2.

[0062] In this embodiment of the invention, the SOI substrate 1 and the borosilicate glass 7 are directly bonded using a silicon-glass anodic bonding process. A groove is etched on the borosilicate glass 7 at a position corresponding to the central mass block 3, creating a gap between the central mass block 3 and the borosilicate glass 7, serving as the working space for the central mass block 3. Furthermore, the central mass block 3 is located in the middle of the SOI substrate 1, and a gap exists between the central mass block 3 and the substrate frame, connected by an embedded microbeam 4. Specifically, the thickness of the central mass block 3 is the same as the thickness of the substrate frame, and a pre-defined groove maintains the working gap between it and the borosilicate glass 7. Under acceleration, the central mass block 3 will undergo a corresponding displacement along the Z-axis, causing the embedded microbeam 4 to bend accordingly.

[0063] Please see Figure 4 In a specific exemplary embodiment of the present invention, the embedded microbeams 4 are symmetrically arranged along the centerline of the central mass block 3, and there are four in total. Optionally, the thickness of the embedded microbeams 4 is 15μm to 50μm, and they are fabricated on the device layer of the SOI substrate 1. In this embodiment of the present invention, there are two schemes for the size of the four embedded microbeams 4: Scheme 1 is that the size of the four embedded microbeams 4 is completely identical, in which case all four embedded microbeams 4 serve as sensitive beams; Scheme 2 is to group two opposite embedded microbeams 4 into a group, with the first group being sensitive beams, including embedded microbeam I 4-1 and embedded microbeam II 4-2, and the second group being support beams, including embedded microbeam III 4-3 and embedded microbeam IV 4-4; wherein the size of the support beams is larger than the size of the sensitive beams. In this embodiment of the invention, there are four varistor strips 5, namely varistor strip I 5-1, varistor strip II 5-2, varistor strip III 5-3, and varistor strip IV 5-4. The four varistor strips 5 have the same resistance value and are arranged on the embedded microbeams 4. They are connected by surface metal leads 6 to form a Wheatstone bridge. Under acceleration, the resistance value of the varistor strips will change; the resistance value of one pair of varistor strips will increase, and the resistance value of the other pair will decrease, thereby converting the acceleration signal into a voltage signal output. Correspondingly, there are two arrangements for the varistor strips 5: Option one is to arrange the varistor strips at the ends of two opposite embedded microbeams. This option is applicable to structures where two embedded microbeams are the sensing beams and four embedded microbeams 4 are the sensing beams. Option two is to arrange the varistor strips on all four embedded microbeams. This option is applicable to structures where all four embedded microbeams are the sensing beams.

[0064] In this embodiment of the invention, the surface metal lead 6 adopts a Pt-Ti-Pt-Au multilayer structure; wherein, the ohmic contact area is made of Pt, and the lead layer adopts a Ti-Pt-Au multilayer metal lead structure; wherein, the Ti layer, as the adhesive layer, has strong adhesion to the substrate, and Au, as the top metal, has good conductivity and can easily lead signals to the PCB board through gold wire leads.

[0065] In a specific and exemplary embodiment of the present invention, the pads 2 are connected to the surface metal leads 6, a total of five, and the signal is exported from the sensor chip to the PCB board through the pads 2.

[0066] In this embodiment of the invention, the DLC film 8 uses sp 3 DLC with a bond content higher than 80% exhibits high resistivity, good insulation, a Young's modulus of 300–600 MPa, and a film thickness of 100–200 nm. Deposited on the upper surface of SOI substrate 1, it covers all areas except for the pads 2. The surface metal leads 6 and varistor strips 5 are also covered, improving the strength of the sensitive structure while providing isolation and protection for the surface metal leads 6 and varistor strips 5. Furthermore, for resistivity greater than or equal to 1 × 10⁻⁶... 8 The DLC film 8 with a resistivity of Ω·cm is deposited directly on the surface of the SOI substrate 1; for applications with resistivity less than 1×10 Ω·cm 8 The DLC film 8 with a density of Ω·cm adopts a process scheme of depositing a silicon dioxide isolation layer between the SOI substrate 1 and the DLC film 8.

[0067] Please see Figure 5 and Figure 6 The present invention provides a method for fabricating an accelerometer chip with a DLC optimized structure, comprising the following steps:

[0068] 1) Cleaning and thermal oxidation of SOI substrate 1, refer to Figure 6 In step (a), after the SOI substrate 1 is cleaned by standard RCA, it is placed in a high-temperature oxidation furnace at 1100°C for high-temperature oxidation, so that silicon dioxide layers are generated on the upper and lower surfaces of the SOI substrate 1 respectively.

[0069] 2) Fabricate a varistor, referring to... Figure 6 Step (b) in the process involves photolithography of the front side of SOI substrate 1 using a varistor mask, with photoresist as a mask, and dry etching to remove the silicon dioxide layer of the varistor strip 5 to create a window in the varistor region; using the silicon dioxide layer as a mask, boron ions are implanted for light doping to form a varistor, then the silicon dioxide mask is removed, and the SOI substrate 1 is then subjected to high-temperature annealing to promote the redistribution of implanted impurities, remove lattice damage, and simultaneously generate a new silicon dioxide layer;

[0070] 3) Construct the ohmic contact area, referring to... Figure 6 Step (c) in the process; wherein, the ohmic contact area on the front side of SOI substrate 1 is photolithographically lithographically formed using an ohmic contact mask, with the silicon dioxide layer as a mask, and boron ion implantation is performed again for heavy doping; then, the SOI substrate 1 is subjected to diffusion annealing to promote the redistribution of implanted impurities, remove lattice damage, and ensure the uniform distribution and concentration requirements of doped impurities.

[0071] 4) Profound back vocalizations, refer to Figure 6 Step (d) in the process; wherein, the back cavity of SOI substrate 1 is photolithographically etched using a cavity deep mask, with the photoresist layer as a mask, and the silicon dioxide layer and the silicon substrate of SOI substrate 1 are etched sequentially using dry etching, with the buried oxide layer serving as an etching self-stopping layer during the etching process.

[0072] 5) Etch the moving cavity, refer to Figure 6 Step (e) in the middle; wherein, using a cavity mask to photolithographically etch boron glass 7, with a photoresist layer as a mask, a wet etching process is used to obtain the moving cavity on boron glass 7;

[0073] 6) Bonding, corresponding to Figure 6 Step (f) in the process; wherein, anodic bonding technology is used to directly bond the SOI substrate 1 and the borosilicate glass 7;

[0074] 7) Fabricate lead holes, sputter metal leads, and pads 2, referring to... Figure 6 Step (g) in the process involves first depositing a silicon dioxide layer on the surface of SOI substrate 1, then photolithographically etching lead holes using a lead hole mask, with a photoresist layer as a mask, removing the silicon dioxide in the lead hole area using a dry etching process, and cleaning and drying SOI substrate 1; then photolithographically etching lead and pad patterns using a metal lead and pad mask, sputtering multiple layers of metal using a magnetron sputtering process, and obtaining the required surface metal leads and pads 2 through a lift-off process;

[0075] 8) Deposition of DLC film 8, refer to Figure 6 In step (h), for the high resistivity DLC film 8, front-side photolithography is performed using a pad mask, the photoresist layer is used as a mask to protect the pad 2, the DLC film 8 is deposited on the surface of the SOI substrate 1 using physical vapor deposition, and finally the pad 2 is exposed again by a stripping process.

[0076] 9) Frontal release structure, refer to Figure 6 Step (i) involves performing front-side photolithography using a front-side release mask, with photoresist as the mask, and then using a dry etching process to etch the remaining silicon film to release the sensor's sensitive structure.

[0077] 10) Dicing; wherein, laser dicing is used to dic the wafer along a pre-processed dicing groove to form a single sensor chip.

[0078] Please see Figure 5 and Figure 7 The present invention provides a method for fabricating an accelerometer chip with a DLC optimized structure, comprising the following steps:

[0079] 1) Cleaning and thermal oxidation of SOI substrate 1, refer to Figure 7 Step (a); wherein, after the SOI substrate 1 is cleaned by standard RCA, it is placed in a high-temperature oxidation furnace at 1100°C for high-temperature oxidation, so that silicon dioxide layers are generated on the upper and lower surfaces of the SOI substrate 1 respectively.

[0080] 2) Fabricate a varistor, referring to... Figure 7 Step (b) involves photolithography of the front side of SOI substrate 1 using a varistor mask, with photoresist as a mask, and dry etching to remove the silicon dioxide layer of the varistor strip 5 to create a window in the varistor region. The silicon dioxide layer is then used as a mask for light doping by boron ion implantation to form a varistor. After removing the silicon dioxide mask, SOI substrate 1 is subjected to high-temperature annealing to promote the redistribution of implanted impurities, remove lattice damage, and simultaneously generate a new silicon dioxide layer.

[0081] 3) Construct the ohmic contact area, referring to... Figure 7 Step (c) involves photolithography of the ohmic contact area on the front side of SOI substrate 1 using an ohmic contact mask, with a silicon dioxide layer as a mask, followed by boron ion implantation for heavy doping. Then, SOI substrate 1 is subjected to diffusion annealing to promote the redistribution of implanted impurities, remove lattice damage, and ensure the uniform distribution and concentration requirements of doped impurities.

[0082] 4) Profound back vocalizations, refer to Figure 7 Step (d); wherein, the back cavity of SOI substrate 1 is photolithographically etched using a cavity deep mask, the photoresist layer is used as a mask, and the silicon dioxide layer and the silicon substrate of SOI substrate 1 are etched sequentially using dry etching, with the buried oxide layer serving as an etching self-stopping layer during the etching process.

[0083] 5) Etch the moving cavity, refer to Figure 7 Step (e); wherein, using a cavity mask to photolithographically etch boron glass 7, with a photoresist layer as a mask, a wet etching process is used to obtain the moving cavity on boron glass 7;

[0084] 6) Bonding, corresponding to Figure 7 Step (f); wherein, anodic bonding technology is used to directly bond the SOI substrate 1 and the borosilicate glass 7;

[0085] 7) Fabricate lead holes, sputter metal leads, and pads 2, referring to... Figure 7 Step (g) involves: firstly, a silicon dioxide layer is deposited on the surface of SOI substrate 1; then, lead holes are photolithographically patterned on the front side using a lead hole mask, with a photoresist layer as a mask; the silicon dioxide in the lead hole area is removed using a dry etching process; and SOI substrate 1 is cleaned and dried. Then, lead and pad patterns are photolithographically patterned using a metal lead and pad mask; multilayer metal is sputtered using a magnetron sputtering process; and the required metal leads and pads 2 are obtained through a lift-off process.

[0086] 8) Deposition of DLC film 8, refer to Figure 7 The (h) step; wherein, for the low resistivity DLC film 8, front-side photolithography is performed using a pad mask, and the photoresist layer is used as a mask to protect the pad 2. First, a silicon dioxide layer is deposited on the surface as an electrical isolation layer. Then, a physical vapor deposition process is used to deposit the DLC film 8 on the surface of the SOI substrate 1. Finally, the pad 2 is exposed again by a stripping process.

[0087] 9) Frontal release structure, refer to Figure 7 Step (i); wherein, front-side photolithography is performed using a front-side release mask, photoresist is used as a mask, and the remaining silicon film is etched using a dry etching process to release the sensor sensitive structure;

[0088] 10) Dicing; wherein, laser dicing is used to dic the wafer along a pre-processed dicing groove to form a single sensor chip.

[0089] In summary, the technical solution provided by the embodiments of the present invention obtains a strength-enhancing beam by depositing a DLC film with good insulation and high Young's modulus on the surface of the accelerometer chip. While ensuring high sensitivity, this significantly improves the strength of the sensitive structure of the accelerometer and increases the natural frequency to a certain extent; it also avoids complicating the sensor structure, reduces the difficulty of processing, and improves the reliability of the structure. The present invention deposits a high sp[…] on the surface of the accelerometer chip… 3The DLC film with high resistivity possesses excellent chemical stability, corrosion resistance, thermal conductivity, thermal shock resistance, and wear resistance, providing effective isolation and protection for the surface metal leads and varistor strips of the sensor chip, significantly improving the sensor's reliability and lifespan. This invention also considers employing multiple process schemes for DLC films with different resistivities. For high-resistivity DLC films, a method of directly depositing the DLC film on the SOI substrate is used, reducing process steps. For low-resistivity DLC films, a process scheme of depositing a silicon dioxide isolation layer between the SOI substrate and the DLC film is used, achieving electrical isolation, reducing the resistivity requirements of the DLC film, and broadening the range of usable DLC films. The embedded microbeam structure used in this invention maximizes the mass block weight and microbeam length within the same sensor chip size, thereby improving sensor sensitivity and reducing sensor size. This invention uses an SOI substrate to process the sensitive structure of the accelerometer chip, allowing for precise control of structural dimensions, especially by fully utilizing the buried oxide layer of SOI as an etching self-stopping layer, thus ensuring the accuracy of the embedded microbeam thickness.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An acceleration sensor chip of a DLC optimized structure, characterized by, include: SOI substrate (1) and borosilicate glass (7), SOI substrate (1) includes substrate frame and central mass block (3); The SOI substrate (1) is bonded to the borosilicate glass (7) through the substrate frame. The central mass block (3) is connected to the substrate frame through four embedded microbeams (4) arranged in a cross shape. Four varistor strips (5) are arranged on the four embedded microbeams (4). The four varistor strips (5) are connected to form a Wheatstone bridge through surface metal leads (6) deposited on the SOI substrate (1) and connected to the pads (2) deposited on the SOI substrate (1). Among them, the central mass block (3) and the substrate frame and borosilicate glass (7) are provided with gaps for working space; a DLC film (8) is deposited on the SOI substrate (1), and the DLC film (8) covers the surface metal leads (6), four varistor strips (5) and the area of ​​the SOI substrate (1) except for the pads (2).

2. The accelerometer chip with a DLC optimized structure according to claim 1, characterized in that, The thickness of the DLC film (8) is 100nm to 200nm; The sp of the DLC employed in the DLC film (8) is 3 The content of the bond is higher than 80%, and the Young's modulus is 300 Mpa ~ 600 Mpa.

3. The accelerometer chip with a DLC optimized structure according to claim 1, characterized in that, The resistivity of the DLC film (8) is greater than or equal to 1×10⁻⁶. 8 Ω·cm.

4. The accelerometer chip with a DLC optimized structure according to claim 1, characterized in that, The resistivity of the DLC film (8) is less than 1 x 10 8 Ω-cm; A silicon dioxide isolation layer is deposited between the SOI substrate (1) and the DLC film (8).

5. An accelerometer chip with a DLC optimized structure according to claim 1, characterized in that, The thickness of the central mass block (3) is the same as the thickness of the substrate frame, and the borosilicate glass (7) has grooves etched at the position corresponding to the central mass block (3).

6. The accelerometer chip with a DLC optimized structure according to claim 1, characterized in that, The embedded microbeam (4) is fabricated on the device layer of the SOI substrate (1), and the thickness of the embedded microbeam (4) is 15μm to 50μm.

7. An accelerometer chip with a DLC optimized structure according to claim 1, characterized in that, The four embedded microbeams (4) are the same size, and the four varistor strips (5) have the same resistance value. Among the four embedded microbeams (4), two opposite embedded microbeams (4) are grouped together. The four varistor strips (5) are respectively set on the four embedded microbeams (4). The varistor strips (5) set on the two embedded microbeams (4) in one group are close to the center of the central mass block (3), and the varistor strips (5) set on the two embedded microbeams (4) in the other group are far away from the center of the central mass block (3). Alternatively, the four varistor strips (5) are respectively set at both ends of the two embedded microbeams (4) in the same group.

8. An accelerometer chip with a DLC optimized structure according to claim 1, characterized in that, The four embedded microbeams (4) are embedded microbeam I (4-1), embedded microbeam II (4-2), embedded microbeam III (4-3), and embedded microbeam IV (4-4). Among them, embedded microbeam I (4-1) and embedded microbeam II (4-2) are a pair, and embedded microbeam I (4-1) and embedded microbeam II (4-2) have the same size. Embedded microbeam III (4-3) and embedded microbeam IV (4-4) are another pair, and embedded microbeam III (4-3) and embedded microbeam IV (4-4) have the same size. The size of embedded microbeam I (4-1) and embedded microbeam II (4-2) is smaller than that of embedded microbeam III (4-3) and embedded microbeam IV (4-4). The four varistor strips (5) are varistor strip I (5-1), varistor strip II (5-2), varistor strip III (5-3), and varistor strip IV (5-4); Among them, the resistance values ​​of the four varistor strips (5) are the same; varistor strips III (5-3) and IV (5-4) are respectively set at the two ends of the embedded microbeam I (4-1) near the center of the central mass block, and varistor strips II (5-2) and I (5-1) are respectively set at the two ends of the embedded microbeam II (4-2) near the center of the central mass block.

9. An accelerometer chip with a DLC optimized structure according to claim 1, characterized in that, The surface metal lead (6) adopts a Pt-Ti-Pt-Au multilayer structure; wherein, the ohmic contact area is made of Pt, and the lead layer adopts a Ti-Pt-Au multilayer metal lead structure; in the lead layer, the Ti layer is used as the adhesive layer, and the Au layer is the top metal layer.

10. A method of manufacturing an acceleration sensor chip of the DLC-optimized structure according to claim 1, characterized in that Includes the following steps: Step 1: Clean and thermally oxidize the SOI substrate to prepare an SOI substrate with silicon dioxide layers on the upper and lower surfaces respectively; Step 2: Photolithography is performed on the front side of the SOI substrate obtained in Step 1 using a varistor mask. The photoresist is used as a mask, and a dry etching process is used to remove the silicon dioxide layer of the varistor strip to create a window in the varistor region. The silicon dioxide layer is then used as a mask for light doping by boron ion implantation to form the varistor strip. After removing the silicon dioxide layer, the SOI substrate is then subjected to high-temperature annealing to promote the redistribution of implanted impurities to remove lattice damage and generate a new silicon dioxide layer. Step 3: Using an ohmic contact mask, the front ohmic contact area of ​​the SOI substrate after step 2 is photolithographically etched. The silicon dioxide layer is used as a mask, and boron ion implantation is performed again for heavy doping. After that, the SOI substrate is subjected to diffusion annealing to promote the redistribution of implanted impurities and remove lattice damage, ensuring the uniform distribution and concentration requirements of doped impurities. Step 4: Use a cavity deep mask to photolithographically etch the back cavity of the SOI substrate after step 3, with the photoresist layer as a mask, and use dry etching to sequentially etch the silicon dioxide layer and the silicon substrate of the SOI substrate. During the etching process, the buried oxide layer serves as an etching self-stopping layer. Step 5: Using anodic bonding technology, the SOI substrate treated in step 4 is directly bonded to borosilicate glass; A silicon dioxide layer is deposited on the surface of the SOI substrate. Then, lead holes are photolithographically patterned on the front side using a lead hole mask. A photoresist layer is used as a mask, and the silicon dioxide in the lead hole area is removed using a dry etching process. The SOI substrate is then cleaned and dried. Next, surface metal lead and pad patterns are photolithographically patterned using a metal lead and pad mask. Multilayer metal is sputtered using a magnetron sputtering process, and surface metal lead and pads are obtained through a lift-off process. Step 6: Deposit a DLC film on the SOI substrate after the processing in step 5; wherein, a front-side photolithography is performed using a pad mask, and a photoresist layer is used as a mask to protect the pads. A physical vapor deposition process is used to deposit a DLC film on the upper surface of the SOI substrate. Finally, a stripping process is used to expose the pads again, so that the DLC film covers the surface metal leads, varistor strips, and the area of ​​the SOI substrate other than the pads. Step 7: Based on the SOI substrate processed in Step 6, release the sensor sensitive structure and dicing it to obtain a single sensor chip.

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