Mask and method of manufacturing mask

Abstract

A mask and a method of manufacturing a mask are provided. The method of manufacturing a mask includes: defining a plurality of cell regions and a mask frame region on a silicon substrate, the mask frame region not including the plurality of cell regions, the mask frame region may include a mask rib region separating the plurality of cell regions and an outer frame region disposed at an outermost position of the silicon substrate; forming a groove in the mask rib region; forming a metal mask rib by forming a metal piece in the recess; forming a photoresist pattern including a plurality of openings in each of the plurality of cell regions; growing a plating film in each of the plurality of unit regions; forming a mask film formed by the plating film by removing the photoresist pattern; and etching the back surface of the silicon substrate to form a plurality of cell openings associated with the plurality of cell regions, respectively.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0128901 filed in the Korean Intellectual Property Office on September 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to masks for deposition and methods of making masks. Background Art

[0004] Wearable devices are being developed in the form of glasses or helmets and form a focus at a position close to the user's eyes. For example, the wearable device may be a head-mounted display (HMD) device or AR glasses. Such a wearable device provides the user with an augmented reality (hereinafter referred to as "AR") screen or a virtual reality (hereinafter referred to as "VR") screen.

[0005] Wearable devices such as HMD devices and AR glasses require display specifications of at least 2000 PPI (pixels per inch) to allow users to use for a long time without feeling dizzy. For this reason, organic light-emitting diodes on silicon (OLEDoS) are emerging, which are high-resolution small organic light-emitting element display devices. OLEDoS is a technology that arranges organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is arranged.

[0006] It is to be understood that this background technology section is intended, in part, to provide a useful background for understanding the technology. However, this background technology section may also include ideas, concepts or cognitions that were not known or recognized by a person skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0007] Various aspects provide a method of manufacturing a mask capable of preventing sagging of the mask by applying a magnetic metal to a rib of the mask.

[0008] According to an embodiment, a method for manufacturing a mask may include: defining a plurality of unit regions and a mask frame region on a silicon substrate, the mask frame region not including the plurality of unit regions, wherein the mask frame region may include a mask rib region separating the plurality of unit regions and an outer frame region arranged at an outermost position of the silicon substrate; forming a groove in the mask rib region; forming a metal mask rib by forming a metal member in the groove; forming a photoresist pattern including a plurality of openings in each of the plurality of unit regions; growing a plating film in each of the plurality of unit regions; forming a mask film formed of the plating film by removing the photoresist pattern; and etching a rear surface of the silicon substrate to form a plurality of unit openings respectively associated with the plurality of unit regions.

[0009] The cross section of the mask film may have a substantially inverse tapered shape in which the width becomes narrower from the front side of the silicon substrate toward the back side of the silicon substrate.

[0010] The thickness of the metal mask rib may be greater than the thickness of the mask film.

[0011] The mask film may include mask shadow portions formed by the plating film and mask openings arranged between adjacent mask shadow portions.

[0012] The cross-section of the mask opening may have a generally tapered shape in which the width becomes wider from the front side of the silicon substrate toward the back side of the silicon substrate.

[0013] The coating may contain tungsten (W).

[0014] The plated film may contain copper (Cu).

[0015] According to an embodiment, a method for manufacturing a mask may include: defining a plurality of unit regions and a mask frame region on a silicon substrate, the mask frame region not including the plurality of unit regions, wherein the mask frame region may include a mask rib region separating the plurality of unit regions and an outer frame region arranged at an outermost position of the silicon substrate; forming a groove in the mask rib region; forming a metal mask rib by forming a metal member in the groove; forming an inorganic film in each of the plurality of unit regions; forming a photoresist pattern including a plurality of openings on the inorganic film; forming a mask film by etching a portion of the inorganic film using the photoresist pattern; removing the photoresist pattern; and etching a rear surface of the silicon substrate to form a plurality of unit openings respectively associated with the plurality of unit regions.

[0016] The cross section of the mask film may have a substantially inverse tapered shape in which the width becomes narrower from the front side of the silicon substrate toward the back side of the silicon substrate.

[0017] The thickness of the metal mask rib may be greater than the thickness of the mask film.

[0018] The mask film may include mask shadow portions formed of an inorganic film and mask openings disposed between adjacent mask shadow portions.

[0019] The cross-section of the mask opening may have a generally tapered shape in which the width becomes wider from the front side of the silicon substrate toward the back side of the silicon substrate.

[0020] According to an embodiment, a deposition mask may include: a silicon substrate including a plurality of unit regions and a mask frame region, the mask frame region not including the plurality of unit regions, wherein the mask frame region may include a mask rib region separating the plurality of unit regions and an outer frame region arranged at an outermost position of the silicon substrate; metal mask ribs arranged in the mask rib region; and a mask film arranged in each of the plurality of unit regions.

[0021] The mask film may be formed of a plated film disposed on a silicon substrate.

[0022] The coating may contain tungsten (W).

[0023] The plated film may contain copper (Cu).

[0024] The mask film may be formed of an inorganic film disposed on a silicon substrate.

[0025] The cross section of the mask film may have a substantially inverse tapered shape in which the width becomes narrower from the front side of the silicon substrate toward the back side of the silicon substrate.

[0026] The thickness of the metal mask rib may be greater than the thickness of the mask film.

[0027] Each of the plurality of cell regions may include a cell opening exposing the mask film as the rear surface of the silicon substrate is etched.

[0028] According to an embodiment, sagging of a mask can be prevented by applying a magnetic metal to a mask rib, and the alignment accuracy of the mask can be increased and uneven defects caused by sagging of the mask can be prevented.

[0029] However, the various aspects are not limited to the aspects set forth herein. The above and other aspects will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0031] Figure 1 is a schematic perspective view of a head mounted display device according to an embodiment.

[0032] Figure 2 yes Figure 1 An exploded perspective view of an example of a head mounted display device.

[0033] Figure 3 is a schematic perspective view of a head mounted display device according to an embodiment.

[0034] Figure 4 is an exploded perspective view showing a display device according to an embodiment.

[0035] Figure 5 is a schematic cross-sectional view showing an example of a portion of a display panel according to an embodiment.

[0036] Figure 6 is a schematic perspective view of a mask according to an embodiment.

[0037] Figure 7 is a schematic plan view of a mask according to an embodiment.

[0038] Figure 8 is a flowchart for illustrating a method of manufacturing a mask according to an embodiment.

[0039] Figures 9 to 14 Schematic cross-sectional views for illustrating process steps of a method of manufacturing a mask according to an embodiment.

[0040] Fig.15 is a flowchart for illustrating a method of manufacturing a mask according to an embodiment.

[0041] Figures 16 to 21 Is used for illustration Fig.15 Schematic cross-sectional views of process steps of a method for manufacturing a mask are shown in FIG. DETAILED DESCRIPTION

[0042] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings in which embodiments are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0043] In the drawings, the size, thickness, ratio, and dimensions of elements may be exaggerated for convenience of description and for clarity. Like reference numerals refer to like elements throughout the specification.

[0044] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in the sense of a conjunction or an antonymous conjunction and may be understood to be equivalent to "and / or".

[0046] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0047] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0048] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the "second" element. Similarly, the second element may also be referred to as the first element.

[0049] The term "overlap" or "overlapped" means that a first object may be above or below or to the side of a second object, and vice versa. Additionally, the term "overlap" may include laminating, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term as will be recognized and understood by those of ordinary skill in the art.

[0050] The terms "facing" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where the third element is between the first element and the second element, although still facing each other, the first element and the second element can be understood to be indirectly opposite to each other.

[0051] When an element is described as “non-overlapping” or “non-overlapping” another element, this may include elements being spaced apart from each other, elements being offset from each other, or elements being separated from each other, or any other suitable terminology as one of ordinary skill in the art would recognize and understand.

[0052] The terms “comprise,” “comprising,” “include,” “including,” “has,” “have,” and / or “having,” and variations thereof, when used in the present specification, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0053] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0054] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and will not be interpreted in an idealized or overly formal sense.

[0055] It will be understood that when an element (or region, layer, part, etc.) is referred to as being "on", "connected to" or "coupled to" another element in the specification, the element can be directly arranged on, connected to or coupled to the other element mentioned above, or intervening elements may be arranged therebetween.

[0056] It will be understood that the term "connected to" or "coupled to" may include a physical connection or coupling or an electrical connection or coupling.

[0057] The features of each of the various embodiments may be partially or completely combined with each other and may technically cooperate with each other differently, and the respective embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0058] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0059] Figure 1 is a schematic perspective view of a head mounted display device according to an embodiment. Figure 2 yes Figure 1 An exploded perspective view of an example of a head mounted display device.

[0060] refer to Figure 1 and Figure 2 According to an embodiment, the head-mounted display device 1 may include a first display device 10_1, a second display device 10_2, a display device housing 110, a housing cover 120, a first eyepiece 131, a second eyepiece 132, a headband 140, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170 and a connector. Figure 1 and Figure 2A first direction X, a second direction Y, and a third direction Z are illustrated.

[0061] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is connected to the reference Figure 4 and Figure 5 The display devices 10 described are substantially the same. Therefore, the description of the first display device 10_1 and the second display device 10_2 will be referred to as Figure 4 and Figure 5 Description instead.

[0062] The first optical member 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0063] The middle frame 160 may be disposed between the first display device 10_1 and the control circuit board 170, and may be disposed between the second display device 10_2 and the control circuit board 170. The middle frame 160 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0064] The control circuit board 170 may be disposed between the middle frame 160 and the display device housing 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 170 may convert an image source input from the outside into digital video data (DATA), and transmit the digital video data (DATA) to the first display device 10_1 and the second display device 10_2 through the connector.

[0065] The control circuit board 170 may transmit digital video data (DATA) related to a left-eye image optimized for the left eye of the user to the first display device 10_1, and transmit digital video data (DATA) related to a right-eye image optimized for the right eye of the user to the second display device 10_2. By way of example, the control circuit board 170 may transmit the same digital video data (DATA) to the first display device 10_1 and the second display device 10_2.

[0066] The display device housing 110 accommodates the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The housing cover 120 is arranged to cover the open face of the display device housing 110. The housing cover 120 may include a first eyepiece 131 in which the user's left eye is placed and a second eyepiece 132 in which the user's right eye is placed. Although the first eyepiece 131 and the second eyepiece 132 are in Figure 1 and Figure 2 13 and 132. In the example shown in FIG. 13, the first eyepiece 131 and the second eyepiece 132 are separately arranged, but the embodiment is not limited thereto. The first eyepiece 131 and the second eyepiece 132 may be combined into a single element.

[0067] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Therefore, the user may observe a virtual image of the image on the first display device 10_1 magnified by the first optical member 151 through the first eyepiece 131, and observe a virtual image of the image on the second display device 10_2 magnified by the second optical member 152 through the second eyepiece 132.

[0068] The headband 140 fixes the display device housing 110 to the user's head so that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 are aligned with the left eye and the right eye of the user, respectively. By realizing a light and small display device housing 120, the head mounted display device 1 may include a Figure 3 140 is a frame of glasses shown in FIG.

[0069] The head mounted display device 1 may further include a battery for supplying power, an external memory slot for inserting an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a USB (Universal Serial Bus) terminal, a display port, or an HDMI (High Definition Multimedia Interface) terminal. The wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0070] Figure 3 is a schematic perspective view of a head mounted display device according to an embodiment.

[0071] refer to Figure 3 The head mounted display device 1_1 according to the embodiment may be a glasses type display device having a light and small display device housing 120_1. The head mounted display device 1_1 according to the embodiment may include a display device 10_3, a left eye lens 311, a right eye lens 312, a support frame 350, temples 341 and 342, an optical member 320, an optical path conversion member 330, and a display device housing 120_1.

[0072] Figure 3 The display device 10_3 shown in FIG. Figure 4 and Figure 5 The display device 10 described is substantially the same. Therefore, the description of the display device 10_3 will be referred to as Figure 4 and Figure 5 Description instead.

[0073] The display device housing 120_1 may include a display device 10_3, an optical member 320, and an optical path conversion member 330. An image displayed on the display device 10_3 may be magnified by the optical member 320, and an optical path of the image may be converted by the optical path conversion member 330 to be provided to the right eye of the user through the right eye lens 312. Therefore, the user is able to view an augmented reality image combining a virtual image displayed on the display device 10_3 and a real-world image observed through the right eye lens 312 with the right eye.

[0074] Although in Figure 3 In the example shown in FIG. 1 , the display device housing 120_1 is arranged at the right end of the support frame 350, but the embodiment is not limited thereto. For example, the display device housing 120_1 may be arranged at the left end of the support frame 350. In this case, the image displayed on the display device 10_3 may be provided to the left eye of the user. By way of example, the display device housing 120_1 may be arranged at both the left and right ends of the support frame 350, respectively. In this case, the user can view the image displayed on the display device 10_3 through the left eye and the right eye.

[0075] Figure 4 is an exploded perspective view showing a display device according to an embodiment.

[0076] refer to Figure 4 , the display device 10 according to the embodiment displays a moving image or a still image. The display device 10 according to the embodiment can be adopted by portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMP), navigation devices, and ultra-mobile personal computers (UMPC). For example, the display device 10 can be used as a display unit of a television, a notebook computer, a monitor, an electronic billboard, or an Internet of Things (IOT) device. By way of example, the display device 10 can be applied to a smart watch, a watch phone, or a head-mounted display (HMD) for realizing virtual reality and augmented reality.

[0077] According to an embodiment, the display device 10 may include a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a driver circuit 440 , and a power circuit 450 .

[0078] When viewed from the top, the display panel 410 may have a shape similar to a rectangular shape. For example, when viewed from the top, the display panel 410 may have a shape similar to a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 410, a corner where a short side in the first direction DR1 intersects with a long side in the second direction DR2 may be optionally rounded or may be a right angle. When viewed from the top, the shape of the display panel 410 is not limited to a rectangular shape, but may be formed into a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The shape of the display device 10 may follow the shape of the display panel 410 when viewed from the top, but the embodiment is not limited thereto.

[0079] The display panel 410 may include a display area in which an image is displayed and a non-display area in which no image is displayed.

[0080] The display area may include a plurality of pixels, and each of the plurality of pixels may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 (see Figure 5 ). The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 include a plurality of pixel transistors. The pixel transistors are formed by a semiconductor process and may be arranged on a semiconductor substrate SSUB (see Figure 5 For example, the pixel transistor may be implemented as a complementary metal oxide semiconductor (CMOS).

[0081] The heat dissipation layer 420 may overlap the display panel 410 in the third direction DR3 which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be arranged on one surface or surfaces of the display panel 410, for example, on the rear surface. The heat dissipation layer 420 is used to discharge heat generated in the display panel 410. The heat dissipation layer 420 may include a metal layer having high thermal conductivity, such as a layer of graphite, silver (Ag), copper (Cu), and aluminum (Al).

[0082] The circuit board 430 may be electrically connected to a plurality of pads in the pad region of the display panel 410 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board made of a flexible material, or a flexible film. Figure 4 The circuit board 430 is unfolded, but the circuit board 430 may be bent. In the case where the circuit board 430 is bent, one end or ends of the circuit board 430 may be arranged on the rear surface of the display panel 410. One end of the circuit board 430 may be opposite to an opposite end of the circuit board 430 connected to a pad in a pad area of ​​the display panel 410 using a conductive adhesive member.

[0083] The driver circuit 440 may receive digital video data and a timing signal from the outside. The driver circuit 440 may generate a scan timing control signal, an emission timing control signal, and a data timing control signal for controlling the display panel 410 in response to the timing signal.

[0084] The power supply circuit 450 may generate a plurality of panel driving voltages in response to a supply voltage from the outside. For example, the power supply circuit 450 may generate a first supply voltage, a second supply voltage, and a third supply voltage to apply them to the display panel 410.

[0085] Each of the driver circuit 440 and the power circuit 450 may be implemented as an integrated circuit (IC) and attached to a surface of the circuit board 430 .

[0086] Figure 5 is a schematic cross-sectional view showing an example of a portion of a display panel according to an embodiment. For example, Figure 5 A cross-sectional structure of a portion of a display area that may include a first sub-pixel SP1 , a second sub-pixel SP2 , and a third sub-pixel SP3 is shown.

[0087] refer to Figure 5 , the display panel 410 may include a semiconductor backplane SBP, an emission material backplane EBP, an emission material layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL, and a polarizer (not shown).

[0088] The semiconductor backplane SBP may include a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the pixel transistors PTR, respectively.

[0089] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions may be positioned (or arranged) in the upper surface of the semiconductor substrate SSUB. The well region may be doped with a second type of impurity. The second type of impurity may be different from the first type of impurity. For example, in the case where the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. For example, in the case where the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0090] Each of the plurality of well regions may include a source area SA associated with a source electrode of the pixel transistor PTR, a drain area DA associated with a drain electrode of the pixel transistor PTR, and a channel area CH between the source area SA and the drain area DA.

[0091] Each of the source region SA and the drain region DA may be doped with a first type impurity. The gate electrode GE of the pixel transistor PTR may overlap the well region in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be positioned on one side or on the side of the gate electrode GE, and the drain region DA may be positioned on the opposite side of the gate electrode GE.

[0092] Each of the plurality of well regions may further include a first low-concentration impurity region disposed between the channel region CH and the source region SA and a second low-concentration impurity region disposed between the channel region CH and the drain region DA. The first low-concentration impurity region may have an impurity concentration lower than that of the source region SA. The second low-concentration impurity region may have an impurity concentration lower than that of the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first low-concentration impurity region and the second low-concentration impurity region. Therefore, the length of the channel region CH of each of the plurality of pixel transistors PTR can be increased, and thus punch-through and hot carrier phenomena caused by a short channel can be prevented.

[0093] The first semiconductor insulating film SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be made of silicon carbonitride (SiCN) or silicon oxide (SiO x )-based inorganic film formation, but not limited to this.

[0094] The second semiconductor insulating film SINS2 may be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiment is not limited thereto.

[0095] A plurality of contact terminals CTE may be arranged on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to one of the gate electrode GE, the source area SA, and the drain area DA of each of the plurality of pixel transistors PTR through a hole penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film INS2. The contact terminal CTE may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these materials.

[0096] The third semiconductor insulating film SINS3 may be arranged on the side surface of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE may not be covered by the third semiconductor insulating film SINS3 but may be exposed. The third semiconductor insulating film SINS3 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiment is not limited thereto.

[0097] The semiconductor substrate SSUB may be replaced by a glass substrate or a polymer resin substrate such as polyimide. In this case, the thin film transistor may be arranged on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that does not bend, while the polymer resin substrate may be a flexible substrate that can be bent or folded.

[0098] The emission material back plate EBP may include first to eighth metal layers ML1 to ML8, first to fourth reflective electrodes RL1 to RL4, first to tenth through holes VA1 to VA10, and a step layer STPL. The emission material back plate EBP may include first to tenth interlayer dielectric films INS1 to INS10 disposed between the third semiconductor insulating film SINS3, the first to eighth metal layers ML1 to ML8, and the pixel defining film PDL.

[0099] The first to eighth metal layers ML1 to ML8 are used to implement a circuit of the first sub-pixel SP1 by connecting a plurality of contact terminals CTE exposed from the semiconductor backplane SBP.

[0100] The first interlayer dielectric film INS1 may be disposed on the semiconductor backplane SBP. Each of the plurality of first vias VA1 may penetrate the first interlayer dielectric film INS1 and may be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the plurality of first metal layers ML1 may be disposed on the first interlayer dielectric film INS1 and may be connected to the first vias VA1.

[0101] The second interlayer dielectric film INS2 may be disposed on the first interlayer dielectric film INS1 and the first metal layer ML1. Each of the plurality of second vias VA2 may penetrate through the second interlayer dielectric film INS2 to be connected to the exposed first metal layer ML1. Each of the plurality of second metal layers ML2 may be disposed on the second interlayer dielectric film INS2 and may be connected to the second vias VA2.

[0102] The third interlayer dielectric film INS3 may be disposed on the second interlayer dielectric film INS2 and the second metal layer ML2. Each of the plurality of third vias VA3 may penetrate through the third interlayer dielectric film INS3 to be connected to the exposed second metal layer ML2. Each of the plurality of third metal layers ML3 may be disposed on the third interlayer dielectric film INS3 and may be connected to the third via VA3.

[0103] The fourth interlayer dielectric film INS4 may be disposed on the third interlayer dielectric film INS3 and the third metal layer ML3. Each of the plurality of fourth vias VA4 may penetrate through the fourth interlayer dielectric film INS4 to be connected to the exposed third metal layer ML3. Each of the plurality of fourth metal layers ML4 may be disposed on the fourth interlayer dielectric film INS4 and may be connected to the fourth via VA4.

[0104] The fifth interlayer dielectric film INS5 may be disposed on the fourth interlayer dielectric film INS4 and the fourth metal layer ML4. Each of the plurality of fifth vias VA5 may penetrate through the fifth interlayer dielectric film INS5 to be connected to the exposed fourth metal layer ML4. Each of the plurality of fifth metal layers ML5 may be disposed on the fifth interlayer dielectric film INS5 and may be connected to the fifth via VA5.

[0105] The sixth interlayer dielectric film INS6 may be disposed on the fifth interlayer dielectric film INS5 and the fifth metal layer ML5. Each of the plurality of sixth vias VA6 may penetrate through the sixth interlayer dielectric film INS6 to be connected to the exposed fifth metal layer ML5. Each of the plurality of sixth metal layers ML6 may be disposed on the sixth interlayer dielectric film INS6 and may be connected to the sixth via VA6.

[0106] The seventh interlayer dielectric film INS7 may be disposed on the sixth interlayer dielectric film INS6 and the sixth metal layer ML6. Each of the plurality of seventh vias VA7 may penetrate through the seventh interlayer dielectric film INS7 to be connected to the exposed sixth metal layer ML6. Each of the plurality of seventh metal layers ML7 may be disposed on the seventh interlayer dielectric film INS7 and may be connected to the seventh via VA7.

[0107] The eighth interlayer dielectric film INS8 may be disposed on the seventh interlayer dielectric film INS7 and the seventh metal layer ML7. Each of the plurality of eighth vias VA8 may penetrate through the eighth interlayer dielectric film INS8 to be connected to the exposed seventh metal layer ML7. Each of the plurality of eighth metal layers ML8 may be disposed on the eighth interlayer dielectric film INS8 and may be connected to the eighth via VA8.

[0108] The first metal layer ML1 to the eighth metal layer ML8 and the first through hole VA1 to the eighth through hole VA8 may be made of substantially the same material. The first metal layer ML1 to the eighth metal layer ML8 and the first through hole VA1 to the eighth through hole VA8 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy containing one of these materials. The first through hole VA1 to the eighth through hole VA8 may be made of substantially the same material. The first interlayer dielectric film INS1 to the eighth interlayer dielectric film INS8 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiment is not limited thereto.

[0109] The thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially all equal.

[0110] The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8. The thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8 may be greater than the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. The thickness of the seventh metal layer ML7 may be substantially equal to the thickness of the eighth metal layer ML8.

[0111] The ninth interlayer dielectric film INS9 may be disposed on the eighth interlayer dielectric film INS8 and the eighth metal layer ML8. The ninth interlayer dielectric film INS9 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiment is not limited thereto.

[0112] Each of the plurality of ninth vias VA9 may penetrate through the ninth interlayer dielectric film INS9 to be connected to the exposed eighth metal layer ML8. The ninth via VA9 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these materials.

[0113] The first reflective electrode RL1 may be disposed on the ninth interlayer dielectric film INS9 and may be connected to the ninth via VA9. The first reflective electrode RL1 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including one of these materials.

[0114] The second reflective electrode RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including one of these materials. For example, the second reflective electrode RL2 may be titanium nitride (TiN).

[0115] In the first sub-pixel SP1, the step layer STPL may be disposed on the second reflective electrode RL2. In each of the second sub-pixel SP2 and the third sub-pixel SP3, the step layer STPL may not be disposed. The thickness of the step layer STPL may be determined based on the wavelength of the light of the first color and the distance from the first intermediate layer IL1 to the fourth reflective electrode RL4, so that the light of the first color emitted from the first intermediate layer IL1 of the first sub-pixel SP1 is favorably reflected. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic film formation, but not limited to this.

[0116] In the first subpixel SP1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In the second subpixel SP2 and the third subpixel SP3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these materials.

[0117] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be eliminated.

[0118] The fourth reflective electrode RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may reflect light from the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3. The fourth reflective electrode RL4 may include a metal having a high reflectivity to facilitate light reflection. The fourth reflective electrode RL4 may be made of aluminum (Al), a stack of aluminum and titanium (Ti / Al / Ti), a stack of aluminum and ITO (ITO / Al / ITO), silver (Ag), palladium (Pd), an APC alloy as an alloy of copper (Cu), and a stack of an APC alloy and ITO (ITO / APC / ITO), but is not limited thereto.

[0119] The tenth interlayer dielectric film INS10 may be disposed on the ninth interlayer dielectric film INS9 and the fourth reflective electrode RL4. The tenth interlayer dielectric film INS10 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiment is not limited thereto.

[0120] Each of the plurality of tenth through holes VA10 may penetrate through the tenth interlayer dielectric film INS10 to be connected to the exposed fourth reflective electrode RL4. The tenth through hole VA10 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including one of these materials. Due to the step layer STPL, the thickness of the tenth through hole VA10 in the first sub-pixel SP1 may be less than the thickness of the tenth through hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3.

[0121] The emission material layer EML may be disposed on the emission material back plate EBP. The emission material layer EML may include: a plurality of light emitting elements LEL each including a first electrode AND, an intermediate layer IL, and a second electrode CAT; and a pixel defining film PDL.

[0122] The first electrode AND of each of the plurality of light emitting elements LEL may be arranged on the tenth interlayer dielectric film INS10 and may be connected to the tenth through hole VA10. The first electrode AND of each of the plurality of light emitting elements LEL may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth through hole VA10, the first reflective electrode RL1 to the fourth reflective electrode RL4, the first through hole VA1 to the ninth through hole VA9, the first metal layer ML1 to the eighth metal layer ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light emitting elements LEL may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these materials. For example, the first electrode AND of each of the plurality of light emitting elements LEL may be titanium nitride (TiN).

[0123] The pixel defining film PDL may be partially disposed on the first electrode AND of each of the plurality of light emitting elements LEL. The pixel defining film PDL may cover the edge of the first electrode AND of each of the plurality of light emitting elements LEL. The pixel defining film PDL is used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0124] The first emission area EA1 may be defined as an area in the first sub-pixel SP1, in which the first electrode AND, the intermediate layer IL, and the second electrode CAT may be sequentially stacked with each other to emit light. The second emission area EA2 may be defined as an area in the second sub-pixel SP2, in which the first electrode AND, the intermediate layer IL, and the second electrode CAT may be sequentially stacked with each other to emit light. The third emission area EA3 may be defined as an area in the third sub-pixel SP3, in which the first electrode AND, the intermediate layer IL, and the second electrode CAT may be sequentially stacked with each other to emit light.

[0125] The pixel definition film PDL may include a first pixel definition film PDL1, a second pixel definition film PDL2, and a third pixel definition film PDL3. The first pixel definition film PDL1 may be arranged on the edge of the first electrode AND of each of the plurality of light emitting elements LEL, the second pixel definition film PDL2 may be arranged on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be arranged on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiment is not limited thereto.

[0126] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0127] The intermediate layer IL may have a series structure including a first intermediate layer IL1, a second intermediate layer IL2, and a third intermediate layer IL3 that emit different lights. For example, the intermediate layer IL may include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a third color, and a third intermediate layer IL3 that emits light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked on each other.

[0128] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic emission layer emitting light of a first color, and a first electron transport layer may be sequentially stacked on each other. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic emission layer emitting light of a third color, and a second electron transport layer may be sequentially stacked on each other. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic emission layer emitting light of a second color, and a third electron transport layer may be sequentially stacked on each other.

[0129] The intermediate layer IL may cover the first electrode AND at the opening of the pixel defining film PDL, may cover the pixel defining film PDL between the adjacent first, second, and third sub-pixels SP1, SP2, and SP3, and may be partially disconnected.

[0130] According to an embodiment, by disconnecting the intermediate layer IL between the adjacent first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3, leakage current between the adjacent first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3 can be prevented and color crosstalk can be prevented. For example, color crosstalk refers to a phenomenon in which a red sub-pixel adjacent to a blue sub-pixel is accidentally turned on when the blue sub-pixel emits blue light. Since color crosstalk occurs due to leakage current, color crosstalk may occur when a blue sub-pixel and a red sub-pixel having a large difference in voltage for driving the sub-pixel are adjacent to each other. For example, when a driving current is supplied to a light-emitting element LEL of a blue sub-pixel so as to turn on the blue sub-pixel, a portion of the driving current may be transmitted to the red sub-pixel through at least some conductive layers of the intermediate layer IL, which is a leakage current. If a leakage current is generated, the red sub-pixel may be accidentally turned on while the blue sub-pixel is turned on.

[0131] The number of the first intermediate layers IL1, the second intermediate layers IL2, and the third intermediate layers IL3 that emit different lights is not limited to Figure 5 For example, the intermediate layer IL may include two intermediate layers. In this case, one of the two intermediate layers is substantially the same as the first intermediate layer IL1, and the other intermediate layer may include a second hole transport layer, a second organic emission layer, a third organic emission layer, and a second electron transport layer. In this case, the charge generation layer may be arranged between the two intermediate layers to supply electrons to one intermediate layer and supply charges to the other intermediate layer.

[0132] Although in Figure 5 The first intermediate layer IL1, the second intermediate layer IL2 and the third intermediate layer IL3 are all arranged in the first emission area EA1, the second emission area EA2 and the third emission area EA3, but the embodiment is not limited thereto. For example, the first intermediate layer IL1 may be arranged in the first emission area EA1, but not in the second emission area EA2 and the third emission area EA3. The second intermediate layer IL2 may be arranged in the second emission area EA2, but not in the first emission area EA1 and the third emission area EA3. The third intermediate layer IL3 may be arranged in the third emission area EA3, but not in the first emission area EA1 and the second emission area EA2. In this case, the first color filter CF1, the second color filter CF2 and the third color filter CF3 of the optical layer OPL may be eliminated.

[0133] The second electrode CAT may be arranged on the third intermediate layer IL3. The second electrode CAT may be arranged on the third intermediate layer IL3 in each of the plurality of grooves. The second electrode CAT may be formed of a transparent conductive material (TCP) such as ITO and IZO capable of transmitting light or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and an alloy of magnesium (Mg) and silver (Ag). In the case where the second electrode CAT is formed of a semi-transmissive conductive material, light extraction efficiency can be increased by using a microcavity in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0134] The encapsulation layer TFE may be arranged on the emission material layer EML. The encapsulation layer TFE may include one or more inorganic films to prevent oxygen or moisture from penetrating into the emission material layer EML. The encapsulation layer TFE may include at least one organic film to protect the emission material layer EML from particles such as dust. For example, the encapsulation layer TFE may include a first inorganic encapsulation film TFE1, an organic encapsulation film TFE2, and a second inorganic encapsulation film TFE3.

[0135] The first inorganic encapsulation film TFE1 may be disposed on the second electrode CAT, the organic encapsulation film TFE2 may be disposed on the first inorganic encapsulation film TFE1, and the second inorganic encapsulation film TFE3 may be disposed on the organic encapsulation film TFE2. The first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 may be formed of a silicon nitride layer (SiN x ), silicon oxynitride layer (SiON), silicon oxide layer (SiO x ), titanium oxide layer (TiO x ) and aluminum oxide layer (AlO x ) is made of a plurality of layers in which one or more inorganic layers are alternately stacked on each other. The organic encapsulation film TFE2 may be a monomer. By way of example, the organic encapsulation film TFE2 may be an organic film including, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0136] The adhesive layer ADL may bond the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. The adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive and a transparent adhesive resin.

[0137] The optical layer OPL may include a plurality of color filters, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0138] The first color filter CF1 may be consistent with the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of a first color, for example, light in a blue wavelength range. The blue wavelength range may be in the range of about 370 nm to about 460 nm. Therefore, the first color filter CF1 may transmit light of a first color among the light emitted from the first emission area EA1.

[0139] The second color filter CF2 may be consistent with the second emission area EA2 of the second subpixel SP2. The second color filter CF2 may transmit light of a second color, for example, light in a green wavelength range. The green wavelength range may be in the range of about 480 nm to about 560 nm. Therefore, the second color filter CF2 may transmit light of a second color among the light emitted from the second emission area EA2.

[0140] The third color filter CF3 may be consistent with the third emission area EA3 of the third sub-pixel SP3. The third color filter CF3 may transmit light of a third color, for example, light within a red wavelength range. The blue wavelength range may be within a range of about 600nm to about 750nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third emission area EA3.

[0141] A plurality of lenses LNS may be disposed on the first, second, and third color filters CF1, CF2, and CF3, respectively. Each of the plurality of lenses LNS may be a structure for increasing the proportion of light directed to the front side of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape convex upward.

[0142] The filling layer FIL may be arranged on the plurality of lenses LNS. The filling layer FIL may have a selectable refractive index so that light travels in the third direction DR3 at the interface between the plurality of lenses LNS and the filling layer FIL. The filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film including, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0143] The cover layer CVL may be arranged on the filling layer FIL. The cover layer CVL may be a glass substrate or a resin such as a polymer resin. If the cover layer CVL is a glass substrate, it may be attached to the filling layer FIL. In this case, the filling layer FIL may adhere to the cover layer CVL. If the cover layer CVL is a glass substrate, it may be used as a packaging substrate. If the cover layer CVL is a resin such as a polymer resin, it may be directly applied to the filling layer FIL.

[0144] A polarizer (not shown) may be arranged on the surface of the cover layer CVL. The polarizer may be a structure for preventing visibility degradation due to reflection of external light. The polarizer may include a linear polarizer and a retardation film. For example, the retardation film may be a λ / 4 plate (quarter wave plate), but the embodiment is not limited thereto. If visibility is sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3 regardless of reflection of external light, the polarizer may be omitted.

[0145] Figure 6 is a schematic perspective view of a mask according to an embodiment. Figure 7 is a schematic plan view of a mask according to an embodiment. Figure 6 In the schematic perspective view of , a plurality of unit masks UM are separated from each other. Figure 6 and Figure 7 The mask MK according to the embodiment shown in FIG. 1 can be used for depositing a Figure 5 The intermediate layer IL is used in the process of at least a portion of the intermediate layer IL of the display panel 410. For example, the intermediate layer IL may emit light of different colors from the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0146] refer to Figure 6 and Figure 7 , the mask MK according to the embodiment may be a shadow mask in which a mask film MM is disposed on the silicon substrate 700. The mask MK according to the embodiment may be referred to as a silicon mask.

[0147] According to an embodiment, the mask MK may include a silicon substrate 700, and a mask rib 7211 (see Fig.14 ) and a mask film MM may be arranged on the silicon substrate 700.

[0148] The mask rib 7211 is formed by a metal member 1010 (see Fig.10 ) is formed, as will be described later. Since the mask rib 7211 may include a metal material, the mask rib 7211 may be referred to as a metal mask rib, etc. within the spirit and scope of the present disclosure. The mask rib 7211 may be used interchangeably with terms such as "mask grid".

[0149] The mask film MM may be a portion of the unit mask UM arranged in each of the plurality of unit regions 710. The mask film MM is formed by the plating film 1210 (see Fig.12 ) or patterned inorganic film 1810 (see Fig. 20 ) is formed. If the mask film MM may include a metal material, the mask film MM may be referred to as a metal mask film, etc. in the spirit and scope of the present disclosure. In the case where the mask film MM may include a metal, a plating film 1210 (see Fig.12) and the metal member 1010 forming the mask rib 7211 may be made of the same material. For example, the mask rib 7211 and the mask film MM may include a plated film containing tungsten (W) or copper (Cu).

[0150] The silicon substrate 700 may include a plurality of cell regions 710 and a mask frame region 720 excluding the plurality of cell regions 710. The mask frame region 720 may include a mask rib area 721 in which mask ribs 7211 are arranged and an outer frame region 722 arranged at the outermost position of the silicon substrate 700. The mask frame MF is arranged in the mask frame region 720. The mask frame MF may include the mask ribs 7211 surrounding the cell regions 710. The silicon substrate 700 may be arranged in the outer frame region 722 as a part of the mask frame MF.

[0151] The mask rib area 721 may separate the plurality of unit areas 710. For example, the plurality of unit areas 710 may be arranged or disposed in a matrix, and the mask rib area 721 may surround the unit areas 710. The mask rib 7211 made of a metal material is disposed in the mask rib area 721. According to an embodiment, the mask rib 7211 is formed of a magnetic metal material, and thus the mask rib 7211 may be formed by using a magnetic member 1410 (see FIG. 14 ) inside a vapor deposition machine (not shown). Fig.14 ) (e.g., a magnetic chuck) to prevent the mask MK from sagging. For example, the mask MK according to the embodiment is designed so that the thickness of the mask rib 7211 is greater than the thickness of the mask film MM, thereby increasing the magnetic force with the magnetic member 1410 and preventing the mask MK from sagging.

[0152] A cell opening COP and a cell mask UM at least partially shielding the cell opening COP may be positioned in each of the plurality of cell regions 710 of the silicon substrate 700 .

[0153] The plurality of cell openings COP may penetrate the mask frame MF in a thickness direction (eg, third direction DR3) of the mask MK. The plurality of cell openings COP may be generated by partially etching the silicon substrate 700 from the back side.

[0154] Each unit mask UM may include a mask film MM. The mask film MM may include a mask shadow portion 1310 (see FIG. 1 ) that at least partially shields the unit opening COP. Fig.14 ) or mask shadow portion 2010 (see Fig.21 ) and a mask opening OP positioned between adjacent mask shadows 1310 or mask shadows 2010. The mask shadows 1310 or mask shadows 2010 may be arranged or disposed in a matrix in each unit mask UM, and the mask opening OP may be positioned between a plurality of mask shadows 1310 or a plurality of mask shadows 2010. For example, the mask shadows 1310 or mask shadows 2010 may be arranged or disposed to surround the mask opening OP.

[0155] The mask shadow portion 1310 or the mask shadow portion 2010 can be used as a deposition source DS (see FIG. Fig.14 ) is formed by a blocking unit that shields a substrate to be deposited (e.g., the display panel 410 or the backplane substrate) in the case of evaporation. Therefore, the deposition material generated from the deposition source DS can be deposited on the surface of the substrate to be deposited (e.g., the display panel 410 or the backplane substrate) through the mask opening OP of the mask film MM.

[0156] The mask opening OP of the mask film MM may be referred to as a hole or a mask hole. The mask opening OP may penetrate the unit mask UM in a thickness direction (eg, third direction DR3) of the mask MK.

[0157] One unit mask UM may be used in a process of depositing one display panel 410. As used herein, the term "unit mask UM" may be used interchangeably with terms such as "mask unit UM" and "a plurality of unit masks UM."

[0158] Figure 8 is a flowchart for illustrating a method of manufacturing a mask according to an embodiment.

[0159] Figures 9 to 14 Schematic cross-sectional views for illustrating process steps of a method of manufacturing a mask according to an embodiment.

[0160] In the following, reference Figures 8 to 14 , a method for manufacturing a mask according to an embodiment in which the mask film MM and the mask rib 7211 are formed of metal will be described. It should be noted that some of the manufacturing processes of the mask will be described. Other processes for forming the elements described herein may be additionally performed before or after the manufacturing process described below. The manufacturing process of the mask may be additionally performed before or after the manufacturing process described below.

[0161] refer to Figure 8 and Fig. 9 In step 810, a groove 910 may be formed in the mask rib region 721 of the silicon substrate 700. The silicon substrate 700 may be defined so that it is divided into a plurality of cell regions 710 and a mask frame region 720 other than the plurality of cell regions 710. The mask frame region 720 may include a mask rib region 721 surrounding the boundaries of the plurality of cell regions 710. In step 810, a groove 910 is formed in the defined mask rib region 721. The groove 910 provides a groove in which a mask rib 7211 (see FIG. 1 ) is formed in a subsequent process. Fig.10 ) space.

[0162] refer to Figure 8 and Fig.10In step 820, a metal member 1010 may be formed in the groove 910 to form a mask rib 7211. For example, the mask rib 7211 may be formed by growing a plated film in the groove 910. The plated film forming the mask rib 7211 may include tungsten (W) or copper (Cu). The mask rib 7211 may be formed in the groove 910 and may surround the boundary of the unit region 710 accordingly.

[0163] refer to Figure 8 and Fig.11 In step 830, a first photoresist pattern PR1 may be formed in each of the plurality of cell regions 710 of the silicon substrate 700. The first photoresist pattern PR1 may be formed by applying a photoresist composition on the silicon substrate 700 and patterning the photoresist composition. The first photoresist pattern PR1 may be arranged in each of the plurality of cell regions 710 and may include a plurality of first openings 1110. The plurality of first openings 1110 of the first photoresist pattern PR1 may expose the front surface of the silicon substrate 700 during the process.

[0164] Although not shown in the drawings, a seed metal layer may be disposed on the silicon substrate 700 , and a first photoresist pattern PR1 may be disposed on the seed metal layer.

[0165] The seed metal layer can be used as a plating prevention film 1210 in the case of performing electroplating (see Fig.12 ) penetrates into the silicon substrate 700 and can be used as a seed. The seed metal layer can be a single layer film selected from conductive metals such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), nickel (Ni), gold (Au) and molybdenum (Mo), or a multilayer film thereof.

[0166] refer to Figure 8 and Fig.12 In step 840, a plating film 1210 may be grown in each of the plurality of unit regions 710. The plating film 1210 may be grown in the first opening 1110 of the first photoresist pattern PR1. The plating film 1210 may be partially connected to the mask rib 7211 surrounding the boundary of the unit region 710. Embodiments are not limited to the plating film 1210 being connected to the mask rib 7211 at the boundary of the unit region 710. For example, at the boundary of the unit region 710, the plating film 1210 and the mask rib 7211 may not be connected to each other but may be disconnected from each other.

[0167] The cross section of the first photoresist pattern PR1 arranged around the plurality of first openings 1110 may have a tapered shape. For example, the first photoresist pattern PR1 may have a tapered shape by patterning a positive photoresist composition. The cross section of the first photoresist pattern PR1 has a tapered shape so that a cross section of a portion of the mask film MM (for example, the plated film 1210 to become the mask shadow portion 1310) has an inverted tapered shape.

[0168] refer to Figure 8 and Fig.13 In step 850, the first photoresist pattern PR1 may be removed. The plating film 1210 remaining after removing the first photoresist pattern PR1 may be used as a mask film MM in each of the plurality of unit regions 710. The mask shadow portion 1310 of the mask film MM may be formed by the plating film 1210, and the cross section may have an inverted tapered shape. The mask film MM may include the mask shadow portion 1310 formed by the plating film 1210 and a mask opening OP positioned between adjacent mask shadow portions 1310 (see Fig.14 ).

[0169] The cross section of the mask film MM may have an inverted tapered shape in which the width narrows from the front side of the silicon substrate 700 (the side in the third direction DR3) toward the back side of the silicon substrate 700 (the side in the fourth direction DR4). The cross section of the mask opening OP may have a tapered shape in which the width widens from the front side of the silicon substrate 700 (the side in the third direction DR3) toward the back side of the silicon substrate 700 (the side in the fourth direction DR4). According to an embodiment, since the cross section of the mask film MM has the inverted tapered shape, shadow defects during a deposition process may be reduced.

[0170] According to an embodiment, the mask rib 7211 is formed of a magnetic metal material, and thus can be formed by using a magnetic member 1410 (see FIG. 14A ) inside a vapor deposition machine (not shown). Fig.14 ) (e.g., a magnetic chuck) to prevent the mask MK from sagging. For example, in the mask MK according to the embodiment, the thickness of the mask rib 7211 is designed to be greater than the thickness of the mask film MM, thereby increasing the magnetic force with the magnetic member 1410 and preventing the mask MK from sagging.

[0171] According to an embodiment, the thickness L1 of the mask rib 7211 may be different from the thickness L2 of the mask film MM. By way of example, the thickness L1 of the mask rib 7211 is greater than the thickness L2 of the mask film MM. According to the present embodiment, the mask rib 7211 can have sufficient magnetic force so that the mask film MM can be prevented from sagging. For example, in the mask MK according to the embodiment, even if the mask film MM sags due to its own weight, the mask rib 7211 surrounding it applies a pulling force to the mask film MM with a relatively strong magnetic force. In this way, the sagging of the mask MK can be reduced.

[0172] refer to Figure 8 and Fig.14 In step 860, the silicon substrate 700 may be etched from the rear surface. For example, a second photoresist pattern (not shown) may be formed on the rear surface of the silicon substrate 700. The second photoresist pattern may include a plurality of second openings (not shown) for respectively defining unit openings COP associated with a plurality of unit masks UM. For example, each of the plurality of second openings may be associated with one unit opening COP. Subsequently, the silicon substrate 700 may be etched from the rear side (a side in the fourth direction DR4) of the silicon substrate 700 using the second photoresist pattern. The rear side (a side in the fourth direction DR4) refers to a side on which the deposition source DS is positioned. The rear surface of the mask film MM formed by the coating film 1210 may be exposed by etching the silicon substrate 700. Although not shown in the drawings, the seed metal layer deposited on the front surface of the silicon substrate 700 before growing the coating film 1210 may be used as an etching stop layer in the case of etching the silicon substrate 700 from the rear surface.

[0173] Fig.15 is a flowchart for illustrating a method of manufacturing a mask according to an embodiment.

[0174] Figures 16 to 21 Is used for illustration Fig.15 Schematic cross-sectional views of process steps of a method for manufacturing a mask are shown in FIG.

[0175] In the following, reference Figures 15 to 21 , a method for manufacturing a mask according to an embodiment will be described, wherein the mask rib 7211 is formed of the metal member 1010 and the mask film MM is formed of the inorganic film 1810. It should be noted that some of the manufacturing processes of the mask will be described. Other processes for forming the elements described herein may be additionally performed before or after the manufacturing process described below. The manufacturing process of the mask may be additionally performed before or after the manufacturing process described below.

[0176] refer to Fig.15 and Fig.16 In step 1510, a groove 910 may be formed in a mask rib region 721 of a silicon substrate 700. The silicon substrate 700 may be defined as being divided into a plurality of cell regions 710 and a mask frame region 720 other than the plurality of cell regions 710. The mask frame region 720 may include a mask rib region 721 surrounding the boundaries of the plurality of cell regions 710. In step 810, a groove 910 is formed in the defined mask rib region 721. The groove 910 provides a space in which a mask rib 7211 (see FIG. 1 ) is formed in a subsequent process. Fig.10 ) space.

[0177] Step 1510 can be compared with the above reference Figure 8 Step 810 described is substantially the same or similar.

[0178] refer to Fig.15 and Fig.17 In step 1520, a metal member 1010 may be formed in the groove 910 to form a mask rib 7211. For example, the mask rib 7211 may be formed by growing a plated film in the groove 910. The plated film forming the mask rib 7211 may include tungsten (W) or copper (Cu). The mask rib 7211 may be formed in the groove 910 and may surround the boundary of the unit region 710 accordingly.

[0179] Step 1520 can be compared with the above reference Figure 8 The described step 820 is substantially the same or similar.

[0180] refer to Fig.15 and Fig.18 In step 1530, an inorganic film 1810 may be formed in each unit region 710. The inorganic film 1810 may be deposited on each unit region 710. The inorganic film 1810 may include a silicon-based material. For example, the pattern of the inorganic film 1810 may include silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide layer (AlO x ) at least one of.

[0181] refer to Fig.15 and Fig.19 In step 1540, a first photoresist pattern may be formed on the inorganic film 1810. The first photoresist pattern PR1 may be formed by applying a photoresist composition on the inorganic film 1810 and patterning the photoresist composition. The first photoresist pattern PR1 may be arranged on the inorganic film 1810 in each of the plurality of unit regions 710 and may include a plurality of first openings 1910. The plurality of first openings 1910 of the first photoresist pattern PR1 may expose the front surface of the inorganic film 1810 during the process.

[0182] The cross section of the first photoresist pattern PR1 may have a tapered shape. For example, the first photoresist pattern PR1 may have a tapered shape by patterning a positive photoresist composition. The cross section of the first photoresist pattern PR1 has a tapered shape so that the cross section of the mask film MM has an inverted tapered shape.

[0183] refer to Fig.15 and Fig. 20In step 1550, the inorganic film 1810 may be partially etched using the first photoresist pattern PR1. In step 1550, the inorganic film 1810 may be etched in the first opening 1910 of the first photoresist pattern PR1. After etching the inorganic film 1810, the first photoresist pattern PR1 is removed. A portion of the inorganic film 1810 remaining after removing the first photoresist pattern PR1 may be referred to as a “pattern of the inorganic film 1810”. The pattern of the inorganic film 1810 remaining after the etching process using the first photoresist pattern PR1 may become the mask film MM. The mask shadow portion 2010 (see FIG. 2010 ) of the mask film MM Fig. 20 ) may be formed of the inorganic film 1810, and the cross section may have an inverted tapered shape. The mask film MM may include mask shadow portions 2010 formed of the inorganic film 1810 and mask openings OP positioned between adjacent mask shadow portions 2010 (see Fig.21 ).

[0184] According to an embodiment, the thickness L1 of the mask rib 7211 may be different from the thickness L2 of the mask film MM. By way of example, the thickness L1 of the mask rib 7211 is greater than the thickness L2 of the mask film MM. According to the present embodiment, the mask rib 7211 can have sufficient magnetic force so that the mask film MM can be prevented from sagging. For example, in the mask MK according to the embodiment, even if the mask film MM sags due to its own weight, the mask rib 7211 surrounding it applies a pulling force to the mask film MM with a relatively strong magnetic force. In this way, the sagging of the mask MK can be reduced.

[0185] refer to Fig.15 and Fig.21 In step 1560, the rear surface of the silicon substrate 700 may be etched. For example, a second photoresist pattern (not shown) may be formed on the rear surface of the silicon substrate 700. The second photoresist pattern may include a plurality of second openings (not shown) for respectively defining unit openings COP associated with a plurality of unit masks UM. For example, each of the plurality of second openings may be associated with one unit opening COP. Subsequently, the silicon substrate 700 may be etched from the rear side (the side in the fourth direction DR4) of the silicon substrate 700 using the second photoresist pattern. The rear side (the side in the fourth direction DR4) refers to the side on which the deposition source DS is positioned. The rear surface of the mask film MM on which the inorganic film 1810 is formed may be exposed by etching the silicon substrate 700.

[0186] According to the method of manufacturing a deposition mask according to an embodiment, by applying a mask grid (or mask rib 7211) to which a magnetic metal is applied to prevent sagging of the mask, alignment accuracy of the mask can be improved and uneven defects caused by sagging of the mask can be prevented.

[0187] At the end of the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the disclosed embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A method for manufacturing a mask, the method comprising: defining a plurality of unit regions and a mask frame region arranged on a silicon substrate, the mask frame region excluding the plurality of unit regions, wherein the mask frame region includes a mask rib region separating the plurality of unit regions and an outer frame region arranged at an outermost position of the silicon substrate; forming a groove in the mask rib region; forming a metal mask rib by forming a metal member in the groove; forming a photoresist pattern including a plurality of openings in each of the plurality of cell regions; growing a plated film in each of the plurality of unit regions; forming a mask film formed of the plating film by removing the photoresist pattern; and The rear surface of the silicon substrate is etched to form a plurality of cell openings respectively associated with the plurality of cell regions.

2. The method for manufacturing a mask according to claim 1, wherein: The cross section of the mask film has an inverse tapered shape in which the width becomes narrower from the front side of the silicon substrate toward the back side of the silicon substrate.

3. The method for manufacturing a mask according to claim 1, wherein: The thickness of the metal mask rib is greater than the thickness of the mask film.

4. The method for manufacturing a mask according to claim 1, wherein: The mask film includes mask shadow portions formed by the plating film and mask openings arranged between adjacent mask shadow portions.

5. The method for manufacturing a mask according to claim 4, wherein: A cross section of the mask opening has a tapered shape whose width becomes wider from the front side of the silicon substrate toward the back side of the silicon substrate.

6. The method for manufacturing a mask according to claim 1, wherein: The coating film contains tungsten.

7. The method for manufacturing a mask according to claim 1, wherein: The plated film contains copper.

8. A method for manufacturing a mask, the method comprising: defining a plurality of unit regions and a mask frame region on a silicon substrate, the mask frame region excluding the plurality of unit regions, wherein the mask frame region includes a mask rib region separating the plurality of unit regions and an outer frame region arranged at an outermost position of the silicon substrate; forming a groove in the mask rib region; forming a metal mask rib by forming a metal member in the groove; forming an inorganic film in each of the plurality of unit regions; forming a photoresist pattern including a plurality of openings on the inorganic film; forming a mask film by etching a portion of the inorganic film using the photoresist pattern; removing the photoresist pattern; and The rear surface of the silicon substrate is etched to form a plurality of cell openings respectively associated with the plurality of cell regions.

9. The method for manufacturing a mask according to claim 8, wherein: The cross section of the mask film has an inverse tapered shape in which the width becomes narrower from the front side of the silicon substrate toward the back side of the silicon substrate.

10. The method for manufacturing a mask according to claim 8, wherein: The thickness of the metal mask rib is greater than the thickness of the mask film.

11. The method for manufacturing a mask according to claim 8, wherein: The mask film includes mask shadow portions formed of the inorganic film and mask openings disposed between adjacent mask shadow portions.

12. The method for manufacturing a mask according to claim 11, wherein: A cross section of the mask opening has a tapered shape whose width becomes wider from the front side of the silicon substrate toward the back side of the silicon substrate.

13. A mask comprising: A silicon substrate, the silicon substrate comprising a plurality of unit regions and a mask frame region, the mask frame region excluding the plurality of unit regions, wherein the mask frame region comprises a mask rib region separating the plurality of unit regions and an outer frame region arranged at an outermost position of the silicon substrate; a metal mask rib disposed in the mask rib region; and A mask film is arranged in each of the plurality of unit regions.

14. The mask according to claim 13, wherein: The mask film is formed of a plating film arranged on the silicon substrate.

15. The mask according to claim 14, wherein: The coating film contains tungsten.

16. The mask according to claim 14, wherein: The plated film contains copper.

17. The mask according to claim 13, wherein: The mask film is formed of an inorganic film arranged on the silicon substrate.

18. The mask according to claim 13, wherein: The cross section of the mask film has an inverse tapered shape in which the width becomes narrower from the front side of the silicon substrate toward the back side of the silicon substrate.

19. The mask according to claim 13, wherein: The thickness of the metal mask rib is greater than the thickness of the mask film.

20. The mask according to claim 13, wherein: Each of the plurality of cell regions includes a cell opening that exposes the mask film as the rear surface of the silicon substrate is etched.

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