Method for identifying epitaxial stacking fault of heavily doped Ph product in advance

Abstract

The invention relates to a method for identifying epitaxial stacking faults of heavily doped Ph products in advance, which belongs to the technical field of semiconductor epitaxial detection and comprises the following operation steps of: 1, preparing two groups of normal and abnormal batches of polished wafer samples, namely four groups of polished wafer samples, to participate in an experiment; 2, selecting one sample in the group A, one sample in the group C and one sample in the group D, and carrying out a corrosion test after first thermal oxidation; and 3, selecting one sample in the group B, one sample in the group C and one sample in the group D, carrying out secondary thermal oxidation, and then carrying out corrosion test. And 4, selecting a normal group of samples and an abnormal group of samples, and testing by using different thermal oxidation conditions and corrosion respectively. And 5, carrying out microscopic examination. And 6, identifying the silicon wafers with stacking faults in advance. The phenomenon of full-surface stacking fault after epitaxial processing of silicon wafers at some positions caused by thermal history difference of heavily doped Ph products is identified in advance. And the situation that the product is wasted due to the fact that the exception can be identified only through epitaxial processing is avoided.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor epitaxy detection, and in particular to a method for pre-identifying epitaxial stacking faults of heavily-doped Ph products. Background Art

[0002] Semiconductor devices are generally formed by growing epitaxy on polished wafers, and further photolithography and ion implantation are performed on the epitaxial layer to form the device. Epitaxy is a method of chemical vapor deposition, which grows a new single crystal thin layer along the original crystal direction on a single crystal substrate with the required conductivity type, resistivity, thickness and lattice structure integrity. The quality of the epitaxial layer has a great influence on the quality of the final device product, so the quality requirement for epitaxy is to minimize defects such as dislocations, stacking faults, pits, fogging defects, and scars.

[0003] However, for super heavily doped Ph substrate silicon wafers, due to differences in thermal history at different crystal segments, the following phenomenon will occur at certain locations in the crystal rod: Due to the presence of oxygen and supersaturated red phosphorus between the silicon lattices, during the pre-baking heating before epitaxial growth, oxygen moves between the lattices and combines with red phosphorus to form clusters of oxygen and red phosphorus (tiny precipitates), which diffuse outward and remain on the surface.

[0004] Immediately following the hydrogen etching treatment before epitaxy, the etching speed of the top layer of the silicon wafer is different from that of the clusters, so the clusters are selectively etched to form tiny pits. When the silicon wafer with the tiny pits undergoes epitaxial growth, a full-surface ESF (Epi Stacking Fault, ESF for short) is generated. A stacking fault is when the normal periodic and repeated stacking sequence of the crystal structure layers is wrong between two layers, resulting in the wrong arrangement of atoms near both sides of the interlayer plane (called the stacking fault plane).

[0005] The ESF is caused by the difference in the thermal history of crystal pulling, not a certain type of defect abnormality caused by crystal pulling. Therefore, routine inspection in the previous polishing process cannot find any abnormality. Only after the epitaxial processing is completed, the ESF defect appears, and the product does not meet the quality requirements and needs to be scrapped, causing great losses. Summary of the invention

[0006] The present invention mainly solves the deficiencies in the prior art and provides a method for pre-identifying epitaxial stacking faults of heavily doped Ph products, which has the advantages of convenient operation and good running stability. Heat treatment and corrosion inspection are used to pre-identify the phenomenon of stacking faults on the surface of silicon wafers at some locations after epitaxial processing due to differences in thermal history of heavily doped Ph products. This avoids the situation where the anomaly needs to be identified through epitaxial processing, resulting in product waste.

[0007] The above technical problems of the present invention are mainly solved by the following technical solutions:

[0008] A method for pre-identifying epitaxial stacking faults in heavily doped Ph products comprises the following steps:

[0009] Step 1: Prepare 4 groups of polishing sheet samples, 2 groups from normal batches and 2 groups from abnormal batches, for the experiment, and name them Group A, Group B, Group C, and Group D respectively; the 2 groups from the normal batches are Group A and Group B, and the 2 groups from the abnormal batches are Group C and Group D.

[0010] Step 2: Select one sample each from Group A, Group C and Group D to conduct the first post-thermal oxidation corrosion test.

[0011] Step 3: Select another sample from each of Group B, Group C and Group D to conduct a second post-thermal oxidation corrosion test.

[0012] Step 4: Select two groups of samples, one normal and one abnormal, and then use different thermal oxidation conditions, using a temperature of 1000°C for thermal oxidation for 2 hours, 4 hours and 12 hours respectively, and Secco liquid corrosion for 30 minutes.

[0013] Step 5: Check under a microscope. Good silicon wafers will be covered with corrosion pits after corrosion, while bad silicon wafers will be normal.

[0014] Step 6: Pre-identify silicon wafers with stacking faults and take countermeasures to screen out abnormal silicon wafers and stop them from continuing the epitaxial processing, while normal silicon wafers continue the epitaxial processing.

[0015] Preferably, in the first corrosion test after thermal oxidation, the thermal oxidation temperature is 1000°C and the test is kept warm for 8 hours. The etching liquid is Secco liquid and the etching time is 30 minutes. After the corrosion is completed, microscopic inspection is performed. There are no corrosion pits on the surface and cross-section of the samples in Group A, and the surfaces and cross-sections of the samples in Groups C and D are full of corrosion pits.

[0016] Preferably, in the second thermal oxidation corrosion test, the thermal oxidation temperature is 1000°C and the test is kept warm for 8 hours. The etching liquid is Secco liquid and the etching time is 30 minutes. After the corrosion is completed, microscopic inspection is performed. There are no corrosion pits on the surface and cross-section of the samples in Group B, and the surfaces and cross-sections of the samples in Groups C and D are full of corrosion pits.

[0017] Preferably, a thin film with a surface silicon thickness of about 0.4 μm is obtained by mechanical thinning and oxidation stripping. The thin film is etched with Secco etching solution, and the defect types are analyzed and the defect density is measured.

[0018] As a preference, the stress density of the film and near the interface was measured using Raman spectroscopy with a wavelength of 0.5145 μm. The results showed that the defects of the film were oxide stacking faults with a density of about 1.8×10 3 / cm2 The total defect density is 2.6×10 3 / cm 2 , tensile stress density δ≤5×103N / cm 2 .

[0019] The present invention can achieve the following effects:

[0020] The present invention provides a method for pre-identifying epitaxial stacking faults of heavily doped Ph products, which has the advantages of convenient operation and good running stability compared with the prior art. Heat treatment and corrosion inspection are used to pre-identify the phenomenon of stacking faults on the silicon wafers at some locations after epitaxial processing due to differences in thermal history of heavily doped Ph products. This avoids the situation where the abnormality needs to be identified through epitaxial processing, resulting in product waste. DETAILED DESCRIPTION

[0021] The technical solution of the invention is further specifically described below through embodiments.

[0022] Embodiment: A method for pre-identifying epitaxial stacking faults in heavily doped Ph products, comprising the following steps:

[0023] Step 1: Prepare 4 groups of polishing sheet samples, 2 groups from normal batches and 2 groups from abnormal batches, for the experiment, and name them Group A, Group B, Group C, and Group D respectively; the 2 groups from the normal batches are Group A and Group B, and the 2 groups from the abnormal batches are Group C and Group D.

[0024] Step 2: One sample from each of Group A, Group T and Group D was selected for the first post-thermal oxidation corrosion test. In the first post-thermal oxidation corrosion test, the thermal oxidation temperature was 1000°C and kept warm for 8 hours, the corrosion liquid was Secco liquid, and the corrosion time was 30 minutes. After the corrosion was completed, a microscope inspection was performed. There were no corrosion pits on the surface and cross-section of the samples in Group A, and the surfaces and cross-sections of the samples in Group T and Group D were full of corrosion pits.

[0025] Step 3: Select another sample from each of Group B, Group T and Group D for the second post-thermal oxidation corrosion test. In the second post-thermal oxidation corrosion test, the thermal oxidation temperature was 1000°C and kept warm for 8 hours, the etching liquid was Secco liquid, and the etching time was 30 minutes. After the corrosion was completed, a microscope inspection was performed. There were no corrosion pits on the surface and cross-section of the samples in Group B, and the surfaces and cross-sections of the samples in Groups C and D were full of corrosion pits.

[0026] Step 4: Select two groups of samples, one normal and one abnormal, and then use different thermal oxidation conditions, using a temperature of 1000°C for thermal oxidation for 2 hours, 4 hours and 12 hours respectively, and Secco liquid corrosion for 30 minutes.

[0027] Step 5: Check under a microscope. Good silicon wafers will be covered with corrosion pits after corrosion, while bad silicon wafers will be normal.

[0028] Step 6: Pre-identify silicon wafers with stacking faults and take countermeasures to screen out abnormal silicon wafers and stop them from continuing the epitaxial processing, while normal silicon wafers continue the epitaxial processing.

[0029] A thin film with a surface silicon thickness of about 0.4 μm was obtained by mechanical thinning and oxidation stripping. The film was etched with Secco etching solution and the defect types were analyzed and the defect density was measured. The stress density of the film and the interface was measured by laser Raman spectroscopy with a wavelength of 0.5145 μm. The results showed that the defects of the film were oxidation stacking faults with a density of about 1.8×10 3 / cm 2 The total defect density is 2.6×10 3 / cm 2 , tensile stress density δ≤5×103N / cm 2 .

[0030] By simulating the pre-baking heat treatment conditions of epitaxy, thermal oxidation treatment at 1000℃ / 2h is the most time-saving and labor-saving. Microscope inspection after 30 minutes of liquid etching found that the silicon wafers in abnormal sections had a large number of corrosion pits, while the silicon wafers in normal sections were still smooth after etching, with very few corrosion pits. There is a clear difference between the two.

[0031] Epitaxial processing of silicon wafers with abnormal sections will produce a large number of stacking faults, while epitaxial processing of silicon wafers with normal sections will not produce stacking faults. By pre-identifying silicon wafers with stacking faults and taking countermeasures, abnormal silicon wafers will be screened out and not continue epitaxial processing, while normal silicon wafers will continue epitaxial processing to avoid losses.

[0032] In summary, the method for pre-identifying epitaxial stacking faults of heavily doped Ph products has the advantages of convenient operation and good running stability. Heat treatment and corrosion inspection are used to pre-identify the phenomenon of stacking faults on the surface of silicon wafers at some locations after epitaxial processing due to differences in thermal history of heavily doped Ph products. This avoids the situation where the abnormality needs to be identified through epitaxial processing, resulting in product waste.

[0033] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by any technician in the field of the present invention are included in the patent scope of the present invention.

Claims

1. A method for pre-identifying epitaxial stacking faults in heavily doped Ph products, characterized in that The steps are as follows: Step 1: Prepare 4 groups of polished wafer samples, 2 groups from normal batches and 2 groups from abnormal batches, for the experiment, named Group A, Group B, Group C, and Group D respectively; the 2 groups from the normal batch are Group A and Group B, and the 2 groups from the abnormal batch are Group C and Group D; Step 2: Select one sample from each of Group A, Group C and Group D to conduct the first post-thermal oxidation corrosion test; Step 3: Select another sample from each of Group B, Group C and Group D to conduct a second post-thermal oxidation corrosion test; Step 4: Select two groups of samples, one normal and one abnormal, and use different thermal oxidation conditions, respectively, with a temperature of 1000°C for 2 hours, 4 hours and 12 hours of thermal oxidation, and Secco liquid corrosion for 30 minutes; Step 5: Check under a microscope. Good silicon wafers are full of corrosion pits after corrosion, while bad silicon wafers are normal. Step 6: Pre-identify silicon wafers with stacking faults and take countermeasures to screen out abnormal silicon wafers and stop them from continuing the epitaxial processing, while normal silicon wafers continue the epitaxial processing.

2. The method for pre-identifying epitaxial stacking faults of heavily doped Ph products according to claim 1, characterized in that: In the first corrosion test after thermal oxidation, the thermal oxidation temperature was 1000℃ and the temperature was kept for 8 hours. The etching liquid was Secco liquid and the etching time was 30 minutes. After the corrosion was completed, microscopic inspection was performed. There were no corrosion pits on the surface and cross-section of the samples in group A, and the surfaces and cross-sections of the samples in groups C and D were full of corrosion pits.

3. The method for pre-identifying epitaxial stacking faults of heavily doped Ph products according to claim 1, characterized in that: In the second corrosion test after thermal oxidation, the thermal oxidation temperature was 1000℃ and the test was kept warm for 8 hours. The corrosion liquid was Secco liquid and the corrosion time was 30 minutes. Microscope inspection was performed after the corrosion was completed. There were no corrosion pits on the surface and cross-section of the samples in group B, while the surfaces and cross-sections of the samples in groups C and D were full of corrosion pits.

4. The method for pre-identifying epitaxial stacking faults of heavily doped Ph products according to claim 1, 2 or 3, characterized in that: A thin film with a surface silicon thickness of about 0.4μm was obtained by mechanical thinning and oxidation stripping. The film was etched with Secco etching solution and the defect types were analyzed and the defect density was measured.

5. The method for pre-identifying epitaxial stacking faults of heavily doped Ph products according to claim 4, characterized in that: The stress density of the film and the interface was measured by laser Raman spectroscopy with a wavelength of 0.5145 μm. The results showed that the defects of the film were oxide stacking faults with a density of about 1.8×10 3 / cm2, the total defect density is 2.6×10 3 / cm2, tensile stress density δ≤5×103N / cm2.