Method for pre-identification of stacking faults in heavily doped ph products

Abstract

The present application relates to a method for pre-identifying the stacking fault of heavily doped Ph products, belonging to the technical field of semiconductor epitaxial detection, comprising the following operation steps: first step: preparing 4 groups of polished wafer samples, 2 groups of normal and abnormal batches, for participating in the experiment. Second step: selecting 1 sample from each of groups A, C and D for the first thermal oxidation and etching test. Third step: selecting another 1 sample from each of groups B, C and D for the second thermal oxidation and etching test. Fourth step: selecting 2 groups of samples from the normal and abnormal samples, and then using different thermal oxidation conditions and etching tests. Fifth step: microscope examination. Sixth step: pre-identifying the silicon wafer with stacking fault. The present application pre-identifies the phenomenon of full-surface stacking fault of silicon wafer after epitaxial processing in some positions of heavily doped Ph products caused by differences in thermal history. The present application avoids the situation of product waste caused by the need to identify abnormalities through epitaxial processing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor epitaxial testing technology, specifically to a method for pre-identifying epitaxial stacking faults in heavily doped Ph products. Background Technology

[0002] Semiconductor devices are typically formed by epitaxy on a polished wafer, followed by further processes such as photolithography and ion implantation on the epitaxial layer. Epitaxy is a chemical vapor deposition process used to grow a new single-crystal thin layer along the original crystal orientation on a single-crystal substrate, achieving the required conductivity, resistivity, thickness, and lattice structure integrity. The quality of the epitaxial layer has a significant impact on the quality of the final device product; therefore, the requirements for epitaxial quality are to minimize defects such as dislocations, stacking faults, pits, haze, and scratches.

[0003] However, for silicon wafers with extremely heavy Ph substrates, due to the difference in thermal history at different crystal segments, the following phenomenon will occur at certain locations in the crystal rod: because there is oxygen and supersaturated red phosphorus between the silicon lattice, the oxygen moves between the lattice and combines with red phosphorus during the pre-baking heating before epitaxial growth, forming clusters of oxygen and red phosphorus (tiny precipitates), which diffuse outward and remain on the outermost layer.

[0004] Following the hydrogen etching process before epitaxy, the outermost layer of the silicon wafer and the clusters are etched at different rates, thus selectively etching the clusters into tiny pits. When epitaxial growth is performed on the silicon wafer with these tiny pits, a full-surface ESF (Epitaphing Stacking Fault) is generated. A stacking fault occurs when the normal periodic stacking sequence of crystal structure layers deviates between two layers, resulting in an incorrect arrangement of atoms along both sides of the plane between those layers (called the stacking fault plane).

[0005] The ESF was caused by differences in the thermal history of crystal pulling, rather than by a specific type of defect in crystal pulling. Therefore, routine inspections during the pre-processing polishing could not detect any abnormalities. The ESF defect only became apparent after the epitaxial processing was completed, and the product failed to meet quality requirements and had to be scrapped, resulting in significant losses. Summary of the Invention

[0006] This invention primarily addresses the shortcomings of existing technologies by providing a method for pre-identifying epitaxial stacking faults in heavily doped Ph products. This method offers advantages such as ease of operation and good operational stability. By employing heat treatment and etching inspection, it pre-identifies instances where, due to differences in thermal history, some locations in heavily doped Ph products exhibit full-surface stacking faults after epitaxial processing. This avoids situations where anomalies can only be identified through epitaxial processing, thus preventing product waste.

[0007] The above-mentioned technical problems of the present invention are mainly solved by the following technical solutions:

[0008] A method for pre-identifying epitaxial stacking faults in heavily Ph-doped products includes the following steps:

[0009] Step 1: Prepare 4 sets of polished wafer samples for the experiment, including 2 sets each of normal and abnormal batches, and name them Group A, Group B, Group C, and Group D respectively; the 2 sets of normal batches are Group A and Group B, and the 2 sets of abnormal batches are Group C and Group D.

[0010] Step 2: Select one sample from each of Group A, Group C, and Group D for the first corrosion test after thermal oxidation.

[0011] Step 3: Select one sample from each of Group B, Group C, and Group D for a second corrosion test after thermal oxidation.

[0012] Step 4: Select two groups of samples, one normal and one abnormal, and then perform thermal oxidation under different conditions, using a temperature of 1000℃ for 2 hours, 4 hours and 12 hours respectively, followed by 30 minutes of Secco solution corrosion.

[0013] Step 5: Perform microscopic examination. Good silicon wafers will have a full surface of corrosion pits after etching, while bad silicon wafers will appear normal.

[0014] Step 6: By pre-identifying silicon wafers with stacking faults and taking countermeasures, abnormal silicon wafers are screened out and not allowed to continue epitaxial processing, while normal silicon wafers continue epitaxial processing.

[0015] As a preferred method, the first corrosion test after thermal oxidation was conducted. The thermal oxidation temperature was 1000℃ and the temperature was maintained for 8 hours. The corrosion solution was Secco solution, and the corrosion time was 30 minutes. After corrosion, microscopic examination was performed. No corrosion pits were found on the surface and cross-section of the samples in group A, while the samples in groups C and D were covered with corrosion pits on both the surface and cross-section.

[0016] As a preferred option, a second corrosion test was conducted after thermal oxidation. The thermal oxidation temperature was 1000℃ and the temperature was maintained for 8 hours. The corrosion solution was Secco solution, and the corrosion time was 30 minutes. After corrosion, microscopic examination was performed. No corrosion pits were found on the surface and cross-section of the B group samples, while the surface and cross-section of the C and D group samples were covered with corrosion pits.

[0017] As a preferred method, a thin film with a surface silicon thickness of about 0.4 μm was obtained by mechanical thinning and oxide stripping. The film was etched with Secco etching solution and the types of defects were analyzed and the defect density was measured.

[0018] As a preferred method, the stress density near the film and interface was measured using laser Raman spectroscopy at a wavelength of 0.5145 μm; the results showed that the defects in the film were oxide stacking faults with a density of approximately 1.8 × 10⁻⁶. 3 / cm2 The total defect density is 2.6 × 10⁻⁶. 3 / cm 2 Tensile stress density δ≤5×103N / cm 2 .

[0019] The present invention can achieve the following effects:

[0020] This invention provides a method for pre-identifying epitaxial stacking faults in heavily doped Ph products. Compared with existing technologies, it has the advantages of convenient operation and good operational stability. By employing heat treatment and etching inspection, it pre-identifies instances of full-surface stacking faults in some locations of the silicon wafer after epitaxial processing due to differences in thermal history. This avoids situations where abnormalities can only be identified through epitaxial processing, thus preventing product waste. Detailed Implementation

[0021] The technical solution of the invention will be further described in detail below through examples.

[0022] Example: A method for pre-identifying epitaxial stacking faults in heavily Ph-doped products, comprising the following steps:

[0023] Step 1: Prepare 4 sets of polished wafer samples for the experiment, including 2 sets each of normal and abnormal batches, and name them Group A, Group B, Group C, and Group D respectively; the 2 sets of normal batches are Group A and Group B, and the 2 sets of abnormal batches are Group C and Group D.

[0024] Step 2: One sample each from Group A, Group t, and Group D was selected for the first post-thermal oxidation corrosion test. The first post-thermal oxidation corrosion test was conducted at a temperature of 1000℃ for 8 hours, using Secco solution for 30 minutes. After corrosion, microscopic examination revealed no corrosion pits on the surface or cross-section of the Group A sample, while the surfaces and cross-sections of the Group t and Group D samples were covered with corrosion pits.

[0025] Step 3: Select one sample each from Group B, Group t, and Group D for a second post-thermal oxidation corrosion test. The second post-thermal oxidation corrosion test was conducted at 1000℃ for 8 hours, using Secco solution for 30 minutes. After corrosion, microscopic examination revealed no corrosion pits on the surface or cross-section of Group B samples, while Group C and Group D samples showed extensive corrosion pits on both their surfaces and cross-sections.

[0026] Step 4: Select two groups of samples, one normal and one abnormal, and then perform thermal oxidation under different conditions, using a temperature of 1000℃ for 2 hours, 4 hours and 12 hours respectively, followed by 30 minutes of Secco solution corrosion.

[0027] Step 5: Perform microscopic examination. Good silicon wafers will have a full surface of corrosion pits after etching, while bad silicon wafers will appear normal.

[0028] Step 6: By pre-identifying silicon wafers with stacking faults and taking countermeasures, abnormal silicon wafers are screened out and not allowed to continue epitaxial processing, while normal silicon wafers continue epitaxial processing.

[0029] A silicon film with a surface layer thickness of approximately 0.4 μm was obtained using mechanical thinning and oxide stripping methods. The film was etched with Secco etching solution, and the types and density of defects were analyzed. The stress density of the film and the vicinity of the interface was measured using Raman spectroscopy with a wavelength of 0.5145 μm. The results showed that the defects in the film were oxide stacking faults, with a density of approximately 1.8 × 10⁻⁶. 3 / cm 2 The total defect density is 2.6 × 10⁻⁶. 3 / cm 2 Tensile stress density δ≤5×103N / cm 2 .

[0030] By simulating the pre-baking heat treatment conditions of epitaxy, performing thermal oxidation at 1000℃ for 2 hours is the most time-saving and labor-saving method. After liquid etching for 30 minutes, microscopic examination revealed that silicon wafers in abnormal sections had a large number of etching pits, while silicon wafers in normal sections remained smooth after etching with very few etching pits, showing a clear difference between the two.

[0031] Epitaxial processing of silicon wafers in abnormal segments will generate a large number of stacking faults, while epitaxial processing of silicon wafers in normal segments will not result in stacking faults. By identifying silicon wafers with stacking faults in advance and taking countermeasures, abnormal silicon wafers are screened out and not allowed to continue epitaxial processing, while normal silicon wafers continue epitaxial processing, thus avoiding losses.

[0032] In summary, this method for pre-identifying epitaxial stacking faults in heavily doped Ph products offers advantages such as ease of operation and good operational stability. By employing heat treatment and etching inspection, it pre-identifies instances of full-surface stacking faults in some locations of the silicon wafer after epitaxial processing due to differences in thermal history. This avoids situations where anomalies can only be identified through epitaxial processing, thus preventing product waste.

[0033] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by those skilled in the art within the scope of the present invention are covered by the patent scope of the present invention.

Claims

1. A method of pre-identifying stacking faults in heavily doped Ph products, characterized by The method comprises the following steps: First step: prepare 4 groups of polished wafer samples, including 2 groups of normal batches and 2 groups of abnormal batches, and name them as group A, group B, group C and group D; the 2 groups of normal batches are group A and group B, and the 2 groups of abnormal batches are group C and group D; Second step: select one sample from each of group A, group C and group D to perform the first heat oxidation and corrosion test; In the first heat oxidation and corrosion test, the heat oxidation temperature is 1000 DEG C and the heat preservation time is 8 hours, the corrosion liquid is Secco liquid, the corrosion time is 30 minutes, and after the corrosion is completed, microscopic detection is performed; the surface and the cross section of the sample in group A are free of corrosion pits, and the surface and the cross section of the samples in group C and group D are full of corrosion pits; Third step: select another sample from each of group B, group C and group D to perform the second heat oxidation and corrosion test; In the second heat oxidation and corrosion test, the heat oxidation temperature is 1000 DEG C and the heat preservation time is 8 hours, the corrosion liquid is Secco liquid, the corrosion time is 30 minutes, and after the corrosion is completed, microscopic detection is performed; the surface and the cross section of the sample in group B are free of corrosion pits, and the surface and the cross section of the samples in group C and group D are full of corrosion pits; Fourth step: select 2 groups of samples from the normal and abnormal batches, and use different heat oxidation conditions to perform heat oxidation at a temperature of 1000 DEG C for 2 hours, 4 hours and 12 hours respectively, and then perform Secco liquid corrosion for 30 minutes; Fifth step: perform microscopic detection; the good silicon wafer is full of corrosion pits after corrosion, and the bad silicon wafer is normal; Sixth step: identify the silicon wafer with stacking fault in advance, take countermeasures, screen the abnormal silicon wafer, and do not continue to perform epitaxial processing flow, and the normal silicon wafer continues to perform epitaxial processing flow. The thin film with the surface layer silicon thickness of 0.4μm was obtained by mechanical thinning and oxidation exfoliation method. The thin film was etched by Secco etching solution and the defect type was analyzed and the defect density was measured. The stress density near the interface of the thin film was measured by laser Raman spectrum with wavelength of 0.5145μm. The results show that the defect of the thin film is oxidation dislocation with density of 1.8×10 3 / cm 2 , the total defect density is 2.6×10 3 / cm 2 and the tensile stress density δ≤5×103N / cm 2 .