Array type electromagnetic eddy current nondestructive testing system

Abstract

The invention relates to an array type electromagnetic eddy current nondestructive testing system, which comprises an excitation signal generation module which is connected with a control signal and is used for generating an original excitation signal by adopting a DDS method under the control of the control signal and performing power amplification on the original excitation signal to obtain an excitation signal; the probes are arranged in an array mode and used for generating a changing magnetic field under excitation of the excitation signal so that the detected pipeline can generate an eddy current signal under the changing magnetic field and pick up the eddy current signal; the echo processing module is used for sequentially carrying out pre-amplification, effective value detection and analog-to-digital conversion processing on the eddy current signal to obtain a digital signal; and the control module is used for generating a control signal and analyzing the digital signal to obtain a detection result of the detected pipeline. According to the invention, the detection reliability can be ensured, the detection precision is improved, and the detection sensitivity is improved.

Description

Technical Field

[0001] The invention relates to the field of pipeline micro-defect detection, and in particular to an array type electromagnetic eddy current non-destructive detection system. Background Art

[0002] When a conductor is placed in a changing magnetic field, eddy currents are generated inside the conductor. The changes in these eddy currents can reflect whether there are defects in the workpiece. Eddy current technology uses the principle of electromagnetic induction to evaluate the performance of conductive materials or discover defects in the workpiece by detecting the changes in induced eddy currents in the workpiece. At present, eddy current detection technology has been widely used in pipeline defect detection to achieve routine and serialized detection. However, the detection ability for tiny defects is still insufficient. Summary of the invention

[0003] The present invention provides an array type electromagnetic eddy current nondestructive testing system to solve at least one of the above technical problems.

[0004] The technical solution of the present invention to solve the above technical problems is as follows: an array electromagnetic eddy current nondestructive testing system, comprising:

[0005] The excitation signal generating module is connected to the control signal, and is used to generate the original excitation signal by using the DDS method under the control of the control signal, and to power-amplify the original excitation signal to obtain the excitation signal;

[0006] The probes arranged in an array are connected to the excitation signal generating module and are used to generate a changing magnetic field under the excitation of the excitation signal, so that the measured pipeline generates an eddy current signal under the changing magnetic field, and picks up the eddy current signal;

[0007] An echo processing module, connected to the probe, for sequentially performing pre-amplification, effective value detection and analog-to-digital conversion processing on the eddy current signal to obtain a digital signal;

[0008] The control module is connected to the excitation signal generating module and the echo processing module, and is used to generate the control signal and analyze the digital signal to obtain the detection result of the detected pipeline.

[0009] The beneficial effects of the present invention are as follows: an array-type electromagnetic eddy current nondestructive testing system of the present invention adopts an excitation signal generating module to generate a power-amplified excitation signal, which is sufficient to excite the probe to generate the required eddy current magnetic field, thereby ensuring the reliability of the detection; at the same time, by adopting the array-type arranged probes, the heat generation of the entire detection probe is small, and the output of the response characteristic curve of the excitation coil load is relatively smooth, and no repeated oscillation will be generated, thereby improving the detection accuracy; in addition, the echo processing module sequentially performs pre-amplification, effective value detection and analog-to-digital conversion processing on the eddy current signal picked up by the probe, thereby optimizing the dynamic response characteristics of the system, reducing the noise of the system, and improving the detection sensitivity of the probe. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a structural block diagram of an array type electromagnetic eddy current nondestructive testing system of the present invention;

[0011] Figure 2 It is a specific structural block diagram of an array type electromagnetic eddy current nondestructive testing system of the present invention;

[0012] Figure 3 It is the schematic diagram of the power amplifier circuit;

[0013] Figure 4 It is the schematic diagram of the limited differential preamplifier subcircuit;

[0014] Figure 5 It is the schematic diagram of the secondary amplifier circuit;

[0015] Figure 6 This is the schematic diagram of the effective value detection circuit. DETAILED DESCRIPTION

[0016] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0017] like Figure 1 As shown, an array type electromagnetic eddy current nondestructive testing system comprises:

[0018] The excitation signal generating module is connected to the control signal, and is used to generate the original excitation signal by using the DDS method under the control of the control signal, and to power-amplify the original excitation signal to obtain the excitation signal;

[0019] The probes arranged in an array are connected to the excitation signal generating module and are used to generate a changing magnetic field under the excitation of the excitation signal, so that the measured pipeline generates an eddy current signal under the changing magnetic field, and picks up the eddy current signal;

[0020] An echo processing module, connected to the probe, for sequentially performing pre-amplification, effective value detection and analog-to-digital conversion processing on the eddy current signal to obtain a digital signal;

[0021] The control module is connected to the excitation signal generating module and the echo processing module, and is used to generate the control signal and analyze the digital signal to obtain the detection result of the detected pipeline.

[0022] An array-type electromagnetic eddy current nondestructive testing system of the present invention adopts an excitation signal generating module to generate a power-amplified excitation signal, which is sufficient to excite the probe to generate the required eddy current magnetic field, thereby ensuring the reliability of detection; at the same time, by adopting the probes arranged in an array, the heat generation of the entire detection probe is small, and the output of the response characteristic curve of the excitation coil load is relatively smooth, and no repeated oscillation is generated, thereby improving the detection accuracy; in addition, the echo processing module sequentially performs pre-amplification, effective value detection and analog-to-digital conversion processing on the eddy current signal picked up by the probe, thereby optimizing the dynamic response characteristics of the system, reducing the noise of the system, and improving the detection sensitivity of the probe.

[0023] In some embodiments, Figure 2 As shown, the excitation signal generating module includes:

[0024] A DDS signal generating circuit, connected to the control module, for generating an original excitation signal under the control of the control signal;

[0025] The power amplifier circuit is connected to the DDS signal generating circuit and the probe, and is used to perform power amplification on the original excitation signal to obtain an excitation signal.

[0026] Specifically, the excitation signal generating module is required to be able to generate sinusoidal signals of different frequencies. The present invention adopts DDS (Direct Digital Frequency Synthesis) technology (ie, direct digital frequency synthesis technology) to design and manufacture the excitation signal generating part.

[0027] The excitation signal generating module works under the control signal output by the control module. The control module specifically selects a high-frequency single-chip microcomputer. The signal is preset by the program, and then the single-chip microcomputer controls the DDS signal generating circuit to generate the original excitation signal, and the power amplifier circuit amplifies the power to generate the required excitation signal.

[0028] The original excitation signal generated by the DDS signal generating circuit is a sinusoidal signal with a voltage amplitude of 0~VCC and a current amplitude of 5mA. Such a current passing through the probe excitation coil is not enough to stimulate the eddy current magnetic field strength required for defect detection, so it is required to amplify the current value of the original excitation signal generated by the DDS signal generating circuit.

[0029] The present invention uses a power amplifier circuit to amplify the power of the original excitation signal; Figure 3 As shown, the power amplifier circuit includes:

[0030] A first resistor R1, one end of which is connected to the DDS signal generating circuit;

[0031] A first operational amplifier A1, an inverting input terminal connected to the other end of the first resistor R1, a non-inverting input terminal connected to a preset reference voltage VREF, a positive power supply terminal connected to a first supply voltage VCC, and a negative power supply terminal connected to ground;

[0032] A second resistor R2 is connected between the inverting input terminal and the output terminal of the first operational amplifier A1;

[0033] A first capacitor C1 is connected in parallel with the second resistor R2;

[0034] A second capacitor C2, one end of which is connected to the output end of the first operational amplifier A1;

[0035] A third capacitor C3, one end of which is connected to the positive power supply terminal of the first operational amplifier A1, and the other end of which is grounded;

[0036] A third resistor R3, one end of which is connected to the other end of the second capacitor C2;

[0037] a fourth resistor R4, one end of which is connected to the other end of the second capacitor C2;

[0038] The complementary push-pull power tube is connected to the other end of the third resistor R3, the other end of the fourth resistor R4 and the probe.

[0039] The power amplifier circuit first passes the original excitation signal through the first operational amplifier A1, and then uses a complementary push-pull power amplifier to amplify the power. Considering the power consumption, heat generation and stability of the generated sinusoidal signal of the operational amplifier, the present invention adopts the first operational amplifier A1 of the TLV2771 model to realize the design of the power amplifier circuit, which has a wide range of voltage input, output voltage swing and a slew rate of up to 2500V / us, and has extremely low noise and a DC-70MHz wide bandwidth. The signal voltage after power amplification by the power amplifier circuit is 0~5V, and the magnitude of the current depends on the magnitude of the resistance of the probe excitation coil connected later, so the final excitation current is amplified from 5mA to 1A, and the function of the power amplifier circuit is realized, and the output current is sufficient to excite the eddy current magnetic field of the required intensity.

[0040] In some embodiments, the probe is a mutual inductance coil sensor made of cylindrical winding.

[0041] Specifically, in the pulse eddy current detection system, the probe part is generally composed of an excitation coil and a detection coil or an excitation coil and a sensor. Most of them are implemented in the form of a combination of an excitation coil and a detection coil. In the present invention, a mutual inductance coil sensor made of cylindrical winding is mainly composed of an excitation coil and a detection coil. The excitation coil is used to load the excitation signal, and the detection coil is mainly used to pick up the pulse eddy current induced voltage signal and the output of the signal. In this way, when a large excitation current is loaded, the heat generated by the entire detection probe is small, and the output of the response characteristic curve of the excitation coil load is relatively smooth, and no repeated oscillations will occur.

[0042] In some embodiments, Figure 2 As shown, the echo processing module includes:

[0043] A preamplifier circuit, connected to the probe, for performing preamplification processing on the eddy current signal to obtain a preamplified signal;

[0044] An effective value detection circuit, connected to the preamplifier circuit, for performing effective value detection processing on the preamplifier signal to obtain an effective value detection signal;

[0045] The analog-to-digital conversion circuit is connected to the effective value detection circuit and the control module, and is used to perform analog-to-digital conversion processing on the effective value detection signal to obtain a digital signal.

[0046] In some embodiments, Figure 2 As shown, the preamplifier circuit includes a limiting differential preamplifier subcircuit, such as Figure 4 As shown, the limiting differential preamplifier subcircuit includes:

[0047] A fifth resistor R5, one end of which is connected to the probe;

[0048] a sixth resistor R6, one end of which is connected to the other end of the fifth resistor R5;

[0049] a seventh resistor R7, one end of which is connected to the other end of the sixth resistor R6;

[0050] A fourth capacitor C4, one end of which is connected to the other end of the fifth resistor R5, and the other end of which is grounded;

[0051] A fifth capacitor C5, one end of which is connected to the other end of the sixth resistor R6, and the other end of which is grounded;

[0052] A second operational amplifier A2, wherein the non-inverting input terminal is connected to the preset reference voltage VREF, the inverting input terminal is connected to the other end of the seventh resistor R7, the positive power supply terminal is connected to the first supply voltage VCC, and the negative power supply terminal is grounded;

[0053] an eighth resistor R8, connected between the inverting input terminal and the output terminal of the second operational amplifier A2;

[0054] A sixth capacitor C6 is connected in parallel with the eighth resistor R8;

[0055] A seventh capacitor C7, one end of which is connected to the positive power supply terminal of the second operational amplifier A2, and the other end of which is grounded;

[0056] A ninth resistor R9, one end of which is connected to the probe;

[0057] a tenth resistor R10, one end of which is connected to the other end of the ninth resistor R9;

[0058] an eleventh resistor R11, one end of which is connected to the other end of the tenth resistor R10;

[0059] an eighth capacitor C8, one end of which is connected to the other end of the ninth resistor R9, and the other end of which is grounded;

[0060] a ninth capacitor C9, one end of which is connected to the other end of the tenth resistor R10, and the other end of which is grounded;

[0061] A third operational amplifier A3, wherein the non-inverting input terminal is connected to the preset reference voltage VREF, the inverting input terminal is connected to the other end of the eleventh resistor R11, the positive power supply terminal is connected to the first supply voltage VCC, and the negative power supply terminal is grounded;

[0062] A twelfth resistor R12 is connected between the inverting input terminal and the output terminal of the third operational amplifier A3;

[0063] a tenth capacitor C10 connected in parallel with the twelfth resistor R12;

[0064] An eleventh capacitor C11 has one end connected to the positive power supply terminal of the third operational amplifier A3 and the other end grounded.

[0065] Specifically, the preamplifier circuit can optimize the dynamic response characteristics of the array electromagnetic eddy current nondestructive testing system, reduce the noise of the system, and improve the detection sensitivity of the probe. On the basis of matching the signal source impedance with the receiving coil in the probe, the present invention designs the following Figure 4 The limiting differential preamplifier subcircuit is shown.

[0066] In the preamplifier circuit, by changing the impedance matching resistor value, the amplitude of the pulse eddy current receiving coil is greatly affected. The function of the matching resistor is similar to that of the sampling resistor, but the optimization effect on the frequency response of the response curve is not very obvious. Therefore, in the limiting differential preamplifier subcircuit of the present invention, the resistance value of the matching resistor (including the fifth resistor R5 to the seventh resistor R7, the ninth resistor R9 to the eleventh resistor R11) between the receiving coil source impedance and the second operational amplifier A2 and the third operational amplifier A3 is much larger than the resistance value of the receiving coil impedance as a standard, so that the entire echo processing module is in an over-damped state, and the excitation source parameters are optimized to make the output response of the entire echo processing module in a critical damped state or a slightly under-damped state, thereby obtaining an output of a pulse eddy current signal with better frequency response characteristics.

[0067] The limited differential preamplifier subcircuit is mainly designed for the late weak eddy current signal received by the probe. Since the amplitude of the early signal of the eddy current transient induced voltage exceeds the amplitude range after the gain of the preamplifier, and even exceeds the power supply voltage, and the eddy current signal transient response overload time is tens or hundreds of microseconds; in order to ensure the safety of the entire echo processing module, a bidirectional transient suppression diode is added to the front end of the impedance matching network to clamp the signal voltage. That is, a first transient suppression diode is connected between the fifth resistor R5 and the probe, and a second transient suppression diode is connected between the ninth resistor R9 and the probe.

[0068] Transient suppression diode is a high-efficiency protection device in the form of a diode. The bidirectional transient suppression diode can instantly absorb the overloaded high-power pulse signal in both the positive and negative directions with a response speed of 1ps (10-12s), and clamp the voltage to a predetermined level, and can withstand instantaneous power of up to kilowatts. The use of transient suppression diodes prevents the eddy current signal from being too large and exceeding the effective range of the acquisition card, effectively ensuring the safety of the entire eddy current signal acquisition.

[0069] The limited differential preamplifier subcircuit adopts a symmetrical differential amplifier circuit structure, the main purpose of which is to improve the signal-to-noise ratio of the late weak eddy current signal, and to amplify and buffer the output of the signal of the receiving coil. According to the characteristics of the late eddy current signal, the bandwidth, common mode rejection ratio, drift, noise and power consumption of the amplifier are comprehensively considered, and the second op amp A2 and the third op amp A3 use precision amplifiers of model AD8541ARTZ.

[0070] The precision amplifier model AD8541ARTZ adopts a three-op-amp combination structure. The first stage of the amplifier adopts a balanced symmetrical structure with a common-phase input design. The advantage of this structure is that it can cancel out the offset voltage, offset current and temperature drift interference in the differential circuit while suppressing common-mode interference. In addition, the instrument amplifier has the advantages of high input impedance and high common-mode rejection ratio, which can effectively amplify weak signals in the presence of common-mode signal interference.

[0071] In some embodiments, Figure 2 As shown, the preamplifier circuit also includes a secondary amplifier circuit, such as Figure 5 As shown, the secondary amplification sub-circuit includes:

[0072] A twelfth capacitor C12, one end of which is connected to the output end of the second operational amplifier A2;

[0073] A thirteenth capacitor C13, one end of which is connected to the output end of the third operational amplifier A3;

[0074] A thirteenth resistor R13, one end of which is connected to the other end of the twelfth capacitor C12;

[0075] A fourteenth resistor R14, one end of which is connected to the other end of the thirteenth capacitor C13;

[0076] A sixteenth resistor R16, one end of which is connected to a preset reference voltage VREF, and the other end of which is connected to the other end of the fourteenth resistor R14;

[0077] A fourth operational amplifier A4, having a non-inverting input terminal connected to the other end of the fourteenth resistor R14, an inverting input terminal connected to the other end of the thirteenth resistor R13, a positive power supply terminal connected to the first supply voltage VCC, a negative power supply terminal connected to ground, and an output terminal connected to the effective value detection circuit;

[0078] A fifteenth resistor R15 is connected between the inverting input terminal and the output terminal of the fourth operational amplifier A4;

[0079] A fourteenth capacitor C14, one end of which is connected to the positive power supply terminal of the fourth operational amplifier A4, and the other end of which is grounded;

[0080] A seventeenth resistor R17, one end of which is connected to the output end of the fourth operational amplifier A4;

[0081] A fifth operational amplifier A5, wherein the non-inverting input terminal is connected to the preset reference voltage VREF, the inverting input terminal is connected to the other end of the seventeenth resistor R17, the positive power supply terminal is connected to the first supply voltage VCC, the negative power supply terminal is grounded, and the output terminal is connected to the effective value detection circuit;

[0082] An eighteenth resistor R18 is connected between the inverting input terminal and the output terminal of the fifth operational amplifier A5;

[0083] The fifteenth capacitor C15 has one end connected to the positive power supply terminal of the fifth operational amplifier A5 and the other end grounded.

[0084] In the secondary amplification subcircuit, the twelfth capacitor C12, the thirteenth capacitor C13, the thirteenth resistor R13, the fourteenth resistor R14, the sixteenth resistor R16 and the fourth operational amplifier A4 constitute an RF I filter; and the fifteenth resistor R15 and the sixteenth resistor R16, the twelfth capacitor C12 and the thirteenth capacitor C13 should be of the same size to ensure that the time constants of C12 / R15 and C13 / R16 match to ensure the balance of the bridge. Among them, the fourteenth capacitor C14 is connected across the output end of the fourth operational amplifier A4, and cooperates with the twelfth capacitor C12 and the thirteenth capacitor C13 to effectively reduce the AC CMR error caused by the mismatch of the time constant. The RF I filter has two different bandwidths, differential bandwidth and common mode bandwidth. The trial selection method is used to select the component value of the RF I filter during circuit design. Under the condition of not attenuating the input signal, the bandwidth of the RF I filter is made as small as possible to determine the differential bandwidth and common mode bandwidth of the RF I filter. The RF I filter design is actually a first-order differential low-pass filter network, which filters out as much RF energy as possible at the positive and negative input terminals of the fourth op amp A4, ensures the signal balance between each input terminal and the ground, and maintains sufficient input impedance within the measurement bandwidth to ensure the load capacity of the input signal source.

[0085] In the secondary amplification sub-circuit, according to the characteristics of the late pulse eddy current signal, the parameter characteristics of the amplifier such as bandwidth, common mode rejection ratio, drift, noise and power consumption are comprehensively considered, and the fourth op amp A4 and the fifth op amp A5 are precision amplifiers with model AD8031ARTZ.

[0086] The precision amplifier model AD8031ARTZ has the advantages of high common mode rejection ratio, low noise, low power consumption, etc., and can set different magnifications of 1 to 1000 by selecting an external resistor. The fourth operational amplifier A4 and the fifth operational amplifier A5 are not designed to obtain a higher gain, but are mainly used to improve the noise performance of the entire system, and the magnification is selected in the range of 1 to 5 times. The gain of the present invention is set to 2 times.

[0087] In some embodiments, Figure 6 As shown, the effective value detection circuit includes:

[0088] A first BNC connector J1, one end of which is connected to the output end of the fourth operational amplifier A4;

[0089] A nineteenth resistor R19, one end of which is connected to the other end of the first BNC connector J1, and the other end of which is grounded;

[0090] A twentieth resistor R20, one end of which is connected to the other end of the first BNC connector J1;

[0091] A twenty-first resistor R21, one end of which is connected to the other end of the twenty-first resistor R20, and the other end of which is grounded;

[0092] The first active connector JP1 includes three terminals; a first terminal of the first active connector JP1 is connected to the other end of the 20th resistor R20, and a second terminal of the first active connector JP1 is grounded;

[0093] a twenty-second resistor R22, one end of which is connected to the third terminal of the first active connector JP1;

[0094] A second BNC connector J2, one end of which is connected to the output end of the fifth operational amplifier A5;

[0095] A twenty-third resistor R23, one end of which is connected to the other end of the second BNC connector J2, and the other end of which is grounded;

[0096] A twenty-fourth resistor R24, one end of which is connected to the other end of the second BNC connector J2;

[0097] A twenty-fifth resistor R25, one end of which is connected to the other end of the twenty-fourth resistor R24, and the other end of which is grounded;

[0098] The second active connector JP2 includes three terminals; a first terminal of the second active connector JP2 is connected to the other end of the second fourth resistor R24, and a second terminal of the second active connector JP2 is grounded;

[0099] a twenty-sixth resistor R26, one end of which is connected to the third terminal of the second active connector JP2;

[0100] LTC1966 chip U1, I N1 pin is connected to the other end of the 22nd resistor R22, I N2 pin is connected to the other end of the 26th resistor R26, VDD pin is connected to the second supply voltage Vdd, and Vss pin is connected to the third supply voltage Vss;

[0101] The twenty-seventh resistor R27, one end of which is connected to the LTC1966 chip U1 Pins;

[0102] A twenty-eighth resistor R28, one end of which is connected to the other end of the twenty-seventh resistor R27, and the other end of which is connected to the control module;

[0103] The third active connector JP3 comprises three terminals; a first terminal of the third active connector JP3 is connected to the GND pin of the LTC1966 chip U1, a second terminal of the third active connector JP3 is connected to the second supply voltage Vdd, and a third terminal of the third active connector JP3 is connected between the twenty-seventh resistor R27 and the twenty-eighth resistor R28;

[0104] A sixteenth capacitor C16, one end of which is connected to the GND pin of the LTC1966 chip U1, and the other end is grounded;

[0105] The fourth active connector JP4 comprises three terminals; a first terminal of the fourth active connector JP4 is connected to a third supply voltage Vss, a second terminal of the fourth active connector JP4 is grounded, and a third terminal of the fourth active connector JP4 is connected to a GND pin of the LTC1966 chip U1;

[0106] A seventeenth capacitor C17, one end of which is connected to the Vss pin of the LTC1966 chip U1, and the other end is grounded;

[0107] An eighteenth capacitor C18, one end of which is connected to the Vss pin of the LTC1966 chip U1, and the other end is grounded;

[0108] A nineteenth capacitor C19, one end of which is connected to the VDD pin of the LTC1966 chip U1, and the other end is grounded;

[0109] A twentieth capacitor C20, one end of which is connected to the VDD pin of the LTC1966 chip U1, and the other end is grounded;

[0110] The fifth active connector JP5 comprises three terminals; a first terminal of the fifth active connector JP5 is connected to a third supply voltage Vss, a second terminal of the fifth active connector JP5 is grounded, and a third terminal of the fifth active connector JP5 is connected to an OUTRTN pin of the LTC1966 chip U1;

[0111] A twenty-first capacitor C21, one end of which is connected to the OUTRTN pin of the LTC1966 chip U1, and the other end of which is grounded;

[0112] A twenty-second capacitor C22 is connected between the OUTRTN pin and the Vout pin of the LTC1966 chip U1;

[0113] A twenty-third capacitor C23 is connected between the OUTRTN pin and the Vout pin of the LTC1966 chip U1;

[0114] The sixth active connector JP6 comprises three terminals; a first terminal of the sixth active connector JP6 is connected to an optional DC precision filter via a twenty-ninth resistor R29, a second terminal of the sixth active connector JP6 is connected to an optional filter buffer, and a third terminal of the sixth active connector JP6 is connected to a Vout pin of the LTC1966 chip U1;

[0115] The optional DC precision filter, the optional filter buffer, the third terminal of the sixth active connector JP6 and the OUTRTN pin of the LTC1966 chip U1 are all connected to the analog-to-digital conversion circuit.

[0116] Wherein, the optional DC precision filter comprises:

[0117] A twenty-fifth capacitor C25, one end of which is connected to the twenty-ninth resistor R29;

[0118] A sixth operational amplifier A6, having an inverting input terminal connected to the other end of the twenty-fifth capacitor C25, a positive power supply terminal connected to the fourth supply voltage Vdd2, and a negative power supply terminal connected to the fifth supply voltage Vss2;

[0119] A twenty-fourth capacitor C24, one end of which is connected to the non-inverting input terminal of the sixth operational amplifier A6, and the other end of which is grounded;

[0120] A 30th resistor R30, one end of which is connected to the non-inverting input terminal of the sixth operational amplifier A6, and the other end of which is grounded;

[0121] A thirty-first resistor R31, one end of which is connected to the non-inverting input terminal of the sixth operational amplifier A6, and the other end of which is connected to the fourth supply voltage Vdd2;

[0122] A twenty-sixth capacitor C26, one end of which is connected to the positive power supply terminal of the sixth operational amplifier A6, and the other end of which is grounded;

[0123] A twenty-seventh capacitor C27, one end of which is connected to the negative power supply terminal of the sixth operational amplifier A6, and the other end of which is grounded;

[0124] A thirty-second resistor R32 is connected between the inverting input terminal and the output terminal of the sixth operational amplifier A6;

[0125] The twenty-eighth capacitor C28 has one end connected to the output end of the sixth operational amplifier A6, and the other end connected to one end of the twenty-fifth capacitor C25 and the analog-to-digital conversion circuit.

[0126] Wherein, the optional filter buffer comprises:

[0127] A thirty-third resistor R33, one end of which is connected to the second terminal of the sixth active connector JP6;

[0128] A thirty-fourth resistor R34, one end of which is connected to the other end of the thirty-third resistor R33;

[0129] A seventh operational amplifier A7, having a non-phase input terminal connected to the other end of the thirty-fourth resistor R34, a positive power supply terminal connected to the fourth supply voltage Vdd2, a negative power supply terminal connected to the fifth supply voltage Vss2, and an output terminal connected to the analog-to-digital conversion circuit;

[0130] A 30th capacitor C30, one end of which is connected to the non-inverting input terminal of the seventh operational amplifier A7, and the other end of which is grounded;

[0131] A thirty-fifth resistor R35, one end of which is connected to the inverting input terminal of the seventh operational amplifier A7, and the other end of which is connected to the output terminal of the seventh operational amplifier A7;

[0132] A twenty-ninth capacitor C29, one end of which is connected between the thirty-third resistor R33 and the thirty-fourth resistor R34, and the other end of which is connected to the other end of the thirty-fifth resistor R35;

[0133] A thirty-first capacitor C31, one end of which is connected to the positive power supply terminal of the seventh operational amplifier A7, and the other end of which is grounded;

[0134] The thirty-second capacitor C32 has one end connected to the negative power supply terminal of the seventh operational amplifier A7 and the other end grounded.

[0135] Specifically, the effective value detection circuit is the core part of the echo processing module. For the subsequent circuit processing, we need to convert the sensor signal into an effective value signal. For this purpose, the effective value detection circuit of the present invention adopts the LTC1966 chip U1. The LTC1966 chip U1 is an integrated circuit that converts effective value into direct current; it adopts a special processing method and has many advantages compared with the traditional processing circuit.

[0136] The traditional effective value circuit uses an analog multiplier and divider, so its linearity is not good, and the temperature change has a great impact on it. In order to solve this problem, the present invention uses the LTC1966 chip U1, which uses an incremental summation ΔΣ modulator to replace the divider and uses a unipolar switch as the multiplier. The ΔΣ modulator has good linearity and a single output bit is used to control whether to convert the input signal or buffer the input signal. Here, the joint role of the ΔΣ modulator and the unipolar switch is the same as the role played by the analog multiplier and divider in the traditional effective value circuit.

[0137] In some embodiments, the analog-to-digital conversion circuit specifically uses a data acquisition card. General data acquisition cards can realize analog-to-digital conversion functions and data acquisition functions, so the present invention uses a data acquisition card to complete the analog-to-digital conversion and data acquisition functions.

[0138] Data acquisition card, i.e., computer expansion card realizing data acquisition function, can be connected to personal computer through bus such as USB, Ethernet, PCI, PCI Express, PXI, FireWire (1394), PCMCIA, IS A, CompactFlash, 485, 232, various wireless networks, etc. According to the collected signal and the actual conditions, the data acquisition card of NI USB-6218 model is adopted in the present invention, which provides 32 analog inputs; 250kS / s single channel sampling rate; 2 analog outputs; 8 digital input lines; 8 digital output lines; 4 programmable input ranges (±0.2V to ±10V) for each channel; digital trigger; 2 counter timers. 60V, CAT I isolation function makes the accuracy and safety better.

[0139] In the present invention, in order for the array-type electromagnetic eddy current nondestructive testing system to be able to effectively extract the weak eddy current signal induced by the probe under the background of stronger and more complex electromagnetic interference and noise. By analyzing the noise that may interfere with the probe, a basis is provided for the subsequent noise suppression measures. In general circuit systems, there are generally two different types of interference, namely interference outside the system and interference inside the system. External interference refers to the noise generated by the interference source outside the system, which is coupled to the signal detection circuit or system in the form of magnetic field coupling or electric field coupling. Internal interference mainly depends on the quality of the components in the circuit; the external interference that affects the circuit is closely related to the layout and structure of the circuit, and also depends on the coupling path of the external interference or the characteristics of the interference source.

[0140] In order to reduce internal and external interference, the present invention takes the following measures:

[0141] (1) Selection of circuit components

[0142] In order to ensure that the weak eddy current signal will not be distorted by noise interference, it is necessary to select appropriate devices when designing the echo processing module. As for the peripheral devices of the integrated amplifier and filter, the resistors use high-precision metal film resistors, and the circuits use resistors with small resistance values ​​as much as possible. Because the resistors themselves will introduce noise in the circuit, which will increase the background noise of the echo processing module. In addition, the filter in the circuit uses an integrated filter, avoiding the use of high-precision capacitors, and ceramic capacitors with better filtering effects are used in the decoupling capacitors of the integrated chip power supply.

[0143] (2) Low ripple floating power supply design

[0144] In the field of weak signal amplification, power frequency interference is a type of interference that is difficult to eliminate. Power frequency noise mainly interferes with the signal in the receiving system through the power supply coupling method of signal conditioning and the electromagnetic coupling method in space.

[0145] In general measuring instruments or systems, the power supply is generally obtained by reducing the voltage, rectifying and filtering the 220V AC. Therefore, after rectification, there is still a small amount of AC ripple entering the amplifier and generating noise. The noise components mainly include the inherent noise of the rectifier, voltage regulator and other components in the power circuit, the power frequency and high-order harmonic components superimposed on the power output, and other noise components on the power frequency power line. For this reason, it is best to use battery power supply for low-noise amplification of weak signals to completely eliminate AC ripple interference.

[0146] For the echo processing module that detects weak eddy current signals, power supply noise is one of the main noise sources, so appropriate measures must be taken to prevent it. In the present invention, the power supply of the amplifier circuit and the active filter in the echo processing module adopts a floating positive and negative dual power supply. The floating power supply refers to the ground terminal of the power supply that is not connected to the ground but is connected to the reference potential of the analog signal system of the signal conditioning circuit, and the reference ground of the analog signal system is isolated from the ground of the digital signal by a magnetic bead. In order to minimize the noise signal output by the power supply voltage source, on the basis of ensuring the minimum area of ​​the power line loop and the measurement loop, the present invention adopts a dry battery combined with a linear voltage regulator tube to design a low-noise, low-ripple, stable power supply voltage source, and adds a filter capacitor at the power supply of the integrated chip, which effectively eliminates the parasitic coupling between the amplifiers of each level in the signal conditioning circuit and the interference of the AC ripple, and ensures the low noise and stability of the power supply of the echo processing module.

[0147] (3) Shielded twisted pair signal transmission line

[0148] In order to effectively weaken the impact of external interference noise on the system, twisted pair cables are used in signal transmission lines where external interference noise is easily coupled. According to the structure of the operational amplifier, the signal source ungrounded balanced differential amplification technology is adopted, and the shielding layer of the shielded twisted pair cable is connected to the reference ground of the echo processing module in a single-point grounding manner.

[0149] Due to the late stage of eddy current signal detection, the induced voltage signal is relatively weak, and in the actual engineering application process, the transmission distance is relatively long, and it is easy to be interfered by the electric field and magnetic field in the environment, resulting in a decrease in the signal-to-noise ratio of the entire detection system. In order to suppress the coupling of external interference noise during the transmission of weak signals, the most direct method is to reduce the distributed capacitance between the interference wire and the sensitive signal line. The most effective way is to use twisted pair transmission lines to convert interference into common mode noise.

[0150] Using shielded twisted pair to transmit signals and combining with relevant operational amplifiers to perform differential balanced preamplification of the signals can effectively reduce the size of the interference noise at the signal input end. Since the shielded twisted pair is twisted very evenly, on the one hand, due to the special structure of the twisted pair, the area of ​​external magnetic field induction can be effectively reduced, and the induced electromotive force generated by adjacent knots of the twisted pair has opposite signs and can cancel each other out, so the twisted pair can effectively suppress the magnetic field interference in the environment; on the other hand, the distributed capacitance between the two signals of the external interference line is roughly equal, so that the electric field or coupling noise is converted into common mode noise for the amplifier, so as long as the common mode rejection ratio of the operational amplifier is high enough, the interference noise can be effectively suppressed.

[0151] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An array type electromagnetic eddy current nondestructive testing system, characterized in that: include: The excitation signal generating module is connected to the control signal, and is used to generate the original excitation signal by using the DDS method under the control of the control signal, and to power-amplify the original excitation signal to obtain the excitation signal; The probes arranged in an array are connected to the excitation signal generating module and are used to generate a changing magnetic field under the excitation of the excitation signal, so that the measured pipeline generates an eddy current signal under the changing magnetic field, and picks up the eddy current signal; An echo processing module, connected to the probe, for sequentially performing pre-amplification, effective value detection and analog-to-digital conversion processing on the eddy current signal to obtain a digital signal; The control module is connected to the excitation signal generating module and the echo processing module, and is used to generate the control signal and analyze the digital signal to obtain the detection result of the detected pipeline.

2. The array type electromagnetic eddy current nondestructive testing system according to claim 1 is characterized in that: The excitation signal generating module comprises: A DDS signal generating circuit, connected to the control module, for generating an original excitation signal under the control of the control signal; The power amplifier circuit is connected to the DDS signal generating circuit and the probe, and is used to perform power amplification on the original excitation signal to obtain an excitation signal.

3. The array type electromagnetic eddy current nondestructive testing system according to claim 2 is characterized in that: The power amplifier circuit comprises: A first resistor, one end of which is connected to the DDS signal generating circuit; A first operational amplifier, wherein the inverting input terminal is connected to the other end of the first resistor, the non-inverting input terminal is connected to a preset reference voltage, the positive power supply terminal is connected to the first supply voltage, and the negative power supply terminal is grounded; A second resistor is connected between the inverting input terminal and the output terminal of the first operational amplifier; A first capacitor connected in parallel with the second resistor; A second capacitor, one end of which is connected to the output end of the first operational amplifier; A third capacitor, one end of which is connected to the positive power supply terminal of the first operational amplifier, and the other end of which is grounded; a third resistor, one end of which is connected to the other end of the second capacitor; a fourth resistor, one end of which is connected to the other end of the second capacitor; A complementary push-pull power amplifier is connected to the other end of the third resistor, the other end of the fourth resistor and the probe.

4. The array type electromagnetic eddy current nondestructive testing system according to claim 1, characterized in that: The probe is a mutual inductance coil sensor made of cylindrical winding.

5. The array type electromagnetic eddy current nondestructive testing system according to claim 1, characterized in that: The echo processing module comprises: A preamplifier circuit, connected to the probe, for performing preamplification processing on the eddy current signal to obtain a preamplified signal; An effective value detection circuit, connected to the preamplifier circuit, for performing effective value detection processing on the preamplifier signal to obtain an effective value detection signal; The analog-to-digital conversion circuit is connected to the effective value detection circuit and the control module, and is used to perform analog-to-digital conversion processing on the effective value detection signal to obtain a digital signal.

6. The array type electromagnetic eddy current nondestructive testing system according to claim 5, characterized in that: The preamplifier circuit includes a limited differential preamplifier subcircuit, and the limited differential preamplifier subcircuit includes: a fifth resistor, one end of which is connected to the probe; a sixth resistor, one end of which is connected to the other end of the fifth resistor; a seventh resistor, one end of which is connected to the other end of the sixth resistor; a fourth capacitor, one end of which is connected to the other end of the fifth resistor, and the other end of which is grounded; a fifth capacitor, one end of which is connected to the other end of the sixth resistor, and the other end of which is grounded; A second operational amplifier, wherein the non-phase input terminal is connected to a preset reference voltage, the inverting input terminal is connected to the other end of the seventh resistor, the positive power supply terminal is connected to the first supply voltage, and the negative power supply terminal is grounded; an eighth resistor, connected between the inverting input terminal and the output terminal of the second operational amplifier; a sixth capacitor connected in parallel with the eighth resistor; a seventh capacitor, one end of which is connected to the positive power supply terminal of the second operational amplifier, and the other end of which is grounded; a ninth resistor, one end of which is connected to the probe; a tenth resistor, one end of which is connected to the other end of the ninth resistor; an eleventh resistor, one end of which is connected to the other end of the tenth resistor; an eighth capacitor, one end of which is connected to the other end of the ninth resistor, and the other end of which is grounded; a ninth capacitor, one end of which is connected to the other end of the tenth resistor, and the other end of which is grounded; A third operational amplifier, wherein the non-phase input terminal is connected to a preset reference voltage, the inverting input terminal is connected to the other end of the eleventh resistor, the positive power supply terminal is connected to the first supply voltage, and the negative power supply terminal is grounded; A twelfth resistor is connected between the inverting input terminal and the output terminal of the third operational amplifier; a tenth capacitor connected in parallel with the twelfth resistor; An eleventh capacitor has one end connected to the positive power supply terminal of the third operational amplifier and the other end connected to the ground.

7. The array type electromagnetic eddy current nondestructive testing system according to claim 6, characterized in that: The preamplifier circuit also includes a secondary amplifier subcircuit, and the secondary amplifier subcircuit includes: a twelfth capacitor, one end of which is connected to the output end of the second operational amplifier; A thirteenth capacitor, one end of which is connected to the output end of the third operational amplifier; a thirteenth resistor, one end of which is connected to the other end of the twelfth capacitor; a fourteenth resistor, one end of which is connected to the other end of the thirteenth capacitor; A sixteenth resistor, one end of which is connected to a preset reference voltage, and the other end of which is connected to the other end of the fourteenth resistor; A fourth operational amplifier, wherein a non-inverting input terminal is connected to the other end of the fourteenth resistor, an inverting input terminal is connected to the other end of the thirteenth resistor, a positive power supply terminal is connected to the first supply voltage, a negative power supply terminal is grounded, and an output terminal is connected to the effective value detection circuit; A fifteenth resistor is connected between the inverting input terminal and the output terminal of the fourth operational amplifier; A fourteenth capacitor, one end of which is connected to the positive power supply terminal of the fourth operational amplifier, and the other end of which is grounded; A seventeenth resistor, one end of which is connected to the output end of the fourth operational amplifier; A fifth operational amplifier, wherein the non-phase input terminal is connected to a preset reference voltage, the inverting input terminal is connected to the other end of the seventeenth resistor, the positive power supply terminal is connected to the first supply voltage, the negative power supply terminal is grounded, and the output terminal is connected to the effective value detection circuit; An eighteenth resistor is connected between the inverting input terminal and the output terminal of the fifth operational amplifier; A fifteenth capacitor has one end connected to the positive power supply terminal of the fifth operational amplifier and the other end connected to the ground.

8. The array type electromagnetic eddy current nondestructive testing system according to claim 6, characterized in that: A first transient voltage suppressor diode is connected between the fifth resistor and the probe, and a second transient voltage suppressor diode is connected between the ninth resistor and the probe.

9. The array type electromagnetic eddy current nondestructive testing system according to claim 7, characterized in that: The effective value detection circuit comprises: A first BNC connector, one end of which is connected to the output end of the fourth operational amplifier; A nineteenth resistor, one end of which is connected to the other end of the first BNC connector, and the other end of which is grounded; A twentieth resistor, one end of which is connected to the other end of the first BNC connector; A twenty-first resistor, one end of which is connected to the other end of the twenty-first resistor, and the other end of which is grounded; A first active connector, comprising three terminals; a first terminal of the first active connector is connected to the other end of the 20th resistor, and a second terminal of the first active connector is grounded; a twenty-second resistor, one end of which is connected to the third terminal of the first active connector; A second BNC connector, one end of which is connected to the output end of the fifth operational amplifier; A twenty-third resistor, one end of which is connected to the other end of the second BNC connector, and the other end of which is grounded; A twenty-fourth resistor, one end of which is connected to the other end of the second BNC connector; A twenty-fifth resistor, one end of which is connected to the other end of the twenty-fourth resistor and the other end of which is grounded; A second active connector, comprising three terminals; a first terminal of the second active connector is connected to the other end of the second fourth resistor, and a second terminal of the second active connector is grounded; a twenty-sixth resistor, one end of which is connected to the third terminal of the second active connector; LTC1966 chip, IN1 pin connected to the other end of the 22nd resistor, IN2 pin connected to the other end of the 26th resistor, VDD pin connected to the second supply voltage, Vss pin connected to the third supply voltage; The twenty-seventh resistor, one end of which is connected to the LTC1966 chip Pins; A twenty-eighth resistor, one end of which is connected to the other end of the twenty-seventh resistor, and the other end of which is connected to the control module; A third active connector, comprising three terminals; a first terminal of the third active connector is connected to a GND pin of the LTC1966 chip, a second terminal of the third active connector is connected to a second supply voltage, and a third terminal of the third active connector is connected between the twenty-seventh resistor and the twenty-eighth resistor; A sixteenth capacitor, one end of which is connected to the GND pin of the LTC1966 chip, and the other end is grounded; A fourth active connector, comprising three terminals; a first terminal of the fourth active connector is connected to a third supply voltage, a second terminal of the fourth active connector is grounded, and a third terminal of the fourth active connector is connected to a GND pin of the LTC1966 chip; A seventeenth capacitor, one end of which is connected to the Vss pin of the LTC1966 chip, and the other end is grounded; An eighteenth capacitor, one end of which is connected to the Vss pin of the LTC1966 chip, and the other end is grounded; A nineteenth capacitor, one end of which is connected to the VDD pin of the LTC1966 chip, and the other end is grounded; A twentieth capacitor, one end of which is connected to the VDD pin of the LTC1966 chip, and the other end is grounded; A fifth active connector, comprising three terminals; a first terminal of the fifth active connector is connected to a third supply voltage, a second terminal of the fifth active connector is grounded, and a third terminal of the fifth active connector is connected to an OUTRTN pin of the LTC1966 chip; A twenty-first capacitor, one end of which is connected to the OUTRTN pin of the LTC1966 chip, and the other end is grounded; A twenty-second capacitor is connected between the OUTRTN pin and the Vout pin of the LTC1966 chip; A twenty-third capacitor is connected between the OUTRTN pin and the Vout pin of the LTC1966 chip; A sixth active connector, comprising three terminals; a first terminal of the sixth active connector is connected to an optional DC precision filter through a twenty-ninth resistor, a second terminal of the sixth active connector is connected to an optional filter buffer, and a third terminal of the sixth active connector is connected to a Vout pin of the LTC1966 chip; The optional DC precision filter, the optional filter buffer, the third terminal of the sixth active connector and the OUTRTN pin of the LTC1966 chip are all connected to the analog-to-digital conversion circuit.

10. The array type electromagnetic eddy current nondestructive testing system according to claim 9, characterized in that: The optional DC precision filter includes: A twenty-fifth capacitor, one end of which is connected to the twenty-ninth resistor; A sixth operational amplifier, having an inverting input terminal connected to the other end of the twenty-fifth capacitor, a positive power supply terminal connected to the fourth supply voltage, and a negative power supply terminal connected to the fifth supply voltage; A twenty-fourth capacitor, one end of which is connected to the non-inverting input terminal of the sixth operational amplifier, and the other end of which is grounded; A 30th resistor, one end of which is connected to the non-inverting input terminal of the sixth operational amplifier, and the other end of which is grounded; A thirty-first resistor, one end of which is connected to the non-inverting input terminal of the sixth operational amplifier, and the other end of which is connected to the fourth supply voltage; A twenty-sixth capacitor, one end of which is connected to the positive power supply terminal of the sixth operational amplifier, and the other end of which is grounded; A twenty-seventh capacitor, one end of which is connected to the negative power supply terminal of the sixth operational amplifier, and the other end of which is grounded; A thirty-second resistor is connected between the inverting input terminal and the output terminal of the sixth operational amplifier; A twenty-eighth capacitor, one end of which is connected to the output end of the sixth operational amplifier, and the other end of which is connected to one end of the twenty-fifth capacitor and the analog-to-digital conversion circuit; The optional filter buffer comprises: A thirty-third resistor, one end of which is connected to the second terminal of the sixth active connector; A thirty-fourth resistor, one end of which is connected to the other end of the thirty-third resistor; a seventh operational amplifier, wherein a non-phase input terminal is connected to the other end of the thirty-fourth resistor, a positive power supply terminal is connected to the fourth supply voltage, a negative power supply terminal is connected to the fifth supply voltage, and an output terminal is connected to the analog-to-digital conversion circuit; a 30th capacitor, one end of which is connected to the non-inverting input terminal of the seventh operational amplifier, and the other end of which is grounded; A thirty-fifth resistor, one end of which is connected to the inverting input terminal of the seventh operational amplifier, and the other end of which is connected to the output terminal of the seventh operational amplifier; A twenty-ninth capacitor, one end of which is connected between the thirty-third resistor and the thirty-fourth resistor, and the other end of which is connected to the other end of the thirty-fifth resistor; A thirty-first capacitor, one end of which is connected to the positive power supply terminal of the seventh operational amplifier, and the other end of which is grounded; A thirty-second capacitor has one end connected to the negative power supply terminal of the seventh operational amplifier and the other end connected to the ground.

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