A synchronous phase acquisition system

Abstract

The application relates to the technical field of electrical equipment, and discloses a synchronous phase acquisition system. The system comprises the following: a flexible current sensor for measuring a current signal in a measured cable and converting the current signal into a voltage signal; a current detection module for reducing the voltage signal to obtain a reduced voltage signal; a trigger signal processing module for performing zero-crossing detection on the reduced voltage signal to obtain a trigger signal, performing level conversion on the trigger signal to obtain a square wave signal; a trigger signal transmitting module for converting the square wave signal into a wireless signal and transmitting the wireless signal to a trigger signal receiving module in a wireless mode; the trigger signal receiving module for receiving the wireless signal and reducing the wireless signal into a trigger signal; and a trigger signal analysis module for converting the trigger signal into a level trigger signal and outputting the level trigger signal to a detection terminal. The application obtains the current in a non-contact mode, converts the current into a voltage, and connects the detection terminal in a wireless mode, so that the effectiveness of local detection is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of electrical equipment technology, and in particular to a synchronous phase acquisition system. Background Technology

[0002] Gas-insulated switchgear (GIS), with its metal casing and conductors arranged coaxially, is a key power equipment using high-voltage SF6 gas insulation. It is widely used in large power plants and substations. GIS equipment offers significant advantages over open-type switchgear, including low unit loss, minimal environmental impact, high operational reliability, and space saving. After on-site assembly, to verify the installation process and ensure no internal defects remain before commissioning, on-site insulation testing is conducted on the GIS equipment. Partial discharge testing is performed at 1.2 times the rated voltage, typically using ultra-high frequency and ultrasonic testing methods. To improve the accuracy of partial discharge diagnosis and anti-interference performance, the phase of the test voltage needs to be acquired during the testing process to generate PRPD and PRPS spectra, determining the phase correlation of the signal.

[0003] During the on-site withstand voltage test of ultra-high voltage GIS, a series resonance method is typically used. The frequency of the test voltage is related to the capacitance of the GIS sample and is distributed between 30Hz and 300Hz. In previous partial discharge detection tests, the internal synchronization method of the detection equipment was usually used to acquire partial discharge pulses. However, as the detection time increases, the internal synchronization phase will deviate significantly, causing the accumulated partial discharge pulses to lose phase correlation, resulting in low accuracy of the experimental results. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to overcome the shortcomings of the prior art and provide a method, apparatus, computer device and readable storage medium for obtaining synchronous phase.

[0005] This invention provides the following technical solution:

[0006] In a first aspect, this disclosure provides a synchronous phase acquisition system, the system comprising a flexible current sensor, a current detection module, a trigger signal processing module, a trigger signal transmitting module, a trigger signal receiving module, and a trigger signal parsing module;

[0007] The flexible current sensor is electrically connected to the current detection module. The current detection module is also electrically connected to the trigger signal processing module. The trigger signal processing module is also electrically connected to the trigger signal transmitting module. The trigger signal transmitting module is also communicatively connected to the trigger signal receiving module. The trigger signal receiving module is also electrically connected to the trigger signal parsing module.

[0008] The flexible current sensor is used to measure the current signal in the cable under test and convert the current signal into a voltage signal.

[0009] The current detection module is used to restore the voltage signal to obtain the restored voltage signal;

[0010] The trigger signal processing module is used to perform zero-crossing detection on the restored voltage signal to obtain a trigger signal, and to perform level conversion on the trigger signal to obtain a square wave signal;

[0011] The trigger signal transmitting module is used to convert the square wave signal into a wireless signal and transmit it wirelessly to the trigger signal receiving module;

[0012] The trigger signal receiving module is used to receive the wireless signal and restore the wireless signal to the trigger signal;

[0013] The trigger signal parsing module is used to convert the trigger signal into a level trigger signal and output the level trigger signal to the detection terminal.

[0014] Optionally, the current detection module includes a single-order RC analog low-pass filter unit, an active integrating amplifier unit, and an ADC acquisition unit;

[0015] The single-order RC analog low-pass filter unit is electrically connected to the flexible current sensor, the single-order RC analog low-pass filter unit is electrically connected to the active integrating amplifier unit, the active integrating amplifier unit is electrically connected to the ADC acquisition unit, and the ADC acquisition unit is electrically connected to the trigger signal processing module.

[0016] The single-stage RC analog low-pass filter unit is used to filter out signals in the voltage signal whose frequency is higher than the preset cutoff frequency, so as to obtain the filtered voltage signal.

[0017] The active integrating amplifier unit is used to condition and amplify the filtered voltage signal to obtain a first voltage signal after conditioning and amplification, and to integrate and restore the first voltage signal after conditioning and amplification to obtain the restored voltage signal.

[0018] The ADC acquisition unit is used to convert the restored voltage signal into a digital voltage signal.

[0019] Optionally, the single-order RC analog low-pass filter unit includes a first diode D1, a first resistor R1, and a first capacitor C1; the active integrating amplifier unit includes a first-stage amplifier circuit, a third capacitor C3, a second-stage integrating circuit, an eighth resistor R8, and a fifth capacitor C5; the first-stage amplifier circuit includes a second resistor R2, a third resistor R3, a fourth resistor R4, a second capacitor C2, and a first precision operational amplifier OP1; the second-stage integrating circuit includes a second precision operational amplifier OPA2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a fourth capacitor C4.

[0020] The first terminal of the first diode D1 is electrically connected to the first terminal of the flexible current sensor and the first terminal of the first resistor R1. The second terminal of the first diode D1 is electrically connected to the second terminal of the flexible current sensor and the second terminal of the first capacitor C1. The second terminal of the first capacitor C1 is grounded. The second terminal of the first resistor R1 is electrically connected to the first terminal of the first capacitor C1 and the first terminal of the second resistor R2. The second terminal of the first capacitor C1 is electrically connected to the first terminal of the third resistor R3. The second terminal of the second resistor R2 is electrically connected to the non-inverting input terminal of the first precision operational amplifier OP1. The second terminal of the third resistor R3 is electrically connected to the inverting input terminal of the first precision operational amplifier OP1, the first terminal of the fourth resistor R4, and the first terminal of the second capacitor C2. The second terminals of the fourth resistor R4 and the second capacitor C2 are both electrically connected to the output terminal of the first precision operational amplifier OP1. The output terminal of the precision operational amplifier OP1 is electrically connected to the first terminal of the third capacitor C3. The second terminal of the third capacitor C3 is electrically connected to the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is electrically connected to the first terminal of the sixth resistor R6, the first terminal of the fourth capacitor C4, and the inverting input terminal of the second precision operational amplifier OPA2. The first terminal of the seventh resistor R7 is electrically connected to the non-inverting input terminal of the second precision operational amplifier OPA2. The second terminal of the seventh resistor R7 is grounded. The second terminals of the sixth resistor R6 and the fourth capacitor C4 are both electrically connected to the output terminal of the second precision operational amplifier OP2. The output terminal of the second precision operational amplifier OP2 is electrically connected to the first terminal of the eighth resistor R8. The second terminal of the eighth resistor R8 is electrically connected to the first terminal of the fifth capacitor C5 and the input terminal of the ADC acquisition unit. The output terminal of the ADC acquisition unit is electrically connected to the trigger signal processing module.

[0021] Optionally, the trigger signal processing module includes an in-phase amplifier unit, a hysteresis zero-crossing comparison unit, and a level conversion unit;

[0022] The in-phase amplifier unit is electrically connected to the ADC acquisition unit, the in-phase amplifier unit is electrically connected to the hysteresis zero-crossing comparator unit, the hysteresis zero-crossing comparator unit is electrically connected to the level conversion unit, and the level conversion unit is electrically connected to the trigger signal transmission module.

[0023] The in-phase amplifier unit is used to condition and amplify the digital voltage signal to obtain a second voltage signal after conditioning and amplification.

[0024] The hysteresis zero-crossing comparison unit is used to perform zero-crossing detection on the conditioned and amplified second voltage signal to obtain the trigger signal;

[0025] The level conversion unit is used to convert the level of the trigger signal to obtain the square wave signal.

[0026] Optionally, the in-phase amplifier unit includes an eighth resistor R8, a sixth capacitor C6, a third precision operational amplifier OPA3, a ninth resistor R9, a tenth resistor R10, and a seventh capacitor C7; the hysteresis zero-crossing comparator unit includes a third-stage amplifier circuit, a second diode D2, and a fourteenth resistor R14; the third-stage amplifier circuit includes a fourth precision operational amplifier OPA4, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and an eighth capacitor C8; and the level conversion unit includes a first MOSFET Q1, a twentieth resistor R20, a twenty-first resistor R21, and a twenty-second resistor R22.

[0027] The first terminal of the eighth resistor R8 is electrically connected to the output terminal of the ADC acquisition unit. The second terminal of the eighth resistor R8 is electrically connected to the first terminal of the sixth capacitor C6 and the non-inverting input terminal of the third precision operational amplifier OPA3. The second terminal of the sixth capacitor C6 and the first terminal of the ninth resistor R9 are both grounded. The second terminal of the ninth resistor R9 is electrically connected to the inverting input terminal of the third precision operational amplifier OP3, the first terminal of the tenth resistor R10, and the first terminal of the seventh capacitor C7. The second terminals of the tenth resistor R10 and the seventh capacitor C7 are both electrically connected to the output terminal of the third precision operational amplifier OP3. The output terminal of the third precision operational amplifier OP3 is electrically connected to the first terminal of the eleventh resistor R11. The second terminal of the eleventh resistor R11 is electrically connected to the first terminal of the thirteenth resistor R13, the first terminal of the eighth capacitor C8, and the non-inverting input terminal of the fourth precision operational amplifier OPA4. The second terminal of the thirteenth resistor R13 and the first terminal of the eighth capacitor C8 are both grounded. Both ends of the resistor R12 are electrically connected to the output of the fourth precision operational amplifier OPA4. The first end of the twelfth resistor R12 is electrically connected to the inverting input of the fourth precision operational amplifier OPA4. The second end of the twelfth resistor R12 is grounded. The output of the fourth precision operational amplifier OPA4 is electrically connected to the first end of the second diode D2. The second end of the second diode D2 is electrically connected to the first end of the fourteenth resistor R14. The first end of the twentieth resistor R20 is electrically connected to the second end of the fourteenth resistor R14 and the drain of the first MOS transistor Q1. The second end of the twentieth resistor R20 is connected to the high-voltage power supply. The gate of the first MOS transistor Q1 is electrically connected to the first end of the twentieth resistor R21. The source of the first MOS transistor Q1 is electrically connected to the first end of the twentieth resistor R22. The second ends of the twentieth resistor R21 and the twentieth resistor R22 are both connected to the low-voltage power supply. The first end of the twentieth resistor R22 is electrically connected to the trigger signal transmitting module.

[0028] Optionally, the trigger signal transmitting module includes a first main controller and a first wireless transceiver module;

[0029] The first main controller is electrically connected to the level conversion unit, the first main controller is connected to the first wireless transceiver module, and the first wireless transceiver module is communicatively connected to the trigger signal receiving module;

[0030] The first master controller is used to receive the trigger signal and generate a sine wave signal with the same frequency as the trigger signal;

[0031] The first wireless transceiver module is used to collect the sine wave signal, modulate the sine wave signal into the wireless signal, and transmit the wireless signal to the trigger signal receiving module wirelessly.

[0032] Optionally, the first main controller includes a DAC module, and the first wireless transceiver module includes an ADC converter, a first MCU chip, and a first RF IC chip;

[0033] The DAC module is electrically connected to the first end of the 22nd resistor R22, the DAC module is connected to the ADC converter, the ADC converter is communicatively connected to the first MCU chip, and the first MCU chip is communicatively connected to the first RF IC chip.

[0034] Optionally, the trigger signal receiving module includes a second main controller and a second wireless transceiver module;

[0035] The second wireless transceiver module is communicatively connected to the first wireless transceiver module, the second wireless transceiver module is communicatively connected to the second main controller, and the second main controller is electrically connected to the trigger signal parsing module;

[0036] The second wireless transceiver module is used to receive the wireless signal and demodulate the wireless signal into the sine wave signal;

[0037] The second master controller is used to restore the sine wave signal to the trigger signal.

[0038] Optionally, the second main controller includes a PWM module, an ADC module, a power port, a data port (Data), and a general purpose input / output port (GPIO); the second wireless transceiver module includes a DAC converter, a second MCU chip, and a second RF IC chip.

[0039] The second RF IC chip is communicatively connected to the first RF IC chip, the second RF IC chip is communicatively connected to the second MCU chip, the second MCU chip is communicatively connected to the DAC converter, the DAC converter is connected to the ADC module, the ADC module is communicatively connected to the PWM module, the data port (Data) and the general purpose input / output port (GPIO) are both electrically connected to the trigger signal parsing module, the power supply port is connected to the low-voltage power supply, and the second main controller is grounded.

[0040] Optionally, the trigger signal parsing module includes a non-inverting level converter, which includes a first port A, a second port B, an output enable port OE, a high-voltage power supply port VCCB, and a low-voltage power supply port VCCA.

[0041] The high-voltage power supply port VCCB is connected to the high-voltage power supply, the low-voltage power supply port VCCA is connected to the low-voltage power supply, the in-phase level converter is grounded, the first port A is electrically connected to the data port Data, the output enable port OE is electrically connected to the general purpose input / output port GPIO, and the second port B outputs a level trigger signal.

[0042] The beneficial effects of this application are:

[0043] The synchronous phase acquisition system provided in this application embodiment obtains the output current of the frequency converter cabinet during the experiment in the ultra-high voltage GIS field withstand voltage test system in a non-contact manner, converts the current waveform into a voltage analog quantity, and then connects to the detection terminal in a wireless communication manner, effectively improving the effectiveness of local detection.

[0044] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0045] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the various drawings, similar components are numbered similarly.

[0046] Figure 1 This paper shows a schematic diagram of the structure of a synchronous phase acquisition system provided in an embodiment of this application;

[0047] Figure 2 This illustration shows a schematic diagram of a synchronous phase acquisition system for partial discharge monitoring in field insulation testing of ultra-high voltage GIS, provided by an embodiment of this application.

[0048] Figure 3 A circuit diagram of a current detection module provided in an embodiment of this application is shown;

[0049] Figure 4 A circuit diagram of a trigger signal processing module provided in an embodiment of this application is shown;

[0050] Figure 5 A schematic diagram illustrating the workflow of a trigger signal transmitting module provided in an embodiment of this application is shown.

[0051] Figure 6 A schematic diagram illustrating the workflow of a trigger signal receiving module provided in an embodiment of this application is shown.

[0052] Figure 7 The diagram shows a circuit schematic of a trigger signal parsing module provided in an embodiment of this application.

[0053] Explanation of key component symbols:

[0054] 100 - Synchronous phase acquisition system; 110 - Flexible current sensor; 120 - Current detection module; 130 - Trigger signal processing module; 140 - Trigger signal transmission module; 150 - Trigger signal reception module; 160 - Trigger signal analysis module; 121 - Single-order RC analog low-pass filter unit; 122 - Active integrating amplifier unit; 123 - ADC acquisition unit; 131 - In-phase amplifier unit; 132 - Hysteresis zero-crossing comparator unit; 133 - Level conversion unit; 141 - First main controller; 142 - First wireless transceiver module; 151 - Second main controller; 152 - Second wireless transceiver module; 161 - In-phase level converter. Detailed Implementation

[0055] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0056] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "electrically connected" to another component, it can be directly electrically connected to the other component or there may be an intervening component. Conversely, when a component is said to be "directly on" another component, there is no intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0057] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "electrical connection," and "fixation," etc., should be interpreted broadly. For example, they can refer to fixed electrical connections, detachable electrical connections, or integral connections; they can refer to mechanical electrical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0058] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the template description is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0060] Example

[0061] like Figure 1 The diagram shown is a structural schematic of a synchronous phase acquisition system 100 according to an embodiment of this application. The synchronous phase acquisition system 100 provided in this embodiment includes a flexible current sensor 110, a current detection module 120, a trigger signal processing module 130, a trigger signal transmitting module 140, a trigger signal receiving module 150, and a trigger signal parsing module 160. The flexible current sensor 110 and the current detection module 120 are electrically connected. The current detection module 120 is also electrically connected to the trigger signal processing module 130. The trigger signal processing module 130 is also electrically connected to the trigger signal transmitting module 140. The trigger signal transmitting module 140 is also communicatively connected to the trigger signal receiving module 150. The trigger signal receiving module 150 is also electrically connected to the trigger signal parsing module 160.

[0062] The flexible current sensor 110 is used to measure the current signal in the cable under test and convert the current signal into a voltage signal.

[0063] Understandably, the pulse phase under AC voltage is an important characteristic parameter in the detection and diagnosis of partial discharge. Therefore, in field acceptance tests, in order to obtain accurate phase information, such as... Figure 2 As shown, in this embodiment, a flexible current coil sensor is used to detect the cable current input at the electrical connection cable between the frequency converter cabinet and the excitation transformer in the field withstand voltage test system. The flexible current coil sensor is a non-contact current detection sensor. Its structure consists of a hollow ring coil uniformly wound on a non-magnetic material. When the current signal of the cable being measured passes through the center of the ring coil, an alternating magnetic field is generated, which in turn generates a voltage signal in the coil. The corresponding voltage is the derivative of the measured current passing through the coil with respect to time.

[0064] The flexible current coil sensor measures current by being secured to the cable under test using cable ties. Compared with traditional current transformers (CTs) with iron cores, the flexible coil can achieve real-time current measurement and has a fast response. At the same time, because the coil uses non-ferromagnetic materials, the coil output will not saturate due to large primary current and there is no magnetization current error. In addition, the sensor is lightweight, has strong resistance to external electromagnetic interference, produces almost no phase error, and ensures electrical safety when opened, without the risk of secondary open circuit.

[0065] For example, this embodiment uses a flexible current sensor 110 with a dynamic current range of 1A to 1kA, a sensitivity of 100uV / A (at 50Hz frequency), a bandwidth range of 1Hz to 100kHz (3dB), zero drift as low as 0.1mV, linearity of 0.2%, sensitivity error of less than 0.5%, and an inner diameter of 150mm to adapt to AC current testing scenarios ranging from a few amperes to several hundred amperes. The specific model of the flexible current sensor 110 can be selected according to the actual situation, and this embodiment does not limit it.

[0066] The current detection module 120 is used to restore the voltage signal to obtain the restored voltage signal.

[0067] Specifically, the current detection module 120 includes a single-order RC analog low-pass filter unit 121, an active integrating amplifier unit 122, and an ADC acquisition unit 123. The single-order RC analog low-pass filter unit 121 is electrically connected to the flexible current sensor 110, the single-order RC analog low-pass filter unit 121 is electrically connected to the active integrating amplifier unit 122, the active integrating amplifier unit 122 is electrically connected to the ADC acquisition unit 123, and the ADC acquisition unit 123 is electrically connected to the trigger signal processing module 130. The single-order RC analog low-pass filter unit 121 is used to filter signals with frequencies higher than a preset cutoff frequency in the voltage signal to obtain a filtered voltage signal. The active integrating amplifier unit 122 is used to condition and amplify the filtered voltage signal to obtain a conditioned and amplified first voltage signal, and to integrate and restore the conditioned and amplified first voltage signal to obtain a restored voltage signal. The ADC acquisition unit 123 is used to convert the restored voltage signal into a digital voltage signal.

[0068] Furthermore, the single-stage RC analog low-pass filter unit 121 includes a first diode D1, a first resistor R1, and a first capacitor C1; the active integrating amplifier unit 122 includes a first-stage amplifier circuit, a third capacitor C3, a second-stage integrating circuit, an eighth resistor R8, and a fifth capacitor C5; the first-stage amplifier circuit includes a second resistor R2, a third resistor R3, a fourth resistor R4, a second capacitor C2, and a first precision operational amplifier OP1; the second-stage integrating circuit includes a second precision operational amplifier OPA2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a fourth capacitor C4.

[0069] The first terminal of the first diode D1 is electrically connected to the first terminal of the flexible current sensor 110 and the first terminal of the first resistor R1. The second terminal of the first diode D1 is electrically connected to the second terminal of the flexible current sensor 110 and the second terminal of the first capacitor C1. The second terminal of the first capacitor C1 is grounded. The second terminal of the first resistor R1 is electrically connected to the first terminal of the first capacitor C1 and the first terminal of the second resistor R2. The second terminal of the first capacitor C1 is electrically connected to the first terminal of the third resistor R3. The second terminal of the second resistor R2 is electrically connected to the non-inverting input terminal of the first precision operational amplifier OP1. The second terminal of the third resistor R3 is electrically connected to the inverting input terminal of the first precision operational amplifier OP1, the first terminal of the fourth resistor R4, and the first terminal of the second capacitor C2. The second terminals of the fourth resistor R4 and the second capacitor C2 are both electrically connected to the output terminal of the first precision operational amplifier OP1. The output terminal of amplifier OP1 is electrically connected to the first terminal of the third capacitor C3. The second terminal of the third capacitor C3 is electrically connected to the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is electrically connected to the first terminal of the sixth resistor R6, the first terminal of the fourth capacitor C4, and the inverting input terminal of the second precision operational amplifier OPA2. The first terminal of the seventh resistor R7 is electrically connected to the non-inverting input terminal of the second precision operational amplifier OPA2. The second terminal of the seventh resistor R7 is grounded. The second terminals of the sixth resistor R6 and the fourth capacitor C4 are both electrically connected to the output terminal of the second precision operational amplifier OP2. The output terminal of the second precision operational amplifier OP2 is electrically connected to the first terminal of the eighth resistor R8. The second terminal of the eighth resistor R8 is electrically connected to the first terminal of the fifth capacitor C5 and the input terminal of the ADC acquisition unit 123. The output terminal of the ADC acquisition unit 123 is electrically connected to the trigger signal processing module 130.

[0070] Understandably, since the voltage output of the flexible current sensor 110 is the derivative of the measured current with respect to time, if there are some high-frequency components in the measured current, the flexible current sensor 110 will generate a large voltage signal, thus drowning out the fundamental signal. Therefore, an active integrating amplifier unit 122 needs to be designed after the flexible current sensor 110 for conditioning. The current detection module 120 consists of three parts: a single-order RC analog low-pass filter unit 121, an active integrating amplifier unit 122, and an ADC acquisition unit 123. The circuit diagram is shown below. Figure 3 As shown. The first resistor R1 and the first capacitor C1 in the single-stage RC analog low-pass filter unit 121 can effectively prevent out-of-band noise and interference from coupling into the relevant frequency band. In this embodiment, the effective frequency range of the measured current is 30Hz to 300Hz. By setting the values ​​of the first resistor R1 and the first capacitor C1, the relatively low cutoff frequency of the analog low-pass filter, 720Hz, is achieved, which is 2.5 times higher than the highest signal frequency, thereby ensuring a flat signal frequency band and sufficient attenuation of harmful out-of-band frequency signals. The active integrating amplifier unit 122 consists of a first-stage amplifier circuit, a third capacitor C3, a second-stage integrating circuit, an eighth resistor R8, and a fifth capacitor C5. The first-stage amplifier circuit consists of a second resistor R2, a third resistor R3, a fourth resistor R4, a second capacitor C2, and a first precision operational amplifier OP1. The first-stage amplifier circuit conditions and amplifies the small voltage signal from the flexible current sensor 110 to obtain the first voltage signal after conditioning and amplification. Because the actual operational amplifier has a DC bias, to avoid the DC bias affecting the real signal, the intermediate stage third capacitor C3 is AC-coupled to suppress the DC component from entering the second-stage integrator circuit, thereby improving the stability of the entire system. The second-stage integrator circuit consists of the second precision operational amplifier OPA2, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the fourth capacitor C4. The second-stage integrator circuit integrates and restores the first voltage signal after conditioning and amplification to obtain the restored voltage signal. The sixth resistor R6 provides a discharge circuit for the integrating capacitor, stabilizing the integration performance and preventing instability caused by long-term integration. The eighth resistor R8 and the fifth capacitor C5 act as filters. Finally, the restored voltage signal is input to the ADC acquisition unit 123, which converts the restored voltage signal into a digital voltage signal.

[0071] The trigger signal processing module 130 is used to perform zero-crossing detection on the restored voltage signal to obtain a trigger signal, and to perform level conversion on the trigger signal to obtain a square wave signal.

[0072] Specifically, the trigger signal processing module 130 includes an in-phase amplifier unit 131, a hysteresis zero-crossing comparator unit 132, and a level conversion unit 133; the in-phase amplifier unit 131 is electrically connected to the ADC acquisition unit 123, the in-phase amplifier unit 131 is electrically connected to the hysteresis zero-crossing comparator unit 132, the hysteresis zero-crossing comparator unit 132 is electrically connected to the level conversion unit 133, and the level conversion unit 133 is electrically connected to the trigger signal transmission module 140; the in-phase amplifier unit 131 is used to condition and amplify the digital voltage signal to obtain a conditioned and amplified second voltage signal; the hysteresis zero-crossing comparator unit 132 is used to perform zero-crossing detection on the conditioned and amplified second voltage signal to obtain a trigger signal; the level conversion unit 133 is used to perform level conversion on the trigger signal to obtain a square wave signal.

[0073] Furthermore, the non-inverting amplifier unit 131 includes an eighth resistor R8, a sixth capacitor C6, a third precision operational amplifier OPA3, a ninth resistor R9, a tenth resistor R10, and a seventh capacitor C7; the hysteresis zero-crossing comparator unit 132 includes a third-stage amplifier circuit, a second diode D2, and a fourteenth resistor R14; the third-stage amplifier circuit includes a fourth precision operational amplifier OPA4, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and an eighth capacitor C8; the level conversion unit 133 includes a first MOSFET Q1, a twentieth resistor R20, a twenty-first resistor R21, and a twenty-second resistor R22; the eighth... The first terminal of resistor R8 is electrically connected to the output terminal of ADC acquisition unit 123. The second terminal of resistor R8 is electrically connected to the first terminal of capacitor C6 and the non-inverting input terminal of precision operational amplifier OPA3. The second terminal of capacitor C6 and the first terminal of resistor R9 are both grounded. The second terminal of resistor R9 is electrically connected to the inverting input terminal of precision operational amplifier OP3, the first terminal of resistor R10, and the first terminal of capacitor C7. The second terminals of resistor R10 and capacitor C7 are both electrically connected to the output terminal of precision operational amplifier OP3. The output terminal is electrically connected to the first terminal of the eleventh resistor R11. The second terminal of the eleventh resistor R11 is electrically connected to the first terminal of the thirteenth resistor R13, the first terminal of the eighth capacitor C8, and the non-inverting input terminal of the fourth precision operational amplifier OPA4. The second terminals of the thirteenth resistor R13 and the eighth capacitor C8 are both electrically connected to the output terminal of the fourth precision operational amplifier OPA4. The first terminal of the twelfth resistor R12 is electrically connected to the inverting input terminal of the fourth precision operational amplifier OPA4. The second terminal of the twelfth resistor R12 is grounded. The output terminal of the fourth precision operational amplifier OPA4 is electrically connected to the first terminal of the second diode D2. The second terminal of diode D2 is electrically connected to the first terminal of the fourteenth resistor R14. The first terminal of the twentieth resistor R20 is electrically connected to the second terminal of the fourteenth resistor R14 and the drain of the first MOSFET Q1. The second terminal of the twentieth resistor R20 is connected to the high-voltage power supply. The gate of the first MOSFET Q1 is electrically connected to the first terminal of the twenty-first resistor R21. The source of the first MOSFET Q1 is electrically connected to the first terminal of the twenty-second resistor R22. The second terminals of the twenty-first resistor R21 and the twenty-second resistor R22 are both connected to the low-voltage power supply. The first terminal of the twenty-second resistor R22 is electrically connected to the trigger signal transmitting module 140.

[0074] Understandably, the digital voltage signal restored by integration in the current detection module 120 is an AC sinusoidal voltage signal in phase with the measured current. Therefore, to obtain the phase information of the measured current, it is necessary to detect and locate the zero point of this digital voltage signal to obtain a trigger signal. The function of the trigger signal processing module 130 is to perform zero-crossing detection processing on the obtained digital voltage signal. The trigger signal processing module 130 includes three parts: an in-phase amplifier unit 131, a hysteresis zero-crossing comparator unit 132, and a level conversion unit 133. The circuit diagram is shown below. Figure 4 As shown.

[0075] First, the digital voltage signal is filtered by the eighth resistor R8 and the sixth capacitor C6. Then, it is conditioned and amplified by the proportional gain amplifier consisting of the third precision operational amplifier OPA3, the ninth resistor R9, and the tenth resistor R10, resulting in a conditioned and amplified second voltage signal. This increases the signal amplitude for easier subsequent processing. The conditioned and amplified second voltage signal is then input to the hysteresis zero-crossing comparator unit 132, which consists of the third-stage amplifier circuit, the second diode D2, and the fourteenth resistor R14. One end of the twelfth resistor R12 is connected to ground. When the voltage at the non-inverting input of the fourth precision operational amplifier OPA4 is greater than the threshold voltage (e.g., 0), the output is high; when the voltage at the non-inverting input is less than the threshold voltage (e.g., 0), the output is low. The values ​​of the eleventh resistor R11 and the thirteenth resistor R13 are used to set the disturbance threshold, preventing multiple zero-crossing noise signals near the zero point of the signal waveform, which could lead to false triggering. This improves the noise immunity and ensures the stability and reliability of the trigger signal. The second diode D2 isolates the analog output from the digital trigger signal, effectively avoiding interference between the analog and digital signals and improving the stability of the entire system.

[0076] Finally, the signal passes through the level conversion unit 133 composed of the first MOSFET Q1. When the waveform of the trigger signal is low, there is a low-voltage power supply VCC_L, the twenty-second resistor R22, and the internal diode circuit of the first MOSFET Q1. Therefore, the source of the first MOSFET Q1 is at a low level. When the waveform of the trigger signal is high, the aforementioned circuit does not exist. Therefore, the source of the first MOSFET Q1 is at a high level due to the pull-up resistor. This realizes the conversion of the trigger signal level from the VCC_H level domain to the VCC_L level domain, improving the system's compatibility and flexibility. Finally, a square wave signal is output.

[0077] The trigger signal transmitting module 140 is used to convert the square wave signal into a wireless signal and transmit it wirelessly to the trigger signal receiving module 150.

[0078] Specifically, the trigger signal transmitting module 140 includes a first main controller 141 and a first wireless transceiver module 142; the first main controller 141 is electrically connected to the level conversion unit 133, the first main controller 141 is connected to the first wireless transceiver module 142, and the first wireless transceiver module 142 is communicatively connected to the trigger signal receiving module 150; the first main controller 141 is used to receive the trigger signal and generate a sine wave signal with the same frequency as the trigger signal; the first wireless transceiver module 142 is used to collect the sine wave signal, modulate the sine wave signal into a wireless signal, and transmit the wireless signal to the trigger signal receiving module 150 wirelessly.

[0079] Furthermore, the first main controller 141 includes a DAC module, and the first wireless transceiver module 142 includes an ADC converter, a first MCU chip, and a first RF IC chip; the DAC module and the first terminal of the 22nd resistor R22 are electrically connected, the DAC module and the ADC converter are connected, the ADC converter and the first MCU chip are communicatively connected, and the first MCU chip and the first RF IC chip are communicatively connected.

[0080] Understandably, the waveform output by the trigger signal processing module 130 is a square wave signal, which can be directly used as a TTL level trigger signal output and connected to the detection terminal via a coaxial cable. However, cable connection sometimes cannot meet the requirements for long distances in the field, and carrying heavy cables is inconvenient. Therefore, in this embodiment, the trigger signal transmitting module 140 can transmit the generated square wave signal to the remote trigger signal receiving module 150 via wireless communication, thereby realizing the wireless connection function. The flowchart of the trigger signal transmitting module 140 is as follows. Figure 5 As shown, the trigger signal transmitting module 140 includes two parts: a first main control chip 141 and a first wireless transceiver module 142. First, a square wave signal is input to the first main control chip 141. The DAC module inside the first main control chip 141 generates a sine wave signal with the same frequency as the trigger signal. The sine wave signal is acquired and processed by the ADC converter of the first wireless transceiver module 142, and then sent to the first RF IC chip through the corresponding digital communication interface via the first MCU chip. The first RF IC chip modulates the sine wave signal into a wireless signal and transmits it through the antenna as a radio wave. This design not only improves the reliability and stability of communication, but also reduces noise interference and attenuation during signal transmission.

[0081] The design of the trigger signal transmitting module 140 solves the inconvenience of cable connections in the field due to excessive distances or heavy cable loads, improving the system's flexibility and portability. Furthermore, it simplifies the system structure, reduces the use of cables and connectors, and lowers system complexity and maintenance costs. Simultaneously, the wireless communication method avoids signal loss and interference issues that may arise from cable connections, improving the overall system performance.

[0082] The trigger signal receiving module 150 is used to receive wireless signals and convert the wireless signals back into trigger signals.

[0083] Specifically, the trigger signal receiving module 150 includes a second main controller 151 and a second wireless transceiver module 152; the second wireless transceiver module 152 is communicatively connected to the first wireless transceiver module 142, the second wireless transceiver module 152 is communicatively connected to the second main controller 151, and the second main controller 151 is electrically connected to the trigger signal parsing module 160; the second wireless transceiver module 152 is used to receive wireless signals and demodulate the wireless signals into sine wave signals; the second main controller 151 is used to restore the sine wave signals into trigger signals.

[0084] Furthermore, the second main controller 151 includes a PWM module, an ADC module, a power port, a data port (Data), and a general purpose input / output (GPIO) port. The second wireless transceiver module 152 includes a DAC converter, a second MCU chip, and a second RF IC chip. The second RF IC chip is communicatively connected to the first RF IC chip, the second RF IC chip is communicatively connected to the second MCU chip, the second MCU chip is communicatively connected to the DAC converter, the DAC converter is connected to the ADC module, the ADC module is communicatively connected to the PWM module, the data port (Data) and the general purpose input / output (GPIO) port (GPIO) are both electrically connected to the trigger signal parsing module 160, the power port is connected to a low-voltage power supply, and the second main controller 151 is grounded.

[0085] Understandably, the workflow diagram of the trigger signal receiving module 150 is as follows: Figure 6 As shown, the trigger signal receiving module 150 is used to establish wireless communication with the trigger signal transmitting module 140. This design makes the connection between the signal source device and the signal receiving device more flexible and convenient, no longer limited by the length and weight of the cable. In use, the trigger signal transmitting module 140 is installed at the signal source device end, and the trigger signal receiving module 150 is installed at the signal receiving device end. The processing of the trigger signal receiving module 150 is the reverse process of the transmitting block. First, the received wireless signal is demodulated by the second RF IC chip in the second wireless transceiver module 152 to obtain the transmitted sine wave signal. This signal is then sent to the DAC converter of the second wireless transceiver module 152 via the second MCU chip through the corresponding digital communication interface. Then, the sine wave signal is restored by the DAC converter and output to the second main controller 151. The PWM module inside the second main controller 151 restores and outputs a trigger signal. This design ensures the accuracy and integrity of the signal during transmission, avoiding false triggering or missed triggering problems caused by signal distortion or loss.

[0086] The trigger signal parsing module 160 is used to convert the trigger signal into a level trigger signal and output the level trigger signal to the detection terminal.

[0087] Specifically, the trigger signal parsing module 160 includes a non-inverting level converter 161, which includes a first port A, a second port B, an output enable port OE, a high-voltage power supply port VCCB, and a low-voltage power supply port VCCA. The high-voltage power supply port VCCB is connected to the high-voltage power supply, the low-voltage power supply port VCCA is connected to the low-voltage power supply, the non-inverting level converter 161 is grounded, the first port A is electrically connected to the data port Data, the output enable port OE is electrically connected to the general purpose input / output port GPIO, and the second port B outputs a level trigger signal.

[0088] Understandably, such as Figure 7 As shown, the trigger signal parsing module 160 includes a non-inverting level converter 161. The main control MCU on the right is the second main control MCU 151 in the trigger signal receiving module 150. The non-inverting level converter 161 can be independently configured with power ports of two different power domains, realizing power domain isolation and conversion. The first port A is used to track the level trigger signal of power domain VCCA. In this embodiment, it tracks the level trigger signal output by the data port Data of the second main control MCU 151 in the trigger signal receiving module 150. The second port B is used to track the level trigger signal of the output power domain VCCB. In this embodiment, it is used to output the level trigger signal TTL. The output enable port OE is used to control the tri-state output state of IO. The level state is controlled by the general purpose input / output port GPIO of the second main control MCU 151. This design provides flexible IO output control function, enabling the trigger signal parsing module 160 to adjust the output state according to actual needs, improving the configurability and scalability of the system.

[0089] The trigger signal parsing module 160 converts the trigger signal into a driving-capable level trigger signal, which is then output to the detection terminal. The phase of this level trigger signal is the phase of the measured current, thus accurately obtaining phase information. This design enhances the signal's driving capability, enabling stable and reliable signal transmission to the detection terminal, thereby improving the system's stability and reliability.

[0090] The synchronous phase acquisition system 100 provided in this application embodiment obtains the output current of the frequency converter cabinet during the experiment in the ultra-high voltage GIS field withstand voltage test system in a non-contact manner, converts the current waveform into a voltage analog quantity, and then connects to the detection terminal in a wireless communication manner, effectively improving the effectiveness of local detection.

[0091] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0092] In addition, the functional modules or units in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0093] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium can be a non-volatile storage medium or a volatile storage medium. For example, the storage medium can be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other medium capable of storing program code.

[0094] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A synchronous phase acquisition system, characterized in that, The system includes a flexible current sensor, a current detection module, a trigger signal processing module, a trigger signal transmitting module, a trigger signal receiving module, and a trigger signal parsing module; The flexible current sensor is electrically connected to the current detection module. The current detection module is also electrically connected to the trigger signal processing module. The trigger signal processing module is also electrically connected to the trigger signal transmitting module. The trigger signal transmitting module is also communicatively connected to the trigger signal receiving module. The trigger signal receiving module is also electrically connected to the trigger signal parsing module. The flexible current sensor is used to measure the current signal in the cable under test and convert the current signal into a voltage signal. The current detection module is used to restore the voltage signal to obtain the restored voltage signal; The trigger signal processing module is used to perform zero-crossing detection on the restored voltage signal to obtain a trigger signal, and to perform level conversion on the trigger signal to obtain a square wave signal; The trigger signal transmitting module is used to convert the square wave signal into a wireless signal and transmit it wirelessly to the trigger signal receiving module; The trigger signal receiving module is used to receive the wireless signal and restore the wireless signal to the trigger signal; The trigger signal parsing module is used to convert the trigger signal into a level trigger signal and output the level trigger signal to the detection terminal; The current detection module includes a single-order RC analog low-pass filter unit, an active integrating amplifier unit, and an ADC acquisition unit. The single-order RC analog low-pass filter unit is electrically connected to the flexible current sensor, the single-order RC analog low-pass filter unit is electrically connected to the active integrating amplifier unit, the active integrating amplifier unit is electrically connected to the ADC acquisition unit, and the ADC acquisition unit is electrically connected to the trigger signal processing module. The single-stage RC analog low-pass filter unit is used to filter out signals in the voltage signal whose frequency is higher than the preset cutoff frequency, so as to obtain the filtered voltage signal. The active integrating amplifier unit is used to condition and amplify the filtered voltage signal to obtain a first voltage signal after conditioning and amplification, and to integrate and restore the first voltage signal after conditioning and amplification to obtain the restored voltage signal. The ADC acquisition unit is used to convert the restored voltage signal into a digital voltage signal; The single-order RC analog low-pass filter unit includes a first diode D1, a first resistor R1, and a first capacitor C1. The active integrating amplifier unit includes a first-stage amplifier circuit, a third capacitor C3, a second-stage integrating circuit, an eighth resistor R8, and a fifth capacitor C5. The first-stage amplifier circuit includes a second resistor R2, a third resistor R3, a fourth resistor R4, a second capacitor C2, and a first precision operational amplifier OP1. The second-stage integrating circuit includes a second precision operational amplifier OPA2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a fourth capacitor C4. The first terminal of the first diode D1 is electrically connected to the first terminal of the flexible current sensor and the first terminal of the first resistor R1. The second terminal of the first diode D1 is electrically connected to the second terminal of the flexible current sensor and the second terminal of the first capacitor C1. The second terminal of the first capacitor C1 is grounded. The second terminal of the first resistor R1 is electrically connected to the first terminal of the first capacitor C1 and the first terminal of the second resistor R2. The second terminal of the first capacitor C1 is electrically connected to the first terminal of the third resistor R3. The second terminal of the second resistor R2 is electrically connected to the non-inverting input terminal of the first precision operational amplifier OP1. The second terminal of the third resistor R3 is electrically connected to the inverting input terminal of the first precision operational amplifier OP1, the first terminal of the fourth resistor R4, and the first terminal of the second capacitor C2. The second terminals of the fourth resistor R4 and the second capacitor C2 are both electrically connected to the output terminal of the first precision operational amplifier OP1. The output terminal of the precision operational amplifier OP1 is electrically connected to the first terminal of the third capacitor C3. The second terminal of the third capacitor C3 is electrically connected to the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is electrically connected to the first terminal of the sixth resistor R6, the first terminal of the fourth capacitor C4, and the inverting input terminal of the second precision operational amplifier OPA2. The first terminal of the seventh resistor R7 is electrically connected to the non-inverting input terminal of the second precision operational amplifier OPA2. The second terminal of the seventh resistor R7 is grounded. The second terminals of the sixth resistor R6 and the fourth capacitor C4 are both electrically connected to the output terminal of the second precision operational amplifier OP2. The output terminal of the second precision operational amplifier OP2 is electrically connected to the first terminal of the eighth resistor R8. The second terminal of the eighth resistor R8 is electrically connected to the first terminal of the fifth capacitor C5 and the input terminal of the ADC acquisition unit. The output terminal of the ADC acquisition unit is electrically connected to the trigger signal processing module.

2. The synchronous phase acquisition system according to claim 1, characterized in that, The trigger signal processing module includes an in-phase amplifier unit, a hysteresis zero-crossing comparison unit, and a level conversion unit; The in-phase amplifier unit is electrically connected to the ADC acquisition unit, the in-phase amplifier unit is electrically connected to the hysteresis zero-crossing comparator unit, the hysteresis zero-crossing comparator unit is electrically connected to the level conversion unit, and the level conversion unit is electrically connected to the trigger signal transmission module. The in-phase amplifier unit is used to condition and amplify the digital voltage signal to obtain a second voltage signal after conditioning and amplification. The hysteresis zero-crossing comparison unit is used to perform zero-crossing detection on the conditioned and amplified second voltage signal to obtain the trigger signal; The level conversion unit is used to convert the level of the trigger signal to obtain the square wave signal.

3. The synchronous phase acquisition system according to claim 2, characterized in that, The in-phase amplification unit includes an eighth resistor R8, a sixth capacitor C6, a third precision operational amplifier OPA3, a ninth resistor R9, a tenth resistor R10, and a seventh capacitor C7. The hysteresis zero-crossing comparator unit includes a third-stage amplification circuit, a second diode D2, and a fourteenth resistor R14. The third-stage amplification circuit includes a fourth precision operational amplifier OPA4, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and an eighth capacitor C8. The level conversion unit includes a first MOSFET Q1, a twentieth resistor R20, a twenty-first resistor R21, and a twenty-second resistor R22. The first terminal of the eighth resistor R8 is electrically connected to the output terminal of the ADC acquisition unit. The second terminal of the eighth resistor R8 is electrically connected to the first terminal of the sixth capacitor C6 and the non-inverting input terminal of the third precision operational amplifier OPA3. The second terminal of the sixth capacitor C6 and the first terminal of the ninth resistor R9 are both grounded. The second terminal of the ninth resistor R9 is electrically connected to the inverting input terminal of the third precision operational amplifier OP3, the first terminal of the tenth resistor R10, and the first terminal of the seventh capacitor C7. The second terminals of the tenth resistor R10 and the seventh capacitor C7 are both electrically connected to the output terminal of the third precision operational amplifier OP3. The output terminal of the third precision operational amplifier OP3 is electrically connected to the first terminal of the eleventh resistor R11. The second terminal of the eleventh resistor R11 is electrically connected to the first terminal of the thirteenth resistor R13, the first terminal of the eighth capacitor C8, and the non-inverting input terminal of the fourth precision operational amplifier OPA4. The second terminal of the thirteenth resistor R13 and the first terminal of the eighth capacitor C8 are both grounded. Both ends of the resistor R12 are electrically connected to the output of the fourth precision operational amplifier OPA4. The first end of the twelfth resistor R12 is electrically connected to the inverting input of the fourth precision operational amplifier OPA4. The second end of the twelfth resistor R12 is grounded. The output of the fourth precision operational amplifier OPA4 is electrically connected to the first end of the second diode D2. The second end of the second diode D2 is electrically connected to the first end of the fourteenth resistor R14. The first end of the twentieth resistor R20 is electrically connected to the second end of the fourteenth resistor R14 and the drain of the first MOS transistor Q1. The second end of the twentieth resistor R20 is connected to the high-voltage power supply. The gate of the first MOS transistor Q1 is electrically connected to the first end of the twentieth resistor R21. The source of the first MOS transistor Q1 is electrically connected to the first end of the twentieth resistor R22. The second ends of the twentieth resistor R21 and the twentieth resistor R22 are both connected to the low-voltage power supply. The first end of the twentieth resistor R22 is electrically connected to the trigger signal transmitting module.

4. The synchronous phase acquisition system according to claim 3, characterized in that, The trigger signal transmitting module includes a first main control unit and a first wireless transceiver module; The first main controller is electrically connected to the level conversion unit, the first main controller is connected to the first wireless transceiver module, and the first wireless transceiver module is communicatively connected to the trigger signal receiving module; The first master controller is used to receive the trigger signal and generate a sine wave signal with the same frequency as the trigger signal; The first wireless transceiver module is used to collect the sine wave signal, modulate the sine wave signal into the wireless signal, and transmit the wireless signal to the trigger signal receiving module wirelessly.

5. The synchronous phase acquisition system according to claim 4, characterized in that, The first main controller includes a DAC module, and the first wireless transceiver module includes an ADC converter, a first MCU chip, and a first RF IC chip; The DAC module is electrically connected to the first end of the 22nd resistor R22, the DAC module is connected to the ADC converter, the ADC converter is communicatively connected to the first MCU chip, and the first MCU chip is communicatively connected to the first RF IC chip.

6. The synchronous phase acquisition system according to claim 5, characterized in that, The trigger signal receiving module includes a second main control module and a second wireless transceiver module. The second wireless transceiver module is communicatively connected to the first wireless transceiver module, the second wireless transceiver module is communicatively connected to the second main controller, and the second main controller is electrically connected to the trigger signal parsing module; The second wireless transceiver module is used to receive the wireless signal and demodulate the wireless signal into the sine wave signal; The second master controller is used to restore the sine wave signal to the trigger signal.

7. The synchronous phase acquisition system according to claim 6, characterized in that, The second main controller includes a PWM module, an ADC module, a power port, a data port (Data), and a general purpose input / output (GPIO) port. The second wireless transceiver module includes a DAC converter, a second MCU chip, and a second RF IC chip. The second RF IC chip is communicatively connected to the first RF IC chip, the second RF IC chip is communicatively connected to the second MCU chip, the second MCU chip is communicatively connected to the DAC converter, the DAC converter is connected to the ADC module, the ADC module is communicatively connected to the PWM module, the data port (Data) and the general purpose input / output port (GPIO) are both electrically connected to the trigger signal parsing module, the power supply port is connected to the low-voltage power supply, and the second main controller is grounded.

8. The synchronous phase acquisition system according to claim 7, characterized in that, The trigger signal parsing module includes an in-phase level converter, which includes a first port A, a second port B, an output enable port OE, a high-voltage power supply port VCCB, and a low-voltage power supply port VCCA. The high-voltage power supply port VCCB is connected to the high-voltage power supply, the low-voltage power supply port VCCA is connected to the low-voltage power supply, the in-phase level converter is grounded, the first port A is electrically connected to the data port Data, the output enable port OE is electrically connected to the general purpose input / output port GPIO, and the second port B outputs a level trigger signal.

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