High-voltage level shift circuit with high dVdt suppression capability

Abstract

The invention provides a high-voltage level shift circuit with high dVdt suppression capability, which is used for converting a signal in a low-voltage domain into a signal in a high-voltage domain and comprises an encyclopedia level shift module, a PMOS (P-channel Metal Oxide Semiconductor) coupling module, a noise current elimination module, a current compensation module, a transmission gate module and an RS (Reed-Solomon) latch module, the level shift module is used for transmitting signals from a low-voltage domain to a high-voltage domain, the PMOS coupling module is used for converting voltage signals transmitted by the level shift module into current signals, accelerating signal transmission and preventing common-mode signals from passing through, and the noise current elimination module is used for mirroring current, accelerating signal transmission and counteracting common-mode noise induction current. The current compensation module is used for compensating the current of a node, the transmission gate is used for transmitting a signal output by the noise elimination module to the RS latch, the RS latch module is used for recovering an edge narrow pulse signal into a square signal, and according to the scheme, the dV / dt noise suppression capability of the circuit is enhanced while low power consumption and low delay are achieved.

Description

Technical Field

[0001] This application relates to the field of intelligent power drive, specifically to a high-voltage level shifting circuit with high dV / dt suppression capability. Background Technology

[0002] High-voltage gate driver chips are a core component in power electronics, primarily responsible for driving and controlling power devices operating in high-voltage environments, such as MOSFETs, IGBTs, GaN, and SiC. Their performance directly impacts the reliability and stability of power electronic systems. During hard switching, large current pulses at the switching node generate dV / dt noise through parasitic inductance. This dV / dt noise is coupled to the high-side floating power rail via the bootstrap path. Due to the large drain-source parasitic capacitance of LDMOS transistors LD1 and LD2, the dV / dt noise creates a displacement current across this capacitance. This displacement current generates a voltage drop Vdrop across the drain resistor of the LDMOS transistor. If the voltage drop Vdrop across the resistor is sufficiently large, exceeding the threshold voltage of the subsequent inverter, the noise signal is transmitted to the next stage circuit, causing the high-side power transistor gate control signal HO to erroneously turn on and off. When dV / dt noise causes HO to erroneously turn on, if the low-side power transistor gate control signal LO is also high at this time, a shoot-through phenomenon will occur, burning out the chip. When dV / dt noise causes HO to turn off incorrectly, it will result in the loss of the normal HO gate control signal of the high-side power transistor. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a high-voltage level shift circuit with high dV / dt noise suppression capability, while simultaneously achieving low power consumption and low latency, thereby improving the operating frequency and reliability of the driver chip.

[0004] This application provides a high-voltage level shifting circuit with high dV / dt suppression capability, including: a level shifting module, a PMOS cross-coupling module, a noise current cancellation module, a current compensation module, a transmission gate module, and an RS latch module; The level shifting module is used to transmit signals from the low-voltage domain to the high-voltage domain. The PMOS cross-coupling module is used to convert the voltage signal transmitted by the level shifting module into a current signal, which speeds up signal transmission and prevents common-mode signals from passing through. The noise current cancellation module is used to mirror the current, speed up signal transmission and cancel the common-mode noise induced current. The current compensation module is used to compensate the current of the node. The transmission gate is used to transmit the signal output by the noise cancellation module to the RS latch. The RS latch module is used to recover the edge narrow pulse signal into a square wave signal. The level shifting module includes two branches, left and right. The left level shifting branch consists of LDMOS transistor LD1, resistor R1, capacitor C1, Zener diode ZD1, and diode D1. The right level shifting branch consists of LDMOS transistor LD2, resistor R2, capacitor C2, Zener diode ZD2, and diode D2. The gate of LD1 is connected to the output of the narrow pulse generation module, the source is grounded, and the drain is connected to node A1; one end of R1 is connected to node A1, and the other end is connected to the high-side floating power supply voltage VB; one end of C1 is connected to node A1, and the other end is connected to the high-side floating power supply voltage VB; one end of ZD1 is connected to node A1, and the other end is connected to the high-side floating power supply voltage VB; one end of D1 is connected to node A1, and the other end is connected to the high-side floating ground VS. The gate of LD2 is connected to the output of the narrow pulse generation module, the source is grounded, and the drain is connected to node A2; one end of R2 is connected to node A2, and the other end is connected to the high-side floating power supply voltage VB; one end of C2 is connected to node A2, and the other end is connected to the high-side floating power supply voltage VB; one end of ZD2 is connected to node A2, and the other end is connected to the high-side floating power supply voltage VB; one end of D2 is connected to node A2, and the other end is connected to the high-side floating ground VS. The PMOS cross-coupled module includes PMOS transistors PM1, PM2, PM3, and PM4. The gate of PM1 is connected to node A2, the drain is connected to node A1, and the source is connected to the high-side floating power supply voltage VB. The gate of PM2 is connected to node A1, the drain is connected to node A2, and the source is connected to the high-side floating power supply voltage VB. The gate of PM3 is connected to node A2, the drain is connected to node B1, and the source is connected to node A1. The gate of PM4 is connected to node A1, the drain is connected to node B2, and the source is connected to node A2. The noise current cancellation module includes NMOS transistors NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, and PMOS transistors PM5, PM6, PM7, and PM8. The gate and drain of NM1 are connected to node B1, and its source is connected to the high-side floating ground VS. The gate of NM2 is connected to node B1, its drain is connected to the drain of PM5, the gate of PM5, and the gate of PM6, and its source is connected to the high-side floating ground VS. The gate of NM3 is connected to node B1, its drain is connected to node C1, and its source is connected to the high-side floating ground VS. The gate of NM4 is connected to node B2, its drain is connected to node C2, and its source is connected to the high-side floating ground VS. The gate of NM5 is connected to node B1. 2. The drain terminal of PM8 is connected to the drain terminal of PM8, the gate terminal of PM8, and the gate terminal of PM7; the source terminal is connected to the high-side floating ground VS. The gate terminal and drain terminal of NM6 are connected to node B1, and the source terminal is connected to the high-side floating ground VS. The gate terminal of NM7 is connected to node A2, the drain terminal is connected to node B1, and the source terminal is connected to the high-side floating ground VS. The gate terminal of NM8 is connected to node A1, the drain terminal is connected to node B2, and the source terminal is connected to the high-side floating ground VS. The gate terminal of NM9 is connected to node A1, the drain terminal is connected to node C1, and the source terminal is connected to the high-side floating ground VS. The gate terminal of NM10 is connected to node A2, the drain terminal is connected to node C2, and the source terminal is connected to the high-side floating ground VS. The source terminal of PM5 is connected to the high-side floating power supply voltage VB. The drain terminal of PM6 is connected to node C2, and the source terminal is connected to the high-side floating power supply voltage VB. The drain terminal of PM7 is connected to node C1, and the source terminal is connected to the high-side floating power supply voltage VB. The source terminal of PM8 is connected to the high-side floating power supply voltage VB. The current compensation module includes PMOS transistors PM9, PM10, PM11, and PM12. The gate of PM9 is connected to node A2, and its drain is connected to the source of PM10, which is connected to the high-side floating power supply voltage VB. The gate and drain of PM10 are connected to node A1. The gate of PM11 is connected to node A1, and its drain is connected to the source of PM12, which is connected to the high-side floating power supply voltage VB. The gate and drain of PM12 are connected to node A2. The transmission gate module includes NMOS transistors NM11, NMOS transistor NM12, PMOS transistor PM13, and PMOS transistor PM14. The gate of NM11 is connected to node A1, its drain is connected to the reset terminal R2 of the RS latch, and its source is connected to node C2. The gate of PM13 is connected to node B1, its drain is connected to the reset terminal R2 of the RS latch, and its source is connected to node C2. The gate of NM12 is connected to node A2, its drain is connected to the set terminal S of the RS latch, and its source is connected to node C1. The gate of PM14 is connected to node B2, its drain is connected to the set terminal S of the RS latch, and its source is connected to node C1. The RS latch includes NMOS transistors NM13, NM14, NM15, NM16, NM17, PMOS transistors PM15, PM16, PM17, PM18, and PM19. The gate of NM13 is connected to the input S, its drain is connected to the drains of NM14 and PM16, the gate of NM17, and the gate of PM19, and its source is connected to the high-side floating ground VS. The gate of NM14 is connected to the output Q, and its source is connected to the high-side floating ground VS. The gate of NM15 is connected to the input R. 1. The drain of NM16 is connected to output Q, and the source is connected to the high-side floating ground VS. The gate of NM16 is connected to input R2, the drain of NM17 is connected to output Q, and the source is connected to the high-side floating ground VS. The gate of PM15 is connected to input S, the drain of PM16 is connected to the source of PM16, and the source is connected to the high-side floating power supply voltage VB. The gate of PM16 is connected to output Q. The gate of PM17 is connected to input R1, the drain of PM18 is connected to the source of PM18, and the source is connected to the high-side floating power supply voltage VB. The gate of PM18 is connected to input R2, and the drain of PM19 is connected to the source of PM19. The drain of PM19 is connected to output Q. Preferably, during operation, it includes two symmetrical branches. LD1, R1, C1, ZD1, and D1 form the left low-voltage to high-voltage signal path, and LD2, R2, C2, ZD2, and D2 form the right low-voltage to high-voltage signal path. R1, C1 and R2, C2 serve as drain loads for LD1 and LD2, keeping nodes A1 and A2 at a high potential when LD1 and LD2 are turned off. Zener diodes ZD1 and ZD2 are used to protect the high-side logic devices from breakdown, and diodes D1 and D2 are used to clamp the voltage of nodes A1 and A2 above VS.

[0005] Preferably, during operation, PM1, PM2, PM3, and PM4 form a cross-coupled PMOS structure; PM1 and PM2 accelerate the rise of the potential at nodes B1 and B2, and PM3 and PM4 convert the voltage signals at nodes A1 and A2 into current signals. When dV / dt occurs, PM1 and PM2 turn on to reduce the voltage drop generated by parasitic current on the load, and PM3 and PM4 turn off to prevent common-mode signals from passing through.

[0006] Preferably, during operation, NM1, NM2, PM5, and PM6 double the current of node B1 and replicate it to node C2 to charge node C2; ​​NM1 and NM3 double the current of node B1 and replicate it to node C1 to discharge node C1; NM5, NM6, PM7, and PM8 double the current of node B2 and replicate it to node C1 to charge node C1; NM4 and NM6 double the current of node B2 and replicate it to node C2 to discharge node C2; ​​NM7, NM8, NM9, and NM10 pull nodes B1, B2, C1, and C2 to a low level when static; when dV / dt occurs, the currents of nodes B1 and B2 are simultaneously replicated to nodes C1 and C2, generating the same charging and discharging currents at nodes C1 and C2, thus canceling out the common-mode noise induced currents.

[0007] Preferably, during operation, NM7 and NM8 set nodes B1 and B2 to low level to reduce power consumption, and NM9 and NM10 set nodes C1 and C2 to low level to maintain the state of the RS latch; when the signal passes through nodes B1, B2, C1, and C2, the corresponding pull-down NMOS transistors are turned off to prevent competition.

[0008] Preferably, during operation, PM9 and PM10 form the left current compensation branch, and PM11 and PM12 form the right current compensation branch, respectively, to compensate the current of nodes A1 and A2. Under normal conditions, neither compensation branch is conducting and there is no static power consumption. When dV / dt occurs, nodes A1 and A2 are pulled down simultaneously, and the current compensation branches are turned on. PM9 and PM10 compensate the current of node A1, and PM11 and PM12 compensate the current of node A1.

[0009] Preferably, during operation, T1 and T2 are always connected because A1 or A2 is in VB and B1 or B2 is in VS; when dV / dt occurs, nodes A1 and A2 are pulled down, nodes B1 and B2 are pulled up, and T1 and T2 are disconnected.

[0010] Preferably, during operation, the reset terminal R2 of the RS latch remains at a low level when the high-side floating power supply voltage is working normally, without affecting the state of the output terminal Q. The reset terminal R2 and the set terminal S control the state of the output terminal Q, converting the narrow pulse signal into a square wave signal. When the high-side floating power supply voltage is undervoltage, the reset terminal R2 becomes high, turning off the output.

[0011] The beneficial effects of this invention are as follows: 1. High dV / dt noise suppression capability. Multiple technologies, including cross-coupled PMOS modules, dynamic current compensation modules, noise current cancellation modules, and transmission gates, are employed to suppress dV / dt noise, achieving ultra-high dV / dt noise suppression capability.

[0012] 2. Low latency. A PMOS transistor is used to convert the voltage signal into a current signal, and a current mirror multiplier structure is employed to accelerate signal switching.

[0013] 3. Low power consumption. Employing a narrow-pulse edge triggering method reduces the LDMOS's conduction time, thereby effectively lowering power consumption. The noise current cancellation module and current compensation module also do not consume additional power during static operation. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the high-voltage level shifting circuit structure provided by the present invention; Figure 2 for Figure 1 Schematic diagram of the RS latch structure; Figure 3 This is a timing diagram of the high-voltage level shifting circuit proposed in this invention; Figure 4 The above diagram shows the node waveforms of the high-voltage level shifting circuit proposed in this invention when dV / dt occurs. Figure 5 This is a schematic diagram of a traditional high-voltage level shifting circuit. Figure 6 This is a schematic diagram of the high-voltage level shifting circuit structure of the prior art. Figure 7 This is a schematic diagram of the high-voltage level shifting circuit structure of the prior art. Detailed Implementation

[0015] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0016] Example 1: Please see Figure 1 As shown: This embodiment of the invention specifically discloses a high-voltage level shift circuit with high dV / dt suppression capability, while achieving low power consumption and low latency, including a level shift module, a PMOS coupling module, a noise current cancellation module, a current compensation module, a transmission gate module, and an RS latch module; The level shifting module is used to transmit signals from the low-voltage domain to the high-voltage domain. The PMOS cross-coupling module is used to convert the voltage signal transmitted by the level shifting module into a current signal, thereby accelerating signal transmission and preventing common-mode signals from passing through. The noise current cancellation module is used to mirror the current, accelerate signal transmission, and cancel the common-mode noise induced current. The current compensation module is used to compensate the current of the node. The transmission gate is used to transmit the signal output by the noise cancellation module to the RS latch. The RS latch module is used to recover the edge-narrow pulse signal into a square wave signal.

[0017] Specifically, the level shifting module includes two branches, left and right. The left low-voltage to high-voltage branch consists of LDMOS transistor LD1, resistor R1, capacitor C1, Zener diode ZD1, and diode D1. The right low-voltage to high-voltage branch consists of LDMOS transistor LD2, resistor R2, capacitor C2, Zener diode ZD2, and diode D2. The gate of LD1 is connected to the output of the narrow pulse generation module, the source is grounded, and the drain is connected to node A1; one end of R1 is connected to node A1, and the other end is connected to the high-side floating power supply voltage VB; one end of C1 is connected to node A1, and the other end is connected to the high-side floating power supply voltage VB; one end of ZD1 is connected to node A1, and the other end is connected to the high-side floating power supply voltage VB; one end of D1 is connected to node A1, and the other end is connected to the high-side floating ground VS. The gate of LD2 is connected to the output of the narrow pulse generation module, the source is grounded, and the drain is connected to node A2; one end of R2 is connected to node A2, and the other end is connected to the high-side floating power supply voltage VB; one end of C2 is connected to node A2, and the other end is connected to the high-side floating power supply voltage VB; one end of ZD2 is connected to node A2, and the other end is connected to the high-side floating power supply voltage VB; one end of D2 is connected to node A2, and the other end is connected to the high-side floating ground VS.

[0018] Both LDMOS transistors LD1 and LD2 are single-sided high-voltage devices. R1, C1 and R2, C2 are used as drain loads for LD1 and LD2, keeping nodes A1 and A2 at a high potential when LD1 and LD2 are turned off. Zener diodes ZD1 and ZD2 are used to protect the high-side logic devices from breakdown, and diodes D1 and D2 are used to clamp the voltage at nodes A1 and A2 above VS.

[0019] The device dimensions of LD1 and LD2 are the same, the resistance values ​​of R1 and R2 are the same, and the capacitance values ​​of C1 and C2 are the same.

[0020] Specifically, the PMOS cross-coupled module includes PMOS transistors PM1, PM2, PM3, and PM4. The gate of PM1 is connected to node A2, the drain is connected to node A1, and the source is connected to the high-side floating power supply voltage VB. The gate of PM2 is connected to node A1, the drain is connected to node A2, and the source is connected to the high-side floating power supply voltage VB. The gate of PM3 is connected to node A2, the drain is connected to node B1, and the source is connected to node A1. The gate of PM4 is connected to node A1, the drain is connected to node B2, and the source is connected to node A2.

[0021] The device dimensions of PM1 and PM2, and PM3 and PM4 are set to be the same.

[0022] Specifically, the noise current cancellation module includes NMOS transistors NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, and PMOS transistors PM5, PM6, PM7, and PM8. The gate and drain of NM1 are connected to node B1, and its source is connected to the high-side floating ground VS. The gate of NM2 is connected to node B1, its drain is connected to the drain of PM5, the gate of PM5, and the gate of PM6, and its source is connected to the high-side floating ground VS. The gate of NM3 is connected to node B1. The drain end is connected to node C1, and the source end is connected to the high-side floating ground VS; the gate end of NM4 is connected to node B2, the drain end is connected to node C2, and the source end is connected to the high-side floating ground VS; the gate end of NM5 is connected to node B2, the drain end is connected to the PM8 drain end, PM8 gate end, and PM7 gate end, and the source end is connected to the high-side floating ground VS; the gate end and drain end of NM6 are connected to node B1, and the source end is connected to the high-side floating ground VS; the gate end of NM7 is connected to node A2, the drain end is connected to node B1, and the source end is connected to the high-side floating ground VS; the gate end of NM8 is connected to node A1, the drain end is connected to node B2, and the source end is connected to the high-side floating ground VS; the gate end of NM9 is connected to node A1, the drain end is connected to node C1, and the source end is connected to the high-side floating ground VS; the NM10 The gate of PM5 is connected to node A2, the drain is connected to node C2, and the source is connected to the high-side floating ground VS; the source of PM5 is connected to the high-side floating power supply voltage VB; the drain of PM6 is connected to node C2, and the source is connected to the high-side floating power supply voltage VB; the drain of PM7 is connected to node C1, and the source is connected to the high-side floating power supply voltage VB; the source of PM8 is connected to the high-side floating power supply voltage VB.

[0023] The device dimensions of NM1 and NM6, NM2 and NM5, NM3 and NM4, NM7 and NM8, NM9 and NM10, PM5 and PM8, and PM6 and PM7 are set to be consistent.

[0024] Specifically, the current compensation module includes two branches, left and right. The current of the compensation node A1 in the left compensation branch is composed of PMOS transistors PM9 and PM10; the current of the compensation node A2 in the right compensation branch is composed of PMOS transistors PM11 and PM12.

[0025] The gate of PM9 is connected to node A2, and the drain is connected to the source of PM10, which is connected to the high-side floating power supply voltage VB. The gate and drain of PM10 are connected to node A1. The gate of PM11 is connected to node A1, and the drain is connected to the source of PM12, which is connected to the high-side floating power supply voltage VB. The gate and drain of PM12 are connected to node A2.

[0026] The device dimensions of PM9 and PM11, and PM10 and PM12 are set to be the same.

[0027] Specifically, the transmission gate module includes two transmission gates. Transmission gate T1 transmits the signal from node C2 to the reset terminal R2 of the RS latch and is composed of NMOS transistor NM11 and PMOS transistor PM13. Transmission gate T2 transmits the signal from node C1 to the set terminal S of the RS latch and is composed of NMOS transistor NM12 and PMOS transistor PM14. The gate of NM11 is connected to node A1, the drain is connected to the reset terminal R2 of the RS latch, and the source is connected to node C2; ​​the gate of PM13 is connected to node B1, the drain is connected to the reset terminal R2 of the RS latch, and the source is connected to node C2; ​​the gate of NM12 is connected to node A2, the drain is connected to the set terminal S of the RS latch, and the source is connected to node C1; the gate of PM14 is connected to node B2, the drain is connected to the set terminal S of the RS latch, and the source is connected to node C1.

[0028] The device dimensions of NM11 and NM12, and PM13 and PM14 are set to be consistent.

[0029] Figure 2 yes Figure 1 The RS latch structure in the text.

[0030] Specifically, the RS latch module includes two NOR gates: a two-input NOR gate NOR2 composed of NM13, NM14, PM15, and PM16, and a three-input NOR gate NOR3 composed of NM15, NM16, NM17, PM17, PM18, and PM19. The gate terminal of NM13 is connected to input S, the drain terminal is connected to the drain terminals of NM14, PM16, NM17, and PM19, and the source terminal is connected to the high-side floating ground VS; the gate terminal of NM14 is connected to output Q, and the source terminal is connected to the high-side floating ground VS; the gate terminal of NM15 is connected to input R1, the drain terminal is connected to output Q, and the source terminal is connected to the high-side floating ground VS; the gate terminal of NM16 is connected to input R2, the drain terminal is connected to output Q, and the source terminal is connected to the high-side floating ground VS; the drain terminal of NM17 is connected to output Q, and the source terminal is connected to the high-side floating ground VS; the gate terminal of PM15 is connected to input S, the drain terminal is connected to the source terminal of PM16, and the source terminal is connected to the high-side floating power supply voltage VB; the gate terminal of PM16 is connected to output Q; the gate terminal of PM17 is connected to input R1, the drain terminal is connected to the source terminal of PM18, and the source terminal is connected to the high-side floating power supply voltage VB; the gate terminal of PM18 is connected to input R2, and the drain terminal is connected to the source terminal of PM19; the drain terminal of PM19 is connected to output Q; The reset terminal R2 of the RS latch is connected to the output of the UVLO circuit, the reset terminal R2 of the RS latch is connected to the output of the transmission gate T1, the set terminal S of the RS latch is connected to the output of the transmission gate T2, and the output terminal Q of the RS latch is connected to the circuit output terminal OUT.

[0031] Figure 1 This is a high-voltage level-shifting circuit with high dV / dt suppression ability proposed by the present invention. It includes two symmetric branches. LD1, R1, and C1 form the left low-voltage to high-voltage signal path, and LD2, R2, and C2 form the right low-voltage to high-voltage signal path.

[0032] Specifically, PM1, PM2, PM3, and PM4 form a PMOS cross-coupled module. PM1 and PM2 are connected in parallel beside R1 and R2. After being turned on, the load resistance values at nodes A1 and A2 are reduced to 1 / gm / / R1, where 2 << R1, 2, raising the potentials at nodes A1 and A2 and accelerating the charging of nodes B1 and B2. PM3 and PM4 convert the voltage signals at nodes A1 and A2 into current signals and transmit them to nodes B1 and B2; when dV / dt occurs, PM1 and PM2 are turned on to charge nodes A1 and A2, and PM3 and PM4 are turned off to prevent the common-mode signal from passing through.

[0033] Specifically, the current mirror composed of NM1 and NM2 copies the current at node B1 to the drain of PM5. The current mirror composed of PM5 and PM6 copies the current at the drain of PM5 to node C2 to charge node C2. The current mirror composed of NM1 and NM3 copies the current at node B1 to node C1 to discharge node C1; the current mirror composed of NM5 and NM6 copies the current at node B2 to the drain of PM8. The current mirror composed of PM7 and PM8 copies the current at the drain of PM8 to node C1 to charge node C1. The current mirror composed of NM4 and NM6 copies the current at node B2 to node C2 to discharge node C2; by multiplying and copying the current, the charging and discharging of nodes C1 and C2 are accelerated. NM7, NM8, NM9, and NM10 pull nodes B1, B2, C1, and C2 to low level at static state; when dV / dt occurs, the currents at nodes B1 and B2 are simultaneously copied to nodes C1 and C2, generating the same charging current and discharging current at nodes C1 and C2, so that the common-mode noise induction currents cancel each other out; Specifically, NM7 and NM8 set nodes B1 and B2 to low level to reduce power consumption. NM9 and NM10 set nodes C1 and C2 to low level to keep the state of the RS latch; when the signal passes through nodes B1, B2, C1, and C2, the corresponding pull-down NMOS transistors are turned off without generating a competition phenomenon; Specifically, PM9 and PM10 form the left current compensation branch, and PM11 and PM12 form the right current compensation branch, respectively, to compensate the current of nodes A1 and A2. Under normal conditions, neither compensation branch is conducting and there is no static power consumption. When dV / dt occurs, nodes A1 and A2 are pulled down simultaneously, and the current compensation branches are turned on. PM9 and PM10 compensate the current of node A1, and PM11 and PM12 compensate the current of node A1.

[0034] Specifically, NM11 and PM13 form transmission gate T1, transmitting the signal from node C2 to the RS latch reset terminal R2, and NM12 and PM14 form transmission gate T2, transmitting the signal from node C1 to the RS latch set terminal S. Under normal conditions, T1 and T2 are always connected because A1 or A2 is in VB and B1 or B2 is in VS. When dV / dt occurs, nodes A1 and A2 are pulled down, nodes B1 and B2 are pulled up, and T1 and T2 are disconnected, preventing signal transmission.

[0035] Figure 2 The RS latch structure of the present invention is such that NM13, NM14, PM15, and PM16 constitute a two-input NOR gate, and NM15, NM16, NM17, PM17, PM18, and PM19 constitute a three-input NOR gate. Specifically, the reset terminal R2 of the RS latch remains at a low level when the high-side floating power supply voltage is operating normally, without affecting the state of the output terminal Q. The reset terminal R2 and the set terminal S control the state of the output terminal Q, converting the narrow pulse signal into a square wave signal. When the high-side floating power supply voltage is undervoltage, the reset terminal R2 goes high, turning off the output.

[0036] Figure 3The timing diagram of the circuit of this invention is shown. When both IN1 and IN2 inputs are low, LD1 and LD2 are turned off, and the potentials of points A1 and A2 are pulled high by the load resistors R1 and R2. PM1, PM2, PM3, PM4, PM9, PM10, PM11, and PM12 are turned off. NM7 and NM8 are controlled by the potentials of points A1 and A2, providing static potentials for B1 and B2. When A1 and A2 are high, NM7 and NM8 are turned on, pulling B1 and B2 low, thus turning off the current mirror structure, and the static power consumption is 0. NM9 and NM10 are controlled by the potentials of points A1 and A2, providing static potentials for points B1 and B2. When A1 and A2 are high, NM9 and NM10 turn on, pulling C1 and C2 low, thus maintaining the output of the RS latch. When IN1 is high, LD1 turns on, pulling the voltage at point A1 low, NM8 turns off, and PM2 and PM4 turn on, pulling the potential at point B2 high. PM2 is connected in parallel with R2. After PM2 is turned on, the load resistance at point A2 becomes 1 / gmPM2 / / R2, accelerating the rise of the potential at point B2. NM5 copies the current flowing through NM6 to PM8, and then to point C1 via PM7. Since NM10 is off at this time, the current at PM7 pulls point C1 high. At the same time, NM4 copies the current flowing through NM6 to point C2, keeping point C2 low. At this time, LD2 is off, the voltage at point A2 remains high, PM1 and PM3 remain off, NM7 remains on, and point B1 remains low. No current flows through NM1, NM2, NM3, PM5, and PM6. The signals at points C1 and C2 are transmitted to the RS latch via T1 and T2. When R is low and S is high, the OUT output flips from low to high. Similarly, when IN2 is high, the OUT output flips from high to low.

[0037] Figure 4 The diagram shows the node waveforms of the present invention when dV / dt occurs. When dV / dt of 600V / ns occurs, the logic states of each node remain unchanged, and the output logic states remain unchanged.

[0038] Comparative Example 1: Figure 5 The diagram shows the structure of a traditional high-voltage level shifter circuit. Due to the large drain-source parasitic capacitance of LDMOS, dV / dt noise forms a displacement current on the parasitic capacitance. The displacement current generates a voltage drop Vdrop across the drain resistor of the LDMOS transistor. When the voltage drop Vdrop across the resistor is large enough, exceeding the threshold voltage of the inverter in the next stage, the noise signal is transmitted to the next stage circuit, causing the gate control signal HO of the high-side power transistor to be erroneously turned on and off.

[0039] In traditional solutions, an RC filter circuit is typically added to the output of the high-voltage level shifter circuit. However, to ensure the effective transmission of narrow pulses normally by the chip, the filter width of the pulse filter circuit cannot exceed the width of the narrow pulse signal normally input to the gate of the LDMOS device. Therefore, this method cannot provide the chip with significant dV / dt noise immunity.

[0040] Comparative Example 2: Figure 6 The diagram illustrates the circuit schematic of prior art 1, which converts the voltage output signal into a current output signal in the transmission path, then filters out common-mode noise through a current amplifier, and finally converts it back into a voltage signal for input to the RS flip-flop for recovery. However, dv / dt noise occurs when the SET / RESET signal is active, making it difficult to completely filter out. If the duration of the dv / dt noise is longer than the pulse width of the input pulse signal, the signal cannot be transmitted normally to the RS flip-flop, resulting in dropped waveforms in the high-voltage shift output. Furthermore, when faced with issues such as process offset and layout mismatch leading to mismatch between the two common-mode noise signals, differential-mode noise is generated, which still requires RC filtering circuitry to resolve, increasing the chip's transmission delay.

[0041] Comparative Example 3: Figure 7 The circuit schematic of prior art 2 is shown, employing two cross-coupled PMOS transistors and utilizing a path to filter dV / dt noise to achieve selective filtering. However, the delay increases. When LMN1 is turned on, VC1 drops to a low level, and LMP2 is turned on, pulling Vs high. At this time, R2, LMP2, and R4 form a current path, generating a voltage drop across R2, which lowers VC2 at the source of LMP2. Furthermore, due to the pull-down effect of resistor R4 on VC2, a significant delay occurs during the Vs pull-up phase. The same applies when LMN2 is turned on. In addition, the use of an RC filter circuit further introduces the delay.

[0042] Embodiment 1 of the present invention achieves high dV / dt suppression capability while ensuring low power consumption and low latency.

[0043] The above description is merely an application embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the protection scope of the present invention patent.

Claims

1. A high voltage level shifting circuit with high dVdt suppression capability, characterized by, include: Level shifting module, PMOS cross-coupling module, noise current cancellation module, current compensation module, transmission gate module, and RS latch module; The level shifting module is used to transmit signals from the low-voltage domain to the high-voltage domain. The PMOS cross-coupling module is used to convert the voltage signal transmitted by the level shifting module into a current signal, which speeds up signal transmission and prevents common-mode signals from passing through. The noise current cancellation module is used to mirror the current, speed up signal transmission and cancel the common-mode noise induced current. The current compensation module is used to compensate the current of the node. The transmission gate is used to transmit the signal output by the noise cancellation module to the RS latch. The RS latch module is used to recover the edge narrow pulse signal into a square wave signal. The level shifting module includes two branches, left and right. The left level shifting branch consists of LDMOS transistor LD1, resistor R1, capacitor C1, Zener diode ZD1, and diode D1. The right level shifting branch consists of LDMOS transistor LD2, resistor R2, capacitor C2, Zener diode ZD2, and diode D2. The gate of LD1 is connected to the output of the narrow pulse generation module, the source is grounded, and the drain is connected to node A1; one end of R1 is connected to node A1, and the other end is connected to the high-side floating power supply voltage VB; one end of C1 is connected to node A1, and the other end is connected to the high-side floating power supply voltage VB; one end of ZD1 is connected to node A1, and the other end is connected to the high-side floating power supply voltage VB; one end of D1 is connected to node A1, and the other end is connected to the high-side floating ground VS. The gate of LD2 is connected to the output of the narrow pulse generation module, the source is grounded, and the drain is connected to node A2; one end of R2 is connected to node A2, and the other end is connected to the high-side floating power supply voltage VB; one end of C2 is connected to node A2, and the other end is connected to the high-side floating power supply voltage VB; one end of ZD2 is connected to node A2, and the other end is connected to the high-side floating power supply voltage VB; one end of D2 is connected to node A2, and the other end is connected to the high-side floating ground VS. The PMOS cross-coupled module includes PMOS transistors PM1, PM2, PM3, and PM4. The gate of PM1 is connected to node A2, the drain is connected to node A1, and the source is connected to the high-side floating power supply voltage VB. The gate of PM2 is connected to node A1, the drain is connected to node A2, and the source is connected to the high-side floating power supply voltage VB. The gate of PM3 is connected to node A2, the drain is connected to node B1, and the source is connected to node A1. The gate of PM4 is connected to node A1, the drain is connected to node B2, and the source is connected to node A2. The noise current cancellation module includes NMOS transistors NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, and PMOS transistors PM5, PM6, PM7, and PM8. The gate and drain of NM1 are connected to node B1, and its source is connected to the high-side floating ground VS. The gate of NM2 is connected to node B1, its drain is connected to the drain of PM5, the gate of PM5, and the gate of PM6, and its source is connected to the high-side floating ground VS. The gate of NM3 is connected to node B1, its drain is connected to node C1, and its source is connected to the high-side floating ground VS. The gate of NM4 is connected to node B2, its drain is connected to node C2, and its source is connected to the high-side floating ground VS. The gate of NM5 is connected to node B1.

2. The drain terminal of PM8 is connected to the drain terminal of PM8, the gate terminal of PM8, and the gate terminal of PM7; the source terminal is connected to the high-side floating ground VS. The gate terminal and drain terminal of NM6 are connected to node B1, and the source terminal is connected to the high-side floating ground VS. The gate terminal of NM7 is connected to node A2, the drain terminal is connected to node B1, and the source terminal is connected to the high-side floating ground VS. The gate terminal of NM8 is connected to node A1, the drain terminal is connected to node B2, and the source terminal is connected to the high-side floating ground VS. The gate terminal of NM9 is connected to node A1, the drain terminal is connected to node C1, and the source terminal is connected to the high-side floating ground VS. The gate terminal of NM10 is connected to node A2, the drain terminal is connected to node C2, and the source terminal is connected to the high-side floating ground VS. The source terminal of PM5 is connected to the high-side floating power supply voltage VB. The drain terminal of PM6 is connected to node C2, and the source terminal is connected to the high-side floating power supply voltage VB. The drain terminal of PM7 is connected to node C1, and the source terminal is connected to the high-side floating power supply voltage VB. The source terminal of PM8 is connected to the high-side floating power supply voltage VB. The current compensation module includes PMOS transistors PM9, PM10, PM11, and PM12. The gate of PM9 is connected to node A2, and its drain is connected to the source of PM10, which is connected to the high-side floating power supply voltage VB. The gate and drain of PM10 are connected to node A1. The gate of PM11 is connected to node A1, and its drain is connected to the source of PM12, which is connected to the high-side floating power supply voltage VB. The gate and drain of PM12 are connected to node A2. The transmission gate module includes NMOS transistors NM11, NMOS transistor NM12, PMOS transistor PM13, and PMOS transistor PM14. The gate of NM11 is connected to node A1, its drain is connected to the reset terminal R2 of the RS latch, and its source is connected to node C2. The gate of PM13 is connected to node B1, its drain is connected to the reset terminal R2 of the RS latch, and its source is connected to node C2. The gate of NM12 is connected to node A2, its drain is connected to the set terminal S of the RS latch, and its source is connected to node C1. The gate of PM14 is connected to node B2, its drain is connected to the set terminal S of the RS latch, and its source is connected to node C1. The RS latch includes NMOS transistors NM13, NM14, NM15, NM16, NM17, PMOS transistors PM15, PM16, PM17, PM18, and PM19. The gate of NM13 is connected to the input S, its drain is connected to the drains of NM14 and PM16, the gate of NM17, and the gate of PM19, and its source is connected to the high-side floating ground VS. The gate of NM14 is connected to the output Q, and its source is connected to the high-side floating ground VS. The gate of NM15 is connected to the input R.

1. The drain of NM16 is connected to output Q, and the source is connected to the high-side floating ground VS. The gate of NM16 is connected to input R2, the drain of NM17 is connected to output Q, and the source is connected to the high-side floating ground VS. The gate of PM15 is connected to input S, the drain of PM16 is connected to the source of PM16, and the source is connected to the high-side floating power supply voltage VB. The gate of PM16 is connected to output Q. The gate of PM17 is connected to input R1, the drain of PM18 is connected to the source of PM18, and the source is connected to the high-side floating power supply voltage VB. The gate of PM18 is connected to input R2, and the drain of PM19 is connected to the source of PM19. The drain of PM19 is connected to output Q.

2. The circuit of claim 1, wherein, When in operation, it contains two symmetrical branches. LD1, R1, C1, ZD1, and D1 form the left low-voltage to high-voltage signal path, and LD2, R2, C2, ZD2, and D2 form the right low-voltage to high-voltage signal path. R1, C1 and R2, C2 are used as drain loads of LD1 and LD2, so that nodes A1 and A2 are kept at a high potential when LD1 and LD2 are turned off. Zener diodes ZD1 and ZD2 are used to protect the high-side logic devices from being broken down, and diodes D1 and D2 are used to clamp the voltage of nodes A1 and A2 above VS.

3. The circuit of claim 2, wherein, During operation, PM1, PM2, PM3, and PM4 form a cross-coupled PMOS structure. PM1 and PM2 accelerate the rise of the potential at nodes B1 and B2, while PM3 and PM4 convert the voltage signals at nodes A1 and A2 into current signals. When dV / dt occurs, PM1 and PM2 turn on to reduce the voltage drop generated by parasitic current on the load, while PM3 and PM4 turn off to prevent common-mode signals from passing through.

4. The circuit of claim 3, wherein, During operation, NM1, NM2, PM5, and PM6 double the current of node B1 and replicate it to node C2 to charge node C2; ​​NM1 and NM3 double the current of node B1 and replicate it to node C1 to discharge node C1; NM5, NM6, PM7, and PM8 double the current of node B2 and replicate it to node C1 to charge node C1; NM4 and NM6 double the current of node B2 and replicate it to node C2 to discharge node C2; ​​NM7, NM8, NM9, and NM10 pull nodes B1, B2, C1, and C2 to a low level when static; when dV / dt occurs, the current of nodes B1 and B2 is simultaneously replicated to nodes C1 and C2, generating the same charging and discharging currents at nodes C1 and C2, thus canceling out the common-mode noise induced currents.

5. The circuit according to claim 4, characterized in that, During operation, NM7 and NM8 set nodes B1 and B2 to low level to reduce power consumption, and NM9 and NM10 set nodes C1 and C2 to low level to maintain the state of the RS latch. When a signal passes through nodes B1, B2, C1, and C2, the corresponding pull-down NMOS transistors are turned off, and no race condition occurs.

6. The circuit according to claim 5, characterized in that, During operation, PM9 and PM10 form the left current compensation branch, and PM11 and PM12 form the right current compensation branch, respectively, to compensate the current of nodes A1 and A2. Under normal conditions, neither compensation branch is conducting and there is no static power consumption. When dV / dt occurs, nodes A1 and A2 are pulled down simultaneously, and the current compensation branches are turned on. PM9 and PM10 compensate the current of node A1, and PM11 and PM12 compensate the current of node A1.

7. The circuit according to claim 6, characterized in that, When working, T1 and T2 are always connected because A1 or A2 is in VB and B1 or B2 is in VS; when dV / dt occurs, nodes A1 and A2 are pulled down, nodes B1 and B2 are pulled up, and T1 and T2 are disconnected.

8. The circuit according to claim 7, characterized in that, During operation, the reset terminal R2 of the RS latch remains at a low level when the high-side floating power supply voltage is working normally, which does not affect the state of the output terminal Q. The reset terminal R2 and the set terminal S control the state of the output terminal Q, converting the narrow pulse signal into a square wave signal. When the high-side floating power supply voltage is undervoltage, the reset terminal R2 becomes high, turning off the output.

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