Equal effect working condition experiment circuit and experiment method thereof

Abstract

The invention relates to an equivalent effect working condition experiment circuit and an experiment method thereof. The equivalent effect working condition experiment circuit comprises a device to be tested and an integrated voltage and current source. The integrated voltage and current source is coupled to two ends of the to-be-tested device, one end of the integrated voltage and current source is coupled to the reference ground, and the integrated voltage and current source is configured to generate voltage stress at two ends of the to-be-tested device when the to-be-tested device is in a blocking state; when the to-be-tested device is in the conducting state, current stress is generated at the two ends of the to-be-tested device; wherein the waveform change of the voltage stress and the waveform change of the current stress both accord with the waveform change of the corresponding electric stress of the to-be-tested device in the actual application working condition. According to the invention, the circuit structure is simplified, and the construction and operation cost of an experiment platform is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics technology, and in particular to an equivalent application condition experimental circuit and an experimental method thereof. Background Art

[0002] The equivalent application condition experiment uses special circuits and methods to generate stress conditions similar to the application conditions of the device under test or the core components in the device under test, so as to verify the functional integrity and long-term reliability of the device under test in actual operation. In the example where the device under test is a power semiconductor device or a converter valve group component, the converter valve equivalent application condition experiment circuit can be used to conduct experiments to verify the power semiconductor device or the converter valve group component. However, the existing converter valve equivalent application condition experiment circuit in the related art has a complex topological structure, a large number of power semiconductor devices, and high requirements for control timing coordination accuracy, resulting in high construction and operation costs of the experimental platform, which is not only not conducive to the promotion and development of the converter valve equivalent stress condition experiment, but also increases the research and development and optimization threshold of power semiconductor devices and components for converter valves, which is likely to hinder the high-quality and rapid development of the UHV DC field. Summary of the invention

[0003] Based on this, the embodiments of the present disclosure provide an equivalent application condition experimental circuit and an experimental method thereof, which simplifies the circuit structure and is conducive to reducing the construction and operation costs of the experimental platform, so as to promote the application of equivalent stress condition experiments of converter valves, thereby promoting high-quality and rapid development in the field of ultra-high voltage direct current.

[0004] In order to achieve the above-mentioned purpose, in the first aspect, some embodiments of the present disclosure provide an equivalent application condition experimental circuit, including: a device under test and an integrated voltage and current source. The integrated voltage and current source is coupled to both ends of the device under test and one end is coupled to the reference ground, and is configured to: generate voltage stress at both ends of the device under test when the device under test is in a blocking state; and generate current stress at both ends of the device under test when the device under test is in a conducting state; wherein the waveform changes of the voltage stress and the current stress are consistent with the waveform changes of the corresponding electrical stress of the device under test in actual application conditions.

[0005] In some embodiments of the present disclosure, the integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a first half-controlled power device, a second half-controlled power device and a reverse resistance fully-controlled device; wherein, one end of the first inductor is coupled to the cathode of the reverse resistance fully-controlled device, and the other end is the output end of the module; one end of the second inductor is coupled to one end of the first capacitor and the cathode of the reverse resistance fully-controlled device, and the other end is coupled to the cathode of the first half-controlled power device and the cathode of the second half-controlled power device; the other end of the first capacitor, the anode of the reverse resistance fully-controlled device and the anode of the first half-controlled power device are all coupled to the negative electrode of the DC voltage source; the anode of the second half-controlled power device is coupled to the positive electrode of the DC voltage source.

[0006] In some embodiments of the present disclosure, the module further includes a second capacitor, and the second capacitor is coupled in parallel with the DC voltage source.

[0007] In some embodiments of the present disclosure, the first capacitor and / or the second capacitor includes: a single capacitor or a plurality of groups of capacitors connected in series and parallel.

[0008] In some other embodiments of the present disclosure, the integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a first reverse resistance fully-controlled device, a half-controlled power device and a second reverse resistance fully-controlled device; wherein, one end of the first inductor is coupled to the cathode of the second reverse resistance fully-controlled device, and the other end is the output end of the module; one end of the second inductor is coupled to one end of the first capacitor and the cathode of the second reverse resistance fully-controlled device, and the other end is coupled to the cathode of the first reverse resistance fully-controlled device and the cathode of the half-controlled power device; the other end of the first capacitor, the anode of the second reverse resistance fully-controlled device and the anode of the first reverse resistance fully-controlled device are all coupled to the negative electrode of the DC voltage source; the anode of the half-controlled power device is coupled to the positive electrode of the DC voltage source.

[0009] In some other embodiments of the present disclosure, the integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a half-controlled power device, a fully-controlled switch and a reverse-resistance fully-controlled device; wherein, one end of the first inductor is coupled to the cathode of the reverse-resistance fully-controlled device, and the other end is the output end of the module; one end of the second inductor is coupled to one end of the first capacitor and the cathode of the reverse-resistance fully-controlled device, and the other end is coupled to the cathode of the half-controlled power device; the other end of the first capacitor, the anode of the reverse-resistance fully-controlled device and the anode of the half-controlled power device are all coupled to the negative electrode of the DC voltage source. Furthermore, one end of the fully-controlled switch is coupled to the positive pole of the DC voltage source, and the other end is coupled to the cathode of the half-controlled power device; or, one end of the fully-controlled switch is coupled to the negative pole of the DC voltage source, and the other end is coupled to the anode of the half-controlled power device; or, the fully-controlled switch includes: a first fully-controlled switch connected in series between the positive pole of the DC voltage source and the cathode of the half-controlled power device, and a second fully-controlled switch connected in series between the negative pole of the DC voltage source and the anode of the half-controlled power device.

[0010] In some other embodiments of the present disclosure, the integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a first reverse resistance fully-controlled device, a fully-controlled switch and a second reverse resistance fully-controlled device; wherein, one end of the first inductor is coupled to the cathode of the second reverse resistance fully-controlled device, and the other end is the output end of the module; one end of the second inductor is coupled to one end of the first capacitor and the cathode of the second reverse resistance fully-controlled device, and the other end is coupled to the cathode of the first reverse resistance fully-controlled device; the other end of the first capacitor, the anode of the second reverse resistance fully-controlled device and the anode of the first reverse resistance fully-controlled device are all coupled to the negative electrode of the DC voltage source. Furthermore, one end of the fully-controlled switch is coupled to the positive electrode of the DC voltage source, and the other end is coupled to the cathode of the first reverse-resistance fully-controlled device; or, one end of the fully-controlled switch is coupled to the negative electrode of the DC voltage source, and the other end is coupled to the anode of the first reverse-resistance fully-controlled device; or, the fully-controlled switch includes: a first fully-controlled switch connected in series between the positive electrode of the DC voltage source and the cathode of the first reverse-resistance fully-controlled device, and a second fully-controlled switch connected in series between the negative electrode of the DC voltage source and the anode of the first reverse-resistance fully-controlled device.

[0011] In some other embodiments of the present disclosure, the integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a current limiting resistor, a half-controlled power device, a fully controlled switch and a reverse resistance fully controlled device; wherein, one end of the first inductor is coupled to the cathode of the reverse resistance fully controlled device, and the other end is the output end of the module; one end of the second inductor is coupled to one end of the first capacitor, the cathode of the reverse resistance fully controlled device and one end of the current limiting resistor, and the other end is coupled to the cathode of the half-controlled power device; the other end of the current limiting resistor is coupled to the positive electrode of the DC voltage source; the other end of the first capacitor, the anode of the reverse resistance fully controlled device and the anode of the half-controlled power device are all coupled to the negative electrode of the DC voltage source. Furthermore, the fully-controlled switch is connected in series between the second inductor and the current-limiting resistor; or, the fully-controlled switch is connected in series between the negative electrode of the DC voltage source and the anode of the half-controlled power device; or, the fully-controlled switch includes: a first fully-controlled switch connected in series between the second inductor and the current-limiting resistor, and a second fully-controlled switch between the negative electrode of the DC voltage source and the anode of the half-controlled power device.

[0012] In some other embodiments of the present disclosure, the integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a current limiting resistor, a first reverse resistance fully-controlled device, a fully-controlled switch and a second reverse resistance fully-controlled device; wherein, one end of the first inductor is coupled to the cathode of the second reverse resistance fully-controlled device, and the other end is the output end of the module; one end of the second inductor is coupled to one end of the first capacitor, the cathode of the second reverse resistance fully-controlled device and one end of the current limiting resistor, and the other end is coupled to the cathode of the first reverse resistance fully-controlled device; the other end of the current limiting resistor is coupled to the positive electrode of the DC voltage source; the other end of the first capacitor, the anode of the second reverse resistance fully-controlled device and the anode of the first reverse resistance fully-controlled device are all coupled to the negative electrode of the DC voltage source. Furthermore, the fully-controlled switch is connected in series between the second inductor and the current-limiting resistor; or, the fully-controlled switch is connected in series between the negative electrode of the DC voltage source and the anode of the first reverse-resistance fully-controlled device; or, the fully-controlled switch includes: a first fully-controlled switch connected in series between the second inductor and the current-limiting resistor, and a second fully-controlled switch between the negative electrode of the DC voltage source and the anode of the first reverse-resistance fully-controlled device.

[0013] In some embodiments of the present disclosure, the reference ground is the negative pole of the DC voltage source.

[0014] In some embodiments of the present disclosure, the integrated voltage and current source includes multiple modules; the implementation of the integrated voltage and current source includes any one of the following:

[0015] In the first embodiment, a plurality of the modules are connected in parallel; wherein the ground terminals of the modules connected to the reference ground are coupled to each other, and the output terminals of the modules are coupled to each other;

[0016] Embodiment 2: A plurality of the modules are connected in series; wherein the output end of the module of the next stage is coupled to the ground end of the module of the previous stage connected to the reference ground; and the output end of the module of the last stage is the output end of the integrated voltage and current source;

[0017] In the third implementation mode, a plurality of the modules are connected in series and in parallel; wherein, the plurality of the modules are connected in series to form a plurality of series experimental circuits with the same output voltage, and the plurality of series experimental circuits are connected in parallel to both ends of the device under test.

[0018] In some embodiments of the present disclosure, the equivalent application working condition experimental circuit further includes: a current source connected in parallel to both ends of the device under test; and the integrated voltage and current source is multiplexed as a voltage source.

[0019] Optionally, the current source includes: a single group of six-pulse bridge current sources, two groups of six-pulse thyristor bridge-drag inductor current sources or a fully controlled bridge current source.

[0020] In some embodiments of the present disclosure, the equivalent application working condition experimental circuit further includes: a voltage source connected in parallel to both ends of the device under test; and the integrated voltage and current source is multiplexed as a current source.

[0021] Optionally, the voltage source includes: a synthetic test voltage source, a DC modular multi-level topology voltage source, an AC modular multi-level topology voltage source, an AC energy-taking modular multi-level topology voltage source or a multi-level DC link topology voltage source.

[0022] In a second aspect, some embodiments of the present disclosure further provide an experimental method for an equivalent application working condition experimental circuit, which is used to perform an equivalent application working condition experiment on the equivalent application working condition experimental circuit described in some of the above embodiments. The experimental method comprises the following steps.

[0023] When the device under test is in a blocking state, the integrated voltage and current source generates voltage stress at both ends of the device under test.

[0024] When the device under test is in the on state, the integrated voltage and current source generates current stress at both ends of the device under test.

[0025] The waveform changes of the above voltage stress and current stress are consistent with the waveform changes of the corresponding electrical stress of the device under test in actual application conditions.

[0026] In some embodiments of the present disclosure, the equivalent application working condition experimental circuit further includes: a current source connected in parallel to both ends of the device under test; wherein the integrated voltage and current source can be reused as a voltage source.

[0027] In some other embodiments of the present disclosure, the equivalent application working condition experimental circuit further includes: a voltage source connected in parallel to both ends of the device under test; wherein the integrated voltage and current source can be reused as a current source.

[0028] The embodiments of the present disclosure may or at least have the following advantages:

[0029] In the embodiment of the present disclosure, an integrated voltage and current power supply is connected at both ends of the device under test, and the integrated voltage and current can generate voltage stress at both ends of the device under test when the device under test is in a blocking state, and generate current stress at both ends of the device under test when the device under test is in a conducting state, while ensuring that the waveform changes of the voltage stress and the current stress are consistent with the waveform changes of the corresponding electrical stress of the device under test in actual application conditions. In this way, the embodiment of the present disclosure can generate all the current and voltage stress waveforms required for the experiment by the same circuit by combining the functions of the voltage source and the current source, with only a small number of components and sequential open-loop logic coordination, simplifying the circuit structure, and helping to reduce the construction and operation costs of the experimental platform, so as to promote the application of the equivalent stress condition experiment of the converter valve, thereby promoting the high-quality and rapid development of the UHV DC field.

[0030] Furthermore, the experimental circuit provided by the embodiment of the present disclosure is modularly configured, that is, multiple groups of modules can be directly cascaded, thereby doubling the voltage and current experimental test range. In this way, the experimental platform can configure the number of modules according to the experimental requirements, and can also increase the number of modules according to its development requirements, with better construction flexibility.

[0031] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 A schematic diagram of a topological structure of an equivalent application working condition experimental circuit provided in some embodiments;

[0034] Figure 2for Figure 1 A schematic diagram of an electric stress waveform generated by the equivalent application working condition experimental circuit shown;

[0035] Figure 3 A schematic diagram of a topological structure of a voltage source in an equivalent application working condition experimental circuit provided in some embodiments;

[0036] Figure 4 A schematic diagram of a topological structure of a current source in an equivalent application working condition experimental circuit provided in some embodiments;

[0037] Figure 5 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0038] Figure 6 A schematic diagram of a topological structure of a single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0039] Figure 7 for Figure 6 A schematic diagram of an electric stress waveform generated by the equivalent application working condition experimental circuit shown;

[0040] Figure 8 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0041] Fig. 9 for Figure 8 A schematic diagram of an electric stress waveform generated by the equivalent application working condition experimental circuit shown;

[0042] Fig.10 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0043] Fig.11 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0044] Fig.12 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0045] Fig.13 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0046] Fig.14 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0047] Fig.15 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0048] Fig.16 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0049] Fig.17 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0050] Fig.18 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0051] Fig.19 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0052] Fig. 20 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0053] Fig.21 A schematic diagram of a topological structure of another single module in another equivalent application working condition experimental circuit provided in some embodiments;

[0054] Fig. 22 A schematic diagram of a topological structure of multiple modules cascaded in another equivalent application working condition experimental circuit provided in some embodiments;

[0055] Fig.23 A schematic diagram of another topological structure of multiple cascaded modules in another equivalent application working condition experimental circuit provided in some embodiments;

[0056] Fig.24 A schematic diagram of a topological structure of a plurality of modules cascaded in another equivalent application working condition experimental circuit provided in some embodiments;

[0057] Fig.25 A schematic diagram of a topological structure of multiple modules connected in parallel in another equivalent application working condition experimental circuit provided in some embodiments;

[0058] Fig.26 A schematic diagram of a topological structure in which multiple modules are connected in series in another equivalent application working condition experimental circuit provided in some embodiments;

[0059] Fig. 27 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0060] Fig.28 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0061] Fig.29 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0062] Fig.30 for Fig.29 A schematic diagram of an electric stress waveform generated by the equivalent application working condition experimental circuit shown;

[0063] Fig.31 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0064] Fig.32 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0065] Fig.33 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0066] Fig.34 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0067] Fig.35 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0068] Fig.36 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0069] Fig.37 for Fig.26 A schematic diagram of an electric stress waveform generated by the equivalent application working condition experimental circuit shown;

[0070] Fig.38 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0071] Fig.39 for Fig.38 A schematic diagram of an electric stress waveform generated by the equivalent application working condition experimental circuit shown;

[0072] Fig.40 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0073] Fig.41A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0074] Fig.42 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0075] Fig.43 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0076] Fig.44 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0077] Fig.45 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0078] Fig.46 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments;

[0079] Fig.47 A schematic diagram of the topological structure of another equivalent application working condition experimental circuit provided in some embodiments. DETAILED DESCRIPTION

[0080] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0081] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0082] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0083] It should be understood that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0084] It should be understood that the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0085] The equivalent application condition experiment uses special circuits and methods to generate stress conditions similar to the application conditions of the device under test or the core components of the device under test, so as to verify the functional integrity and long-term reliability of the device under test in actual operation. At present, in the example where the device under test is a power semiconductor device or a converter valve group component, the converter valve equivalent application condition experiment circuit can be used to conduct experiments to verify the power semiconductor device or the converter valve group component.

[0086] Equivalent application condition experiments are an important means to verify the functional integrity and long-term reliability of power semiconductor devices or converter valve group components in actual operation.

[0087] In some embodiments, components of the equivalent application working condition experimental circuit are shown as follows: Figure 1 , where the voltage source, current source and the device under test are in parallel topology. During the equivalent application condition experiment, the control instructions of the voltage source, current source and the device under test cooperate with each other in timing. The voltage source applies voltage stress to the device under test when it is in the blocking state, and the current source applies current stress to the device under test when it is in the conducting state. The electrical stress waveforms generated by the two are as follows: Figure 2 As shown in , it is used for the actual operating conditions of the equivalent converter valve.

[0088] For example, Figure 3 The topological structure of a voltage source in an equivalent application working condition experimental circuit is shown in FIG. The voltage stress output by the voltage source comes from the voltage of capacitor C1, wherein capacitor C1 and inductor L1 and inductor L2 form two pairs of series resonant circuits, and semi-controlled power devices V3 and V5 are used to start the above two sets of series resonant circuits respectively, and semi-controlled power device V2 is used to control the DC voltage source u DCTo restore the voltage of capacitor C1, the semi-controlled power device V4 is used to provide a negative voltage stress output channel when the voltage of capacitor C1 is negative. Figure 2 During the time period from t1 to t2 shown, the voltage of capacitor C1 is positive; at time t2, the semi-controlled power device V3 is turned on, the inductor L1 and the capacitor C1 are in series resonance, the current of the inductor L1 is sinusoidally increased first and then decreased, and the voltage of the capacitor C1 decreases from positive to negative; at time t3, the current of the inductor L1 crosses zero in the negative direction, the semi-controlled power device V3 is automatically turned off, the voltage of the capacitor C1 reaches the minimum value, the semi-controlled power device V4 is turned on, and the voltage source outputs a negative voltage stress; at time t4, the semi-controlled power device V5 is turned on, the capacitor C1 and the inductor L2 are in series resonance, the current of the inductor L2 is sinusoidally increased first and then decreased, and the voltage of the inductor and capacitor C1 increases from negative to positive; at time t5, the semi-controlled power device V3 is turned on, and the voltage source outputs a positive voltage stress; at time t6, the semi-controlled power device V2 is turned on, and the DC voltage source u DC1 The capacitor C1 is charged through the inductor L2, and the voltage of the capacitor C1 is finally equal to the DC voltage source u DC1 The voltage is consistent.

[0089] For example, Figure 4 The topological structure of the current source in an equivalent application working condition experimental circuit is shown in FIG. The working principle of the current source is that two groups of six-pulse bridge converters are operated in pairs to generate a constant current on the inductor L3. Figure 2 In the time period from t1 to t3 shown, the bridge arm where the device under test and the semi-controlled power device V1 are located is in the commutation conduction period, the current of the inductor L3 passes through the above device, and the current source outputs current stress to the device under test. Among them, the semi-controlled power device V1 is an isolation valve that prevents the voltage stress of the voltage source from affecting the operation of the current source, and is triggered and turned on at the same time as the device under test at time t1.

[0090] As mentioned above, the topological structure of the equivalent application condition experimental circuit is complex, the number of power semiconductor devices is large, and the control timing coordination accuracy requirements are high, resulting in high construction and operation costs of the experimental platform. This is not only not conducive to the promotion and development of equivalent stress condition experiments for converter valves, but also raises the research and development and optimization threshold for power semiconductor devices and components for converter valves, which is likely to hinder the high-quality and rapid development of the UHV DC field.

[0091] Based on this, in order to reduce the construction and operation costs of the converter valve equivalent application condition experimental platform, the embodiment of the present disclosure provides a concise equivalent application condition experimental circuit and experimental method, which can generate all the current and voltage stress waveforms required for the experiment by the same circuit by combining the voltage source and current source functions, with only a small number of components and sequential open-loop logic coordination. Furthermore, the experimental circuit provided by the embodiment of the present disclosure is modular, that is, multiple groups of circuit modules can be directly cascaded to achieve a doubling of the voltage and current experimental test range. In this way, the experimental platform can configure the number of modules according to the experimental requirements, and can also increase the number of modules according to its development requirements, with better construction flexibility.

[0092] In some embodiments of the present disclosure, please refer to Figure 5 The equivalent application condition experimental circuit includes: a device under test and an integrated voltage and current power supply. The integrated voltage and current source is coupled to both ends of the device under test and one end is coupled to the reference ground, and is configured to: generate voltage stress at both ends of the device under test when the device under test is in a blocking state; and generate current stress at both ends of the device under test when the device under test is in a conducting state; wherein the waveform changes of the voltage stress and the current stress are consistent with the waveform changes of the corresponding electrical stress of the device under test in actual application conditions.

[0093] Accordingly, some embodiments of the present disclosure further provide an experimental method for an equivalent application working condition experimental circuit, which is used to perform an equivalent application working condition experiment on the equivalent application working condition experimental circuit described in some of the above embodiments. The experimental method includes the following steps S100 and S200.

[0094] S100, when the device under test is in a blocking state, the integrated voltage and current power supply generates voltage stress at both ends of the device under test.

[0095] S200, when the device under test is in a conducting state, the integrated voltage and current power supply generates current stress at both ends of the device under test.

[0096] Here, the waveform changes of voltage stress and current stress are consistent with the waveform changes of the corresponding electrical stress of the device under test in actual application conditions, which means that: the waveform changes of voltage stress and current stress are equivalent to the waveform changes of the corresponding electrical stress of the device under test in actual application conditions, or the two are similar within the target deviation range, or the waveforms of voltage stress and current stress are accelerated degradation stress waveforms of the corresponding electrical stress of the device under test in actual application conditions.

[0097] For example, the voltage stress and the current stress are equivalent electrical stresses or accelerated degradation stresses corresponding to the electrical stresses of the device under test in actual application conditions.

[0098] In the embodiment of the present disclosure, an integrated voltage and current power supply is connected at both ends of the device under test, and the integrated voltage and current can generate voltage stress at both ends of the device under test when the device under test is in a blocking state, and generate current stress at both ends of the device under test when the device under test is in a conducting state, while ensuring that the waveform changes of the voltage stress and the current stress are consistent with the waveform changes of the corresponding electrical stress of the device under test in actual application conditions. In this way, the embodiment of the present disclosure can generate all the current and voltage stress waveforms required for the experiment by the same circuit by combining the functions of the voltage source and the current source, with only a small number of components and sequential open-loop logic coordination, simplifying the circuit structure, and helping to reduce the construction and operation costs of the experimental platform, so as to promote the application of the equivalent stress condition experiment of the converter valve, thereby promoting the high-quality and rapid development of the UHV DC field.

[0099] In some embodiments of the present disclosure, please refer to Figure 6 The integrated voltage and current source includes at least one module, the module includes: a DC voltage source u DC2 , a first inductor L4, a second inductor L5, a first capacitor C3, a first half-controlled power device V7, a second half-controlled power device V8 and a reverse resistance fully-controlled device V6. Among them, one end of the first inductor L4 is coupled to the cathode of the reverse resistance fully-controlled device V6, and the other end is the output end of the module. One end of the second inductor L5 is coupled to one end of the first capacitor C3 and the cathode of the reverse resistance fully-controlled device V6, and the other end is coupled to the cathode of the first half-controlled power device V7 and the cathode of the second half-controlled power device V8. The other end of the first capacitor C3, the anode of the reverse resistance fully-controlled device V6 and the anode of the first half-controlled power device V7 are all connected to the DC voltage source u DC2 The anode of the second half-controlled power device V8 is connected to the DC voltage source u DC2 The positive coupling of

[0100] In some embodiments of the present disclosure, please continue to refer to Figure 6 The module of the integrated voltage and current source further includes a second capacitor C4. The second capacitor C4 is connected to the DC voltage source u DC2 In this way, when the DC voltage source u DC2 When the DC voltage source is not ideal, the second capacitor C4 and the non-ideal DC voltage source u DC2 When coupled in parallel, it can be used as a voltage stabilizing capacitor to provide a stable input DC voltage for the circuit.

[0101] In some embodiments of the present disclosure, a half-controlled power device refers to a power semiconductor device and combination that can only be turned on but not turned off by a gate. For example, the first half-controlled power device V7 and / or the second half-controlled power device V8 include but are not limited to thyristors.

[0102] In some embodiments of the present disclosure, a reverse resistance fully controlled device refers to: a power semiconductor device and combination that has a bidirectional voltage blocking capability and can be turned on and off by gate control.

[0103] By way of example, the reverse-blocking fully-controlled device V6 includes, but is not limited to: a gate turn-off thyristor, an integrated gate-commutated thyristor, a reverse-blocking insulated-gate bipolar thyristor (IGBT), a power semiconductor device with a diode in series and used to block a unidirectional voltage and control the switch through a gate, a metal oxide semiconductor field effect thyristor (MOSFET) in series with a common source / emitter, an insulated-gate bipolar thyristor in series with a common source / emitter, a metal oxide semiconductor field effect thyristor in series with a common drain / collector, an insulated-gate bipolar thyristor in series with a common drain / collector, an insulated-gate bipolar thyristor in series with a common collector and an anti-parallel diode, or an insulated-gate bipolar thyristor in series with a common emitter and an anti-parallel diode.

[0104] In some embodiments of the present disclosure, the first inductor L4 and / or the second inductor L5 include but are not limited to: a single inductor consisting of a fixed inductor or an adjustable inductor, or a plurality of inductors consisting of either a fixed inductor or an adjustable inductor connected in series or parallel.

[0105] In some embodiments of the present disclosure, the first capacitor C3 and / or the second capacitor C4 include but are not limited to: a single capacitor or a plurality of groups of capacitors connected in series and parallel.

[0106] In some embodiments of the present disclosure, the reference ground is a DC voltage source u DC2 of the negative electrode.

[0107] From the above, the equivalent working condition application experimental circuit provided by the embodiment of the present disclosure adopts a modular setting, that is: its integrated voltage and current source can adopt a single module or a plurality of modules directly cascaded to achieve doubling of the voltage and current experimental range.

[0108] In some embodiments, the structure of the integrated voltage and current source is as follows: Figure 6 As shown in , a single module is used. Figure 6 After the integrated voltage and current source shown in the figure is subjected to an equivalent application condition experiment, the integrated voltage and current source composed of the single module can generate the following on the device under test: Figure 7 The voltage and current stress waveforms are shown.

[0109] For example, please combine Figure 6 and Figure 7 Understand, in having Figure 6In the equivalent application condition experimental circuit of the integrated voltage and current source shown, the process of the integrated voltage and current source generating voltage and current stress in its experimental method can be specifically referred to the relevant descriptions at the following moments.

[0110] Before time t1, the device under test is in a blocking state, and the first capacitor C3 applies a positive voltage stress to the device under test.

[0111] At time t1, the device under test is in the on state, the first capacitor C3 and the first inductor L4 are in series resonance, the voltage of the first capacitor C3 drops, and the current of the first inductor L4 increases and starts to apply current stress to the device under test.

[0112] At time t2, the voltage of the first capacitor C3 drops to zero, the current of the first inductor L4 rises to a maximum value, and the reverse resistance fully controlled device V6 is turned on.

[0113] During the time period from time t2 to time t3, the first inductor L4 continues current through the device under test and the reverse resistance fully controlled device V6, and the current of the first inductor L4 and the current stress of the device under test remain approximately unchanged.

[0114] At time t3, the duration of the current stress of the device under test reaches the equivalent condition, the reverse resistance fully controlled device V6 is actively turned off, the first inductor L4 continues to resonate in series with the first capacitor C3 through the device under test, the voltage of the first capacitor C3 increases negatively, and the current of the first inductor L4 and the current stress of the device under test decrease sinusoidally.

[0115] At time t4, the current of the first inductor L4 and the current stress of the device under test drop to zero, and the device under test resumes the blocking state. At this time, the voltage of the first capacitor C3 drops to the minimum value and outputs a continuous negative voltage stress for the device under test.

[0116] At time t5, the first half-controlled power device V7 is turned on, the second inductor L5 and the first capacitor C3 are resonated in series, the first half-controlled power device V7 resumes the blocking state when the current of the second inductor L5 drops through zero, and the voltage of the first capacitor C3 and the voltage stress of the device under test turn from negative to positive during the resonance process.

[0117] At time t6, the second half-controlled power device V8 is turned on, and the DC voltage source u DC2 The first capacitor C3 is charged by the second inductor L5 to supplement the loss. The voltage of the first capacitor C3 is finally equal to the DC voltage source u DC2 The voltage is consistent to enable repeated testing in the next cycle.

[0118] The time points from time t1 to time t6 mentioned above only represent the order of occurrence, and the time intervals between the various moments can be adjusted according to experimental requirements and circuit parameters.

[0119] In some other embodiments of the present disclosure, please refer to Figure 8 The integrated voltage and current source includes at least one module, the module includes: a DC voltage source u DC2 , a first inductor L4, a second inductor L5, a first capacitor C3, a first reverse resistance fully controlled device V7, a half-controlled power device V8 and a second reverse resistance fully controlled device V6. Among them, one end of the first inductor L4 is coupled to the cathode of the second reverse resistance fully controlled device V6, and the other end is the output end of the module. One end of the second inductor L5 is coupled to one end of the first capacitor C3 and the cathode of the second reverse resistance fully controlled device V6, and the other end is coupled to the cathode of the first reverse resistance fully controlled device V7 and the cathode of the half-controlled power device V8. The other end of the first capacitor C3, the anode of the second reverse resistance fully controlled device V6 and the anode of the first reverse resistance fully controlled device V7 are all connected to the DC voltage source u DC2 The anode of the semi-controlled power device V8 is connected to the DC voltage source u DC2 The positive coupling of

[0120] Compared to Figure 6 The integrated voltage and current source shown in the embodiment of the present disclosure uses a first reverse resistance fully controlled device V7 to replace the first half-controlled power device V7. Figure 8 After the integrated voltage and current source shown in the figure is subjected to an equivalent application condition experiment, the integrated voltage and current source composed of the single module can generate the following on the device under test: Fig. 9 The voltage and current stress waveforms are shown.

[0121] Before time t1, the device under test is in a blocking state, and the first capacitor C3 applies a positive voltage stress to the device under test.

[0122] At time t1, the device under test is in the on state, the first capacitor C3 and the first inductor L4 are in series resonance, the voltage of the first capacitor C3 drops, and the current of the first inductor L4 increases and starts to apply current stress to the device under test.

[0123] At time t2, the voltage of the first capacitor C3 drops to zero, the current of the first inductor L4 rises to a maximum value, and the second reverse resistance fully controlled device V6 is turned on.

[0124] During the time period from time t2 to time t3, the first inductor L4 continues current through the device under test and the second reverse resistance fully controlled device V6, and the current of the first inductor L4 and the current stress of the device under test remain approximately unchanged.

[0125] At time t3, the duration of the current stress of the device under test reaches the equivalent condition, the second reverse resistance fully controlled device V6 is actively turned off, the first inductor L4 continues to resonate in series with the first capacitor C3 through the device under test, the voltage of the first capacitor C3 increases negatively, and the current of the first inductor L4 and the current stress of the device under test decrease sinusoidally.

[0126] At time t4, the current of the first inductor L4 and the current stress of the device under test drop to zero, and the device under test resumes the blocking state. At this time, the voltage of the first capacitor C3 drops to the minimum value and outputs a continuous negative voltage stress for the device under test.

[0127] At time t5, the first reverse resistance fully controlled device V7 is turned on, the second inductor L5 and the first capacitor C3 are in series resonance, the current of the second inductor L5 decreases in a sinusoidal shape, and the voltage of the first capacitor C3 increases in a sinusoidal shape.

[0128] At time t6, the current of the second inductor L5 crosses zero in the negative direction, the voltage of the first capacitor C3 and the positive voltage stress of the device under test reach the maximum value, and the first reverse resistance full-controlled device V7 is actively turned off to cut off the series resonance of the branch.

[0129] At time t7, the second half-controlled power device V8 is turned on, and the DC voltage source u DC2 The first capacitor C3 is charged by the second inductor L5 to supplement the loss. The voltage of the first capacitor C3 is finally equal to the DC voltage source u DC2 The voltage is consistent to enable repeated testing in the next cycle.

[0130] The time points from time t1 to time t7 mentioned above only represent the order of occurrence, and the time intervals between the various moments can be adjusted according to experimental requirements and circuit parameters.

[0131] In some other embodiments of the present disclosure, please refer to Figure 10 to Figure 12 The integrated voltage and current source includes at least one module, the module includes: a DC voltage source u DC2 , a first inductor L4, a second inductor L5, a first capacitor C3, a half-controlled power device V7, a fully-controlled switch V8, and a reverse-resistance fully-controlled device V6. Among them, one end of the first inductor L4 is coupled to the cathode of the reverse-resistance fully-controlled device V6, and the other end is the output end of the module. One end of the second inductor L5 is coupled to one end of the first capacitor C3 and the cathode of the reverse-resistance fully-controlled device V6, and the other end is coupled to the cathode of the half-controlled power device V7. The other end of the first capacitor C3, the anode of the reverse-resistance fully-controlled device V6, and the anode of the half-controlled power device V7 are all connected to the DC voltage source u DC2 The negative pole of the .

[0132] Alternatively, if Fig.10 As shown in FIG. 1 , one end of the fully controlled switch V8 is connected to the DC voltage source uDC2 The other end is coupled to the cathode of the half-controlled power device V7.

[0133] Alternatively, if Fig.11 As shown in FIG. 1 , one end of the fully controlled switch V8 is connected to the DC voltage source u DC2 The other end is coupled to the negative electrode of the half-controlled power device V7.

[0134] Alternatively, if Fig.12 As shown in FIG, the fully controlled switch includes: a DC voltage source u connected in series DC2 The first fully controlled switch V between the positive electrode and the cathode of the half-controlled power device V7 81 , and connected in series to a DC voltage source u DC2 The second fully controlled switch V between the negative electrode and the anode of the half-controlled power device V7 82 .

[0135] Compared to Figure 6 The integrated voltage and current source shown in the embodiment of the present disclosure adopts a fully controlled switch V8 to replace the second half-controlled power device V8. The fully controlled switch V8 refers to: an element that can control the conduction and blocking of the branch by a signal, including but not limited to relays, contactors and fully controlled power semiconductor devices. Figure 10 to Figure 12 After the integrated voltage and current source shown in the figure is subjected to an equivalent application condition experiment, the voltage and current stress waveform that the integrated voltage and current source composed of the single module can generate on the device under test can be referred to Fig. 9 understand.

[0136] Before time t1, the device under test is in a blocking state, and the first capacitor C3 applies a positive voltage stress to the device under test.

[0137] At time t1, the device under test is in the on state, the first capacitor C3 and the first inductor L4 are in series resonance, the voltage of the first capacitor C3 drops, and the current of the first inductor L4 increases and starts to apply current stress to the device under test.

[0138] At time t2, the voltage of the first capacitor C3 drops to zero, the current of the first inductor L4 rises to a maximum value, and the reverse resistance fully controlled device V6 is turned on.

[0139] During the time period from time t2 to time t3, the first inductor L4 continues current through the device under test and the reverse resistance fully controlled device V6, and the current of the first inductor L4 and the current stress of the device under test remain approximately unchanged.

[0140] At time t3, the duration of the current stress of the device under test reaches the equivalent condition, the reverse resistance fully controlled device V6 is actively turned off, the first inductor L4 continues to resonate in series with the first capacitor C3 through the device under test, the voltage of the first capacitor C3 increases negatively, and the current of the first inductor L4 and the current stress of the device under test decrease sinusoidally.

[0141] At time t4, the current of the first inductor L4 and the current stress of the device under test drop to zero, and the device under test resumes the blocking state. At this time, the voltage of the first capacitor C3 drops to the minimum value and outputs a continuous negative voltage stress for the device under test.

[0142] At time t5, the half-controlled power device V7 is turned on, the second inductor L5 and the first capacitor C3 are in series resonance, and the half-controlled power device V7 resumes the blocking state when the current of the second inductor L5 drops through zero. The voltage of the first capacitor C3 and the voltage stress of the device under test turn from negative to positive during the resonance process and reach the maximum value at time t6.

[0143] At time t7, the fully controlled switch V8 is turned on, and the DC voltage source u DC2 The first capacitor C3 is charged by the second inductor L5 to supplement the loss. The voltage of the first capacitor C3 is finally equal to the DC voltage source u DC2 The voltage of the battery is consistent, and the fully controlled switch V8 disconnects the charging branch before time t1 of the next experimental cycle to have the ability to repeat the test in the next cycle.

[0144] In some other embodiments of the present disclosure, please refer to Figure 13 to Figure 15 The integrated voltage and current source includes at least one module, the module includes: a DC voltage source u DC2 , a first inductor L4, a second inductor L5, a first capacitor C3, a first reverse resistance fully controlled device V7, a fully controlled switch V8 and a second reverse resistance fully controlled device V6. Among them, one end of the first inductor L4 is coupled to the cathode of the second reverse resistance fully controlled device V6, and the other end is the output end of the module. One end of the second inductor L5 is coupled to one end of the first capacitor C3 and the cathode of the second reverse resistance fully controlled device V6, and the other end is coupled to the cathode of the first reverse resistance fully controlled device V7. The other end of the first capacitor C3, the anode of the second reverse resistance fully controlled device V6 and the anode of the first reverse resistance fully controlled device V7 are all connected to the DC voltage source u DC2 The negative pole of the .

[0145] Alternatively, if Fig.13 As shown in FIG. 1 , one end of the fully controlled switch V8 is connected to the DC voltage source u DC2 The other end is coupled to the positive electrode of the first reverse resistance fully controlled device V7.

[0146] Alternatively, if Fig.14 As shown in FIG. 1 , one end of the fully controlled switch V8 is connected to the DC voltage source uDC2 The other end is coupled to the negative electrode of the first reverse resistance fully controlled device V7.

[0147] Alternatively, if Fig.15 As shown in FIG, the fully controlled switch includes: a DC voltage source u connected in series DC2 The first fully controlled switch V between the positive electrode and the cathode of the first reverse resistance fully controlled device V7 81 , and connected in series to a DC voltage source u DC2 The second fully controlled switch V between the negative electrode of and the anode of the first reverse resistance fully controlled device V7 82 .

[0148] Compared to Figure 6 The integrated voltage and current source shown in the embodiment of the present disclosure uses a first reverse resistance fully controlled device V7 to replace the first half-controlled power device V7, and uses a fully controlled switch V8 to replace the second half-controlled power device V8. Figure 13 to Figure 15 After the integrated voltage and current source shown in the figure is subjected to an equivalent application condition experiment, the voltage and current stress waveform that the integrated voltage and current source composed of the single module can generate on the device under test can be referred to Fig. 9 understand.

[0149] Before time t1, the device under test is in a blocking state, and the first capacitor C3 applies a positive voltage stress to the device under test.

[0150] At time t1, the device under test is in the on state, the first capacitor C3 and the first inductor L4 are in series resonance, the voltage of the first capacitor C3 drops, and the current of the first inductor L4 increases and starts to apply current stress to the device under test.

[0151] At time t2, the voltage of the first capacitor C3 drops to zero, the current of the first inductor L4 rises to a maximum value, and the second reverse resistance fully controlled device V6 is turned on.

[0152] During the time period from time t2 to time t3, the first inductor L4 continues current through the device under test and the second reverse resistance fully controlled device V6, and the current of the first inductor L4 and the current stress of the device under test remain approximately unchanged.

[0153] At time t3, the duration of the current stress of the device under test reaches the equivalent condition, the second reverse resistance fully controlled device V6 is actively turned off, the first inductor L4 continues to resonate in series with the first capacitor C3 through the device under test, the voltage of the first capacitor C3 increases negatively, and the current of the first inductor L4 and the current stress of the device under test decrease sinusoidally.

[0154] At time t4, the current of the first inductor L4 and the current stress of the device under test drop to zero, and the device under test resumes the blocking state. At this time, the voltage of the first capacitor C3 drops to the minimum value and outputs a continuous negative voltage stress for the device under test.

[0155] At time t5, the first reverse resistance fully controlled power device V7 is turned on, the second inductor L5 and the first capacitor C3 are in series resonance, the current of the second inductor L5 decreases sinusoidally, and the voltage of the first capacitor C3 increases sinusoidally.

[0156] At time t6, the current of the second inductor L5 crosses zero in the negative direction, the voltage of the first capacitor C3 and the positive voltage stress of the device under test reach the maximum value, and the first reverse resistance full-controlled device V7 is actively turned off to cut off the series resonance of the branch.

[0157] At time t7, the fully controlled switch V8 is turned on, and the DC voltage source u DC2 The first capacitor C3 is charged by the second inductor L5 to supplement the loss. The voltage of the first capacitor C3 is finally equal to the DC voltage source u DC2 The voltage of the battery is consistent, and the fully controlled switch V8 disconnects the charging branch before time t1 of the next experimental cycle to have the ability to repeat the test in the next cycle.

[0158] In some other embodiments of the present disclosure, please refer to Figure 16 to Figure 18 The integrated voltage and current source includes at least one module, the module includes: a DC voltage source u DC2 , a first inductor L4, a second inductor L5, a first capacitor C3, a current limiting resistor R1, a half-controlled power device V7, a fully-controlled switch V8, and a reverse-resistance fully-controlled device V6. Among them, one end of the first inductor L4 is coupled to the cathode of the reverse-resistance fully-controlled device V6, and the other end is the output end of the module. One end of the second inductor L5 is coupled to one end of the first capacitor C3, the cathode of the reverse-resistance fully-controlled device V6, and one end of the current limiting resistor R1, and the other end is coupled to the cathode of the half-controlled power device V7. The other end of the current limiting resistor R1 is connected to the DC voltage source u DC2 The other end of the first capacitor C3, the anode of the reverse resistance full-controlled device V6 and the anode of the half-controlled power device V7 are all connected to the DC voltage source u DC2 The negative pole of the .

[0159] Alternatively, if Fig.16 As shown in FIG. 1 , the fully controlled switch V8 is connected in series between the second inductor L5 and the current limiting resistor R1 .

[0160] Alternatively, if Fig.17 As shown in FIG. 1 , the fully controlled switch V8 is connected in series to the DC voltage source u DC2 Between the negative electrode and the anode of the half-controlled power device V7.

[0161] Alternatively, if Fig.18 As shown in FIG, the fully controlled switch includes: a first fully controlled switch V connected in series between the second inductor L5 and the current limiting resistor R1 81 , and connected in series to a DC voltage source u DC2 The second fully controlled switch V between the negative electrode and the anode of the half-controlled power device V7 82 .

[0162] Compared to Figure 6 The integrated voltage and current source shown in the embodiment of the present disclosure adds a current limiting resistor R1, and adopts a fully controlled switch V8 to replace the second half-controlled power device V8. The first capacitor C3 can be charged under the control of the fully controlled switch V8 through the current limiting resistor R1 to replace the charging branch of the second inductor L5. The embodiment of the present disclosure adopts a resistor-capacitor charging method, which can ensure that the voltage stress increase of the device under test is more stable and less oscillating and less generating spikes during the voltage recovery process of the first capacitor C3. Accordingly, the embodiment of the present disclosure adopts a fully controlled switch V8, which can not only avoid the problem of being unable to reliably restore the blocking state due to the lack of zero-crossing points generated by current oscillation when using a half-controlled power device, but also effectively reduce the risk of the half-controlled power device re-conducting and introducing a DC voltage source to destroy the working state when the voltage of the first capacitor C3 drops sharply due to series resonance.

[0163] Based on Figure 16 to Figure 18 After the integrated voltage and current source shown in the figure is subjected to an equivalent application condition experiment, the voltage and current stress waveform that the integrated voltage and current source composed of the single module can generate on the device under test can be referred to Fig. 9 understand.

[0164] Before time t1, the device under test is in a blocking state, and the first capacitor C3 applies a positive voltage stress to the device under test.

[0165] At time t1, the device under test is in the on state, the first capacitor C3 and the first inductor L4 are in series resonance, the voltage of the first capacitor C3 drops, and the current of the first inductor L4 increases and starts to apply current stress to the device under test.

[0166] At time t2, the voltage of the first capacitor C3 drops to zero, the current of the first inductor L4 rises to a maximum value, and the reverse resistance fully controlled device V6 is turned on.

[0167] During the time period from time t2 to time t3, the first inductor L4 continues current through the device under test and the reverse resistance fully controlled device V6, and the current of the first inductor L4 and the current stress of the device under test remain approximately unchanged.

[0168] At time t3, the duration of the current stress of the device under test reaches the equivalent condition, the reverse resistance fully controlled device V6 is actively turned off, the first inductor L4 continues to resonate in series with the first capacitor C3 through the device under test, the voltage of the first capacitor C3 increases negatively, and the current of the first inductor L4 and the current stress of the device under test decrease sinusoidally.

[0169] At time t4, the current of the first inductor L4 and the current stress of the device under test drop to zero, and the device under test resumes the blocking state. At this time, the voltage of the first capacitor C3 drops to the minimum value and outputs a continuous negative voltage stress for the device under test.

[0170] At time t5, the half-controlled power device V7 is turned on, the second inductor L5 and the first capacitor C3 are in series resonance, and the half-controlled power device V7 resumes the blocking state when the current of the second inductor L5 drops through zero. The voltage of the first capacitor C3 and the voltage stress of the device under test turn from negative to positive during the resonance process and reach the maximum value at time t6.

[0171] At time t7, the fully controlled switch V8 is turned on, and the DC voltage source u DC2 The first capacitor C3 is charged through the current limiting resistor R1 to supplement the loss. The voltage of the first capacitor C3 is finally equal to the DC voltage source u DC2 The voltage of the battery is consistent, and the fully controlled switch V8 disconnects the charging branch before time t1 of the next experimental cycle to have the ability to repeat the test in the next cycle.

[0172] In some other embodiments of the present disclosure, please refer to Figure 19 to Figure 21 The integrated voltage and current source includes at least one module, the module includes: a DC voltage source u DC2 , a first inductor L4, a second inductor L5, a first capacitor C3, a current limiting resistor R1, a first reverse resistance fully controlled device V7, a fully controlled switch V8 and a second reverse resistance fully controlled device V6. Among them, one end of the first inductor L4 is coupled to the cathode of the second reverse resistance fully controlled device V6, and the other end is the output end of the module. One end of the second inductor L5 is coupled to one end of the first capacitor C3, the cathode of the second reverse resistance fully controlled device V6 and one end of the current limiting resistor R1, and the other end is coupled to the cathode of the first reverse resistance fully controlled device V7. The other end of the current limiting resistor R1 is connected to the DC voltage source u DC2 The other end of the first capacitor C3, the anode of the second reverse resistance fully controlled device V6 and the anode of the first reverse resistance fully controlled device V7 are all connected to the DC voltage source u DC2 The negative pole of the .

[0173] Alternatively, if Fig.19 As shown in FIG. 1 , the fully controlled switch V8 is connected in series between the second inductor L5 and the current limiting resistor R1 .

[0174] Alternatively, if Fig. 20As shown in FIG. 1 , the fully controlled switch V8 is connected in series to the DC voltage source u DC2 between the negative electrode and the anode of the first reverse resistance fully controlled device V7.

[0175] Alternatively, if Fig.21 As shown in FIG, the fully controlled switch includes: a first fully controlled switch V connected in series between the second inductor L5 and the current limiting resistor R1 81 , and connected in series to a DC voltage source u DC2 The second fully controlled switch V between the negative electrode of and the anode of the first reverse resistance fully controlled device V7 82 .

[0176] Compared to Figure 16 to Figure 18 The integrated voltage and current source shown in the embodiment of the present disclosure uses the first reverse resistance fully controlled device V7 to replace the half-controlled power device V7. Figure 19 to Figure 21 After the integrated voltage and current source shown in the figure is subjected to an equivalent application condition experiment, the voltage and current stress waveform that the integrated voltage and current source composed of the single module can generate on the device under test can be referred to Fig. 9 understand.

[0177] Before time t1, the device under test is in a blocking state, and the first capacitor C3 applies a positive voltage stress to the device under test.

[0178] At time t1, the device under test is in the on state, the first capacitor C3 and the first inductor L4 are in series resonance, the voltage of the first capacitor C3 drops, and the current of the first inductor L4 increases and starts to apply current stress to the device under test.

[0179] At time t2, the voltage of the first capacitor C3 drops to zero, the current of the first inductor L4 rises to a maximum value, and the second reverse resistance fully controlled device V6 is turned on.

[0180] During the time period from time t2 to time t3, the first inductor L4 continues current through the device under test and the second reverse resistance fully controlled device V6, and the current of the first inductor L4 and the current stress of the device under test remain approximately unchanged.

[0181] At time t3, the duration of the current stress of the device under test reaches the equivalent condition, the second reverse resistance fully controlled device V6 is actively turned off, the first inductor L4 continues to resonate in series with the first capacitor C3 through the device under test, the voltage of the first capacitor C3 increases negatively, and the current of the first inductor L4 and the current stress of the device under test decrease sinusoidally.

[0182] At time t4, the current of the first inductor L4 and the current stress of the device under test drop to zero, and the device under test resumes the blocking state. At this time, the voltage of the first capacitor C3 drops to the minimum value and outputs a continuous negative voltage stress for the device under test.

[0183] At time t5, the first reverse resistance fully controlled device V7 is turned on, the second inductor L5 and the first capacitor C3 are in series resonance, the current of the second inductor L5 decreases in a sinusoidal shape, and the voltage of the first capacitor C3 increases in a sinusoidal shape.

[0184] At time t6, the current of the second inductor L5 crosses zero in the negative direction, the voltage of the first capacitor C3 and the positive voltage stress of the device under test reach the maximum value, and the first reverse resistance full-controlled device V7 is actively turned off to cut off the series resonance of the branch.

[0185] At time t7, the fully controlled switch V8 is turned on, and the DC voltage source u DC2 The first capacitor C3 is charged through the current limiting resistor R1 to supplement the loss. The voltage of the first capacitor C3 is finally equal to the DC voltage source u DC2 The voltage of the battery is consistent, and the fully controlled switch V8 disconnects the charging branch before time t1 of the next experimental cycle to have the ability to repeat the test in the next cycle.

[0186] It is worth mentioning that when the integrated voltage and current source uses multiple groups of modules directly cascaded, the range of electrical stress output by the converter valve equivalent application condition experimental circuit to the device under test can be effectively expanded. The following embodiments of the present disclosure exemplarily give some possible implementation methods of the integrated voltage and current source multiple groups of modules cascaded, but are not limited to this.

[0187] Implementation method 1: Fig. 22 As shown in , multiple modules are connected in parallel; wherein the ground terminals of each module connected to the reference ground are coupled to each other, and the output terminals of each module are coupled to each other. In this way, the ground terminals of each module connected to the reference ground can be coupled to each other and can serve as the total reference ground terminal of the integrated voltage and current source, and the output terminals of each module can be coupled to each other and can serve as the total output terminal of the integrated voltage and current source, so that the output current stress of each module can be applied to the device under test after superposition.

[0188] Implementation method 2: Fig.23 As shown in , multiple modules are connected in series; wherein the output end of the latter module is coupled to the ground end of the previous module connected to the reference ground. In this way, the ground end of the first module connected to the reference ground can be used as the ground end of the integrated voltage and current source, and the output end of the last module can be used as the output end of the integrated voltage and current source, so that the output current stress of each module can be applied to the device under test after superposition.

[0189] Implementation method three: Fig.24As shown in , multiple modules are connected in series and in parallel; wherein, multiple modules are connected in series to form multiple groups of series experimental circuits U with the same output voltage, and multiple groups of series experimental circuits U are connected in parallel to the two ends of the device under test. In this way, the grounding ends of each series experimental circuit U connected to the reference ground can be coupled to each other and can be used as the grounding end of the integrated voltage and current source, and the output ends of each series experimental circuit U can be coupled to each other and can be used as the output end of the integrated voltage and current source, so that the voltage stress and current stress output by each module can be correspondingly superimposed and then applied to the device under test, so as to simultaneously achieve the expansion of voltage stress and current stress.

[0190] In addition, it can be understood that to match the cascade mode of multiple groups of modules in the integrated voltage and current source, the DC voltage power supply or other external electronic components can be adaptively adjusted. For example, when multiple groups of modules are connected in series, the DC voltage power supply can use a voltage doubling rectifier power supply. The embodiments of the present disclosure do not make specific limitations on this.

[0191] In order to more clearly illustrate the equivalent application working condition experimental circuit and experimental method provided by the embodiment of the present disclosure, Fig.25 and Fig.26 Two different multi-module cascade topologies are illustrated. Figure 6 Taking the module structure shown in as an example, the experimental method of the equivalent effect application working condition experimental circuit is illustrated.

[0192] In some embodiments, Fig.25 As shown, the integrated voltage and current source uses two modules in parallel to expand the testable current stress. Module 1 includes a first inductor L 4_1 , the second inductor L 5_1 , the first capacitor C 3_1 , the second capacitor C 4_1 , the first half-controlled power device V 7_1 , the second half-controlled power device V 8_1 And reverse resistance fully controlled device V 6_1 Module 2 includes a first inductor L 4_2 , the second inductor L 5_2 , the first capacitor C 3_2 , the second capacitor C 4_2 , the first half-controlled power device V 7_2 , the second half-controlled power device V 8_2 And reverse resistance fully controlled device V 6_2 Moreover, module 1 and module 2 can share the same DC voltage source u DC3 .

[0193] For example, the second capacitor C of module 1 4_1 And the second capacitor C of module 2 4_2 With DC voltage source u DC3 The second half-controlled power device V of module 1 is connected in parallel.8_1 The anode and the second half-controlled power device V of module two 8_2 The anodes of DC3 The positive electrode of module 1 is coupled to the second half-controlled power device V 8_1 The cathode of module 2 and the second half-controlled power device V 8_2 The cathode of module 1 and the first half-controlled power device V 7_1 The cathode and the first half-controlled power device V of module 2 7_2 The cathodes of the first half-controlled power device V of module 1 are coupled to each other. 7_1 The anode of module 2 and the first half-controlled power device V 7_1 Anode and DC power supply u DC3 The negative electrodes are coupled to each other.

[0194] The second inductor L of module 1 5_1 One end of the first half-controlled power device V 7_1 The cathode of the capacitor C is connected to the other end of the capacitor C 3_1 One end and the reverse resistance fully controlled device V 6_1 The cathode of module 1 is coupled. 3_1 The other end and its reverse resistance fully controlled device V 6_1 The anodes are connected to the DC power supply u DC3 Similarly, the second inductor L of module 2 5_2 One end of the first half-controlled power device V 7_2 The cathode of the capacitor C is connected to the other end of the capacitor C 3_2 One end and its reverse resistance fully controlled device V 6_2 The cathode of module 2 is coupled. 3_2 The other end and its reverse resistance fully controlled device V 6_2 The anodes of the DC3 The negative pole of the .

[0195] The first inductor L of module 1 4_1 One end of the reverse resistance fully controlled device V 6_1 The cathode of module 2 is coupled to the first inductor L 4_2 One end of the reverse resistance fully controlled device V 6_2 The first inductor L of module 1 is coupled to the cathode of 4_1 The other end is connected to the first inductor L of module 2 4_2 The other end of the integrated voltage and current source can be coupled to the output end of the integrated voltage and current source, and the reference ground connected to the integrated voltage and current source is the DC power supply u DC3 of the negative electrode.

[0196] Understandably, Fig.25The integrated voltage and current source shown is composed of two single modules connected in parallel. The voltage and current stress waveform that can be generated on the device under test can also be referred to Figure 7 The voltage and current stress waveforms shown in the figure are only the current stress amplitudes compared to Figure 6 The single module shown would be taller.

[0197] For example, in a case with Fig.25 In the equivalent application condition experimental circuit of the integrated voltage and current source shown, the process of the integrated voltage and current source generating voltage and current stress in its experimental method can be specifically referred to the relevant descriptions at the following moments.

[0198] Before time t1, the device under test is in a blocking state, and the first capacitor C of module 1 3_1 and the first capacitor C of module 2 3_2 Apply the same positive voltage stress to the device under test.

[0199] At time t1, the device under test is in the on state, and the first capacitor C of module 1 3_1 With its first inductor L 4_1 Series resonance, the first capacitor C of module 2 3_2 With its first inductor L 4_2 Series resonance, the first capacitor C of module 1 3_1 and the first capacitor C of module 2 3_2 The voltage drop of module 1 is 4_1 and the first inductor L of module 2 4_2 Since both resonant currents pass through the device under test, the current stress of the device under test is the superposition of the above two currents.

[0200] At time t2, the first capacitor C of module 1 3_1 and the first capacitor C of module 2 3_2 The voltage of module 1 drops to zero, and the first inductor L 4_1 and the first inductor L of module 2 4_2 The current rises to the maximum value. The reverse resistance fully controlled device V 6_1 And the reverse resistance fully controlled device V of module 2 6_2 Conducting at the same time.

[0201] During the time period from time t2 to time t3, the first inductor L of module 1 4_1 and the first inductor L of module 2 4_2 Through the device under test and the corresponding reverse resistance fully controlled device V 6_1 and V 6_2 The first inductor L of module 1 4_1 Current, the first inductor L of module 2 4_2The current and thus the current stress on the device under test remain approximately constant.

[0202] At t3, the current stress duration of the device under test reaches the equivalent condition, and the reverse resistance fully controlled device V 6_1 And the reverse resistance fully controlled device V of module 2 6_2 Active shutdown, the first inductor L of module 1 4_1 Through the device under test and its first capacitor C 3_1 Continuing with series resonance, the first inductor L of module 2 4_2 Through the device under test and its first capacitor C 3_2 Continuing with series resonance, the first capacitor C of module 1 3_1 Voltage and the first capacitor C of module 2 3_2 The voltage increases negatively, and the first inductor L of module 1 4_1 Current, the first inductor L of module 2 4_2 The current and thus the current stress of the device under test decreases sinusoidally.

[0203] At time t4, the first inductor L of module 1 4_1 Current, the first inductor L of module 2 4_2 The current and the current stress of the device under test drop to zero, and the device under test returns to the blocking state. At this time, the first capacitor C 3_1 and the first capacitor C of module 2 3_2 The voltage drops to the minimum value and outputs a continuous negative voltage stress to the device under test.

[0204] At time t5, the first half-controlled power device V 7_1 and the first half-controlled power device V 7_2 The second inductor L of module 1 is turned on. 5_1 With its first capacitor C 3_1 Series resonance, the second inductor L of module 2 5_2 With its first capacitor C 3_2 Series resonance, first half-controlled power device V of module 1 7_1 and the first half-controlled power device V 7_2 In the corresponding second inductor L 5_1 and L 5_2 When the current drops to zero, the blocking state is restored. The first capacitor C of module 1 3_1 Voltage, the first capacitor C of module 2 3_2 The voltage and the voltage stress of the device under test change from negative to positive during the resonance process.

[0205] At time t6, the second half-controlled power device V 8_1 and the second half-controlled power device V 8_2 On, DC voltage source uDC3 Through the second inductor L 5_1 and L 5_2 is the corresponding first capacitor C 3_1 and C 3_2 Charge to replenish the loss consumption, so that the first capacitor C of module 1 3_1 Voltage, the first capacitor C of module 2 3_2 The voltage is finally equal to the DC voltage source u DC3 The voltage is consistent to enable repeated testing in the next cycle.

[0206] The time points from time t1 to time t6 mentioned above only represent the order of occurrence, and the time intervals between the various moments can be adjusted according to experimental requirements and circuit parameters.

[0207] In other embodiments, Fig.26 As shown, the integrated voltage and current source uses two modules connected in series to expand the testable voltage stress. Module 1 includes a first inductor L 4_3 , the second inductor L 5_3 , the first capacitor C 3_3 , the second capacitor C 4_3 , the first half-controlled power device V 7_3 , the second half-controlled power device V 8_3 And reverse resistance fully controlled device V 6_3 Module 2 includes a first inductor L 4_4 , the second inductor L 5_4 , the first capacitor C 3_4 , the second capacitor C 4_4 , the first half-controlled power device V 7_4 , the second half-controlled power device V 8_4 And reverse resistance fully controlled device V 6_4 Furthermore, module 1 and module 2 may share the same DC voltage source, which is, for example, a voltage-doubling rectifier power supply. The disclosed embodiment does not limit the internal circuit structure of the voltage-doubling rectifier power supply. Fig.26 This is only a schematic expression, that is, the voltage doubler rectifier power supply can have different Fig.26 The structure shown in .

[0208] Here, when the voltage doubler rectifier power supply is in a no-load state, the voltage doubler rectifier power supply can be connected to the first capacitor C of module 1. 4_3 and the first capacitor C of module 2 4_4 The amplitude is twice that of the AC voltage source u AC Peak DC voltage.

[0209] For example, the first capacitor C of module 2 4_4 The negative electrode is coupled to the low voltage end of the voltage doubler rectifier power supply, and the first capacitor C 4_3The positive electrode is coupled to the high voltage end of the voltage doubler rectifier power supply, and the first capacitor C 4_3 The negative electrode and the first capacitor C of module 2 4_4 Positive coupling, the first capacitor C of module 2 4_4 The negative electrode can be used as an integrated voltage and current source to connect to the ground terminal of the reference ground.

[0210] The second half-controlled power device V 8_3 The anode and its first capacitor C 4_3 Positive coupling, the second half-controlled power device V of module 2 8_4 The anode and its first capacitor C 4_4 Positive coupling, the second half-controlled power device V of module 1 8_3 Cathode, the second half-controlled power device V of module 2 8_4 Cathode, the first half-controlled power device V of module one 7_3 The cathode and the first half-controlled power device V of module 2 7_4 The cathodes are coupled to each other. The first half-controlled power device V 7_3 Anode, the first half-controlled power device V of module 2 7_4 Anode, first capacitor C of module 1 4_3 The negative electrode and the first capacitor C of module 2 4_4 The negative electrodes are coupled to each other.

[0211] The second inductor L of module 1 5_3 One end and its first half-controlled power device V 7_3 The cathode is coupled, and the other end is connected to the first capacitor C 3_3 One-terminal and reverse resistance fully controlled device V 6_3 The first capacitor C of module 1 is connected to the cathode. 3_3 The other end and its reverse resistance fully controlled device V 6_3 Anode, second capacitor C 4_3 Similarly, the second inductor L of module 2 5_4 One end and its first half-controlled power device V 7_4 The cathode is coupled, and the other end is connected to the first capacitor C 3_4 One-terminal and reverse resistance fully controlled device V 6_4 The cathode is coupled. The first capacitor C of module 2 3_4 The other end and its reverse resistance fully controlled device V 6_4 Anode, second capacitor C 4_4 Negative coupling.

[0212] The first inductor L of module 2 4_4 One end and its reverse resistance fully controlled device V 6_4 The cathode is coupled, and the other end is connected to the reverse resistance fully controlled device V 6_3 Anode coupling. The first inductor L of module 14_3 One end and its reverse resistance fully controlled device V 6_3 The cathode is coupled, and the other end serves as the output end of the integrated voltage-current source.

[0213] Understandably, Fig.26 The integrated voltage and current source shown is composed of two single modules in series. The voltage and current stress waveform that can be generated on the device under test can also be referred to Figure 7 The voltage and current stress waveforms shown in Figure 6 The single module shown would be taller.

[0214] For example, in a case with Fig.26 In the equivalent application condition experimental circuit of the integrated voltage and current source shown, the process of the integrated voltage and current source generating voltage and current stress in its experimental method can be specifically referred to the relevant descriptions at the following moments.

[0215] Before time t1, the device under test is in a blocking state, and the first capacitor C of module 1 3_3 and the first capacitor C of module 2 3_4 The total series voltage applies a positive voltage stress to the device under test.

[0216] At time t1, the device under test is in the on state, and the first capacitor C of module 1 3_3 、The first capacitor C of module 2 3_4 , the first inductor L of module 1 4_3 And the first inductor L of module 2 4_4 Series resonance, the first capacitor C 3_3 and C 3_4 The voltage drop of the first inductor L 4_3 and L 4_4 The current rises and the current stress of the device under test is the series resonant current.

[0217] At time t2, the first capacitor C 3_3 and C 3_4 The total voltage drops to zero, the first inductor L 4_3 and L 4_4 The current rises to the maximum value, and the reverse resistance fully controlled device V 6_3 And the reverse resistance fully controlled device V of module 2 6_4 Conducting at the same time.

[0218] During the time period from t2 to t3, the first inductor L 4_3 and L 4_4 Through the device under test and the corresponding reverse resistance fully controlled device V 6_3 and V 6_4 Freewheeling, the first inductor L of module 1 4_3 Current, the first inductor L of module 24_4 The current and thus the current stress on the device under test remain approximately constant.

[0219] At t3, the current stress duration of the device under test reaches the equivalent condition. 6_3 And the reverse resistance fully controlled device V of module 2 6_4 Active shutdown, the first capacitor C 3_3 and C 3_4 and the first inductor L 4_3 and L 4_4 Continuing with series resonance, the first capacitor C 3_3 and C 3_4 The voltage of module 1 increases negatively, and the first inductor L 4_3 Current, the first inductor L of module 2 4_4 The current and thus the current stress of the device under test decreases sinusoidally.

[0220] At time t4, the first inductor L of module 1 4_3 Current, the first inductor L of module 2 4_4 The current and the current stress of the device under test drop to zero, and the device under test returns to the blocking state. At this time, the first capacitor C 3_3 and C 3_4 The voltage drops to the minimum value and after being connected in series, a continuous negative voltage stress is output to the device under test.

[0221] At time t5, the first half-controlled power device V 7_3 and the first half-controlled power device V 7_4 The second inductor L of module 1 is turned on. 5_3 With its first capacitor C 3_3 Series resonance, the second inductor L of module 2 5_4 With its first capacitor C 3_4 Series resonance, first half-controlled power device V of module 1 7_3 In its second inductor L 5_3 When the current drops to zero, it returns to the blocking state. The first half-controlled power device V 7_4 In its second inductor L 5_4 When the current drops to zero, the blocking state is restored. The first capacitor C of module 1 3_3 Voltage, the first capacitor C of module 2 3_4 The voltage and the voltage stress of the device under test change from negative to positive during the resonance process.

[0222] At time t6, the second half-controlled power device V 8_3 and the second half-controlled power device V 8_4 The second capacitor C of module 1 is turned on. 4_3 Through its second inductor L 5_3The first capacitor C 3_3 Charging, the second capacitor C of module 2 4_4 Through its second inductor L 5_4 The first capacitor C 3_4 To charge and replenish the loss, the first capacitor C of module 1 3_3 Voltage and the second capacitor C 3_4 The voltage finally reaches the first capacitor C of module 2. 4_3 And the second capacitor C 4_4 The voltage is consistent to enable repeated testing in the next cycle.

[0223] The time points from time t1 to time t6 mentioned above only represent the order of occurrence, and the time intervals between the various moments can be adjusted according to experimental requirements and circuit parameters.

[0224] In summary, the equivalent application condition experimental circuit provided by the embodiment of the present disclosure has a simple topological structure, and the number of components is less than that of the existing equivalent application condition experimental circuit, and the construction cost of the required experimental platform is also low. The embodiment of the present disclosure only requires the sequence of the trigger signals of each power semiconductor device to be executed in a timely manner, which can avoid the mutual coordination of the current source and the voltage source. Its control logic is simple. In the example where each power semiconductor element in the circuit adopts a mature thyristor device, the overall operation reliability is high. In addition, in the embodiment of the present disclosure, the DC voltage power supply used for power supply only needs to supplement the capacitor voltage drop caused by the loss, which can eliminate a large amount of reactive power caused by the drag inductance in the current source, and can also avoid a large amount of active power caused by directly charging the negative voltage capacitor, thereby effectively reducing the operating cost and facilitating the long-term equivalent reliability verification experiment. In addition, the equivalent application condition experimental circuit provided by the embodiment of the present disclosure has a high degree of modularization, and the number of modules can be configured according to the experimental requirements, and the number of modules can also be increased according to the development requirements of the converter valve assembly. It has high construction flexibility and can effectively reduce repeated investment.

[0225] It is worth mentioning that, based on the above embodiments, please refer to Fig. 27 and Fig.28 The equivalent application working condition experimental circuit also includes: a current source or a voltage source connected in parallel to both ends of the device under test.

[0226] It can be understood that the integrated voltage and current source mentioned in the aforementioned embodiments of the present disclosure has the functions of both a voltage source and a current source. Therefore, when the equivalent application working condition experimental circuit also includes a current source connected in parallel to both ends of the device under test, the integrated voltage and current source can be reused as a voltage source; when the equivalent application working condition experimental circuit also includes a voltage source connected in parallel to both ends of the device under test, the integrated voltage and current source can be reused as a current source. In other words, the integrated voltage and current source mentioned in the aforementioned embodiments of the present disclosure can be replaced by a single voltage source or a current source, and at the same time cooperate with traditional or new circuits to realize another corresponding function. For the convenience of description, the integrated voltage and current sources in some of the following embodiments are all used Figure 6 The module structure shown is for illustration only, but the integrated voltage and current source can be implemented in various different ways in the aforementioned embodiments.

[0227] From the above, no matter whether the integrated voltage and current source is replaced by a voltage source or a current source alone, or a voltage source or a current source is added in parallel, it is topologically parallel to the device under test, and the control timing of the voltage source, the current source and the device under test cooperate with each other during the experiment. The voltage source applies voltage stress to the device under test when it is in a blocked state, and the current source applies current stress to the device under test when it is in a conducting state.

[0228] In some embodiments, a single module of the integrated voltage and current source is replaced by a voltage source, and the corresponding parallel current source can be implemented in a variety of different ways. For example, the current source connected in parallel outside the integrated voltage and current source includes but is not limited to: a single group of six-pulse bridge current sources, two groups of six-pulse thyristor bridges with inductor current sources, or a fully controlled bridge current source.

[0229] For example, see Fig.29 and Fig.30 , the current source connected in parallel outside the integrated voltage and current source is two groups of six-pulse thyristor bridges to drag inductor current sources. Among them, one group of six-pulse thyristor bridges works in rectification mode, and the other group of thyristor bridges works in inverter mode. The device under test is connected in series with the isolation valve V1 as a bridge arm of the inverter thyristor bridge. The isolation valve V1 plays the role of blocking the grid voltage and preventing current reverse. The DC sides of the two groups of thyristor bridges are connected through the load inductor L3, and the AC sides of the two groups of thyristor bridges are connected to the same AC grid. Energy circulates between the AC grid and the load inductor L3 through the two groups of thyristor bridges. Adjusting the trigger angle can change the load inductor L3 and the average current of the device under test.

[0230] For example, in Fig.29 In the equivalent application condition experimental circuit shown in the figure, the voltage and current stress waveforms generated by the experimental method on the device under test are as follows Fig.30 as shown in .

[0231] Before time t1, the device under test is in a blocking state, and the first capacitor C3 applies a positive voltage stress to the device under test.

[0232] At time t1, the isolation valve V1 and the device under test are in the on state, the first capacitor C3 in the integrated voltage and current source (multiplexed as a voltage source) resonates in series with the first inductor L4, the voltage of the first capacitor C3 drops, the current of the first inductor L4 rises and begins to apply current stress to the device under test. At the same time, the rectifier thyristor bridge in the current source begins to change phase, the current of the isolation valve V1 rises and applies current stress to the device under test. Moreover, in the time period from time t1 to time t6, the current stress of the device under test includes two parts, which come from the integrated voltage and current source (multiplexed as a voltage source) and the current source respectively.

[0233] At time t2, the voltage of the first capacitor C3 drops to zero, the current of the first inductor L4 rises to the maximum value, and the reverse resistance fully controlled device V6 is turned on. In addition, during the time period from time t2 to time t5, the first inductor L4 continues to flow through the device under test and the reverse resistance fully controlled device V6, and the current of the first inductor L4 and the current stress of the device under test remain approximately unchanged.

[0234] At time t3, the current source rectifies the thyristor bridge and completes the phase change, and the current of the current source flows through the device under test. During the time period from time t3 to time t4, the current source is the main source of current stress in the device under test.

[0235] At time t5, the reverse resistance fully controlled device V6 is actively turned off, the first inductor L4 continues to resonate in series with the first capacitor C3 through the device under test, the voltage of the first capacitor C3 increases negatively, and the current of the first inductor L4 and the current stress of the device under test both decrease sinusoidally.

[0236] At time t6, the currents of the isolation valve V1, the first inductor L4 and the device under test drop to zero, the device under test resumes the blocking state, the voltage of the first capacitor C3 drops to the minimum value and outputs a continuous negative voltage stress for the device under test.

[0237] At time t7, the first half-controlled power device V7 is turned on, the second inductor L5 and the first capacitor C3 are in series resonance, the current of the second inductor L5 rises first and then falls sinusoidally, and the voltage of the first capacitor C3 rises sinusoidally.

[0238] At time t8, the current of the second inductor L5 crosses zero in the negative direction, the voltage of the first capacitor C3 and the positive voltage stress of the device under test reach the maximum value, and the first semi-controlled power device V7 automatically resumes blocking, cutting off the series resonance of the branch.

[0239] At time t9, the second half-controlled power device V8 is turned on, and the DC voltage source u DC2The first capacitor C3 is charged by the second inductor L5 to supplement the loss. The voltage of the first capacitor C3 is finally equal to the DC voltage source u DC2 The voltage is consistent to enable repeated testing in the next cycle.

[0240] The time points from time t1 to time t9 mentioned above only represent the order of occurrence, and the time intervals between the various moments can be adjusted according to experimental requirements and circuit parameters.

[0241] For example, see Fig.31 , the current source connected in parallel with the integrated voltage and current source is a single six-pulse bridge current source. The six-pulse thyristor bridge works in the inverter mode, and the isolation valve V1 blocks the grid voltage and prevents the current from reversing. The energy circulates between the load inductor L3 and the AC grid through the six-pulse thyristor bridge. Adjusting the trigger angle can change the load inductor L3 and the average current of the device under test. And, Fig.31 In the equivalent application condition experimental circuit shown in the figure, the voltage and current stress waveforms generated by the experimental method on the device under test can be referred to Fig.30 , and the control timing of the experimental method is the same as the control timing of the two groups of six-pulse thyristor bridges to drag the inductor current source. No further description is given here.

[0242] For example, see Fig.32 , the current source connected in parallel with the integrated voltage and current source is a fully controlled bridge current source. In the fully controlled bridge current source, switches S2, S3 and S5 are inductors L 31 and L 32 Switching the charge and discharge paths, diodes D1, D4 and D6 are inductors L 31 and L 32 Providing a freewheeling path, the isolation valve V1 blocks the grid voltage and prevents current reverse. The energy in the DC power supply u DC1 and inductor L 31 , L 32 By adjusting the action sequence and opening time of each switch, the current stress of the device under test can be changed.

[0243] For example, in Fig.32 In the equivalent application condition experimental circuit shown in the figure, the voltage and current stress waveforms generated by the experimental method on the device under test can be referred to Fig.30 .

[0244] Before time t1, the device under test is in a blocking state, and the first capacitor C3 applies a positive voltage stress to the device under test.

[0245] At time t1, the isolation valve V1 and the device under test are in the on state, the first capacitor C3 in the integrated voltage and current source (multiplexed as a voltage source) is in series resonance with the first inductor L4, the voltage of the first capacitor C3 drops, the current of the first inductor L4 rises and begins to apply current stress to the device under test. At the same time, the switches S2 and S5 in the current source are turned on, and the DC power supply u DC1 Through switch S5, isolation valve V1, device under test and switch S2, the inductor L 32 Charging, inductance L 32 The current rises linearly and applies current stress to the device under test. In addition, during the time period from time t1 to time t6, the current stress of the device under test includes two parts, which come from the integrated voltage and current source (multiplexed as a voltage source) and the current source.

[0246] At time t2, the voltage of the first capacitor C3 drops to zero, the current of the first inductor L4 rises to the maximum value, and the reverse resistance fully controlled device V6 is turned on. In addition, during the time period from time t2 to time t5, the first inductor L4 continues to flow through the device under test and the reverse resistance fully controlled device V6, and the current of the first inductor L4 and the current stress of the device under test remain approximately unchanged.

[0247] At t3, the current stress amplitude of the device under test reaches the experimental requirements, switches S2 and S5 are turned off, and the inductor L 32 The current continues to flow through the diode D6, the isolation valve V1 and the device under test, and the current stress of the device under test remains unchanged.

[0248] At time t3, the current stress time of the device under test reaches the experimental requirements, switches S2 and S3 are turned on, and the DC power supply u DC1 Through switches S2 and S3, inductor L 32 is the inductance L 31 Charging, inductance L 31 The current rises from zero, but at this time the inductor L 32 There is still current on the inductor L 32 The current is greater than the inductance L 31 Part of the current still flows through the isolation valve V1 and the device under test, and the current stress of the device under test decreases linearly.

[0249] At time t5, the reverse resistance fully controlled device V6 is actively turned off, the first inductor L4 continues to resonate in series with the first capacitor C3 through the device under test, the voltage of the first capacitor C3 increases negatively, and the current of the first inductor L4 and the current stress of the device under test both decrease sinusoidally.

[0250] Before time t6, the inductor L 31 The current exceeds the inductance L 32 , inductance L 32The current no longer flows through the isolation valve V1 and the device under test. The isolation valve V1 automatically returns to the blocking state after the current reaches zero. The current stress of the device under test is only the part provided by the voltage source. After that, the switches S2 and S3 are turned off, and the inductor L 31 and inductor L 32 The DC voltage source u is connected to the DC1 Discharge follow-up, inductance L 31 and inductor L 32 After the current drops to zero, diodes D1 and D4 resume blocking.

[0251] At time t6, the currents of the isolation valve V1, the first inductor L4 and the device under test drop to zero, the device under test resumes the blocking state, the voltage of the first capacitor C3 drops to the minimum value and outputs a continuous negative voltage stress for the device under test.

[0252] At time t7, the first half-controlled power device V7 is turned on, the second inductor L5 and the first capacitor C3 are in series resonance, the current of the second inductor L5 rises first and then falls sinusoidally, and the voltage of the first capacitor C3 rises sinusoidally.

[0253] At time t8, the current of the second inductor L5 crosses zero in the negative direction, the voltage of the first capacitor C3 and the positive voltage stress of the device under test reach the maximum value, and the first semi-controlled power device V7 automatically resumes blocking, cutting off the series resonance of the branch.

[0254] At time t9, the second half-controlled power device V8 is turned on, and the DC voltage source u DC2 The first capacitor C3 is charged by the second inductor L5 to supplement the loss. The voltage of the first capacitor C3 is finally equal to the DC voltage source u DC2 The voltage is consistent to enable repeated testing in the next cycle.

[0255] It should be added that, in some embodiments, the integrated voltage and current source can be composed of multiple modules connected in series and reused as a voltage source to expand the experimental voltage output capacity. Accordingly, the current source connected in parallel outside the integrated voltage and current source can refer to the relevant records in some of the aforementioned embodiments, and the control method of the integrated voltage and current source is the same as the control method of the integrated voltage and current source of the aforementioned single module, which will not be described in detail here.

[0256] For example, see Fig.33 The integrated voltage and current source can be formed by connecting multiple modules in series. The current source connected in parallel outside the integrated voltage and current source is two groups of six-pulse thyristor bridge-drag inductor current sources.

[0257] For example, see Fig.34 The integrated voltage and current source can be composed of multiple modules connected in series. The current source connected in parallel outside the integrated voltage and current source is a single group of six-pulse bridge current sources.

[0258] For example, see Fig.35 The integrated voltage and current source can be composed of multiple modules connected in series. The current source connected in parallel with the integrated voltage and current source is a fully controlled bridge current source.

[0259] Similarly, in other embodiments, a single module of the integrated voltage and current source is replaced by a current source, and the corresponding parallel voltage source can be implemented in a variety of different ways. For example, the voltage source connected in parallel with the integrated voltage and current source includes, but is not limited to: a synthetic test voltage source, a DC modular multi-level topology voltage source, an AC modular multi-level topology voltage source, an AC energy modular multi-level topology voltage source, or a multi-level DC link topology voltage source.

[0260] For example, see Fig.36 The voltage source connected in parallel with the integrated voltage and current source is the synthetic test voltage source. The voltage and current stress waveforms generated by the equivalent application working condition experimental circuit on the device under test are as follows: Fig.37 as shown in .

[0261] Before time t1, the device under test, the semi-controlled power device V3 and the isolation valve V1 are in a blocked state, and the parasitic capacitance of the device under test applies a constant positive voltage stress thereto.

[0262] At time t1, the isolation valve V1 and the device under test are turned on, the capacitor C3 of the integrated voltage and current source (multiplexed as a current source) resonates in series with the inductor L4, the voltage of the capacitor C3 drops, the current of the inductor L4 rises and starts to apply current stress to the device under test.

[0263] At time t2, the voltage of capacitor C3 drops to zero, the current of inductor L4 rises to the maximum value, and the reverse resistance fully controlled device V6 is turned on. In addition, during the time period from time t2 to time t3, the inductor L4 continues to flow through the device under test and the reverse resistance fully controlled device V6, and the current of the inductor L4 and the current stress of the device under test remain approximately unchanged.

[0264] At time t3, the duration of the current stress of the device under test reaches the equivalent condition, the reverse resistance fully controlled device V6 is actively turned off, the inductor L4 continues to resonate in series with the capacitor C3 through the device under test, the voltage of the capacitor C3 increases negatively, and the current of the inductor L4 and the current stress of the device under test decrease sinusoidally.

[0265] At time t4, the semi-controlled power device V3 is turned on, the inductor L1 and the capacitor C1 resonate in series, the current of the inductor L1 increases first and then decreases in a sinusoidal shape, the voltage of the capacitor C1 decreases from positive to negative, and the current of the inductor L1 and the current of the current source are superimposed on the device under test.

[0266] During the time period from time t4 to time t5, the current of the inductor L4 and the device under test drops to zero, and the isolation valve V1 automatically returns to the blocking state. At this time, the voltage of the capacitor C3 drops to the minimum negative value.

[0267] At time t5, the current of the inductor L1 crosses zero in a negative direction, the half-controlled power device V3 is automatically turned off, the voltage of the capacitor C1 reaches a minimum value, the half-controlled power device V4 is turned on, and the voltage source outputs a negative voltage stress.

[0268] At time t6, the semi-controlled power device V5 is turned on, the capacitor C1 and the inductor L2 are connected in series to resonate, the current of the inductor L2 increases sinusoidally first and then decreases, and the voltage of the capacitor C1 increases from negative to positive; at the same time, the semi-controlled power device V7 is turned on, the inductor L5 and the capacitor C3 are connected in series to resonate, the current of the inductor L5 increases sinusoidally first and then decreases, and the voltage of the capacitor C3 increases sinusoidally. After the current of the inductor L5 passes through zero, the semi-controlled power device V7 automatically resumes the blocking state, and the voltage of the capacitor C3 reaches the maximum positive value.

[0269] At time t7, the voltage of capacitor C1 crosses zero in the positive direction, the half-controlled power device V3 is turned on, and the voltage source outputs a positive voltage stress.

[0270] At time t8, the half-controlled power device V2 and the half-controlled power device V8 are turned on, and the DC voltage source u DC1 The capacitor C1 is charged through the inductor L2 to supplement the loss consumption, and the DC voltage source u DC2 The capacitor C3 is charged through the inductor L5 to supplement the loss. The final voltage of the capacitor C1 and the capacitor C3 is respectively DC1 and DC voltage source u DC2 The voltage is consistent to enable repeated testing in the next cycle.

[0271] For example, see Fig.38 The voltage source connected in parallel with the integrated voltage and current source is a DC modular multi-level topology voltage source. The DC modular multi-level topology voltage source consists of a DC voltage source u DC1 , commutation equivalent inductor L1 and N modular multi-level converter full-bridge sub-modules SM1-SMN, each full-bridge sub-module includes a support capacitor C SM1 -C SMN The DC port of the full-bridge structure is connected to the support capacitor, and the AC port side of the first-stage full-bridge submodule SM1 is connected to the DC voltage source u DC1 The positive electrode is connected, one side of the AC port of the last full-bridge submodule SMN is connected to one end of the inductor L1, and the AC ports of the remaining full-bridge submodules are connected in series. The other end of the inductor L1 is connected to one end of the device under test, and the other end of the device under test is connected to the reference ground and the DC voltage source u DC1Negative connection. Support capacitor C SM1 -C SMN During operation, the DC voltage source u is modulated and controlled DC1 Take energy, its voltage is the same as the DC voltage source u DC1 By controlling the disconnection combination of each fully controlled power device of the full-bridge submodule, the AC side can output three levels: u DC1 、-u DC1 and 0. By coordinating the output levels of each full-bridge submodule, DC1 to (N+1)u DC1 Any programmable voltage stress waveform can be generated for the device under test within a certain range.

[0272] For example, in Fig.33 In the equivalent application condition experimental circuit shown in the figure, the voltage and current stress waveforms generated by the experimental method on the device under test can be referred to Fig.39 .

[0273] Before time t1, the isolation valve V1 and the device under test are in a blocked state, and the voltage source applies a positive voltage stress to the device under test.

[0274] At time t1, the device under test is turned on, the voltage source outputs zero level, the capacitor C3 of the current source resonates in series with the inductor L4, the voltage of the capacitor C3 drops, the current of the inductor L4 rises and starts to apply current stress to the device under test.

[0275] At time t2, the voltage of capacitor C3 drops to zero, the current of inductor L4 rises to the maximum value, and the reverse resistance fully controlled device V6 is turned on.

[0276] During the time period from time t2 to time t3, the inductor L4 continues to flow through the device under test and the reverse resistance fully controlled device V6, and the current of the inductor L4 and the current stress of the device under test remain approximately unchanged.

[0277] At time t3, the duration of the current stress of the device under test reaches the equivalent condition, the reverse resistance fully controlled device V6 is actively turned off, the inductor L4 continues to resonate in series with the capacitor C3 through the device under test, the voltage of the capacitor C3 increases negatively, and the current of the inductor L4 and the current stress of the device under test decrease sinusoidally.

[0278] At time t4, the current of the inductor L4 and the current stress of the device under test drop to zero, the device under test and the isolation valve V1 resume the blocking state, and at this time, the voltage of the capacitor C3 of the current source drops to the minimum negative value.

[0279] At time t4 and thereafter, the voltage source starts to output corresponding voltage stress to the device under test according to the setting.

[0280] For example, see Fig.40, the voltage source connected in parallel with the integrated voltage and current source is an AC energy modular multi-level topology voltage source. The AC energy modular multi-level topology voltage source consists of an AC voltage source, a commutation equivalent inductor L1, and N multi-level converter full-bridge sub-modules SM1-SMN with diode rectifier bridges; each sub-module includes a support capacitor C SM1 -C SMN , AC isolation transformer T SM1 -T SMN , an uncontrolled rectifier bridge composed of diodes and a full-bridge structure composed of fully controlled power devices. The DC ports of the uncontrolled rectifier bridge and the full-bridge structure are connected to the supporting capacitor, the AC port of the uncontrolled rectifier bridge is connected to the secondary side of the AC isolation transformer, the primary side of the AC isolation transformer is connected to the AC voltage source, the AC isolation transformer provides potential isolation between the sub-modules, and supplies energy to the supporting capacitor through the uncontrolled rectifier bridge during operation. One side of the AC port of the first-level sub-module SM1 is connected to one end of the device under test and the reference ground, one side of the AC port of the last-level sub-module SMN is connected to one end of the inductor L1, the AC ports of the remaining full-bridge sub-modules are connected in series, and the other end of the inductor L1 is connected to one end of the device under test. Support capacitor C SM1 -C SMN The voltage of the AC voltage is the DC voltage u after rectification DC1 By controlling the disconnection combination of each fully controlled power device of the full-bridge submodule, the AC side can output three levels: u DC1 、-u DC1 and 0. By coordinating the output levels of each full-bridge submodule, DC1 To Nu DC1 Any programmable voltage stress waveform can be generated for the device under test within a certain range.

[0281] For example, in Fig.40 In the equivalent application condition experimental circuit shown in the figure, the voltage and current stress waveforms generated by the experimental method on the device under test can be referred to Fig.39 .

[0282] Before time t1, the isolation valve V1 and the device under test are in a blocked state, and the voltage source applies a positive voltage stress to the device under test.

[0283] At time t1, the device under test is turned on, the voltage source outputs zero level, the capacitor C3 of the current source resonates in series with the inductor L4, the voltage of the capacitor C3 drops, the current of the inductor L4 rises and starts to apply current stress to the device under test.

[0284] At time t2, the voltage of capacitor C3 drops to zero, the current of inductor L4 rises to the maximum value, and the reverse resistance fully controlled device V6 is turned on.

[0285] During the time period from time t2 to time t3, the inductor L4 continues to flow through the device under test and the reverse resistance fully controlled device V6, and the current of the inductor L4 and the current stress of the device under test remain approximately unchanged.

[0286] At time t3, the duration of the current stress of the device under test reaches the equivalent condition, the reverse resistance fully controlled device V6 is actively turned off, the inductor L4 continues to resonate in series with the capacitor C3 through the device under test, the voltage of the capacitor C3 increases negatively, and the current of the inductor L4 and the current stress of the device under test decrease sinusoidally.

[0287] At time t4, the current of the inductor L4 and the current stress of the device under test drop to zero, the device under test and the isolation valve V1 resume the blocking state, and at this time, the voltage of the capacitor C3 of the current source drops to the minimum negative value.

[0288] At time t4 and thereafter, the voltage source starts to output corresponding voltage stress to the device under test according to the setting.

[0289] For example, see Fig.41 The voltage source connected in parallel with the integrated voltage and current source is a multi-level DC link topology voltage source. The multi-level DC link topology voltage source consists of an AC voltage source, a commutation equivalent inductor L1, a high-voltage full-bridge structure composed of fully controlled power devices, and N multi-level converter full-bridge sub-modules SM1-SMN with diode rectifier bridges. Each sub-module includes a support capacitor C SM1 -C SMN , AC isolation transformer T SM1 -T SMN , an uncontrolled rectifier bridge composed of diodes and a half-bridge structure composed of fully controlled power devices.

[0290] In each submodule, the DC port of the uncontrolled rectifier bridge and the half-bridge structure is connected to the supporting capacitor, the AC port of the uncontrolled rectifier bridge is connected to the secondary side of the AC isolation transformer, the primary side of the AC isolation transformer is connected to the AC voltage source, and the AC isolation transformer provides potential isolation between the submodules and supplies energy to the supporting capacitor through the uncontrolled rectifier bridge during operation. The low-voltage DC port of the first-level submodule SM1 is connected to the low-voltage side of the high-voltage full-bridge structure, the AC port of the last-level submodule SMN is connected to the high-voltage side of the high-voltage full-bridge structure, and the AC ports of the remaining full-bridge submodules are connected in series with the low-voltage DC ports of the next-level submodules.

[0291] Support capacitor C SM1 -C SMN The voltage of the AC voltage is the DC voltage u after rectification DC1 By controlling the disconnection combination of each fully controlled power device of the full-bridge submodule, the AC side can output two levels: u DC1 and 0, the voltages of all sub-modules are superimposed in series to form a DC voltage input of a high-voltage full-bridge structure.

[0292] The AC side of the high-voltage full-bridge structure can adjust the voltage direction of the total output of the submodules for a second time. The voltage on the AC side can be directly output or inverted to output the voltage on its DC port. One end of the AC side of the high-voltage full-bridge structure is connected to one end of the device under test through inductor L1, and the other end of the AC side of the high-voltage full-bridge structure is connected to the other end of the device under test and the reference ground. Therefore, by coordinating the output levels of each submodule and the state of the high-voltage full-bridge structure, the -Nu DC1 To Nu DC1 Any programmable voltage stress waveform can be generated for the device under test within a certain range.

[0293] For example, in Fig.41 In the equivalent application condition experimental circuit shown in the figure, the voltage and current stress waveforms generated by the experimental method on the device under test can be referred to Fig.39 .

[0294] Before time t1, the isolation valve V1 and the device under test are in a blocked state, and the voltage source applies a positive voltage stress to the device under test.

[0295] At time t1, the device under test is turned on, the voltage source outputs zero level, the capacitor C3 of the current source resonates in series with the inductor L4, the voltage of the capacitor C3 drops, the current of the inductor L4 rises and starts to apply current stress to the device under test.

[0296] At time t2, the voltage of capacitor C3 drops to zero, the current of inductor L4 rises to the maximum value, and the reverse resistance fully controlled device V6 is turned on.

[0297] During the time period from time t2 to time t3, the inductor L4 continues to flow through the device under test and the reverse resistance fully controlled device V6, and the current of the inductor L4 and the current stress of the device under test remain approximately unchanged.

[0298] At time t3, the duration of the current stress of the device under test reaches the equivalent condition, the reverse resistance fully controlled device V6 is actively turned off, the inductor L4 continues to resonate in series with the capacitor C3 through the device under test, the voltage of the capacitor C3 increases negatively, and the current of the inductor L4 and the current stress of the device under test decrease sinusoidally.

[0299] At time t4, the current of the inductor L4 and the current stress of the device under test drop to zero, the device under test and the isolation valve V1 resume the blocking state, and at this time, the voltage of the capacitor C3 of the current source drops to the minimum negative value.

[0300] At time t4 and thereafter, the voltage source starts to output corresponding voltage stress to the device under test according to the setting.

[0301] For example, see Fig.42 The voltage source connected in parallel with the integrated voltage and current source is an AC modular multi-level topology voltage source. The AC modular multi-level topology voltage source consists of a positive and negative DC voltage source uDC1P and u DC1N , Positive and negative pole commutation equivalent inductance L 1P and L 1N , and N multi-level converter submodules SMP1-SMPN and SMN1-SMNN for positive and negative electrodes. Each submodule includes a supporting capacitor C SMP1 -C SMPN , C SMN1 -C SMNN And a bridge structure composed of fully controlled power devices. Among them, the positive and negative DC voltage sources u DC1P and u DC1N After the neutral line is removed, it can be combined into a unified DC voltage source u DC1 The bridge structure of the submodule can be a half-bridge, full-bridge, multi-level half-bridge, multi-level full-bridge and other variants. The topology and working principle of the half-bridge structure will be described in detail later.

[0302] In each submodule, the DC port of the half-bridge structure is connected to the support capacitor. The low-voltage DC port of the positive first-stage submodule SMP1 is connected to the positive inductor L 1P Connect the neutral line to one end of the device under test and the positive DC voltage source u DC1P The low voltage end and the negative DC voltage source u DC1N The AC port of the last-stage positive submodule SMPN is connected to the positive DC voltage source u DC1P The AC port of the negative last-stage submodule SMNN is connected through the positive inductor L 1P Connect the neutral line, the low voltage DC port of the negative first-stage submodule SMN1 and the negative DC voltage source u DC1P The low voltage end of the submodule is connected to the other end of the device under test. The AC ports of the remaining submodules are connected to the low voltage DC ports of the next submodule.

[0303] Positive support capacitor C SMP1 -C SMPN The voltage and DC voltage u DC1P / N remain the same, the negative electrode support capacitor C SMN1 -C SMNN The voltage and DC voltage u DC1N By controlling the disconnection combination of each fully controlled power device of the positive half-bridge submodule, the AC side can output two levels: u DC1P / N and 0. By controlling the disconnection combination of each fully controlled power device of the negative half-bridge sub-module, the AC side can output two levels: u DC1N / N and 0, the voltage of all submodules is connected in series with the DC voltage source and acts on the inductor and the device under test. Therefore, by coordinating the output levels of each submodule, DC1N to u DC1PAny programmable voltage stress waveform can be generated for the device under test within a certain range.

[0304] For example, in Fig.42 In the equivalent application condition experimental circuit shown in the figure, the voltage and current stress waveforms generated by the experimental method on the device under test can be referred to Fig.39 .

[0305] Before time t1, the isolation valve V1 and the device under test are in a blocked state, and the voltage source applies a positive voltage stress to the device under test.

[0306] At time t1, the device under test is turned on, the voltage source outputs zero level, the capacitor C3 of the current source resonates in series with the inductor L4, the voltage of the capacitor C3 drops, the current of the inductor L4 rises and starts to apply current stress to the device under test.

[0307] At time t2, the voltage of capacitor C3 drops to zero, the current of inductor L4 rises to the maximum value, and the reverse resistance fully controlled device V6 is turned on.

[0308] During the time period from time t2 to time t3, the inductor L4 continues to flow through the device under test and the reverse resistance fully controlled device V6, and the current of the inductor L4 and the current stress of the device under test remain approximately unchanged.

[0309] At time t3, the duration of the current stress of the device under test reaches the equivalent condition, the reverse resistance fully controlled device V6 is actively turned off, the inductor L4 continues to resonate in series with the capacitor C3 through the device under test, the voltage of the capacitor C3 increases negatively, and the current of the inductor L4 and the current stress of the device under test decrease sinusoidally.

[0310] At time t4, the current of the inductor L4 and the current stress of the device under test drop to zero, the device under test and the isolation valve V1 resume the blocking state, and at this time, the voltage of the capacitor C3 of the current source drops to the minimum negative value.

[0311] At time t4 and thereafter, the voltage source starts to output corresponding voltage stress to the device under test according to the setting.

[0312] It should be added that, in some embodiments, the integrated voltage and current source can be composed of multiple modules connected in parallel and reused as a current source to expand the experimental current output capacity. Accordingly, the voltage source connected in parallel outside the integrated voltage and current source can refer to the relevant records in some of the aforementioned embodiments, and the control method of the integrated voltage and current source is the same as the control method of the integrated voltage and current source of the aforementioned single module, which will not be described in detail here.

[0313] For example, see Fig.43 The integrated voltage and current source can be formed by connecting multiple modules in parallel. The voltage source connected in parallel with the integrated voltage and current source is a synthetic test voltage source.

[0314] For example, see Fig.44 The integrated voltage and current source can be formed by connecting multiple modules in parallel. The voltage source connected in parallel outside the integrated voltage and current source is a DC modular multi-level topology voltage source.

[0315] For example, see Fig.45 The integrated voltage and current source can be formed by connecting multiple modules in parallel. The voltage source connected in parallel with the integrated voltage and current source is an AC energy-taking modular multi-level topology voltage source.

[0316] For example, see Fig.46 The integrated voltage and current source can be formed by connecting multiple modules in parallel. The voltage source connected in parallel outside the integrated voltage and current source is a multi-level DC link topology voltage source.

[0317] For example, see Fig.47 The integrated voltage and current source can be formed by connecting multiple modules in parallel. The voltage source connected in parallel outside the integrated voltage and current source is an AC modular multi-level topology voltage source.

[0318] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0319] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. An equivalent application working condition experimental circuit, characterized in that: include: Device under test; An integrated voltage and current source is coupled to the two ends of the device under test and one end is coupled to the reference ground, and is configured to: generate voltage stress at the two ends of the device under test when the device under test is in a blocking state; and generate current stress at the two ends of the device under test when the device under test is in a conducting state; wherein the waveform changes of the voltage stress and the current stress both conform to the waveform changes of the corresponding electrical stress of the device under test in actual application conditions.

2. The equivalent application working condition experimental circuit according to claim 1 is characterized in that: The integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a first half-controlled power device, a second half-controlled power device and a reverse resistance fully controlled device; wherein, One end of the first inductor is coupled to the cathode of the reverse resistance fully controlled device, and the other end is the output end of the module; One end of the second inductor is coupled to one end of the first capacitor and the cathode of the reverse resistance fully-controlled device, and the other end is coupled to the cathode of the first half-controlled power device and the cathode of the second half-controlled power device; the other end of the first capacitor, the anode of the reverse resistance fully-controlled device and the anode of the first half-controlled power device are all coupled to the negative electrode of the DC voltage source; the anode of the second half-controlled power device is coupled to the positive electrode of the DC voltage source.

3. The equivalent application working condition experimental circuit according to claim 2 is characterized in that: The module also includes a second capacitor; the second capacitor is coupled in parallel with the DC voltage source.

4. The equivalent application working condition experimental circuit according to claim 3 is characterized in that: The first capacitor and / or the second capacitor includes: a single capacitor or a plurality of capacitors connected in series and parallel.

5. The equivalent application working condition experimental circuit according to claim 1 is characterized in that: The integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a first reverse resistance fully controlled device, a half-controlled power device and a second reverse resistance fully controlled device; wherein, One end of the first inductor is coupled to the cathode of the second reverse resistance fully controlled device, and the other end is the output end of the module; One end of the second inductor is coupled to one end of the first capacitor and the cathode of the second reverse resistance fully-controlled device, and the other end is coupled to the cathode of the first reverse resistance fully-controlled device and the cathode of the half-controlled power device; the other end of the first capacitor, the anode of the second reverse resistance fully-controlled device and the anode of the first reverse resistance fully-controlled device are all coupled to the negative electrode of the DC voltage source; the anode of the half-controlled power device is coupled to the positive electrode of the DC voltage source.

6. The equivalent application working condition experimental circuit according to claim 1 is characterized in that: The integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a half-controlled power device, a fully-controlled switch and a reverse resistance fully-controlled device; wherein, One end of the first inductor is coupled to the cathode of the reverse resistance fully controlled device, and the other end is the output end of the module; One end of the second inductor is coupled to one end of the first capacitor and the cathode of the reverse resistance fully controlled device, and the other end is coupled to the cathode of the half-controlled power device; the other end of the first capacitor, the anode of the reverse resistance fully controlled device and the anode of the half-controlled power device are all coupled to the negative electrode of the DC voltage source; One end of the fully-controlled switch is coupled to the positive pole of the DC voltage source, and the other end is coupled to the cathode of the half-controlled power device; or, one end of the fully-controlled switch is coupled to the negative pole of the DC voltage source, and the other end is coupled to the anode of the half-controlled power device; or, the fully-controlled switch includes: a first fully-controlled switch connected in series between the positive pole of the DC voltage source and the cathode of the half-controlled power device, and a second fully-controlled switch connected in series between the negative pole of the DC voltage source and the anode of the half-controlled power device.

7. The equivalent application working condition experimental circuit according to claim 1 is characterized in that: The integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a first reverse resistance fully controlled device, a fully controlled switch and a second reverse resistance fully controlled device; wherein, One end of the first inductor is coupled to the cathode of the second reverse resistance fully controlled device, and the other end is the output end of the module; One end of the second inductor is coupled to one end of the first capacitor and the cathode of the second reverse resistance fully-controlled device, and the other end is coupled to the cathode of the first reverse resistance fully-controlled device; the other end of the first capacitor, the anode of the second reverse resistance fully-controlled device and the anode of the first reverse resistance fully-controlled device are all coupled to the negative electrode of the DC voltage source; One end of the fully-controlled switch is coupled to the positive electrode of the DC voltage source, and the other end is coupled to the cathode of the first reverse-resistance fully-controlled device; or, one end of the fully-controlled switch is coupled to the negative electrode of the DC voltage source, and the other end is coupled to the anode of the first reverse-resistance fully-controlled device; or, the fully-controlled switch includes: a first fully-controlled switch connected in series between the positive electrode of the DC voltage source and the cathode of the first reverse-resistance fully-controlled device, and a second fully-controlled switch connected in series between the negative electrode of the DC voltage source and the anode of the first reverse-resistance fully-controlled device.

8. The equivalent application working condition experimental circuit according to claim 1 is characterized in that: The integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a current limiting resistor, a half-controlled power device, a fully controlled switch and a reverse resistance fully controlled device; wherein, One end of the first inductor is coupled to the cathode of the reverse resistance fully controlled device, and the other end is the output end of the module; One end of the second inductor is coupled to one end of the first capacitor, the cathode of the reverse resistance fully controlled device and one end of the current limiting resistor, and the other end is coupled to the cathode of the half-controlled power device; the other end of the current limiting resistor is coupled to the positive electrode of the DC voltage source; the other end of the first capacitor, the anode of the reverse resistance fully controlled device and the anode of the half-controlled power device are all coupled to the negative electrode of the DC voltage source; The fully-controlled switch is connected in series between the second inductor and the current-limiting resistor; or, the fully-controlled switch is connected in series between the negative electrode of the DC voltage source and the anode of the half-controlled power device; or, the fully-controlled switch includes: a first fully-controlled switch connected in series between the second inductor and the current-limiting resistor, and a second fully-controlled switch between the negative electrode of the DC voltage source and the anode of the half-controlled power device.

9. The equivalent application working condition experimental circuit according to claim 1 is characterized in that: The integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a current limiting resistor, a first reverse resistance fully controlled device, a fully controlled switch and a second reverse resistance fully controlled device; wherein, One end of the first inductor is coupled to the cathode of the second reverse resistance fully controlled device, and the other end is the output end of the module; One end of the second inductor is coupled to one end of the first capacitor, the cathode of the second reverse resistance fully controlled device and one end of the current limiting resistor, and the other end is coupled to the cathode of the first reverse resistance fully controlled device; the other end of the current limiting resistor is coupled to the positive electrode of the DC voltage source; the other end of the first capacitor, the anode of the second reverse resistance fully controlled device and the anode of the first reverse resistance fully controlled device are all coupled to the negative electrode of the DC voltage source; The fully-controlled switch is connected in series between the second inductor and the current-limiting resistor; or, the fully-controlled switch is connected in series between the negative electrode of the DC voltage source and the anode of the first reverse-resistance fully-controlled device; or, the fully-controlled switch includes: a first fully-controlled switch connected in series between the second inductor and the current-limiting resistor, and a second fully-controlled switch between the negative electrode of the DC voltage source and the anode of the first reverse-resistance fully-controlled device.

10. The equivalent application working condition experimental circuit according to any one of claims 2 to 9, characterized in that: The reference ground is the negative electrode of the DC voltage source.

11. The equivalent application working condition experimental circuit according to any one of claims 2 to 9, characterized in that: The integrated voltage and current source includes a plurality of modules; the implementation method of the integrated voltage and current source includes any one of the following: In the first embodiment, a plurality of the modules are connected in parallel; wherein the ground terminals of the modules connected to the reference ground are coupled to each other, and the output terminals of the modules are coupled to each other; Embodiment 2: A plurality of the modules are connected in series; wherein the output end of the module of the next stage is coupled to the ground end of the module of the previous stage connected to the reference ground; and the output end of the module of the last stage is the output end of the integrated voltage and current source; In the third implementation mode, a plurality of the modules are connected in series and in parallel; wherein, the plurality of the modules are connected in series to form a plurality of series experimental circuits with the same output voltage, and the plurality of series experimental circuits are connected in parallel to both ends of the device under test.

12. The equivalent application working condition experimental circuit according to claim 1, characterized in that: Also includes: a current source connected in parallel to both ends of the device under test; The integrated voltage and current source is multiplexed into a voltage source; Optionally, the current source includes: a single group of six-pulse bridge current sources, two groups of six-pulse thyristor bridge-drag inductor current sources or a fully controlled bridge current source.

13. The equivalent application working condition experimental circuit according to claim 1, characterized in that: Also includes: a voltage source connected in parallel to both ends of the device under test; The integrated voltage and current source is multiplexed into a current source; Optionally, the voltage source includes: a synthetic test voltage source, a DC modular multi-level topology voltage source, an AC modular multi-level topology voltage source, an AC energy-taking modular multi-level topology voltage source or a multi-level DC link topology voltage source.

14. An experimental method for an equivalent application working condition experimental circuit, characterized in that: Applicable to the equivalent application working condition experimental circuit according to any one of claims 1 to 13, the experimental method comprising: When the device under test is in a blocking state, the voltage stress is generated at both ends of the device under test by the integrated voltage and current source; When the device under test is in a conducting state, the integrated voltage and current source generates the current stress at both ends of the device under test; The waveform changes of the voltage stress and the current stress are consistent with the waveform changes of the corresponding electrical stress of the device under test in actual application conditions.

15. The experimental method of the equivalent application working condition experimental circuit according to claim 14, characterized in that: The equivalent application working condition experimental circuit also includes: a current source connected in parallel to both ends of the device under test; wherein the integrated voltage and current source can be reused as a voltage source.

16. The experimental method of the equivalent application working condition experimental circuit according to claim 14, characterized in that: The equivalent application working condition experimental circuit also includes: a voltage source connected in parallel to both ends of the device under test; wherein the integrated voltage and current source can be reused as a current source.

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