Chip power consumption test method, device, equipment and medium

Abstract

The invention relates to the technical field of chip testing, and discloses a chip power consumption testing method and device, equipment and a medium, and the method comprises the steps: obtaining a first abstraction layer corresponding to a first circuit of a to-be-tested chip; reading and writing a plurality of types of to-be-tested objects of the first abstraction layer through a register abstraction layer tool of a general verification method to obtain an actual access result corresponding to each type of to-be-tested object; comparing each actual access result with the expected access result of the corresponding type, and judging whether the to-be-tested object of each type meets a first preset condition or not; if not, modifying a first abstraction layer corresponding to the first circuit; iterating the power consumption test of the to-be-tested chip until each type of to-be-tested object of the updated first abstraction layer meets a first preset condition; and determining power consumption data of the chip to be tested according to the convergence access result set. Therefore, the overall test cost is reduced, and the economic benefit of chip development is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a chip power consumption testing method, device, equipment and medium. Background Art

[0002] In the integrated circuit design process, chip power consumption simulation test is a key link, which can predict and analyze chip power consumption before manufacturing to optimize design, reduce power consumption and improve energy efficiency. Existing tests are difficult to cover the full operating range of the chip under normal and peak working conditions. The amount of calculation is huge, which takes a lot of time and resources. Power consumption simulation needs to comprehensively consider the energy efficiency of the entire system, including factors such as power management and low-power design. Summary of the invention

[0003] In view of this, the present invention provides a chip power consumption testing method, device, equipment and medium to solve the problem of how to efficiently test chip power consumption.

[0004] In a first aspect, the present invention provides a method for testing chip power consumption, which is applied to a simulation test platform and includes:

[0005] Acquire a first abstraction layer corresponding to a first circuit of the chip to be tested, wherein the first abstraction layer includes multiple types of objects to be tested;

[0006] Read and write the multiple types of objects to be tested in the first abstract layer through a universal verification method register abstract layer tool to obtain actual access results corresponding to each type of object to be tested;

[0007] Compare each of the above actual access results with the expected access results of the corresponding type to determine whether each type of the object to be tested meets the first preset condition, where the first preset condition is that the expected access result is less than or equal to the corresponding actual access result;

[0008] If not, obtaining a first target set of objects to be tested through all the objects to be tested that do not meet the first preset condition, and modifying the first abstraction layer corresponding to the first circuit according to the first target set of objects to be tested to obtain an updated first abstraction layer;

[0009] The updated first abstract layer is read and written by the register abstract layer tool of the general verification method to obtain the actual access result corresponding to the updated first abstract layer, and the power consumption test of the chip under test is iterated until each type of the object under test of the updated first abstract layer meets the first preset condition, and a convergent access result set is obtained, wherein the convergent access result set includes: the actual access result corresponding to each type of the object under test that meets the first preset condition;

[0010] According to the converged access result set, the power consumption data of the chip to be tested is determined.

[0011] The present invention provides a chip power consumption testing method, which has the following advantages:

[0012] By using the verification method register abstraction layer tool to read and write the above multiple types of objects under test of the above first abstraction layer, the test process of different types of objects under test is simplified and the verification efficiency is improved. By iterating the power consumption test process of the chip under test and comparing the actual access results with the expected access results, the power consumption performance of the chip under test can be accurately identified and corrected, thereby ensuring the reliability of the test results. Automatic screening and modification of objects under test that do not meet the preset conditions reduces the need for manual intervention and improves test efficiency. Dynamically adjusting the abstraction layer according to the actual access results can respond to the state changes of the chip under test in a timely manner and adapt to different test scenarios and requirements. By converging the access result set, the power consumption performance of the chip under test under different conditions can be comprehensively evaluated, providing data support for subsequent design and optimization. The optimized test process reduces the time and resource investment of repeated testing, thereby reducing the overall test cost and improving the economic benefits of chip development.

[0013] In an optional implementation manner, obtaining a first abstraction layer corresponding to a first circuit of a chip to be tested includes:

[0014] Obtaining the netlist data of the chip under test;

[0015] Divide the overall circuit of the chip under test according to the netlist data to obtain the first circuit, where the first circuit is one of the multiple partial circuits divided from the overall circuit;

[0016] The first abstract layer is defined in the register abstract layer tool of the general verification method, and a mapping relationship between the lines and registers in the first circuit and the multiple types of objects to be tested is established to obtain the first abstract layer corresponding to the first circuit.

[0017] The method provided in this embodiment can systematically divide the overall circuit by processing the netlist data, so as to more clearly understand the structure and function of the circuit. By defining the first abstract layer in the general verification method register abstract layer tool and establishing a mapping relationship between the line and register and the object to be tested, the accurate identification and operation of the object to be tested is ensured, and the pertinence of the test is improved. The defined first abstract layer provides a basis for subsequent verification, can simplify the verification process, and provide effective data support for subsequent iterations and optimizations.

[0018] In an optional implementation, the overall circuit of the chip under test is divided according to the netlist data to obtain the first circuit, including:

[0019] Convert the acquired netlist data into a unified data format;

[0020] Determine the component list and connection information of the overall circuit according to the netlist data;

[0021] According to the component list and the connection information, as well as the second preset condition, the overall circuit is divided into a plurality of circuit partitions;

[0022] Use a circuit simulation tool to independently simulate each partition to obtain functional requirement information and performance indicator information of each of the above circuit partitions;

[0023] According to the expected functional requirement information and the expected performance indicator information, determine whether the functions of each of the above partitions are complete;

[0024] If yes, determining the type of each circuit partition according to the functional requirement information and performance indicator information of each circuit partition;

[0025] A circuit partition corresponding to a target type is selected from the circuit partitions of multiple different types as the first circuit.

[0026] The method provided in this embodiment converts netlist data into a unified data format, which is convenient for subsequent analysis and operation. According to the components and connection information, as well as the second preset condition, the overall circuit is divided into multiple circuit partitions, making the management and testing of complex circuits more accurate and concise. By independently simulating each circuit partition, the function and performance of each partition can be deeply analyzed to obtain detailed functional requirement information and performance index information. By judging whether the function of each partition is complete, the cost of subsequent debugging and modification is reduced. According to the functional requirements and performance indicators, the type of each circuit partition is determined, which is convenient for classification management in subsequent design and testing to improve efficiency. Selecting a partition of the target type from different types of circuit partitions as the first circuit makes the selection process more targeted and can better meet specific functional requirements. Through the combination of the above steps, comprehensive optimization of circuit testing can be achieved, the accuracy and effectiveness of the overall test can be improved, and the quality and performance of the final chip can be ensured to meet the standards.

[0027] In an optional implementation, modifying the first abstraction layer corresponding to the first circuit according to the first target set of objects to be tested to obtain an updated first abstraction layer includes:

[0028] According to the first target set of objects to be tested, determining a second circuit corresponding to the first target set of objects to be tested;

[0029] A second abstraction layer corresponding to the second circuit is obtained as the updated first abstraction layer, wherein the second abstraction layer includes a plurality of types of updated objects to be tested, and the first objects to be tested have the same number and type as the updated objects to be tested.

[0030] The method provided in this embodiment ensures that the updated abstract layer can accurately reflect the new test requirements and enhance the relevance of the test by making the first target set of objects to be tested correspond to the second circuit. The updated first abstract layer and the second abstract layer are consistent in the number and types of objects to be tested. This consistency helps to simplify the test process and reduce potential errors and confusion. The ability to flexibly adjust the abstract layer according to different sets of objects to be tested enhances the adaptability of the circuit design and enables it to better meet diverse test requirements. Through this process, the accuracy, efficiency and flexibility of circuit design and testing can be improved, providing support for improving the overall chip quality and performance.

[0031] In an optional implementation, determining the power consumption data of the chip under test according to the converged access result set includes:

[0032] Determine the actual coverage rate corresponding to the low power consumption signal and the power consumption management function according to the actual access result corresponding to each type of the object to be tested that meets the first preset condition and the third preset condition;

[0033] Determine the actual power consumption of the low power consumption signal according to the flip ratio, static power consumption and flip power consumption of the low power consumption signal;

[0034] The actual coverage and the actual power consumption are used as power consumption data of the chip under test.

[0035] The method provided in this embodiment effectively evaluates the power consumption performance of the chip to be tested, ensuring that the actual performance of the low-power signal can be accurately analyzed during the design verification phase. By combining the actual access results, coverage, and power consumption parameters, the energy consumption characteristics of the chip under different working conditions can be more fully understood. This method not only improves the accuracy of power consumption data, but also provides a valuable basis for subsequent optimization design, thereby ultimately enhancing the energy efficiency and market competitiveness of the chip.

[0036] In an optional implementation, reading and writing the multiple types of objects to be tested of the first abstract layer through the universal verification method register abstract layer tool to obtain actual access results corresponding to each type of object to be tested includes:

[0037] Establishing a link between the first abstraction layer and the front- and back-door access interfaces of the general verification method register abstraction layer tool;

[0038] The test cases are input into the first abstract layer through the front- and back-door access interfaces, and the actual access results corresponding to each type of the object to be tested generated by the first abstract layer are collected.

[0039] The method provided in this embodiment can more accurately evaluate the power consumption performance of the chip under test in actual applications by analyzing the actual access results corresponding to each type of object under test and combining preset conditions. The effectiveness of the low-power signal and the power management function is calculated according to the actual coverage to ensure that the key power paths can be identified and optimized during the design process and improve the overall power management capability. By calculating the flip ratio, static power consumption and flip power consumption of the low-power signal, a basis is provided for subsequent optimization design. Through systematic power consumption analysis, the cost and time of later modifications can be reduced. A quantitative basis is provided for the realization of the power management function to meet the needs of different application scenarios. Through this process, the accuracy and efficiency of the power consumption evaluation of the chip under test can be significantly improved.

[0040] In an optional implementation, after inputting the test case to the first abstraction layer through the front and back door access interfaces, the method further includes:

[0041] According to the above test cases, the above expected access results of each type are generated through the above general verification method register abstraction layer tool.

[0042] The method provided in this embodiment can ensure that the output of the test case is consistent with the design expectation through the expected access result generated by the general verification method register abstraction layer tool, thereby improving the accuracy of the test process.

[0043] In a second aspect, the present invention provides a chip power consumption test device, which is applied to a simulation test platform and includes:

[0044] An acquisition module, used for acquiring a first abstraction layer corresponding to a first circuit of the chip to be tested, wherein the first abstraction layer includes multiple types of objects to be tested;

[0045] A test module, used for reading and writing the above-mentioned multiple types of objects to be tested of the above-mentioned first abstract layer through a universal verification method register abstract layer tool, and obtaining actual access results corresponding to each type of object to be tested;

[0046] A judgment module, used to compare each of the above actual access results with the expected access results of the corresponding type, and judge whether each type of the object to be tested meets a first preset condition, wherein the first preset condition is that the expected access result is less than or equal to the corresponding actual access result;

[0047] A modification module, for, if not, obtaining a first target set of objects to be tested through all the objects to be tested that do not meet the first preset condition, and modifying the first abstraction layer corresponding to the first circuit according to the first target set of objects to be tested to obtain an updated first abstraction layer;

[0048] An iteration module is used to read and write the updated first abstract layer through the general verification method register abstract layer tool to obtain the actual access result corresponding to the updated first abstract layer, and iterate the power consumption test of the chip to be tested until each type of the object to be tested of the updated first abstract layer meets the first preset condition, and obtain a convergent access result set, wherein the convergent access result set includes: the actual access result corresponding to each type of the object to be tested that meets the first preset condition;

[0049] The determination module is used to determine the power consumption data of the chip to be tested according to the converged access result set.

[0050] The chip power consumption test device provided by the present invention has the following advantages:

[0051] By using the universal verification method register abstraction layer tool to read and write the above multiple types of objects under test of the above first abstraction layer, the test process of different types of objects under test is simplified and the verification efficiency is improved. By iterating the power consumption test process of the chip under test and comparing the actual access results with the expected access results, the power consumption performance of the chip under test can be accurately identified and corrected, thereby ensuring the reliability of the test results. Automatic screening and modification of objects under test that do not meet the preset conditions reduces the need for manual intervention and improves test efficiency. Dynamically adjusting the abstraction layer according to the actual access results can respond to the state changes of the chip under test in a timely manner and adapt to different test scenarios and requirements. By converging the access result set, the power consumption performance of the chip under test under different conditions can be comprehensively evaluated, providing data support for subsequent design and optimization. The optimized test process reduces the time and resource investment of repeated testing, thereby reducing the overall test cost and improving the economic benefits of chip development.

[0052] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the chip power consumption testing method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0053] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the chip power consumption testing method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 is a schematic diagram of a simulation test platform for chip power consumption according to an embodiment of the present invention;

[0056] Figure 2 is a schematic diagram of the derivation relationship between classes modeled by the abstract layer according to an embodiment of the present invention;

[0057] Figure 3 is a schematic diagram of a chip power consumption test platform according to an embodiment of the present invention;

[0058] Figure 4 is one of the flow charts of the chip power consumption testing method according to an embodiment of the present invention;

[0059] Figure 5 This is a second flowchart of a method for testing chip power consumption according to an embodiment of the present invention;

[0060] Figure 6 is a schematic diagram of dividing a chip to be tested according to an embodiment of the present invention;

[0061] Figure 7 is a third flowchart of a method for testing chip power consumption according to an embodiment of the present invention;

[0062] Figure 8 is a schematic diagram of a chip power consumption testing device according to an embodiment of the present invention;

[0063] Fig. 9 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0065] According to an embodiment of the present invention, an embodiment of a method for testing chip power consumption is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0066] Universal Verification Methodology (UVM) is a standardized hardware design verification method, especially suitable for the verification of integrated circuits (IC) and system on chip (SoC). UVM divides the verification environment into multiple components, such as drivers, monitors, agents, and scoreboards. Each component has clear responsibilities, thereby simplifying management and improving reusability.

[0067] The Register Abstraction Layer (UVM-RAL) is an important part of UVM, focusing on the processing and abstraction of register models. RAL provides a standardized method for representing, accessing, and verifying registers and their behavior in designs.

[0068] Chip power consumption simulation is a key step in the integrated circuit design process, which enables designers to predict and analyze the power consumption of chips before actual manufacturing. Through simulation, the design can be optimized to reduce power consumption and improve energy efficiency, which is critical for modern electronic devices. The process of power consumption analysis includes setting up analysis functions, selecting analysis modes, reading design and library files, specifying operating conditions, performing timing analysis, collecting activity data, configuring analysis options, performing power consumption analysis, and generating analysis reports. The analysis tool propagates this information through the internal simulator to calculate the flip rate of all nodes for power consumption analysis. As power consumption optimization becomes increasingly important, chip teams need a comprehensive solution to reduce power consumption and verify power consumption management to ensure that the entire ecosystem from design to software release can effectively control power consumption.

[0069] Front door access is performed through the sequencer and driver in UVM. This process simulates the access process from outside the chip to registers, memory, low-power switches, and key paths.

[0070] Backdoor access is to modify or obtain the state of registers, memory and low-power switches directly in the UVM-RAL software model without going through the driver. This method allows the device under test (DUT) to be quickly adjusted to the working state of power consumption simulation.

[0071] RAL supports automatic prediction function, which can automatically update the register status in the RAL model when performing register read and write operations. By judging the written value, this function provides the RAL model with the expected feedback value to verify whether the design working status meets the expectations.

[0072] Figure 1 Schematic diagram of a chip power consumption simulation test platform according to an embodiment of the present invention. Figure 1 As shown, the simulation test platform is connected to the device under test (DUT). The device under test, that is, the chip under test, includes multiple types of objects under test, namely, key path net, low-power switch, normal register, and memory.

[0073] The simulation test platform includes: a register model (Reg_model), an adapter (Adapter), a user-defined transaction item (User_define_item), an agent (Agent), and a scoreboard (Scoreboard) which are connected in sequence. The scoreboard is also connected to the register model. The register model is also connected to each object under test of the device under test.

[0074] The agent includes: a sequencer, a driver and a monitor. The monitor is connected to the device under test and the scoreboard respectively. The driver is connected to the sequencer and the device under test respectively.

[0075] The base class (Uvm_reg_item) in the general verification method derives the bus operation (Uvm_reg_bus_op) on the register and inputs it into the user-defined transaction item. The sequence (Sequence) is input into the agent.

[0076] In addition, it should be understood that the simulation test platform and the device under test may also include other more or fewer components, which is not limited in this embodiment.

[0077] Figure 2 is a schematic diagram of the derivation relationship between classes modeled by the abstract layer according to an embodiment of the present invention, such as Figure 2As shown, the universal verification method base class derives four subclasses: register address map (Uvm_reg_map), universal verification method register block (Uvm_reg_block), universal verification method register field (Uvm_reg_field), and universal verification method register (Uvm_reg).

[0078] The register address map derives three subclasses: memory (Uvm_mem), switch path map (Uvm_swp_map), and key path map (Uvm_keyp_map). The universal verification method register block derives the abstract register layer power block (Uvm_pwr_block). The universal verification method register field derives the universal verification method register field power (Uvm_pwr_field). The universal verification method register derives two subclasses: critical path network and low power switch.

[0079] In the structure, register address map, memory, switch path map, critical path map and common verification method register are included in the common verification method register block. Common verification method register field and common verification method register field power are included in the common verification method register.

[0080] Specifically, the register field of the general verification method is the smallest unit in the model, which is used to describe the bit meaning of the register functional domain, as well as the bit meaning of the flip-flop flip in the power consumption simulation and the bit meaning of the critical path.

[0081] Register address mapping, switch path mapping, and critical path mapping are used to carry registers, critical paths, and low-power switches. The latter two correspond to each register in the DUT and can instantiate and configure multiple universal verification method register field objects. Derived classes can also instantiate and configure universal verification method register field power objects.

[0082] The memory matches the storage model of the DUT and is used to record the flipping of the memory inside the chip.

[0083] Register address mapping, switch path mapping, and critical path mapping are used to specify the offset address, access attributes, and bus of the register; they are also used to define the hierarchical relationship, harness attributes, and bus of the critical path; as well as the hierarchical relationship and switch attributes of the power switch.

[0084] The universal verification method register block can accommodate multiple registers, critical paths, low-power switches, memories, and model lists (register address mapping, switch path mapping, critical path mapping), and supports nesting of other universal verification method register blocks. In the register model, at least one universal verification method register block is required.

[0085] The address mapping objects (default_map) of register address mapping, switch path mapping, and critical path mapping in the register block are used for address mapping and front and back door access operations of registers. A register block can contain multiple mappings to implement applications with different buses / paths / switches / address segments.

[0086] Figure 3 is a schematic diagram of a chip power consumption test platform according to an embodiment of the present invention, such as Figure 3 As shown, the register model includes: register address mapping, memory, switch path mapping, critical path mapping, universal verification method registers with independent universal verification method register field power (1 to 3), critical path network, and low power switches.

[0087] In this embodiment, a chip power consumption test method is provided, which can be used in the above-mentioned simulation test platform. Figure 4 is one of the flow charts of a method for testing chip power consumption according to an embodiment of the present invention, the method comprising:

[0088] Step S401, obtaining a first abstraction layer corresponding to a first circuit of a chip to be tested.

[0089] The first abstraction layer includes multiple types of objects to be tested. The chip to be tested may be a SoC chip, and the first circuit may be a part of the circuit in the SoC chip, such as a register, a memory, a low-power switch, and a critical path. The circuit of the processor part. The first abstraction layer may be a circuit simulated by a register abstraction layer tool of a general verification method for the first circuit.

[0090] One implementation method of obtaining the first abstract layer is to pre-establish a first abstract layer corresponding to the first circuit of the chip under test in a simulation test platform, and obtain the first abstract layer from the simulation test platform when testing the power consumption of the chip under test.

[0091] Step S402 : reading and writing multiple types of objects to be tested of the first abstraction layer through a general verification method register abstraction layer tool to obtain actual access results corresponding to each type of object to be tested.

[0092] One implementation method of reading and writing multiple types of objects under test at the first abstract layer may be: sending stimulus signals to multiple types of objects under test at the first abstract layer through the Sequencer and Driver of UVM, and reading the signal output by each type of object under test through UVM, that is, the actual access result.

[0093] Step S403: compare each actual access result with the expected access result of the corresponding type to determine whether each type of the object to be tested meets the first preset condition.

[0094] The first preset condition is that the expected access result is less than or equal to the corresponding actual access result.

[0095] The expected access result is an expected value corresponding to the actual access result, and is used to verify whether the working state of the first circuit meets the expected value.

[0096] An implementation method for determining whether each type of object to be tested meets the first preset condition is: for each type of object to be tested, take its expected access result and actual access result. Use a conditional judgment function to check whether the actual access result is greater than or equal to the expected access result. If the actual access result meets the condition (that is, the actual access result is not less than the expected access result), it is recorded as "satisfied". If the condition is not met, it is recorded as "not met". After all objects to be tested have been checked, the objects to be tested that meet and do not meet the condition are summarized.

[0097] Step S404: if not, obtain a first target set of objects to be tested through all the objects to be tested that do not meet the first preset condition, and modify the first abstraction layer corresponding to the first circuit according to the first target set of objects to be tested to obtain an updated first abstraction layer.

[0098] The first target set of objects to be tested is a set including all objects to be tested that do not meet the first preset condition.

[0099] An implementation method of modifying the abstraction layer corresponding to the first circuit is: for each object to be tested, analyzing the reason why it does not meet the preset conditions, which may be incorrect input signals, internal logic errors, or improper parameter settings, etc. According to the analysis results, for each object to be tested that does not meet the conditions, modify the state of the object to be tested. Adjust the mapping relationship between the excitation signal and the actual access result.

[0100] Step S405, read and write the updated first abstract layer through the general verification method register abstract layer tool to obtain the actual access result corresponding to the updated first abstract layer, and iterate the power consumption test of the chip to be tested until each type of object to be tested in the updated first abstract layer meets the first preset condition, and obtain a converged access result set.

[0101] The converged access result set includes: the actual access result corresponding to each type of the tested object that meets the first preset condition. If each type of the tested object of the updated first abstract layer meets the first preset condition, it means that the actual access result of the power consumption test of the tested chip has converged, i.e., the converged access result.

[0102] Specifically, the power consumption test of the iterative chip under test is performed by repeating steps 401 to 404, judging the actual access results of the updated first abstract layer, iteratively updating the total of the first target objects under test, and updating the first abstract layer, iteratively testing the updated first abstract layer until each type of object under test in the updated first abstract layer meets the first preset condition, and collecting the actual access results of all objects under test that meet the first preset condition as a converged access result set.

[0103] Step S406: determining the power consumption data of the chip to be tested according to the converged access result set.

[0104] The power consumption data may be the average actual power, maximum actual power, minimum actual power, etc. of each object under test of the chip under test during the above test process.

[0105] One implementation method of determining the power consumption data of the chip under test may be: classifying the collected power consumption data according to the test conditions and working states, such as different working frequencies and different load conditions of the object under test. The power consumption data of each object under test under specific conditions is counted and its average power is calculated. The maximum power consumption and the minimum power consumption of each object under test are extracted from the recorded data.

[0106] The present invention provides a chip power consumption testing method, which has the following advantages:

[0107] By using the verification method register abstraction layer tool to read and write the above multiple types of objects under test of the first abstraction layer, the test process of different types of objects under test is simplified and the verification efficiency is improved. By iterating the power consumption test process of the chip under test and comparing the actual access results with the expected access results, the power consumption performance of the chip under test can be accurately identified and corrected, thereby ensuring the reliability of the test results. Automatic screening and modification of objects under test that do not meet the preset conditions reduces the need for manual intervention and improves test efficiency. Dynamically adjusting the abstraction layer according to the actual access results can respond to the state changes of the chip under test in a timely manner and adapt to different test scenarios and requirements. By converging the access result set, the power consumption performance of the chip under test under different conditions can be comprehensively evaluated, providing data support for subsequent design and optimization. The optimized test process reduces the time and resource investment of repeated testing, thereby reducing the overall test cost and improving the economic benefits of chip development.

[0108] In an optional implementation, in order to further accurately obtain the first abstraction layer, the register Figure 5 This is a second flowchart of a method for testing chip power consumption according to an embodiment of the present invention, step S401 comprises:

[0109] Step S501, obtaining the netlist data of the chip to be tested.

[0110] The netlist data of the chip under test can be a SoC netlist, which is a file that describes the internal structure and connections of an integrated circuit. It contains information about all components in the circuit (such as logic gates, registers, input and output ports, etc.) and their interconnected relationships.

[0111] Specifically, it can be to extract the netlist data of the chip under test from the design tool, such as EDA tool. Make sure the netlist contains all necessary components, connections and parameter information. Check the integrity and accuracy of the extracted netlist data to ensure that no important circuit information is lost.

[0112] Step S502 , dividing the entire circuit of the chip to be tested according to the netlist data to obtain a first circuit.

[0113] The first circuit is one of the multiple partial circuits divided from the overall circuit.

[0114] Specifically, an algorithm, such as a partitioning algorithm based on graph theory, can be used to analyze the netlist data and identify different parts of the circuit. The overall circuit is divided into multiple partial circuits based on circuit function, signal flow and modular design principles. A partial circuit is selected from the partition results as the first circuit. This part should be representative or a key functional module.

[0115] Step S503, defining the first abstraction layer in the general verification method register abstraction layer tool, and establishing a mapping relationship between the wires and registers in the first circuit and multiple types of objects to be tested, to obtain the first abstraction layer corresponding to the first circuit.

[0116] Specifically, a first abstraction layer may be created in a general verification method register abstraction layer (RAL) tool to ensure that it can be mapped to the structure of the first circuit. Signals, registers, and related parameters involved in the abstraction layer are defined. A mapping relationship between the first circuit and the object under test is established based on the components, connections, and register information in the first circuit. Ensure that the mapping covers multiple types of objects under test, including input / output interfaces, registers, and control signals. Verify the established mapping relationship to ensure that each signal and register can correctly reflect the function and behavior of the circuit in the abstraction layer.

[0117] The method provided in this embodiment can systematically divide the overall circuit by processing the netlist data, so as to more clearly understand the structure and function of the circuit. By defining the first abstract layer in the general verification method register abstract layer tool and establishing a mapping relationship between the line and register and the object to be tested, the accurate identification and operation of the object to be tested is ensured, and the pertinence of the test is improved. The defined first abstract layer provides a basis for subsequent verification, can simplify the verification process, and provide effective data support for subsequent iterations and optimizations.

[0118] In an optional implementation, in order to further accurately divide the overall circuit of the chip to be tested, step S502 includes:

[0119] The obtained netlist data is converted into a unified data format.

[0120] This can be converted to a common format such as Verilog or VHDL.

[0121] According to the above netlist data, the component list and connection information of the above overall circuit are determined.

[0122] Extract all components such as logic gates, registers, memory, low-power switches, etc. from the converted netlist and generate a component list. Record the connection relationship between each component to form a connection diagram.

[0123] According to the component list, the connection information, and the second preset condition, the overall circuit is divided into a plurality of circuit partitions.

[0124] The second preset condition is to divide the overall circuit based on the functions of the components and the corresponding signal flows.

[0125] According to the component list and the connection information, combined with the second preset condition, the overall circuit is divided into a plurality of partitions.

[0126] Specifically, it can be divided into processor partition, high-speed interface partition, low-speed interface partition, algorithm partition, and system bus partition.

[0127] Use circuit simulation tools to independently simulate each partition to obtain functional requirement information and performance indicator information of each circuit partition.

[0128] Specifically, each divided circuit partition can be simulated independently using circuit simulation tools such as ModelSim, Cadence, LTspice, etc. Functional requirement information and performance indicator information of each partition, such as delay, power consumption, throughput, etc., can be recorded.

[0129] Based on the expected functional requirement information and expected performance indicator information, determine whether the functions of each of the above partitions are complete.

[0130] The expected functional requirement information and expected performance indicator information may be preset delay, power consumption, throughput, etc.

[0131] Specifically, each partition may be evaluated based on expected functional requirements and performance indicators to determine whether its functions are complete. If the function of a partition does not meet expectations, it needs to be modified or re-divided.

[0132] If yes, then the type of each circuit partition is determined according to the functional requirement information and performance indicator information of each circuit partition.

[0133] That is, if a partition is fully functional, the type of the partition is determined based on its functional requirements and performance indicators, such as processor partition, high-speed interface partition, low-speed interface partition, algorithm partition, and system bus partition.

[0134] A circuit partition corresponding to a target type is selected from the circuit partitions of multiple different types as the first circuit.

[0135] Specifically, a target type of partition may be selected from multiple different types of circuit partitions as the first circuit. The selection may be based on functional importance, performance priority or specific design requirements, or may be based on the order of power consumption tests.

[0136] The method provided in this embodiment converts netlist data into a unified data format, which is convenient for subsequent analysis and operation. According to the components and connection information, as well as the second preset condition, the overall circuit is divided into multiple circuit partitions, making the management and testing of complex circuits more accurate and concise. By independently simulating each circuit partition, the function and performance of each partition can be deeply analyzed to obtain detailed functional requirement information and performance index information. By judging whether the function of each partition is complete, the cost of subsequent debugging and modification is reduced. According to the functional requirements and performance indicators, the type of each circuit partition is determined, which is convenient for classification management in subsequent design and testing to improve efficiency. Selecting a partition of the target type from different types of circuit partitions as the first circuit makes the selection process more targeted and can better meet specific functional requirements. Through the combination of the above steps, comprehensive optimization of circuit testing can be achieved, the accuracy and effectiveness of the overall test can be improved, and the quality and performance of the final chip can be ensured to meet the standards.

[0137] In an optional implementation, in order to further accurately update the first abstraction layer, step S404 includes:

[0138] According to the first target set of objects to be tested, a second circuit corresponding to the first target set of objects to be tested is determined.

[0139] Specifically, the first target set of objects to be tested may be analyzed for characteristics and functions to identify the second circuit corresponding thereto, which may be achieved by searching circuit design documents, libraries or previous design experience.

[0140] A second abstraction layer corresponding to the second circuit is obtained as the updated first abstraction layer, wherein the second abstraction layer includes a plurality of types of updated objects to be tested, and the first objects to be tested have the same number and type as the updated objects to be tested.

[0141] Specifically, the design data or model related to the second circuit may be accessed to obtain the corresponding second abstraction layer information. The second abstraction layer should describe the structure and behavior of the circuit in detail, including different types of updated objects to be tested. The obtained second abstraction layer is used as the updated first abstraction layer. It is ensured that the updated first abstraction layer contains multiple types of updated objects to be tested corresponding to the first target object to be tested.

[0142] The method provided in this embodiment ensures that the updated abstract layer can accurately reflect the new test requirements and enhance the relevance of the test by making the first target set of objects to be tested correspond to the second circuit. The updated first abstract layer and the second abstract layer are consistent in the number and types of objects to be tested. This consistency helps to simplify the test process and reduce potential errors and confusion. The ability to flexibly adjust the abstract layer according to different sets of objects to be tested enhances the adaptability of the circuit design and enables it to better meet diverse test requirements. Through this process, the accuracy, efficiency and flexibility of circuit design and testing can be improved, providing support for improving the overall chip quality and performance.

[0143] In an optional implementation, in order to further accurately determine the power consumption data of the chip to be tested, step S405 includes:

[0144] According to the actual access result corresponding to each type of the object to be tested that meets the first preset condition and the third preset condition, the actual coverage corresponding to the low power consumption signal and the power consumption management function is determined.

[0145] Specifically, the ratio of the number of low-power signals actually accessed to the number of all potential low-power signals may be calculated to obtain the actual coverage.

[0146] The actual power consumption of the low power consumption signal is determined according to the flip ratio, static power consumption and flip power consumption of the low power consumption signal.

[0147] Among them, the flip ratio refers to the number of times a signal flips (from high to low or from low to high) within a certain period of time. The flip ratio is usually expressed as the number of flips per second, reflecting the frequency of signal changes in the circuit. A higher flip ratio usually means higher dynamic power consumption. Static power consumption refers to the power consumed by the circuit when it is not performing any operation. This is usually caused by leakage current, especially in CMOS circuits, where static power consumption is mainly related to power supply voltage and process parameters. Optimizing static power consumption can effectively reduce overall energy consumption, especially in standby mode. Flip power consumption refers to the power consumed by the circuit when the signal flips. It is usually related to the flip ratio, power supply voltage and capacitance. Dynamic power consumption dominates in high-frequency operations.

[0148] Specifically, the flip ratio can be calculated based on the number of flips of the monitoring signal of each type of object under test within a specific time. The static power consumption value is obtained based on the circuit design and process parameters. The load capacitance and supply voltage are determined, and the dynamic power consumption is calculated. The static power consumption and dynamic power consumption are added to obtain the total actual power consumption of the signal.

[0149] The actual coverage and the actual power consumption are used as power consumption data of the chip under test.

[0150] That is, the power consumption data may be defined as a class in UVM, and the actual coverage and actual power consumption may be objects in the class.

[0151] The method provided in this embodiment effectively evaluates the power consumption performance of the chip to be tested, ensuring that the actual performance of the low-power signal can be accurately analyzed during the design verification phase. By combining the actual access results, coverage, and power consumption parameters, the energy consumption characteristics of the chip under different working conditions can be more fully understood. This method not only improves the accuracy of power consumption data, but also provides a valuable basis for subsequent optimization design, thereby ultimately enhancing the energy efficiency and market competitiveness of the chip.

[0152] In an optional implementation, in order to further provide a method for a general verification method register abstraction layer tool to read and write the first abstraction layer, step S402 includes:

[0153] A link is established between the first abstraction layer and the front- and back-door access interfaces of the general verification method register abstraction layer tool.

[0154] Specifically, it can be achieved by defining the front-door access interface between the first abstraction layer and the general verification method register abstraction layer tool, which can be achieved through an API or other communication mechanism to ensure smooth data transmission between the two.

[0155] The test cases are input into the first abstract layer through the front- and back-door access interfaces, and the actual access results corresponding to each type of the object to be tested generated by the first abstract layer are collected.

[0156] Specifically, a series of test cases can be designed and prepared, which should cover various possible access modes and scenarios. The test cases are input into the first abstraction layer through the front-end and back-end interfaces. This process can be automated using scripts or tools to improve efficiency and accuracy. During the execution of the test cases, the actual access results corresponding to each type of object under test generated by the first abstraction layer are collected. These results may include the success or failure of read and write operations, response time, data consistency, etc. The collected results are stored in a structured data format for subsequent analysis and verification.

[0157] The method provided in this embodiment can more accurately evaluate the power consumption performance of the chip under test in actual applications by analyzing the actual access results corresponding to each type of object under test and combining preset conditions. The effectiveness of the low-power signal and the power management function is calculated according to the actual coverage to ensure that the key power paths can be identified and optimized during the design process and improve the overall power management capability. By calculating the flip ratio, static power consumption and flip power consumption of the low-power signal, a basis is provided for subsequent optimization design. Through systematic power consumption analysis, the cost and time of later modifications can be reduced. A quantitative basis is provided for the realization of the power management function to meet the needs of different application scenarios. Through this process, the accuracy and efficiency of the power consumption evaluation of the chip under test can be significantly improved.

[0158] In an optional implementation, in order to further provide a method for obtaining the expected access result, after inputting the test case to the first abstraction layer through the front and back door access interfaces, the method further includes:

[0159] According to the above test cases, the above expected access results of each type are generated through the above general verification method register abstraction layer tool.

[0160] Specifically, the automatic prediction function of the register abstraction layer tool of the general verification method may be used to predict the corresponding expected access result according to the above test case.

[0161] The method provided in this embodiment can ensure that the output of the test case is consistent with the design expectation through the expected access result generated by the general verification method register abstraction layer tool, thereby improving the accuracy of the test process.

[0162] In an optional implementation, in order to further determine the power consumption distribution, after the power consumption test is completed, the converged access result set may be analyzed to identify the contribution of each object under test to the overall power consumption, and the analysis step includes:

[0163] The actual access results in the converged access result set are counted to determine the access frequency and duration of each object to be tested.

[0164] Based on the access frequency and duration of each object to be tested and its corresponding power consumption characteristics, the specific contribution value of each object to be tested to the overall power consumption is calculated.

[0165] According to the power consumption contribution value of each object under test, optimization feedback is proposed to reduce the overall power consumption of the chip under test. The optimization feedback includes adjusting the circuit design, modifying the power consumption management strategy or updating the simulation model.

[0166] Figure 6It is a schematic diagram of the division of a chip to be tested according to an embodiment of the present invention. The chip to be tested is a SoC chip, which includes processor partitions, high-speed interface partitions, low-speed interface partitions, algorithm partitions, and system bus partitions. The processor partition also includes core 1 partitions and core 2 partitions.

[0167] Each partition captures waveforms through an independent model capturer (waveform capturer 0 to 5). Specifically, the built-in function of Verdi (a comprehensive tool for chip design and verification) can be used to capture the jump data of the lines and registers in the circuit. The collected waveforms are converted to SAIF format through the SAIF (Standard Annotation Interchange Format) conversion function. Use a special parsing tool or script to analyze the data in the SAIF file and extract the jump information of each signal and device in the circuit. Compare with the expected coverage model in the design to identify which paths are not activated. Usually, these paths involve certain logical branches or conditions in the circuit. Feedback the uncovered device paths and related information to the RAL model for further verification and optimization.

[0168] Figure 7 This is the third flowchart of the chip power consumption testing method according to an embodiment of the present invention. The flow includes: a creation phase, a simulation phase, and a convergence phase.

[0169] The creation phase includes: instantiation of the general verification method register abstraction layer tool; establishing the link between the abstraction layer and the front and back doors; establishing the mapping between the circuit partition to be tested and the abstraction layer; covering the objects to be tested of the circuit partition to be tested (such as registers, memory, low-power switches, critical path networks).

[0170] Among them, the register abstraction layer tool instantiates the content and architecture according to the general verification method Figure 2 and Figure 3 The circuit to be tested is partitioned according to Figure 6 divided in the same way.

[0171] The simulation phase includes: starting simulation one by one according to the circuit partitions; collecting the abstraction layer front door access results of each partition mapping.

[0172] The access results are as follows: Figure 2 The power consumption objects are classified.

[0173] The convergence phase includes: judging whether the low-power switch is covered, whether the critical path network is covered, and whether the signal flip ratio of the register and memory is qualified; if not, retain the coverage item, feedback the uncovered circuit, modify the front door to a qualified configuration item, and re-execute the simulation phase; if all are judged to be yes, end the simulation.

[0174] The present invention also provides a chip power consumption test device, which is applied to a simulation test platform. Figure 8 1 is a schematic diagram of a chip power consumption testing device according to an embodiment of the present invention, the device comprising:

[0175] The acquisition module 801 is used to acquire a first abstraction layer corresponding to a first circuit of a chip under test, wherein the first abstraction layer includes multiple types of objects under test.

[0176] The testing module 802 is used to read and write the multiple types of objects to be tested of the first abstract layer through a universal verification method register abstract layer tool to obtain actual access results corresponding to each type of object to be tested.

[0177] The judgment module 803 is used to compare each of the above actual access results with the expected access results of the corresponding type, and judge whether each type of the object to be tested meets the first preset condition, and the above first preset condition is that the above expected access result is less than or equal to the corresponding actual access result.

[0178] The modification module 804 is used to, if not, obtain a first target set of objects to be tested through all objects to be tested that do not meet the first preset condition, and modify the first abstraction layer corresponding to the first circuit according to the first target set of objects to be tested to obtain an updated first abstraction layer.

[0179] Iteration module 805 is used to read and write the updated first abstract layer through the general verification method register abstract layer tool to obtain the actual access result corresponding to the updated first abstract layer, and iterate the power consumption test of the chip to be tested until each type of the object to be tested in the updated first abstract layer meets the first preset condition, and obtain a convergent access result set, the convergent access result set includes: the actual access result corresponding to each type of the object to be tested that meets the first preset condition.

[0180] The determination module 806 is used to determine the power consumption data of the chip under test according to the converged access result set.

[0181] The chip power consumption test device provided by the present invention has the following advantages:

[0182] By using the universal verification method register abstraction layer tool to read and write the above multiple types of objects under test of the above first abstraction layer, the test process of different types of objects under test is simplified and the verification efficiency is improved. By iterating the power consumption test process of the chip under test and comparing the actual access results with the expected access results, the power consumption performance of the chip under test can be accurately identified and corrected, thereby ensuring the reliability of the test results. Automatic screening and modification of objects under test that do not meet the preset conditions reduces the need for manual intervention and improves test efficiency. Dynamically adjusting the abstraction layer according to the actual access results can respond to the state changes of the chip under test in a timely manner and adapt to different test scenarios and requirements. By converging the access result set, the power consumption performance of the chip under test under different conditions can be comprehensively evaluated, providing data support for subsequent design and optimization. The optimized test process reduces the time and resource investment of repeated testing, thereby reducing the overall test cost and improving the economic benefits of chip development.

[0183] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0184] The chip power consumption test device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0185] The embodiment of the present invention also provides a computer device having the above Figure 8 The chip power consumption is shown in the test setup.

[0186] See also Fig. 9 , Fig. 9 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig. 9 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig. 9A processor 10 is taken as an example.

[0187] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include an integrated circuit. The integrated circuit may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0188] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0189] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0190] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0191] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0192] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0193] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A chip power consumption testing method, characterized in that: The method is applied to a simulation test platform, and the method comprises: Acquire a first abstraction layer corresponding to a first circuit of the chip to be tested, where the first abstraction layer includes multiple types of objects to be tested; Read and write the multiple types of objects to be tested of the first abstract layer through a universal verification method register abstract layer tool to obtain actual access results corresponding to each type of object to be tested; Compare each of the actual access results with the expected access results of the corresponding type to determine whether each type of the object to be tested meets a first preset condition, where the first preset condition is that the expected access result is less than or equal to the corresponding actual access result; If not, obtaining a first target set of objects to be tested through all the objects to be tested that do not meet the first preset condition, and modifying the first abstraction layer corresponding to the first circuit according to the first target set of objects to be tested to obtain an updated first abstraction layer; The updated first abstract layer is read and written by the general verification method register abstract layer tool to obtain the actual access result corresponding to the updated first abstract layer, and the power consumption test of the chip to be tested is iterated until each type of the object to be tested of the updated first abstract layer meets the first preset condition, and a convergent access result set is obtained, wherein the convergent access result set includes: the actual access result corresponding to each type of the object to be tested that meets the first preset condition; The power consumption data of the chip to be tested is determined according to the converged access result set.

2. The method according to claim 1, characterized in that Acquiring a first abstraction layer corresponding to a first circuit of the chip to be tested includes: Obtaining netlist data of the chip to be tested; Divide the overall circuit of the chip under test according to the netlist data to obtain the first circuit, where the first circuit is one of the multiple partial circuits divided from the overall circuit; The first abstract layer is defined in the general verification method register abstract layer tool, and a mapping relationship between the lines and registers in the first circuit and the multiple types of objects to be tested is established to obtain a first abstract layer corresponding to the first circuit.

3. The method according to claim 2, characterized in that The overall circuit of the chip to be tested is divided according to the netlist data to obtain the first circuit, including: Converting the acquired netlist data into a unified data format; Determining a component list and connection information of the overall circuit according to the netlist data; According to the component list and the connection information, and a second preset condition, the overall circuit is divided into a plurality of circuit partitions; Use a circuit simulation tool to independently simulate each partition to obtain functional requirement information and performance indicator information of each circuit partition; Determining whether the functions of each partition are complete according to the expected functional requirement information and the expected performance indicator information; If yes, determining the type of each circuit partition according to the functional requirement information and performance indicator information of each circuit partition; A circuit partition corresponding to a target type is selected from a plurality of different types of the circuit partitions as the first circuit.

4. The method according to any one of claims 1 to 3, characterized in that: Modifying the first abstraction layer corresponding to the first circuit according to the first target set of objects to be tested to obtain an updated first abstraction layer includes: Determining, according to the first target set of objects to be tested, a second circuit corresponding to the first set of target objects to be tested; A second abstraction layer corresponding to the second circuit is obtained as the updated first abstraction layer, wherein the second abstraction layer includes a plurality of types of updated objects to be tested, and the number and type of the objects to be tested are the same as those of the updated objects to be tested.

5. The method according to any one of claims 1 to 3, characterized in that: Determining the power consumption data of the chip to be tested according to the converged access result set includes: Determine the actual coverage rate corresponding to the low power consumption signal and the power consumption management function according to the actual access result corresponding to each type of the object to be tested that meets the first preset condition and the third preset condition; Determining the actual power consumption of the low power consumption signal according to the flip ratio, static power consumption and flip power consumption of the low power consumption signal; The actual coverage and the actual power consumption are used as power consumption data of the chip under test.

6. The method according to any one of claims 1 to 3, characterized in that: Reading and writing the multiple types of objects to be tested of the first abstract layer through the universal verification method register abstract layer tool to obtain actual access results corresponding to each type of object to be tested, including: Establishing a link between the first abstraction layer and the front- and back-door access interfaces of the universal verification method register abstraction layer tool; The test cases are input into the first abstract layer through the front- and back-door access interfaces, and the actual access results corresponding to each type of the object to be tested generated by the first abstract layer are collected.

7. The method according to claim 6, characterized in that After inputting the test case into the first abstract layer through the front and back door access interfaces, the method further includes: According to the test case, the expected access result of each type is generated by the general verification method register abstraction layer tool.

8. A chip power consumption test device, characterized in that: The device is applied to a simulation test platform, and the device comprises: An acquisition module, used to acquire a first abstraction layer corresponding to a first circuit of the chip to be tested, wherein the first abstraction layer includes multiple types of objects to be tested; A test module, used for reading and writing the multiple types of objects to be tested of the first abstract layer through a universal verification method register abstract layer tool, and obtaining actual access results corresponding to each type of object to be tested; A judgment module, used to compare each of the actual access results with the expected access results of the corresponding type, and judge whether each type of the object to be tested meets a first preset condition, wherein the first preset condition is that the expected access result is less than or equal to the corresponding actual access result; a modification module, configured to, if not, obtain a first target set of objects to be tested through all the objects to be tested that do not meet the first preset condition, and modify the first abstraction layer corresponding to the first circuit according to the first target set of objects to be tested to obtain an updated first abstraction layer; An iteration module is used to read and write the updated first abstract layer through the general verification method register abstract layer tool to obtain the actual access result corresponding to the updated first abstract layer, and iterate the power consumption test of the chip to be tested until each type of the object to be tested of the updated first abstract layer meets the first preset condition, and obtain a convergent access result set, the convergent access result set including: the actual access result corresponding to each type of the object to be tested that meets the first preset condition; A determination module is used to determine the power consumption data of the chip to be tested according to the converged access result set.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the chip power consumption testing method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the chip power consumption testing method according to any one of claims 1 to 7.

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