Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate, the display panel and the display device are used for reducing resistance of a first signal line. The array substrate comprises a first substrate body and a plurality of first signal lines. The first substrate comprises a plurality of sub-pixel regions and a wiring region; each first signal line comprises a plurality of first parts, a plurality of second parts and a plurality of third parts; in the extension direction of each first signal line, the first parts and the second parts are alternately arranged and electrically connected; the third part is connected in parallel with the first part; the extension direction of the first part intersects with the extension direction of the second part, and the extension direction of the third part intersects with the extension direction of the second part. Orthographic projections of a part of the first part and a part of the third part on the first substrate are located in a wiring area between two adjacent sub-pixel areas in the first direction; the orthographic projection of the second part on the first substrate is located in the wiring area between the two adjacent sub-pixel areas in the second direction, and the two first parts connected with the second part are located in different columns in the second direction.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the continuous development and application of display technology, users have higher and higher requirements on the display effects of electronic display products.

[0003] At present, in order to reduce costs and increase the screen ratio, LCD products use a dual gate design. That is, one data line can drive sub-pixels located in two adjacent columns. In order to improve the uniformity of the voltage polarity of the same sub-pixels, bow-shaped data lines are usually used. However, compared with straight data lines, the length of the bow-shaped data lines is greatly increased, and the corresponding data line resistance is also increased, which can easily cause insufficient pixel charging, resulting in differences in charging rates between different pixels, resulting in vertical stripes and affecting the display effect. Summary of the invention

[0004] Embodiments of the present application provide an array substrate, a display panel, and a display device, which are used to reduce the resistance of a first signal line.

[0005] An array substrate provided in an embodiment of the present application includes: a first base substrate, and a plurality of first signal lines located on one side of the first base substrate;

[0006] The first substrate includes a plurality of sub-pixel regions arrayed along a first direction and a second direction and a wiring region outside the sub-pixel regions; the first direction intersects the second direction;

[0007] Each first signal line includes: a plurality of first portions, a plurality of second portions, and a plurality of third portions; in the extension direction of each first signal line, the first portions and the second portions are alternately arranged and electrically connected; the third portions are connected in parallel with the first portions; the extension direction of the first portions intersects with the extension direction of the second portions, and the extension direction of the third portions intersects with the extension direction of the second portions;

[0008] The orthographic projections of part of the first portion and part of the third portion on the first base substrate are located in a wiring area between two adjacent sub-pixel areas in the first direction;

[0009] The orthographic projection of the second portion on the first base substrate is located in a wiring region between two adjacent sub-pixel regions in the second direction, and the two first portions connected to the second portion are located in different columns in the second direction.

[0010] In some embodiments, in the first direction, the first portions and the third portions are arranged alternately, and a sub-pixel region is spaced between at least some adjacent first portions and third portions and the orthographic projection of the first substrate.

[0011] In some embodiments, the third portion is connected to the two second portions respectively.

[0012] In some embodiments, the first signal line further includes a plurality of fourth portions; two ends of the fourth portion are respectively connected to the third portion and the first portion;

[0013] The orthographic projection of the fourth portion on the first base substrate is located in a wiring area between two adjacent sub-pixel areas in the second direction;

[0014] In the first direction, the second portion and the fourth portion connected to the first portion are respectively located at two sides of the first portion.

[0015] In some embodiments, two first portions connected to at least a portion of the second portions are separated by n sub-pixel regions in the first direction, where n is an integer greater than 1;

[0016] The second part includes: n first sub-parts and n-1 second sub-parts; the first sub-parts correspond to the sub-pixel areas;

[0017] Part IV includes: Subpart III;

[0018] The first sub-portion and the third sub-portion extend along the first direction, and the extension direction of the second sub-portion intersects both the first direction and the second direction;

[0019] The second sub-portion connects the two first sub-portions, and the n first sub-portions included in the second portion are located on different straight lines in the first direction;

[0020] In the second direction, the first subsection is adjacent to the third subsection.

[0021] In some embodiments, the array substrate further comprises a plurality of thin film transistors, a plurality of scan lines and a plurality of first electrodes; the thin film transistor comprises: a first electrode, a second electrode and a third electrode; the first electrode is electrically connected to the scan line, and the third electrode is electrically connected to the first signal line; the plurality of thin film transistors comprises a plurality of first thin film transistors and a plurality of second thin film transistors;

[0022] The scanning line comprises a plurality of strip electrode lines; the plurality of strip electrode lines are alternately arranged and electrically connected with a plurality of first electrodes corresponding to the scanning line; in the second direction, the width of the first electrode is greater than the width of the strip electrode line; the orthographic projections of the second electrode and the third electrode on the first substrate overlap with the orthographic projection of the first electrode on the first substrate;

[0023] The strip electrode line and the edge of the first electrode on a side away from the first electrode are located in the same straight line;

[0024] The second electrode of the first thin film transistor reuses the third sub-portion, and the second electrode of the second thin film transistor reuses the first sub-portion.

[0025] In some embodiments, the sub-pixel area and the wiring area are divided into: a plurality of sub-pixel rows and wiring area rows arranged along the second direction and extending along the first direction, and a plurality of sub-pixel columns extending along the second direction and arranged along the first direction; the sub-pixel rows and the wiring area rows are arranged alternately;

[0026] The plurality of thin film transistors corresponding to the i-th row of wiring regions are divided into a plurality of first repeating unit groups, and the plurality of thin film transistors corresponding to the i+1-th row of wiring regions are divided into a plurality of second repeating unit groups; i is a positive integer;

[0027] The first repeating unit group includes m first units and k second units, and the second repeating unit group includes k first units and m second units; wherein m and k are both positive integers and m and k are not equal;

[0028] In the first row of wiring area and the last row of wiring area, the first unit includes a first thin film transistor and the second unit includes a second thin film transistor;

[0029] In the remaining wiring area rows except the first wiring area row and the last wiring area row, the first unit includes two first thin film transistors corresponding to different sub-pixel rows and corresponding to different sub-pixel columns, and the second unit includes two second thin film transistors corresponding to different sub-pixel rows and corresponding to different sub-pixel columns;

[0030] In the second direction, the first units and the second units are arranged alternately.

[0031] In some embodiments, m=2, k=1;

[0032] In the first direction, in the remaining wiring area rows except the first wiring area row and the last wiring area row, in the adjacent first unit and the second unit, the first thin film transistor and the second thin film transistor located in the adjacent sub-pixel column correspond to the same sub-pixel row;

[0033] The plurality of scanning lines include a plurality of first scanning lines and a plurality of second scanning lines; in the second direction, the first scanning lines and the second scanning lines are arranged alternately;

[0034] The wiring area row between two adjacent sub-pixel rows includes a first scan line and a second scan line;

[0035] In the i-th row of the wiring area, among the plurality of thin film transistors electrically connected to the second scan line, two adjacent first thin film transistors are spaced apart by one sub-pixel column, the second thin film transistor and the first thin film transistor adjacent to it in the positive direction of the first direction are located in adjacent sub-pixel columns, and the second thin film transistor and the first thin film transistor adjacent to it in the negative direction of the first direction are spaced apart by two sub-pixel columns;

[0036] In the i-th row of the wiring area, among the plurality of thin film transistors electrically connected to the first scan line, two adjacent first thin film transistors are spaced apart by one sub-pixel column, the second thin film transistor and the first thin film transistor adjacent to it in the negative direction of the first direction are located in adjacent sub-pixel columns, and the second thin film transistor and the first thin film transistor adjacent to it in the positive direction of the first direction are spaced apart by two sub-pixel columns;

[0037] In the i+1th row of the wiring area, among the plurality of thin film transistors electrically connected to the second scan line, one sub-pixel column is spaced between two adjacent second thin film transistors, a first thin film transistor and a second thin film transistor adjacent to it in the positive direction of the first direction are located in adjacent sub-pixel columns, and the first thin film transistor and a second thin film transistor adjacent to it in the negative direction of the first direction are spaced two sub-pixel columns;

[0038] In the i+1th row of the wiring area, among the multiple thin film transistors electrically connected to the first scanning line, there is one sub-pixel column between two adjacent second thin film transistors, the first thin film transistor and the second thin film transistor adjacent to it in the negative direction of the first direction are located in adjacent sub-pixel columns, and the first thin film transistor and the second thin film transistor adjacent to it in the positive direction of the first direction are separated by two sub-pixel columns.

[0039] In some embodiments, in the i-th row of the wiring area, in adjacent first units and second units, a first thin film transistor and a second thin film transistor electrically connected to the same first signal line are spaced apart by one sub-pixel column; in two adjacent first units, two first thin film transistors electrically connected to the same first signal line are spaced apart by two sub-pixel columns;

[0040] In the i+1th row of wiring area, in adjacent first units and second units, the first thin film transistor and the second transistor electrically connected to the same first signal line are separated by one sub-pixel column; in two adjacent first units, the two first thin film transistors electrically connected to the same first signal line are located in adjacent sub-pixel columns.

[0041] In some embodiments, in the i-th row of wiring regions, the fourth sub-portion and the second sub-portion extend along the third direction, and the fifth sub-portion extends along the fourth direction;

[0042] In the (i+1)th row of wiring regions, the fourth sub-portion and the second sub-portion extend along the fourth direction, and the fifth sub-portion extends along the third direction;

[0043] The angle between the third direction and the positive direction of the first direction is greater than 90° and less than 180°, and the angle between the fourth direction and the positive direction of the first direction is greater than 0° and less than 90°.

[0044] In some embodiments, the third electrode includes: a first sub-electrode, a second sub-electrode, and a third sub-electrode;

[0045] The second sub-electrode is connected to the first sub-electrode and the third sub-electrode, and the orthographic projections of the first sub-electrode and the third sub-electrode on the first substrate are strips extending along the first direction; in the first direction, the width of the second sub-electrode is smaller than the length of the first sub-electrode and the length of the third sub-electrode;

[0046] In the second direction, the first sub-electrode is arranged opposite to the second electrode, the orthographic projection of the first sub-electrode on the first substrate overlaps with the orthographic projection of the first electrode on the first substrate, the orthographic projection of the third sub-electrode on the first substrate overlaps with the orthographic projection of the first electrode on the first substrate, and the first electrode is electrically connected to the third sub-electrode.

[0047] In some embodiments, the orthographic projections of the second portion and the fourth portion on the first substrate fall within the orthographic projection of the first substrate in a region between two adjacent scan lines in the wiring region.

[0048] In some embodiments, the array substrate further includes: a second electrode located on a side of the first signal line away from the first base substrate, and a plurality of second signal lines electrically connected to the second electrode;

[0049] The second signal line includes: a plurality of fifth portions and a plurality of sixth portions; the fifth portions and the sixth portions are alternately arranged and electrically connected;

[0050] The orthographic projection of the fifth portion on the first base substrate is located in the wiring area between two adjacent sub-pixel areas in the first direction;

[0051] The orthographic projection of the sixth portion on the first base substrate is located in a wiring region between two adjacent sub-pixel regions in the second direction, and the two fifth portions connected to the sixth portion are located in different columns in the second direction.

[0052] In some embodiments, the shape of the pattern of the second signal line on the first substrate is the same as the shape of the pattern of the plurality of first portions and the plurality of second portions of the first signal line on the first substrate;

[0053] The orthographic projection of the fifth portion on the first base substrate is adjacent to the orthographic projection of the first portion on the first base substrate, and the orthographic projection of the fifth portion on the first base substrate does not overlap with the orthographic projection of the first portion on the first base substrate.

[0054] An embodiment of the present application provides a display panel, which includes: an array substrate provided in the embodiment of the present application, an opposite substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the opposite substrate.

[0055] An embodiment of the present application provides a display device, and the display device includes the display panel provided by the embodiment of the present application.

[0056] In the array substrate, display panel and display device provided by the embodiments of the present disclosure, the first signal line includes a first part and a second part which are alternately arranged and electrically connected, and the extension directions of the first part and the second part intersect, that is, the pattern of the first signal line includes a part extending in a "bow" shape, which can improve the uniformity of the polarity of the sub-pixel. In addition, the first signal line also includes a third part connected in parallel with the first part, so that the resistance of the first signal line can be reduced, the impedance of the first signal line can be reduced, and insufficient charging can be avoided, thereby improving the uniformity of the charging rate of the sub-pixel area, avoiding the occurrence of vertical stripes, and improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0058] Figure 1 A structural schematic diagram of an array substrate provided for related technology;

[0059] Figure 2 A structural schematic diagram of another array substrate provided for related technology;

[0060] Figure 3 A schematic diagram of the structure of an array substrate provided in an embodiment of the present application;

[0061] Figure 4 A schematic diagram of the structure of another array substrate provided in an embodiment of the present application;

[0062] Figure 5 A method provided in the embodiment of the present application Figure 4 Schematic diagram of the enlarged structure of the middle E region;

[0063] Figure 6 A schematic diagram of the structure of another array substrate provided in an embodiment of the present application;

[0064] Figure 7 A schematic diagram of the structure of another array substrate provided in an embodiment of the present application;

[0065] Figure 8 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0066] Fig. 9 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0067] Fig.10 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0068] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. And in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in the field without creative work belong to the scope of protection of this application.

[0069] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. "First", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and other similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0070] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present application. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0071] In related technologies, such as Figure 1 As shown, the length L1 of the linear data line 24 corresponding to each sub-pixel is equal to a, and the resistance Rn of the data line segment is equal to R1. Figure 2 As shown, the length of each sub-pixel corresponding to the "bow"-shaped data line 24 is L2=a+4×(a / 3)=2.3a, and the resistance of this data line segment is Rn'=2.3R1. That is, the "bow"-shaped data line will increase the length and resistance of the data line. When the line width of the data line remains unchanged, the impedance and capacitance of the data line are increased. In this way, when the sub-pixels are charged by the data line, the sub-pixels farther away from the signal input end are more likely to be undercharged, resulting in differences in the sub-pixel charging rate of the entire product, resulting in vertical stripes and poor display effects.

[0072] The present application embodiment provides an array substrate, such as Figure 3 As shown, the array substrate comprises: a first base substrate 1, and a plurality of first signal lines 2 located on one side of the first base substrate 1;

[0073] The first base substrate 1 includes a plurality of sub-pixel regions 101 arranged in an array along a first direction X and a second direction Y and a wiring region 102 located outside the sub-pixel region 101; the first direction X intersects the second direction Y;

[0074] Each first signal line 2 includes: a plurality of first portions 201, a plurality of second portions 202, and a plurality of third portions 203; in the extension direction of each first signal line 2, the first portions 201 and the second portions 202 are alternately arranged and electrically connected; the third portion 203 is connected in parallel with the first portion 201; the extension directions of the first portion 201 and the second portion 202 intersect, and the extension directions of the third portion 203 and the second portion 202 intersect;

[0075] The orthographic projection of a portion of the first portion 201 and a portion of the third portion 203 on the first base substrate 1 is located in the wiring area 102 between two adjacent sub-pixel areas 101 in the first direction X;

[0076] The orthographic projection of the second portion 202 on the first base substrate 1 is located in the wiring area 102 between two adjacent sub-pixel areas 101 in the second direction Y, and the two first portions 201 connected to the second portion 202 are located in different columns in the second direction Y.

[0077] It should be noted that if Figure 3 As shown, in the extension direction of each of the first signal lines 2, the first part 201 and the second part 202 are alternately arranged and electrically connected, which means that: in each of the first signal lines 2, the two ends of the first part 201 are respectively electrically connected to two different second parts 202, and the two ends of the remaining second parts 202 except the first second part 202 and the last second part 202 are respectively electrically connected to two different first parts 201.

[0078] In the array substrate provided by the embodiment of the present disclosure, the first signal line includes a first part and a second part that are alternately arranged and electrically connected, and the extension directions of the first part and the second part intersect, that is, the pattern of the first signal line includes a part extending in a "bow" shape, which can improve the polarity uniformity of the sub-pixel. In addition, the first signal line also includes a third part connected in parallel with the first part, so that the resistance of the first signal line can be reduced, the impedance of the first signal line can be reduced, and insufficient charging can be avoided, thereby improving the uniformity of the charging rate of the sub-pixel area, avoiding the occurrence of vertical stripes, and improving the display effect.

[0079] In some embodiments, the first portion and the third portion extend substantially along the second direction Y, and the second portion extends substantially along the first direction X. The first portion and the third portion extending substantially along the second direction Y means that at least a portion of the first portion and the third portion extend along the first direction, or the angle between the actual extension direction of at least a portion of the first portion and the third portion and the first direction X is small. The second portion extending substantially along the first direction X means that at least a portion of the second portion extends along the first direction X, or the angle between the actual extension direction of at least a portion of the second portion and the first direction X is small.

[0080] In some embodiments, Figure 3 As shown, the array substrate further includes: a plurality of thin film transistors TFT, a plurality of scanning lines 3 and a plurality of first electrodes 4. The thin film transistor TFT includes a first electrode, a second electrode and a third electrode; the first electrode is electrically connected to the scanning line 4, the second electrode is electrically connected to the first signal line 2, and the third electrode is electrically connected to the first electrode 4. That is, the first electrode is a gate electrode, the second electrode is a source electrode, and the third electrode is a drain electrode. The first signal line is a data line, which is used to provide a data signal to the thin film transistor.

[0081] In some embodiments, the second electrode, the third electrode, and the first signal line are arranged in the same layer. The scanning line and the first electrode are arranged in the same layer. The second electrode, the third electrode, and the first signal line are located on the side of the scanning line and the first electrode away from the first substrate, and the second electrode is located on the side of the second electrode, the third electrode, and the first signal line away from the first substrate.

[0082] It should be noted that in the present disclosure, "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to a mask (also called a photomask). Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.

[0083] In some embodiments, Figure 3 As shown, in the second direction Y, the wiring area 102 between any two adjacent sub-pixel areas 101 is provided with two scan lines 3. Specifically, the plurality of scan lines 3 include a plurality of first scan lines 4-1 and a plurality of second scan lines 3-2; the first scan lines 3-1 and the second scan lines 3-2 are arranged alternately; and between two adjacent sub-pixel areas 101 in the second direction Y, there is one first scan line 3-1 and one second scan line 3-2.

[0084] In a specific implementation, a row of sub-pixel regions arranged along the first direction corresponds to a first scan line and a second scan line; that is, in the second direction, a first scan line and a second scan line are respectively located on both sides of a row of sub-pixel regions. That is, the scan line of the array substrate provided in the embodiment of the present disclosure is a Dual Gate design.

[0085] It should be noted that when the array substrate is applied to a display product, the array substrate is divided into a display area and a peripheral area surrounding the display area, the sub-pixel area is only located in the display area, and the display area and the peripheral area both include a wiring area. The sub-pixel area corresponds to the sub-pixel opening area of ​​the display area of ​​the display product, and the wiring area corresponds to the sub-pixel non-opening area and the peripheral area of ​​the display area of ​​the display product. In the display area, the wiring area is located between adjacent sub-pixel areas.

[0086] In specific implementation, Figure 3 As shown, the plurality of sub-pixel regions 102 include a plurality of red sub-pixel regions r, a plurality of blue sub-pixel regions b, and a plurality of green sub-pixel regions g; a column of sub-pixel regions 102 in the second direction Y are sub-pixel regions 102 of the same color, and in the first direction X, two adjacent sub-pixel regions 102 are sub-pixel regions 102 of different colors. The red sub-pixel region r, the blue sub-pixel region b, and the green sub-pixel region g constitute one pixel.

[0087] In a specific implementation, when the array substrate is applied to a display product, the display area includes an array composed of a plurality of pixels. When the first signal is loaded on the scan line to control the thin film transistor to turn on, the first signal line charges the first electrode in sequence. When the second electrode is fully charged, the second signal is loaded on the scan line to control the thin film transistor to turn off, and the first electrode enters a holding state. If the thin film transistor is an N-type transistor, the first signal is a high-level signal and the second signal is a low-level signal. In a specific implementation, in each frame display stage, multiple scan lines can be used to scan line by line to charge the first electrode.

[0088] In some embodiments, Figure 3 As shown, each first portion 201 is connected in parallel with a third portion 203 .

[0089] In some embodiments, Figure 3 As shown, in the first direction X, the first portions 201 and the third portions 203 are arranged alternately, and at least part of the adjacent first portions 201 and third portions 203 are separated by a sub-pixel region 101 between the orthographic projections of the first substrate 1 .

[0090] The embodiments of this application provide Figure 3In the array substrate shown in FIG. 1 , if the length of the first portion 201 and the third portion 203 in the second direction Y is a, the resistance is R1, and the length of the second portion 202 in the first direction X is 2×(a / 3), then the resistance of the first signal line corresponding to each sub-pixel area Rn″=(R1×4×(R1 / 3)) / (R1+(4×R1 / 3))=4R1 / 7≈0.57R1, compared with the related art such as Figure 2 In the case where the resistance of the bow-shaped first signal line Rn'=2.3R1, the design method of the first signal line provided in the embodiment of the present application can greatly reduce the resistance, thereby reducing the impedance of the first signal line, avoiding insufficient charging, thereby improving the uniformity of the charging rate of the sub-pixel area, avoiding vertical stripes, and improving the display effect.

[0091] In a specific implementation, in the display area, any adjacent first portion and third portion are separated by a sub-pixel area between the orthographic projections of the first base substrate.

[0092] In some embodiments, the lengths of the plurality of first signal lines are all equal. This ensures that the resistances of the plurality of first signal lines are consistent, which is beneficial to the uniformity of signal transmission. Accordingly, the first portion or the third portion of the first signal line at the edge is located in the peripheral area. There is no sub-pixel area between the first portion or the third portion at the edge and located in the peripheral area and the first signal line adjacent thereto, but the distance between the first portion or the third portion at the edge and located in the peripheral area and the first signal line adjacent thereto is equal to the distance between the adjacent first and third portions in the display area.

[0093] In some embodiments, in the first direction X, distances between any adjacent first portions and third portions are equal.

[0094] Alternatively, in some embodiments, the distance between the first portion or the third portion in the peripheral area and the first signal line adjacent thereto is smaller than the distance between the adjacent first portion and third portion in the display area, thereby reducing the size of the peripheral area and facilitating narrow-frame display.

[0095] In some embodiments, Figure 3 As shown, the third part 203 is connected to the two second parts 202 respectively.

[0096] Or, in some embodiments, Figure 4 As shown, the first signal line 2 further includes a plurality of fourth portions 204; two ends of the fourth portion 204 are respectively connected to the third portion 203 and the first portion 201;

[0097] The orthographic projection of the fourth portion 204 on the first base substrate 1 is located in the wiring area 102 between two adjacent sub-pixel areas 101 in the second direction Y;

[0098] In the first direction X, the second portion 202 and the fourth portion 204 connected to the first portion 201 are respectively located on both sides of the first portion 201 .

[0099] In some embodiments, Figure 4 As shown, two first portions 201 connected to at least a portion of the second portion 202 are separated by n sub-pixel regions 101 in the second direction Y, where n is an integer greater than 1;

[0100] The second portion 202 includes: n first sub-portions 2021 and n-1 second sub-portions 2022; the first sub-portion 2021 corresponds to the sub-pixel area 101;

[0101] The fourth section 204 includes: a third subsection 2041;

[0102] The first sub-portion 2021 and the third sub-portion 2041 extend along the first direction X, and the extension direction of the second sub-portion 2022 intersects both the first direction X and the second direction Y;

[0103] The second sub-portion 2022 connects the two first sub-portions 2021 , and the n first sub-portions 2021 included in the second portion 202 are located on different straight lines in the first direction X;

[0104] In the second direction Y, the first sub-portion 2021 is adjacent to the third sub-portion 2041 .

[0105] It should be noted that, for the first portion and the second portion located in the display area, two first portions connected to the second portion are spaced apart by n sub-pixel regions in the second direction Y.

[0106] In some embodiments, Figure 4 As shown, n=2.

[0107] In some embodiments, Figure 4 As shown, the scanning line 3 includes a plurality of strip electrode lines 301; the plurality of strip electrode lines 301 are alternately arranged and electrically connected with a plurality of first electrodes G corresponding to the scanning line 3; in the second direction Y, the width of the first electrode G is greater than the width of the strip electrode line 301; the orthographic projections of the second electrode S and the third electrode D on the first substrate 1 overlap with the orthographic projection of the first electrode G on the first substrate 1;

[0108] The strip electrode line 301 and the edge of the first electrode G away from the first electrode 4 are located in the same straight line;

[0109] Part of the second pole S reuses the first sub-portion 2021 , and the rest of the second pole S reuses the third sub-portion 2041 .

[0110] The array substrate provided in the embodiment of the present application is as follows: Figure 4As shown, the strip electrode line 301 and the edge of the first electrode G facing the first electrode 4 are located in the same straight line, and in the second direction Y, the width of the first electrode G is greater than the width of the strip electrode line 301, that is, the pattern composed of the scanning line 3 and the plurality of first electrodes G has a protrusion at the first electrode G that is away from the first electrode 4 adjacent to the two. The protrusion of the first electrode faces the side of the first electrode, which can increase the area of ​​the sub-pixel region and thus increase the sub-pixel aperture ratio. In addition, the second electrode reuses the first sub-portion or the third sub-portion, and there is no need to set up an additional second electrode, thereby saving wiring space.

[0111] In some embodiments, Figure 4 As shown, the second electrode S and the third electrode D are arranged along the second direction Y, and the thin film transistor TFT further includes an active layer 7 .

[0112] In some embodiments, Figure 4 As shown, the plurality of thin film transistors TFT include a plurality of first thin film transistors TFT1 and a plurality of second thin film transistors TFT2; the second electrode S of the first thin film transistor TFT1 reuses the third sub-portion 2041, and the second electrode S of the second thin film transistor TFT2 reuses the first sub-portion 2021.

[0113] In some embodiments, Figure 4 As shown, the sub-pixel area 101 and the wiring area 102 are divided into: a plurality of sub-pixel rows 5 and wiring area rows 6 arranged along the second direction Y and extending along the first direction X, and a plurality of sub-pixel columns 25 and wiring area columns 26 extending along the second direction Y and arranged along the first direction X; the sub-pixel rows 5 and the wiring area rows 6 are arranged alternately, and the sub-pixel columns 25 and the wiring area columns 26 are arranged alternately. The orthographic projections of the first portion 201 and the third portion 203 on the first substrate 1 are located in the wiring area column 26, and the orthographic projections of the second portion 202 on the first substrate 1 are located in the wiring area row 6.

[0114] In some embodiments, Figure 4 As shown, for the multiple thin film transistors TFT corresponding to each wiring area row 6, the thin film transistors TFT correspond to the sub-areas 1021 one by one, the multiple thin film transistors TFT corresponding to the wiring area row 6 are arranged in sequence along the first direction X, and the multiple thin film transistors TFT corresponding to the wiring area row 6 located between two sub-pixel rows 5 correspond to different sub-pixel rows 5.

[0115] In some embodiments, Figure 4 As shown, the multiple thin film transistors TFT corresponding to row 6 of the i-th wiring area are divided into multiple first repeating unit groups 1101, and the multiple thin film transistors TFT corresponding to row 6 of the i+1-th wiring area are divided into multiple second repeating unit groups 1102; i is a positive integer;

[0116] The first repeating unit group 1101 includes m first units 9 and k second units 1010, and the second repeating unit group 1102 includes k first units 9 and m second units 10; wherein m and k are both positive integers and m and k are not equal;

[0117] The first unit 9 includes one or two first thin film transistors TFT1 , and the second unit 10 includes one or two second thin film transistors TFT2 . In the second direction Y, the first unit 9 and the second unit 10 are arranged alternately.

[0118] That is, in the specific implementation, Figure 4 As shown, in the second direction Y, one side of each sub-pixel row 5 corresponds to a plurality of first repeating unit groups 1101 , and the other side corresponds to a second repeating unit group 1102 .

[0119] In a specific implementation, the i-th row wiring area row is an odd-numbered row wiring area row, and the i+1-th row wiring area row is an even-numbered row wiring area row, that is, the multiple thin film transistors corresponding to the odd-numbered row wiring area row are divided into multiple first repeating unit groups, and the multiple thin film transistors corresponding to the even-numbered row wiring area row are divided into multiple second repeating unit groups. Alternatively, the i-th row wiring area row is an even-numbered row wiring area row, and the i+1-th row wiring area row is an odd-numbered row wiring area row, that is, the multiple thin film transistors corresponding to the even-numbered row wiring area row are divided into multiple first repeating unit groups, and the multiple thin film transistors corresponding to the odd-numbered row wiring area row are divided into multiple second repeating unit groups.

[0120] In a specific implementation, the first row of wiring area rows includes a first scan line but does not include a second scan line, the first unit includes a first thin film transistor electrically connected to the first scan line, and the second unit includes a second thin film transistor electrically connected to the first scan line. The last row of wiring area rows includes the second scan line but does not include the first scan line, the first unit includes a first thin film transistor electrically connected to the second scan line, and the second unit includes a second thin film transistor electrically connected to the second scan line. In the remaining wiring area rows except the first row of wiring area row 6 and the last row of wiring area row 6, as shown in FIG. Figure 4 As shown, the first unit 9 includes two first thin film transistors TFT1 corresponding to different sub-pixel rows 5 and corresponding to different sub-pixel columns 25, and the two first thin film transistors TFT1 are electrically connected to the first scan line 3-1 and the second scan line 3-2, respectively. The second unit 10 includes two second thin film transistors TFT2 corresponding to different sub-pixel rows 5 and corresponding to different sub-pixel columns 25, and the two second thin film transistors TFT2 are electrically connected to the first scan line 3-1 and the second scan line 3-2, respectively.

[0121] In some embodiments, Figure 4 As shown, m=2, k=1;

[0122] In the first direction X, in the remaining wiring area rows 6 except the first row wiring area row 6 and the last row wiring area row 6, in the adjacent first unit 9 and second unit 10 in the first repeating unit group 1101 or the second repeating unit group 1102, the first thin film transistor TFT1 and the second thin film transistor TFT2 located in the adjacent sub-pixel column 25 correspond to the same sub-pixel row 5;

[0123] In the i-th row wiring area row 6, among the plurality of thin film transistors electrically connected to the second scan line 3-2, two adjacent first thin film transistors TFT1 are spaced apart by one sub-pixel column 25, the second thin film transistor TFT2 and the first thin film transistor TFT1 adjacent thereto in the positive direction X+ of the first direction X are located in the adjacent sub-pixel column 25, and the second thin film transistor TFT2 and the first thin film transistor TFT1 adjacent thereto in the negative direction X- of the first direction X are spaced apart by two sub-pixel columns 25;

[0124] In the i-th row wiring area row 6, among the plurality of thin film transistors electrically connected to the first scan line 3-1, two adjacent first thin film transistors TFT1 are spaced apart by one sub-pixel column 25, the second thin film transistor TFT2 and the first thin film transistor TFT1 adjacent thereto in the negative direction X- of the first direction X are located in the adjacent sub-pixel column 25, and the second thin film transistor TFT2 and the first thin film transistor TFT1 adjacent thereto in the positive direction X+ of the first direction X are spaced apart by two sub-pixel columns 25;

[0125] In the i+1th row wiring area row 6, among the plurality of thin film transistors electrically connected to the second scan line 3-2, two adjacent second thin film transistors TFT2 are spaced apart by one sub-pixel column 25, the first thin film transistor TFT1 and the second thin film transistor TFT2 adjacent thereto in the positive direction X+ of the first direction X are located in adjacent sub-pixel columns 25, and the first thin film transistor TFT1 and the second thin film transistor TFT2 adjacent thereto in the negative direction X- of the first direction X are spaced apart by two sub-pixel columns 25;

[0126] In the i+1th row wiring area row 6, among the multiple thin film transistors electrically connected to the first scan line 3-1, there is one sub-pixel column 25 between two adjacent second thin film transistors TFT2, the first thin film transistor TFT1 and the second thin film transistor TFT2 adjacent to it in the negative direction X- of the first direction X are located in adjacent sub-pixel columns 25, and the first thin film transistor TFT1 and the second thin film transistor TFT2 adjacent to it in the positive direction X+ of the first direction X are separated by two sub-pixel columns 25.

[0127] It should be noted that Figure 4 In the description, an example is given in which the direction extending to the right is the positive direction X+ of the first direction X, and the direction extending to the left is the negative direction X− of the first direction X.

[0128] In some embodiments, Figure 4 As shown, in the i-th row wiring area row 6, in adjacent first units 9 and second units 10, a first thin film transistor TFT1 electrically connected to the same first signal line 2 is spaced apart by one sub-pixel column 25; in two adjacent first units 9, two first thin film transistors TFT1 electrically connected to the same first signal line 2 are spaced apart by two sub-pixel columns 25;

[0129] In the i+1th row wiring area row 6, in adjacent first units 9 and second units 10, the first thin film transistor TFT1 and the second thin film transistor TFT2 electrically connected to the same first signal line 2 are separated by a sub-pixel column 25; in two adjacent first units 9, the two first thin film transistors TFT1 electrically connected to the same first signal line 2 are located in adjacent sub-pixel columns 25.

[0130] In some embodiments, Figure 4 As shown, in the remaining wiring area rows 6 except the first wiring area row 6 and the last wiring area row 6, both sides of the second portion 202 in the first direction X are electrically connected to the fourth portion.

[0131] In some embodiments, in the first row of wiring area row 6 and the last row of wiring area row 6, the first sub-portion 2021 of each first signal line 2 is multiplexed as the second pole S or the third sub-portion 2041 is multiplexed as the second pole S;

[0132] like Figure 4 As shown, every three first signal lines 2 in the plurality of first signal lines 2 serve as a first signal line group 8, that is, the pattern of the first signal line group 8 serves as a repeating unit of the arrangement of the first signal lines 2. The first signal line group 8 includes a first first signal line 2-1, a second first signal line 2-2, and a third first signal line 2-3;

[0133] The i-th row of wiring area row 6 and the i+1-th row of wiring area row 6 are the remaining wiring area rows 6 except the first row of wiring area row 6 and the last row of wiring area row 6; in each first first signal line 2-1, the third sub-portions 2041 located on both sides of the second part 202 in the i-th row of wiring area row 6 are multiplexed as the second pole S, and the two first sub-portions 2021 in the i+1-th row of wiring area row 6 are multiplexed as the second pole S; in each second first signal line 2-2 and each third first signal line 2-3, in the i-th row of wiring area row 6 and the i+1-th row of wiring area row 6, one of the first sub-portions 2021 is multiplexed as the second pole S, and one of the third sub-portions 2041 is multiplexed as the second pole S.

[0134] In some embodiments, Figure 4 , Figure 5As shown, the third electrode D includes: a first sub-electrode D1, a second sub-electrode D2 and a third sub-electrode D3. The second sub-electrode D2 connects the first sub-electrode D1 and the third sub-electrode D3. The orthographic projections of the first sub-electrode D1 and the third sub-electrode D3 on the first substrate 1 are strips extending along the first direction X. In the second direction Y, the first sub-electrode D1 is arranged opposite to the second electrode S. The orthographic projection of the first sub-electrode D1 on the first substrate 1 overlaps with the orthographic projection of the first electrode G on the first substrate 1. The orthographic projection of the third sub-electrode D3 on the first substrate 1 overlaps with the orthographic projection of the first electrode 4 on the first substrate 1. The first electrode 4 is electrically connected to the third sub-electrode D3. In the first direction X, the width of the second sub-electrode D2 is less than the length of the first sub-electrode D1 and the length of the third sub-electrode D3.

[0135] It should be noted that Figure 5 for Figure 4 A magnified schematic diagram of area E in the middle.

[0136] In the array substrate provided in the embodiment of the present application, the third pole D includes a first sub-electrode D1, a second sub-electrode D2 and a third sub-electrode D3 in the shape of an "I". The first sub-electrode D1 and the third sub-electrode D3 are in the shape of a bar, and the second sub-electrode D2 is smaller in size, thereby ensuring the electrical connection area between the third pole and the first electrode and reducing the overlapping capacitance between the third pole and the first pole, thereby reducing the jump of the pixel voltage caused by the overlapping capacitance between the third pole and the first pole and improving the working stability of the thin film transistor.

[0137] In some embodiments, Figure 4 , Figure 5 As shown, the shape of the orthographic projection of the active layer 7 on the first substrate 1 is a rectangle.

[0138] It should be noted that Figure 4 , Figure 5 In the example, the overlapping parts of the orthogonal projections of the second pole S and the third pole D and the first pole G are all in the shape of strips, and the shape of the channel of the thin film transistor is a "U" shape. Of course, in the specific implementation, the channel of the thin film transistor can also be other shapes, such as a "U" shape, the orthogonal projection of the second pole on the first substrate substrate and the orthogonal projection of the first pole on the first substrate substrate have a pattern of overlapping in the shape of a "U" shape, and the orthogonal projection of the third pole on the first substrate substrate and the orthogonal projection of the first pole on the first substrate substrate have a pattern of overlapping in the shape of a strip. In the specific implementation, if the first pole is located on one side of the sub-pixel area in the second direction, a part of the area of ​​the first sub-part or the third sub-part can be reused as a "U"-shaped second pole. Alternatively, the first pole is located between two adjacent sub-pixel areas in the first direction, and a part of the area of ​​the first part or the third part is reused as a "U"-shaped second pole.

[0139] In some embodiments, the first electrode may be directly overlapped with the third sub-electrode, or the first electrode may be overlapped with the third sub-electrode through a via hole penetrating the insulating layer between the first electrode and the third sub-electrode.

[0140] In some embodiments, Figure 4 As shown, the fourth part 204 also includes: a fourth sub-part 2042 connected to the third part 203 and the third sub-part 2041, and a fifth sub-part 2043 connected to the third sub-part 2041 and the first part 201; the second part 202 also includes a sixth sub-part 2023 connecting the first part 201 and the first sub-part 2011.

[0141] In some embodiments, Figure 4 As shown, the third portion 203 and the third sub-portion 2041 need to be connected via the fourth sub-portion 2042 .

[0142] In some embodiments, the third sub-portion and the first portion need to be connected via the fifth sub-portion, or, as Figure 4 As shown, part of the third sub-portion 2041 and the first portion 201 may be connected via the fifth sub-portion 2043 , and the rest of the third sub-portion 2041 may be connected to the sixth sub-portion 2023 .

[0143] In some embodiments, both the first portion and the first sub-portion need to be connected via the sixth sub-portion, or, as Figure 4 As shown, part of the first portion 201 and the first sub-portion 2011 may be connected via the sixth sub-portion 2023 , and the rest of the first portion 201 and the first sub-portion 2011 may be directly connected.

[0144] In some embodiments, Figure 4 As shown, the fourth sub-portion 2042 is adjacent to the second sub-portion 2022 , both are located on different first signal lines 2 , and extend in the same direction; the fifth sub-portion 2043 is adjacent to the fifth sub-portion 2043 , both are located on different first signal lines 2 , and extend in the same direction.

[0145] In some embodiments, Figure 4 As shown, in the fourth sub-portion 2042 and the fifth sub-portion 2043 that are at least partially connected to the same third sub-portion 2041, the angle between the extension direction of one of them and the positive direction X+ of the first direction X is greater than 0° and less than 90°, and the angle between the extension direction of the other of them and the positive direction X+ of the first direction X is greater than 90° and less than 180°.

[0146] It should be noted that the angle between the positive direction X+ of the first direction X and the positive direction X+ is greater than 0° and less than 90°, which means that when the extension direction passes through the origin of the coordinate system composed of the first direction X and the second direction Y, the angle between the portion located in the positive direction Y+ of the second direction Y and the positive direction X+ of the first direction X is greater than 0° and less than 90°, that is, the extension direction extends along the first and third quadrants of the coordinate system composed of the first direction X and the second direction Y. The angle between the positive direction X+ of the first direction X and the positive direction X+ is greater than 90° and less than 180°, which means that when the extension direction passes through the origin of the coordinate system composed of the first direction X and the second direction Y, the angle between the portion located in the positive direction Y+ of the second direction Y and the positive direction X+ of the first direction X is greater than 90° and less than 180°, that is, the extension direction extends along the second and fourth quadrants of the coordinate system composed of the first direction X and the second direction Y.

[0147] In specific implementation, Figure 4 As shown, in the fourth sub-portion 2042 and the fifth sub-portion 2043 connected to the third sub-portion 2041 multiplexed as the second pole, the angle between the extension direction of one of them and the positive direction X+ of the first direction X is greater than 0° and less than 90°, and the angle between the extension direction of the other of them and the positive direction X+ of the first direction X is greater than 90° and less than 180°.

[0148] In some embodiments, Figure 4 As shown, in the i-th wiring area row 6, the fourth sub-portion 2042 and the second sub-portion 2022 extend along the third direction X1, and the fifth sub-portion 2043 extends along the fourth direction X2;

[0149] In the (i+1)th wiring area row 6, the fourth sub-portion 2042 and the second sub-portion 2022 extend along the fourth direction X2, and the fifth sub-portion 2043 extends along the third direction X1;

[0150] The angle between the third direction X1 and the positive direction X+ of the first direction X is greater than 90° and less than 180°, and the angle between the fourth direction X2 and the positive direction X+ of the first direction X is greater than 0° and less than 90°.

[0151] In a specific implementation, the i-th wiring area row 6 is an odd-numbered wiring area row 6, and the i+1-th wiring area row 6 is an even-numbered wiring area row 6. That is, in the odd-numbered wiring area row 6, the fourth sub-portion 2042 and the second sub-portion 2022 extend along the third direction X1, and the fifth sub-portion 2043 extends along the fourth direction X2; in the even-numbered wiring area row 6, the fourth sub-portion 2042 and the second sub-portion 2022 extend along the fourth direction X2, and the fifth sub-portion 2043 extends along the third direction X1. Alternatively, the i-th wiring area row 6 is an even-numbered wiring area row 6, and the i+1-th wiring area row 6 is an odd-numbered wiring area row 6. That is, in the even-numbered row wiring area row 6, the fourth sub-portion 2042 and the second sub-portion 2022 extend along the third direction X1, and the fifth sub-portion 2043 extends along the fourth direction X2; in the odd-numbered row wiring area row 6, the fourth sub-portion 2042 and the second sub-portion 2022 extend along the fourth direction X2, and the fifth sub-portion 2043 extends along the third direction X1.

[0152] In some embodiments, Figure 4 As shown, the orthographic projections of the second portion 202 and the fourth portion 204 on the first substrate 1 fall within the orthographic projection of the first substrate 1 in the region between two adjacent scanning lines 3 in the wiring region 102 .

[0153] In some embodiments, Figure 6 As shown, the array substrate also includes: a second electrode 12 located on the side of the first signal line 2 away from the first base substrate 1; the first electrode 4 is located on the side of the second electrode 12 away from the first signal line 2; the array substrate also includes: a gate insulating layer 13 located between the active layer (not shown) and the scanning line (not shown), an interlayer insulating layer 14 located between the scanning line (not shown) and the first signal line 2, a first insulating layer 15 located between the first signal line 2 and the second electrode 12, and a second insulating layer 16 located between the second electrode 12 and the first electrode 4.

[0154] In some embodiments, the thickness of the first insulating layer is greater than 6000 angstroms, for example, the thickness of the first insulating layer is 20000 angstroms.

[0155] In the related art, the thickness of the insulating layer between the first signal line and the second electrode is 6000 angstroms, and the dielectric constant is 6.8. When the thickness of the first insulating layer is 20000 angstroms, the dielectric constant is 3.2. The array substrate provided in the embodiment of the present application reduces the dielectric constant and capacitance between the first signal line and the second electrode by increasing the thickness of the insulating layer between the first signal line and the second electrode, thereby preventing the capacitance formed between the two from affecting the display effect.

[0156] It should be noted that the present application only provides a description of the thickness of the first insulating layer and the corresponding dielectric constant. In specific implementation, the thickness and dielectric constant of the first insulating layer can be selected as needed.

[0157] In some embodiments, the first electrode is a pixel electrode, and the second electrode is a common electrode; the second electrode may be disposed on the entire surface, for example.

[0158] In a specific implementation, the first electrode or the second electrode further includes a slit portion, and the slit portion corresponds to the sub-pixel area and includes a plurality of slits.

[0159] In some embodiments, the second electrode is multiplexed as a touch electrode.

[0160] In some embodiments, Figure 7 As shown, the array substrate further includes: a plurality of second signal lines 17 electrically connected to the second electrodes (not shown); that is, the second signal lines 17 can be used to transmit touch signals in the touch stage;

[0161] The second signal line 17 includes: a plurality of fifth portions 1701 and a plurality of sixth portions 1702; the fifth portions 1701 and the sixth portions 1702 are alternately arranged and electrically connected;

[0162] The orthographic projection of the fifth portion 1701 on the first base substrate 1 is located in the wiring area 102 between two adjacent sub-pixel areas 101 in the first direction X;

[0163] The orthographic projection of the sixth portion 1702 on the first substrate 1 is located in the wiring area 102 between two adjacent sub-pixel areas 101 in the second direction Y, the two fifth portions 1701 connected to the sixth portion 1702 are located in different columns in the second direction Y, and at least part of the two fifth portions 1701 connected to the sixth portion 1702 are separated by n sub-pixel areas 101 in the second direction Y.

[0164] In the array substrate provided by the embodiment of the present application, the second signal line includes a fifth portion and a sixth portion alternately arranged and electrically connected in the extension direction thereof, the extension directions of the fifth portion and the sixth portion intersect, and the two fifth portions connected by at least part of the sixth portion are separated by at least two sub-pixel areas in the second direction Y, that is, the pattern of the second signal line extends in a "bow" shape. And the second signal line is located in the wiring area, which can avoid affecting the sub-pixel aperture ratio.

[0165] In some embodiments, Figure 7 As shown, the shape of the pattern of the second signal line 17 on the first base substrate 1 is the same as the shape of the pattern of the plurality of first portions 201 and the plurality of second portions 202 of the first signal line 2 on the first base substrate 1;

[0166] The orthographic projection of the fifth portion 1701 on the first substrate 1 is adjacent to the orthographic projection of the first portion 201 on the first substrate 1, and the orthographic projection of the fifth portion 1701 on the first substrate 1 does not overlap with the orthographic projection of the first portion 201 on the first substrate 1. Thus, interference with the touch signal caused by the fifth portion and the first portion facing each other can be avoided.

[0167] In some embodiments, Figure 7 As shown, there is no gap between the orthographic projection of the fifth portion 1701 on the first base substrate 1 and the orthographic projection of the first portion 201 on the first base substrate 1. This can further save wiring space in the wiring area.

[0168] In some embodiments, the second signal line is located on the side of the first signal line away from the first substrate, that is, the second signal line and the first signal line are located in different film layers, so that the second signal line can avoid interfering with the first signal line and reduce the design difficulty of the signal line. For example, the second signal line is located between the first insulating layer and the second electrode, and the array substrate also includes a third insulating layer between the second electrode and the second signal line. Alternatively, the second signal line is located on the side of the second electrode away from the first substrate. For example, the second signal line is arranged in the same layer as the first electrode. Alternatively, the second signal line may be located between the second insulating layer and the first electrode, and the array substrate also includes a fourth insulating layer between the first electrode and the second signal line.

[0169] In some embodiments, Figure 7 As shown, the orthographic projection of the sixth portion 1702 on the first substrate 1 overlaps with the orthographic projection of the second portion 202 on the first substrate 1. This saves wiring space in the wiring area, avoids increasing the size of the wiring area, avoids reducing the size of the sub-pixel area, and avoids reducing the sub-pixel aperture ratio.

[0170] In some embodiments, Figure 7 As shown, the sixth part 1702 includes: n seventh sub-parts 17021, and n-1 eighth sub-parts 17022; the eighth sub-part 17022 connects two seventh sub-parts 17021; the seventh sub-part 17021 and the first sub-part ( Figure 7) have the same extension direction; in the adjacent first signal line 2 and the second signal line 17, the eighth sub-portion 17022 and the second sub-portion 2022 have the same extension direction, and the eighth sub-portion 17022 is adjacent to the second sub-portion 2022; at least part of the sixth portion also includes a ninth sub-portion 17023 connecting the seventh sub-portion 17021 and the fifth portion 1702, and at least part of the second portion 202 also includes a tenth sub-portion 2023 connecting the first sub-portion and the first portion 201; in the adjacent first signal line 2 and the second signal line 17, the ninth sub-portion 17023 and the tenth sub-portion 2023 have the same extension direction, and the ninth sub-portion 17023 and the tenth sub-portion 2023 are adjacent to each other.

[0171] In some embodiments, Figure 7 As shown, in at least partially adjacent first signal line 2 and second signal line 17, the orthographic projection of the first sub-portion on the first substrate substrate 1 overlaps with the orthographic projection of the seventh sub-portion 1701 on the first substrate substrate 1, and the orthographic projection of the first sub-portion on the first substrate substrate 1 and the orthographic projection of the seventh sub-portion 1701 on the first substrate substrate 1 are located on the same straight line, that is, the orthographic projection of the first sub-portion on the first substrate substrate 1 is covered by the orthographic projection of the seventh sub-portion 1701 on the first substrate substrate 1.

[0172] In a specific implementation, in some adjacent first signal lines and second signal lines, the first sub-portion and the seventh sub-portion whose orthographic projections overlap may not be located on the same straight line.

[0173] In some embodiments, the line width of the fifth portion is less than or equal to the line width of the first portion. Since the wiring area between two adjacent sub-pixel areas in the first direction X is small and the wiring space is limited, when the orthographic projection of the first portion on the first substrate substrate is adjacent to the orthographic projection of the fifth portion on the first substrate substrate, the line width of the fifth portion is less than or equal to the line width of the first portion, which is beneficial to saving wiring space and avoiding affecting the sub-pixel aperture ratio.

[0174] In some embodiments, a line width of the sixth portion is less than or equal to a line width of the second portion.

[0175] In a specific implementation, for example, the line width of the fifth portion is smaller than the line width of the first portion, and the line width of the sixth portion is equal to the line width of the second portion. When the wiring space of the wiring area row 6 is sufficient, the line width of the sixth portion is not reduced, that is, the line width of the sixth portion is equal to the line width of the second portion, which is beneficial to reducing the resistance of the second signal line.

[0176] In a specific implementation, the first substrate is, for example, a glass substrate. The material of the active layer may be amorphous silicon (a-Si), polycrystalline silicon (poly), oxide (Oxide, such as indium gallium zinc oxide IGZO), etc. The materials of the first electrode, the second electrode, the third electrode, the scan line, and the first signal line may include metals such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), and may be a single-layer structure or a laminated structure, for example, the laminated structure is a laminated structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer. The material of the first electrode and the second electrode is the same, for example, a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0177] Based on the same inventive concept, the embodiment of the present application further provides a display panel, such as Figure 8 As shown, the display panel includes: an array substrate 19 provided in an embodiment of the present application, an opposite substrate 20 arranged opposite to the array substrate 19 , and a liquid crystal layer 21 located between the array substrate 19 and the opposite substrate 20 .

[0178] In some embodiments, the array substrate includes a thin film transistor, and the opposite substrate includes: a second base substrate, and a plurality of spacers located on a side of the second base substrate facing the liquid crystal layer;

[0179] like Fig. 9 As shown, the orthographic projection of the spacer 18 on the first substrate 1 falls within the orthographic projection of the first electrode G of the thin film transistor TFT on the first substrate 1 .

[0180] In some embodiments, Fig. 9 As shown, the orthographic projection of the active layer 7 on the first base substrate 1 falls within the orthographic projection of the spacer 18 on the first base substrate 1, and the orthographic projection of the spacer 18 on the first base substrate 1 overlaps with the orthographic projections of the second pole S and the third pole D on the first base substrate 1. Thus, the support area of ​​the spacer can be guaranteed and the support strength of the spacer can be improved.

[0181] In some embodiments, the width of the first electrode in the first direction X is greater than the width of the spacer in the first direction X, and the width of the first electrode in the second direction Y is greater than the width of the spacer in the second direction Y.

[0182] In a specific implementation, an alignment layer is further provided on a side of the array substrate close to the liquid crystal layer and a side of the opposite substrate close to the liquid crystal layer.

[0183] In some embodiments, the counter substrate further includes a black matrix and color resists on the side of the second substrate facing the liquid crystal layer. The black matrix has an opening area, and the color resists are located in the opening area; the spacers are located on the side of the black matrix facing the liquid crystal layer.

[0184] In a specific implementation, the orthographic projection of the black matrix on the array substrate falls into the wiring area. The color resist corresponds to the sub-pixel area one by one, and the orthographic projection of the color resist on the array substrate falls into the sub-pixel area. The color resist includes a red color resist corresponding to the red sub-pixel area, a blue color resist corresponding to the blue sub-pixel area, and a green color resist corresponding to the green sub-pixel area.

[0185] An embodiment of the present application provides a display device, and the display device includes the display panel provided by the embodiment of the present application.

[0186] In some embodiments, in the above display device provided by the embodiments of the present disclosure, if Fig.10 As shown, a backlight module 23 may also be included on the light incident side of the array substrate 19. The backlight module may be a direct-lit backlight module or an edge-lit backlight module.

[0187] In a specific implementation, the side-entry backlight module may include a light bar, a reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, and the reflective sheet includes an opening arranged directly opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.). Submillimeter-level or even micron-level micro light-emitting diodes are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, it has a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because the light emission of inorganic light-emitting diodes is based on metal semiconductors with more stable properties and lower resistance, it has the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life than organic light-emitting diodes that emit light based on organic matter. Moreover, when micro light-emitting diodes are used as backlight sources, more sophisticated dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0188] The display device provided in the embodiment of the present application is any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by a person skilled in the art, and will not be described in detail here, nor should they be used as a limitation to the present application. The implementation of the display device can refer to the embodiments of the above-mentioned array substrate and display panel, and the repeated parts will not be described in detail.

[0189] In summary, the array substrate, display panel and display device provided by the embodiments of the present disclosure, the first signal line includes a first part and a second part that are alternately arranged and electrically connected, the extension directions of the first part and the second part intersect, and the two first parts connected to at least part of the second part are separated by at least 2 sub-pixel areas in the second direction Y, that is, the pattern of the first signal line includes a part extending in a "bow" shape, which can improve the uniformity of the polarity of the sub-pixel. In addition, the first signal line also includes a third part connected in parallel with the first part, so that the resistance of the first signal line can be reduced, the impedance of the first signal line can be reduced, and insufficient charging can be avoided, thereby improving the uniformity of the charging rate of the sub-pixel area, avoiding the occurrence of vertical stripes, and improving the display effect.

[0190] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0191] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An array substrate, characterized in that: The array substrate comprises: a first base substrate, and a plurality of first signal lines located on one side of the first base substrate; The first substrate includes a plurality of sub-pixel regions arranged in an array along a first direction and a second direction and a wiring region outside the sub-pixel regions; the first direction intersects the second direction; Each of the first signal lines comprises: a plurality of first portions, a plurality of second portions and a plurality of third portions; in the extension direction of each of the first signal lines, the first portions and the second portions are alternately arranged and electrically connected; the third portions are connected in parallel with the first portions; the extension direction of the first portions intersects with the extension direction of the second portions, and the extension direction of the third portions intersects with the extension direction of the second portions; The orthographic projections of part of the first portion and part of the third portion on the first substrate are located in the wiring area between two adjacent sub-pixel areas in the first direction; An orthographic projection of the second portion on the first base substrate is located in the wiring region between two adjacent sub-pixel regions in the second direction, and the two first portions connected by the second portion are located in different columns in the second direction.

2. The array substrate according to claim 1, characterized in that: In the first direction, the first portions and the third portions are arranged alternately, and at least some of the adjacent first portions and the third portions are separated by one sub-pixel region between the orthographic projections of the first substrate.

3. The array substrate according to claim 2, characterized in that: The third part is connected to two of the second parts respectively.

4. The array substrate according to claim 2, characterized in that: The first signal line further includes a plurality of fourth portions; two ends of the fourth portion are respectively connected to the third portion and the first portion; The orthographic projection of the fourth portion on the first base substrate is located in the wiring area between two adjacent sub-pixel areas in the second direction; In the first direction, the second portion and the fourth portion connected to the first portion are respectively located at both sides of the first portion.

5. The array substrate according to claim 4, characterized in that: Two of the first portions connected to at least some of the second portions are separated by n sub-pixel regions in the first direction, where n is an integer greater than 1; The second part includes: n first sub-parts, and n-1 second sub-parts; the first sub-parts correspond to the sub-pixel area; The fourth part includes: a third sub-part; The first sub-portion and the third sub-portion extend along the first direction, and the extension direction of the second sub-portion intersects both the first direction and the second direction; The second sub-portion connects two of the first sub-portions, and the n first sub-portions included in the second portion are located on different straight lines in the first direction; In the second direction, the first subsection is adjacent to the third subsection.

6. The array substrate according to claim 5, characterized in that: The array substrate further comprises a plurality of thin film transistors, a plurality of scan lines and a plurality of first electrodes; the thin film transistors comprise: a first electrode, a second electrode and a third electrode; the first electrode is electrically connected to the scan line, and the third electrode is electrically connected to the first signal line; the plurality of thin film transistors comprise a plurality of first thin film transistors and a plurality of second thin film transistors; The scanning line comprises a plurality of strip electrode lines; the plurality of strip electrode lines are alternately arranged and electrically connected with the plurality of first electrodes corresponding to the scanning line; in the second direction, the width of the first electrode is greater than the width of the strip electrode line; the orthographic projections of the second electrode and the third electrode on the first substrate overlap with the orthographic projection of the first electrode on the first substrate; The strip electrode line and the edge of the first electrode facing away from the first electrode are located in the same straight line; The second electrode of the first thin film transistor reuses the third sub-portion, and the second electrode of the second thin film transistor reuses the first sub-portion.

7. The array substrate according to claim 6, characterized in that: The sub-pixel area and the wiring area are divided into: a plurality of sub-pixel rows and wiring area rows arranged along the second direction and extending along the first direction, and a plurality of sub-pixel columns extending along the second direction and arranged along the first direction; the sub-pixel rows and the wiring area rows are arranged alternately; The plurality of thin film transistors corresponding to the wiring area row in the i-th row are divided into a plurality of first repeating unit groups, and the plurality of thin film transistors corresponding to the wiring area row in the (i+1)-th row are divided into a plurality of second repeating unit groups; i is a positive integer; The first repeating unit group includes m first units and k second units, and the second repeating unit group includes k first units and m second units; wherein m and k are both positive integers and m and k are not equal; In the first row of the wiring area row and the last row of the wiring area row, the first unit includes one first thin film transistor and the second unit includes one second thin film transistor; In the remaining wiring area rows except the first row of the wiring area rows and the last row of the wiring area rows, the first unit includes two first thin film transistors corresponding to different sub-pixel rows and corresponding to different sub-pixel columns, and the second unit includes two second thin film transistors corresponding to different sub-pixel rows and corresponding to different sub-pixel columns; In the second direction, the first units and the second units are arranged alternately.

8. The array substrate according to claim 7, characterized in that: m=2, k=1; In the first direction, in the remaining wiring area rows except the first row of the wiring area rows and the last row of the wiring area rows, in adjacent first units and second units, the first thin film transistor and the second thin film transistor located in adjacent sub-pixel columns correspond to the same sub-pixel row; The plurality of scan lines include a plurality of first scan lines and a plurality of second scan lines; in the second direction, the first scan lines and the second scan lines are arranged alternately; The wiring area row between two adjacent sub-pixel rows includes the first scan line and the second scan line; In the i-th row of the wiring area, among the plurality of thin film transistors electrically connected to the second scan line, two adjacent first thin film transistors are spaced apart by one sub-pixel column, the second thin film transistor and the first thin film transistor adjacent to it in the positive direction of the first direction are located in adjacent sub-pixel columns, and the second thin film transistor and the first thin film transistor adjacent to it in the negative direction of the first direction are spaced apart by two sub-pixel columns; In the i-th row of the wiring area, among the plurality of thin film transistors electrically connected to the first scan line, two adjacent first thin film transistors are spaced apart by one sub-pixel column, the second thin film transistor and the first thin film transistor adjacent to it in the negative direction of the first direction are located in adjacent sub-pixel columns, and the second thin film transistor and the first thin film transistor adjacent to it in the positive direction of the first direction are spaced apart by two sub-pixel columns; In the row of the wiring area in the i+1th row, among the plurality of thin film transistors electrically connected to the second scan line, two adjacent second thin film transistors are spaced apart by one sub-pixel column, the first thin film transistor and the second thin film transistor adjacent to it in the positive direction of the first direction are located in adjacent sub-pixel columns, and the first thin film transistor and the second thin film transistor adjacent to it in the negative direction of the first direction are spaced apart by two sub-pixel columns; In the i+1th row of the wiring area, among the plurality of thin film transistors electrically connected to the first scanning line, two adjacent second thin film transistors are separated by one sub-pixel column, the first thin film transistor and the second thin film transistor adjacent to it in the negative direction of the first direction are located in adjacent sub-pixel columns, and the first thin film transistor and the second thin film transistor adjacent to it in the positive direction of the first direction are separated by two sub-pixel columns.

9. The array substrate according to claim 8, characterized in that: In the i-th row of the wiring area, in the adjacent first unit and the second unit, the first thin film transistor and the second transistor electrically connected to the same first signal line are separated by one sub-pixel column; in two adjacent first units, the two first thin film transistors electrically connected to the same first signal line are separated by two sub-pixel columns; In the i+1th row of the wiring area, in adjacent first units and second units, the first thin film transistor and the second thin film transistor electrically connected to the same first signal line are separated by one sub-pixel column; in two adjacent first units, the two first thin film transistors electrically connected to the same first signal line are located in adjacent sub-pixel columns.

10. The array substrate according to claim 9, characterized in that: In the i-th row of the wiring areas, the fourth sub-portion and the second sub-portion extend along the third direction, and the fifth sub-portion extends along the fourth direction; In the row of the wiring areas in the (i+1)th row, the fourth sub-portion and the second sub-portion extend along the fourth direction, and the fifth sub-portion extends along the third direction; The angle between the third direction and the positive direction of the first direction is greater than 90° and less than 180°, and the angle between the fourth direction and the positive direction of the first direction is greater than 0° and less than 90°.

11. The array substrate according to any one of claims 6 to 10, characterized in that: The third electrode includes: a first sub-electrode, a second sub-electrode and a third sub-electrode; The second sub-electrode connects the first sub-electrode and the third sub-electrode, and the orthographic projections of the first sub-electrode and the third sub-electrode on the first substrate are strips extending along the first direction; in the first direction, the width of the second sub-electrode is smaller than the length of the first sub-electrode and the length of the third sub-electrode; In the second direction, the first sub-electrode is arranged opposite to the second electrode, the orthographic projection of the first sub-electrode on the first substrate overlaps with the orthographic projection of the first electrode on the first substrate, the orthographic projection of the third sub-electrode on the first substrate overlaps with the orthographic projection of the first electrode on the first substrate, and the first electrode is electrically connected to the third sub-electrode.

12. The array substrate according to any one of claims 4 to 10, characterized in that: The orthographic projections of the second portion and the fourth portion on the first substrate fall within a region between two adjacent scanning lines in the wiring region and are within the orthographic projection of the first substrate.

13. The array substrate according to any one of claims 1 to 10, characterized in that: The array substrate further comprises: a second electrode located on a side of the first signal line away from the first base substrate, and a plurality of second signal lines electrically connected to the second electrode; The second signal line includes: a plurality of fifth portions and a plurality of sixth portions; the fifth portions and the sixth portions are alternately arranged and electrically connected; An orthographic projection of a portion of the fifth portion on the first substrate is located in the wiring area between two adjacent sub-pixel areas in the first direction; The orthographic projection of the sixth portion on the first base substrate is located in the wiring region between two adjacent sub-pixel regions in the second direction, and the two fifth portions connected by the sixth portion are located in different columns in the second direction.

14. The array substrate according to claim 13, characterized in that: The shape of the pattern of the second signal line on the first base substrate is the same as the shape of the pattern of the plurality of first portions and the plurality of second portions of the first signal line on the first base substrate; The orthographic projection of the fifth portion on the first substrate is adjacent to the orthographic projection of the first portion on the first substrate, and the orthographic projection of the fifth portion on the first substrate does not overlap with the orthographic projection of the first portion on the first substrate.

15. A display panel, characterized in that: The display panel comprises: the array substrate according to any one of claims 1 to 14, an opposite substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the opposite substrate.

16. A display device, characterized in that: The display device comprises the display panel according to claim 15 .

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