Photoetching machine exposure method, photoetching equipment and storage medium

Abstract

The invention discloses a photoetching machine exposure method, photoetching equipment, a storage medium, a vertical measurement correction amount calculation method, a device, equipment and a medium, the relative offset error of the vertical height of a silicon wafer is obtained through measurement and calculation, the optimized surface height of the silicon wafer is calculated according to the relative offset error, and the vertical measurement correction amount of the silicon wafer is calculated. And carrying out photoetching operation by taking the optimized surface height of the silicon wafer as a reference. According to the method, the problems of high equipment cost and low measurement speed in relative offset error calculation in the prior art are solved, the vertical height measurement value of the processed silicon wafer is compensated through the correction values obtained through calculation, the measurement precision is improved, and the product yield of the exposure process of the photoetching machine is further improved.

Description

Technical Field

[0001] The present invention relates to the field of photolithography technology, and in particular to a photolithography machine exposure method, photolithography equipment and storage medium. Background Art

[0002] During the photolithography process, it is generally necessary to vertically measure the surface height fluctuations of the substrate silicon wafer in order to control the height of the mask plate at an equal distance from the substrate silicon wafer, so as to focus and control the exposure of the substrate silicon wafer. Currently, the triangulated optical ranging method is mainly used to measure the vertical height of the substrate silicon wafer. However, there is a problem that when there is a patterned figure on the surface of the substrate silicon wafer, that is, the substrate silicon wafer has undergone one or more processing steps, the reflectivity and absolute height of the substrate silicon wafer surface are different from those of the unprocessed substrate silicon wafer, and the reflectivity and absolute height of each area on the substrate surface will also be different, which will affect the accuracy of the vertical height of the substrate silicon wafer measured by the triangulated optical ranging method and reduce the product yield.

[0003] Therefore, it is necessary to propose a solution that can solve the above problems. Summary of the invention

[0004] The present invention provides a lithography machine exposure method, lithography equipment and medium, which can obtain the relative offset error of the vertical height of a silicon wafer through measurement and calculation methods, and then obtain the optimized silicon wafer surface height, and perform lithography operations with the optimized silicon wafer surface height. By calculating various correction amounts, the vertical height measurement value of the processed silicon wafer is compensated, thereby improving the measurement accuracy and the product yield.

[0005] According to a first aspect of the present invention, there is provided a lithography machine exposure method, comprising the following steps:

[0006] The relative offset error of the vertical height of the silicon wafer is obtained by measuring and calculating;

[0007] Calculating and obtaining an optimized silicon wafer surface height according to the relative offset error;

[0008] The photolithography operation is performed based on the optimized silicon wafer surface height.

[0009] Optionally, obtaining the relative offset error of the vertical height of the silicon wafer by measuring and calculating specifically comprises the following steps:

[0010] Control the workpiece table to move in the vertical direction;

[0011] Each time the workpiece stage is at a height, obtaining a vertical measurement height of at least one point on the surface of the silicon wafer;

[0012] The relative offset error is calculated according to the vertical measurement height of each point measured after each vertical movement of the workpiece stage.

[0013] Optionally, the calculating the relative offset error according to the vertical measurement height of each point measured after each vertical movement of the workpiece stage specifically includes:

[0014] Obtaining the vertical measurement heights of multiple points on the silicon wafer at at least two heights;

[0015] Obtaining a first preset relationship by a measurement and calibration method, wherein the first preset relationship is a relationship expression between the vertical measurement height and the vertical correction height of each point;

[0016] Obtaining gain correction factors at different points by differences in the first preset relationships at different points;

[0017] Converting the vertical measured height into a vertical corrected height expression;

[0018] Substituting the vertical measurement height into the vertical correction height expression to obtain the vertical correction height;

[0019] Separating the vertical correction height from the silicon wafer upper surface height and the chip processing technology characteristics at at least one height to obtain the influence of the silicon wafer upper surface height and the chip processing technology characteristics on the height;

[0020] The relative height correction amount in the influence of the chip processing technology characteristics on the height is the relative offset error.

[0021] Optionally, the vertical correction height corresponding to each of the vertical measurement heights corresponding to each point on the silicon wafer satisfies the following relationship:

[0022] z cal =f -1 (βz raw )-wn;

[0023] Among them, z raw represents the vertical measurement height, z cal represents the vertical correction height, β represents the gain correction factor, and f -1 represents the inverse relationship of the first preset corresponding relationship, and wn represents noise.

[0024] Optionally, in the separate calculation of the silicon wafer upper surface height and the chip processing technology characteristics, each vertical correction height corresponding to each point satisfies the following relationship:

[0025] z cal =z wafer +z process

[0026] Among them, z cal represents the vertical correction height, z wafer Indicates the height of the silicon wafer top surface, zprocess Represents the impact of chip processing characteristics on height.

[0027] z process =z ro +offset

[0028] Among them, z ro Represents the relative offset error, and offset represents the absolute offset error.

[0029] The vertical measurement height of any point on the surface of the silicon wafer at two or more different heights of the workpiece stage and the gain correction factor satisfy the following relationship:

[0030] f -1 (βz raw,2 )-f -1 (βz raw,1 ) = Δz;

[0031] Among them, z raw,1 represents the first vertical measurement height measured by the measurement system when the workpiece stage is at the first height, z raw,2 represents the second vertical measurement height measured by the measurement system when the workpiece stage is at the second height, β represents the gain correction factor, and f -1 is the inverse relationship of the first preset relationship, and Δz is the height difference between the first height and the second height.

[0032] The first preset relationship is obtained by the measurement and calibration method, and the first preset relationship is a relationship expression between the vertical measurement height and the vertical correction height of each point, which specifically includes:

[0033] The first preset corresponding relationship is, on an original silicon wafer without a photolithography pattern, a corresponding relationship between the vertical measurement height and the vertical correction height of any point on the surface of the silicon wafer;

[0034] The first preset relationship is calibrated by the following steps, including:

[0035] Controlling the workpiece table to move vertically;

[0036] Each time the workpiece stage is at a height, obtaining the vertical measured height and the vertical true height of at least one point on the surface of the silicon wafer;

[0037] According to the vertical measurement height and the vertical true height obtained each time, a corresponding relationship between each vertical measurement height and each vertical true height is established through a modeling method.

[0038] The step of calculating the optimized silicon wafer surface height specifically includes:

[0039] The optimized silicon wafer surface height is calculated by the following formula;

[0040] z wafer1 :f -1 (βz raw )-z ro -offset where z wafer1 is the optimized silicon wafer surface height, z raw is the vertical measurement height, β is the gain correction factor, and f -1 is the inverse relationship of the first preset relationship, z ro is the relative offset error, and offset is the absolute offset error.

[0041] The step of calculating the optimized silicon wafer surface height specifically includes:

[0042] After separating the vertical correction height into the silicon wafer upper surface height and the chip processing process characteristics at at least one height, the optimized silicon wafer surface height is obtained by the following decomposition formula:

[0043]

[0044] Among them, z wafer1 is the optimized silicon wafer surface height, Zer i represents a set of decomposition polynomials, such as Zernike decomposition polynomials, Legendre decomposition polynomials, etc.; α i are the polynomial coefficients.

[0045] According to a second aspect of the present invention, there is provided a lithographic apparatus, wherein the lithographic apparatus comprises:

[0046] Radiation systems, mask stages, workpiece stages, projection systems, measurement systems and electronics;

[0047] The electronic device comprises at least one processor; and a memory in communication connection with the at least one processor; wherein,

[0048] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the lithography machine exposure method as claimed in claim 1.

[0049] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to implement the aforementioned lithography machine exposure method when executed by a processor.

[0050] The technical solution of the embodiment of the present invention controls the workpiece stage to move in the vertical direction, and obtains the vertical measurement height of at least one point on the surface of the silicon wafer every time the workpiece stage is at a height, and then calculates the relative offset error and the gain correction factor according to the vertical measurement height of each point measured after each vertical movement of the workpiece stage, thereby solving the problems of calculating the relative offset error, high equipment cost and slow measurement speed in the related art. By calculating and obtaining each correction amount, the vertical height measurement value of the processed silicon wafer can be compensated, thereby improving the measurement accuracy and further improving the product yield of the exposure process of the lithography machine.

[0051] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 is a flow chart of a photolithography machine exposure method proposed in an embodiment of the present invention;

[0054] Figure 2 is a flow chart of a method for calculating a vertical measurement correction amount in lithography proposed in an embodiment of the present invention;

[0055] Figure 3-Figure 5 is the relative offset error z obtained by simulation using the calculation method in the embodiment of the present invention. ro The simulation diagram of Fig.

[0056] Figure 6 It is a schematic diagram of the structure of the electronic equipment in the lithography equipment proposed in an embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0059] Figure 1 1 is a flow chart of the exposure method of the photolithography machine proposed in the embodiment of the present invention. Figure 1 As shown, the method comprises the following steps:

[0060] S101, obtaining a relative offset error of a vertical height of a silicon wafer by measuring and calculating;

[0061] S102, calculating and obtaining an optimized silicon wafer surface height according to the relative offset error;

[0062] S103, performing photolithography operation based on the optimized silicon wafer surface height.

[0063] The method obtains the relative offset error of the vertical height of the silicon wafer by measuring and calculating, which solves the problems of calculating the relative offset error, high equipment cost and slow measurement speed in the related technology. The various correction amounts obtained by calculation are used to compensate the vertical height measurement value of the processed silicon wafer, thereby improving the measurement accuracy and further improving the product yield of the lithography machine exposure process.

[0064] Figure 2 1 is a flowchart of the specific steps of measuring and calculating the relative offset error of the vertical height of the silicon wafer in an embodiment of the present invention. Figure 2 As shown, the specific steps include the following steps:

[0065] S1011, controlling the workpiece table to move in the vertical direction;

[0066] S1012, obtaining a vertical measurement height of at least one point on the surface of the silicon wafer each time the workpiece stage is at a height;

[0067] S1013, calculating the relative offset error according to the vertical measurement height of each point measured after each vertical movement of the workpiece stage.

[0068] In an optional embodiment, S1013 calculates the relative offset error according to the vertical measurement height of each point measured after each vertical movement of the workpiece stage, specifically including:

[0069] S10131, obtaining the vertical measurement heights of multiple points on the silicon wafer at at least two heights;

[0070] S10132, obtaining a first preset relationship through a measurement and calibration method, wherein the first preset relationship is a relationship expression between the vertical measurement height and the vertical correction height of each point;

[0071] S10133, obtaining gain correction factors of different points by differences of the first preset relationships at different points;

[0072] S10134, converting the vertical measurement height into a vertical correction height expression;

[0073] S10135, substituting the vertical measurement height into the vertical correction height expression to obtain the vertical correction height;

[0074] S10136, separating the vertical correction height from the silicon wafer upper surface height and the chip processing technology characteristics at at least one height to obtain the influence of the silicon wafer upper surface height and the chip processing technology characteristics on the height;

[0075] The relative height correction amount in the influence of the chip processing technology characteristics on the height is the relative offset error.

[0076] Specifically, when the workpiece stage is at a first height, the control measurement system sequentially traverses and scans the silicon wafer to obtain a first set of vertical measurement heights of each point on the surface of the silicon wafer; then, the workpiece stage is controlled to move a certain distance vertically, and the control measurement system sequentially traverses and scans different areas of the silicon wafer to obtain a second set of vertical measurement heights of each point on the surface of the silicon wafer; and so on, multiple sets of vertical measurement heights of each point on the surface of the silicon wafer when the workpiece stage is at different heights can be obtained.

[0077] In an optional embodiment, the vertical correction height corresponding to each of the vertical measurement heights corresponding to each point on the silicon wafer satisfies the following relationship:

[0078] z cal =f -1 (βz raw )-wn;

[0079] Among them, z raw represents the vertical measurement height, z cal represents the vertical correction height, β represents the gain correction factor, and f -1represents the inverse relationship of the first preset corresponding relationship, wn represents noise, wherein the gain correction factor is the reciprocal of the ratio of the change rate of the measured height of the photolithographic pattern on a silicon wafer to the measured height of the silicon wafer without photolithographic pattern at the same position.

[0080] In another optional embodiment, in the separate calculation of the silicon wafer upper surface height and the chip processing technology characteristics, each vertical correction height corresponding to each point satisfies the following relationship:

[0081] z cal =z wafer +z process

[0082] Among them, z cal represents the vertical correction height, z wafer Indicates the height of the silicon wafer top surface, z process Represents the impact of chip processing characteristics on height.

[0083] z process =z ro +offset

[0084] Among them, z ro Represents the relative offset error, and offset represents the absolute offset error.

[0085] The absolute offset error refers to the absolute position of the silicon wafer that is independent of the historical processing technology of the silicon wafer and is related to the current process such as the silicon wafer clamping position. The relative offset error is the vertical height correction deviation on a silicon wafer that is related to the historical processing technology and the lithography pattern. The sum of the relative offset error and the absolute offset error together constitutes the impact of the silicon wafer processing technology on the vertical correction height of the silicon wafer. In addition, z ro , β are both spatial periodic functions, and the period is the size of an exposure field.

[0086] In another optional embodiment, the vertical measurement height of any point on the silicon wafer surface at two or more different heights of the workpiece stage and the gain correction factor satisfy the following relationship:

[0087] f -1 (βz raw,2 )-f -1 (βz raw,1 ) = Δz;

[0088] Among them, z raw,1 represents the first vertical measurement height measured by the measurement system when the workpiece stage is at the first height, z raw,2 represents the second vertical measurement height measured by the measurement system when the workpiece stage is at the second height, β represents the gain correction factor, and f -1is the inverse relationship of the first preset relationship, and Δz is the height difference between the first height and the second height. After the first preset relationship f has been calibrated, multiple sets of z have been measured and obtained. raw After Δz and Δz, the gain correction factor β can be obtained according to this relationship.

[0089] In addition, this method can be used for processing and calculating measurement results at more altitudes.

[0090] In an optional embodiment, a first preset relationship is obtained by a measurement and calibration method, and the first preset relationship is a relationship expression between the vertical measurement height and the vertical correction height of each point, which specifically includes:

[0091] The first preset corresponding relationship is, on an original silicon wafer without a photolithography pattern, a corresponding relationship between the vertical measurement height and the vertical correction height of any point on the surface of the silicon wafer;

[0092] The first preset relationship is calibrated by the following steps, including:

[0093] Controlling the workpiece table to move vertically;

[0094] Each time the workpiece stage is at a height, obtaining the vertical measured height and the vertical true height of at least one point on the surface of the silicon wafer;

[0095] According to the vertical measurement height and the vertical true height obtained each time, a corresponding relationship between each vertical measurement height and each vertical true height is established by a modeling method, wherein the modeling method may be polynomial regression modeling.

[0096] In addition, the vertical true height can be obtained by other means different from the measurement system, such as by an interferometer. Finally, a polynomial fitting is performed through multiple sets of vertical measurement heights and multiple sets of vertical true heights when the workpiece stage is located at different heights to obtain the first preset corresponding relationship f.

[0097] In other embodiments, other fitting methods may also be used to obtain. In actual use, the first preset corresponding relationship f may be pre-stored in the processor of the device in advance and directly called during calculation.

[0098] In an optional embodiment, the optimized silicon wafer surface height can be obtained by the following method:

[0099] The optimized silicon wafer surface height can be calculated by the following formula;

[0100] z wafer1 :f -1 (βz raw )-z ro -offset

[0101] Among them, z wafer1 is the optimized silicon wafer surface height, z raw is the vertical measurement height, β is the gain correction factor, and f -1 is the inverse relationship of the first preset relationship, z ro is the relative offset error, and offset is the absolute offset error.

[0102] In addition, in another optional embodiment, after separating the vertical correction height into the silicon wafer upper surface height and the chip processing process characteristics at at least one height, the optimized silicon wafer surface height is obtained by the following decomposition formula:

[0103]

[0104] Among them, z wafer1 is the optimized silicon wafer surface height, Zer i represents a set of decomposition polynomials, such as Zernike decomposition polynomials, Legendre decomposition polynomials, etc.; α i are the polynomial coefficients.

[0105] After solving the optimized silicon wafer surface height, performing lithography operations based on the optimized silicon wafer surface height can improve vertical control accuracy and lithography quality.

[0106] In summary, the calculation method proposed in the embodiment of the present invention can decompose the vertical correction height into the silicon wafer surface morphology part and the chip processing part, and calculate the gain correction factor β and the relative offset error z in the photolithography process through the measured multiple groups of vertical measurement heights and the first preset relationship. ro These correction values ​​can be used to correct the vertical height measurement value, optimize the vertical control of lithography, and improve the lithography quality and yield.

[0107] Figure 3 , 4 5 is the relative offset error z obtained by simulation using the calculation method in the embodiment of the present invention ro The simulation diagram of Fig. Figure 3 Is Figure 4 The original relative offset error z ro , the vertical relative offset error z obtained by the algorithm in this paper is ro result. Figure 4 is the original offset error z used in the simulation ro picture; Figure 5 yes Figure 3 The relative offset error z ro , Figure 4 The original relative offset error z in roFigure 2 is a schematic diagram of the residuals of the two.

[0108] from Figure 5 It can be seen that the relative offset error z calculated by the above calculation method is ro and the true relative offset error z ro The difference between the two is basically between -20 and 20. Figure 4 The true relative offset error z ro The difference is relatively small, so this method can better separate and calculate the true relative offset error. Figure 3 , Figure 4 and Figure 5 0-60 and 0-80 represent the wafer area (x, y). The right side of each picture is a grayscale bar, and the grayscale represents the relative offset error z ro The value of .

[0109] Figure 6 : is a schematic diagram of the structure of an electronic device in a lithography device according to an embodiment of the present invention. The lithography device includes:

[0110] Radiation systems, mask stages, workpiece stages, projection systems, measurement systems and electronics;

[0111] like Figure 6 As shown, the electronic device includes at least one processor; and a memory connected to the at least one processor in communication; wherein,

[0112] The memory stores a computer program executable by at least one processor, and the computer program is executed by at least one processor so that the at least one processor can execute the method for calculating the vertical measurement correction amount in lithography proposed in any embodiment of the present invention.

[0113] An embodiment of the present invention further proposes a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method for calculating the vertical measurement correction amount in lithography proposed in any embodiment of the present invention when executed.

[0114] Figure 6 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0115] like Figure 6 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0116] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0117] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a method for calculating a vertical measurement correction amount in lithography.

[0118] In some embodiments, the method for calculating the vertical measurement correction amount in lithography can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the method for calculating the vertical measurement correction amount in lithography described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the method for calculating the vertical measurement correction amount in lithography by any other appropriate means (for example, by means of firmware).

[0119] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, at least one input device, and at least one output device.

[0120] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0121] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0122] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0123] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0124] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0125] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0126] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A photolithography exposure method, characterized in that: The following steps are involved: The relative offset error of the vertical height of the silicon wafer is obtained by measuring and calculating; Calculating and obtaining an optimized silicon wafer surface height according to the relative offset error; The photolithography operation is performed based on the optimized silicon wafer surface height.

2. The lithography exposure method according to claim 1, characterized in that: The step of obtaining the relative offset error of the vertical height of the silicon wafer by measuring and calculating specifically comprises the following steps: Control the workpiece table to move in the vertical direction; Each time the workpiece stage is at a height, obtaining a vertical measurement height of at least one point on the surface of the silicon wafer; The relative offset error is calculated according to the vertical measurement height of each point measured after each vertical movement of the workpiece stage.

3. The photolithography exposure method according to claim 2, characterized in that: The step of calculating the relative offset error according to the vertical measurement height of each point measured after each vertical movement of the workpiece table specifically includes: Obtaining the vertical measurement heights of multiple points on the silicon wafer at at least two heights; Obtaining a first preset relationship by a measurement and calibration method, wherein the first preset relationship is a relationship expression between the vertical measurement height and the vertical correction height of each point; Obtaining gain correction factors at different points by differences in the first preset relationships at different points; Converting the vertical measured height into a vertical corrected height expression; Substituting the vertical measurement height into the vertical correction height expression to obtain the vertical correction height; Separating the vertical correction height from the silicon wafer upper surface height and the chip processing technology characteristics at at least one height to obtain the influence of the silicon wafer upper surface height and the chip processing technology characteristics on the height; The relative height correction amount in the influence of the chip processing technology characteristics on the height is the relative offset error.

4. The photolithography exposure method according to claim 3, characterized in that: The vertical correction height corresponding to each of the vertical measurement heights corresponding to each point on the silicon wafer satisfies the following relationship: z cal =f -1 (βz raw )-w.n.; Among them, z raw represents the vertical measurement height, z cal represents the vertical correction height, β represents the gain correction factor, and f -1 represents the inverse relationship of the first preset corresponding relationship, and wn represents noise.

5. The photolithography exposure method according to claim 4, characterized in that: In the separate calculation of the silicon wafer upper surface height and the chip processing technology characteristics, the vertical correction heights corresponding to the points satisfy the following relationship: With cal =from wafer +from process Among them, z cal represents the vertical correction height, z wafer Indicates the height of the silicon wafer top surface, z process Represents the impact of chip processing characteristics on height. With process =from ro +offset Among them, z ro Represents the relative offset error, and offset represents the absolute offset error.

6. The photolithography exposure method according to claim 5, characterized in that: The vertical measurement height of any point on the silicon wafer surface at two or more different heights of the workpiece stage and the gain correction factor satisfy the following relationship: f -1 (bz raw,2 )-f -1 (bz raw,1 )=Δz; Among them, z raw,1 represents the first vertical measurement height measured by the measurement system when the workpiece stage is at the first height, z raw,2 represents the second vertical measurement height measured by the measurement system when the workpiece stage is at the second height, β represents the gain correction factor, and f -1 is the inverse relationship of the first preset relationship, and Δz is the height difference between the first height and the second height.

7. The photolithography exposure method according to claim 3, characterized in that: The first preset relationship is obtained by the measurement and calibration method, and the first preset relationship is a relationship expression between the vertical measurement height and the vertical correction height of each point, which specifically includes: The first preset corresponding relationship is, on an original silicon wafer without a photolithography pattern, a corresponding relationship between the vertical measurement height and the vertical correction height of any point on the surface of the silicon wafer; The first preset relationship is calibrated by the following steps, including: Controlling the workpiece table to move vertically; Each time the workpiece stage is at a height, obtaining the vertical measured height and the vertical true height of at least one point on the surface of the silicon wafer; According to the vertical measurement height and the vertical true height obtained each time, a corresponding relationship between each vertical measurement height and each vertical true height is established through a modeling method.

8. The photolithography exposure method according to claim 6, characterized in that: The step of calculating the optimized silicon wafer surface height specifically includes: The optimized silicon wafer surface height is calculated by the following formula; z wafer1 :f -1 (βz raw )-z ro -offset where z wafer1 is the optimized silicon wafer surface height, z raw is the vertical measurement height, β is the gain correction factor, and f -1 is the inverse relationship of the first preset relationship, z ro is the relative offset error, and offset is the absolute offset error.

9. The photolithography exposure method according to claim 6, characterized in that: The step of calculating the optimized silicon wafer surface height specifically includes: After separating the vertical correction height into the silicon wafer upper surface height and the chip processing process characteristics at at least one height, the optimized silicon wafer surface height is obtained by the following decomposition formula: Among them, z wafer1 is the optimized silicon wafer surface height, Zer i represents a set of factorized polynomials; α i are the polynomial coefficients.

10. A lithography apparatus, characterized in that: The lithography apparatus comprises: Radiation systems, mask stages, workpiece stages, projection systems, measurement systems and electronics; The electronic device comprises at least one processor; and a memory in communication connection with the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the lithography machine exposure method according to any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the lithography machine exposure method according to any one of claims 1 to 9 when executed.

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