CAN bus message sending method and system

Abstract

The invention discloses a CAN bus message sending method and system. The method comprises the following steps: an upper computer sends a linked list message to a programmable logic device, wherein the linked list message comprises a CAN bus message; the programmable logic device stores the linked list message in a static access memory; after a CAN bus message sending command is obtained, the programmable logic device reads the linked list message in the static access memory; analyzing the linked list message to generate an analysis result; and executing a corresponding operation according to the analysis result so as to realize the transmission of the CAN bus message. According to the CAN bus message sending method and system, accurate time control, flexible message scheduling and efficient message transmission can be realized, and the CAN bus message sending method and system have the advantages of being high in real-time performance, high in stability, flexible in scheduling, small in burden of an upper computer and the like.

Description

Technical Field

[0001] The present disclosure relates to the field of computer information processing, and in particular to a CAN bus message sending method and system. Background Art

[0002] In traditional CAN bus systems, the sending time of messages is mainly controlled by software timing. However, software timing is affected by the interference of other tasks in the system and the scheduling mechanism of the operating system, and cannot guarantee the precise time control of message sending. Especially when the system load is high, software timing is prone to jitter, resulting in uneven message sending intervals. This will cause serious problems in scenarios with high real-time requirements, such as engine control, transmission control and safety systems (such as ABS and airbags) in automotive electronic systems, which require time intervals accurate to microseconds to ensure system stability and safety.

[0003] Although some real-time operating systems (RTOS) can improve the timing accuracy of messages to a certain extent, it is still difficult to achieve time interval control accurate to within 1 millisecond due to the overhead of the operating system itself and the scheduling of other parallel tasks. In high-load or complex environments, time delay or jitter will increase significantly, and may even affect the overall performance of the system, making it impossible to meet strict time control requirements.

[0004] Similarly, in fields such as aerospace and medical equipment that require extremely high safety and reliability, communication delays or timing jitter may cause system failures or even serious consequences. These applications usually require message intervals to be accurate to microseconds or even smaller time units, and the traditional CAN bus message sending method cannot meet this high-precision requirement because it relies on software and processor performance.

[0005] Therefore, a new CAN bus message sending method and system is needed.

[0006] The above information disclosed in the Background section is only for enhancement of understanding of the background of the present application and therefore it may contain information that does not constitute the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0007] In view of this, the present application provides a CAN bus message sending method and system, which can achieve precise time control, flexible message scheduling and efficient message transmission, and has the advantages of strong real-time performance, high stability, flexible scheduling and small burden on the host computer.

[0008] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0009] According to one aspect of the present application, a CAN bus message sending method is proposed, the method comprising: a host computer sends a linked list message to a programmable logic device, the linked list message including a CAN bus message; the programmable logic device stores the linked list message in a static access memory; after obtaining a CAN bus message sending command, the programmable logic device reads the linked list message in the static access memory; parses the linked list message to generate a parsing result; and executes corresponding operations according to the parsing result to realize the sending of the CAN bus message.

[0010] In an exemplary embodiment of the present application, a host computer sends a linked list message to a programmable logic device, including: determining a data structure of the linked list message; determining data to be sent; the host computer assembles the data to be sent according to the data structure to generate the linked list message; and sending the linked list message to the programmable logic device.

[0011] In an exemplary embodiment of the present application, determining the data to be sent includes: determining a message time interval; and / or determining control data; and / or determining a CAN bus message to be sent.

[0012] In an exemplary embodiment of the present application, the host computer assembles the data to be sent according to the data structure to generate the linked list message, including: determining the message scheduling order; generating the next message address based on the message scheduling order; the host computer generates the linked list message based on the data structure by assembling the data to be sent and its corresponding next message address.

[0013] In an exemplary embodiment of the present application, before the programmable logic device stores the linked list message in the static access memory, the method further includes: determining the data width and data depth of the static access memory according to the data structure of the linked list message.

[0014] In an exemplary embodiment of the present application, obtaining a CAN bus message sending command includes: obtaining a CAN bus message sending command sent by a host computer.

[0015] In an exemplary embodiment of the present application, corresponding operations are performed according to the analysis results to realize the sending of CAN bus messages, including: obtaining the message time interval and the CAN bus message from the analysis results; and calling an external clock based on the message time interval to send the CAN bus message.

[0016] In an exemplary embodiment of the present application, the external clock is called based on the message time interval to send the CAN bus message, including: sending the CAN bus message in the current linked list message; obtaining the address of the next message from the parsing result; and obtaining the subsequent linked list message from the next message address based on the message time interval to perform the corresponding operation.

[0017] In an exemplary embodiment of the present application, corresponding operations are performed according to the analysis results to realize the sending of CAN bus messages, including: obtaining control data from the analysis results; when the status of the control data is valid, the programmable logic device sends an interrupt instruction to the host computer; the host computer sends a new linked list message according to the interrupt instruction.

[0018] In an exemplary embodiment of the present application, corresponding operations are performed according to the analysis results to realize the sending of CAN bus messages, including: obtaining frame attribute data from the analysis results, the frame attribute data including frame format, frame type, frame identifier, and valid byte number; and sending CAN bus messages according to the frame attribute data.

[0019] According to one aspect of the present application, a CAN bus message sending system is proposed, which includes: a host computer, used to send a linked list message to a programmable logic device, wherein the linked list message includes a CAN bus message; and also used to generate a CAN bus message sending command; the programmable logic device, used to store the linked list message in a static access memory; after obtaining the CAN bus message sending command, reading the linked list message in the static access memory; parsing the linked list message to generate a parsing result; executing corresponding operations according to the parsing result to realize the sending of the CAN bus message; and a static access memory, used to store the linked list message.

[0020] According to one aspect of the present application, an electronic device is proposed, which includes: one or more processors; a storage device for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the method as described above.

[0021] According to one aspect of the present application, a computer-readable medium is provided, on which a computer program is stored. When the program is executed by a processor, the method described above is implemented.

[0022] According to the CAN bus message sending method and system of the present application, a linked list message is sent to a programmable logic device through a host computer, and the linked list message includes a CAN bus message; the programmable logic device stores the linked list message in a static access memory; after obtaining a CAN bus message sending command, the programmable logic device reads the linked list message in the static access memory; the linked list message is parsed to generate a parsing result; and corresponding operations are performed according to the parsing result to realize the sending of the CAN bus message. This method can realize accurate time control, flexible message scheduling and efficient message transmission, and has the advantages of strong real-time performance, high stability, flexible scheduling and low burden on the host computer.

[0023] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the present application will become more apparent by describing in detail the exemplary embodiments thereof with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of the present application, and it is clear to a person skilled in the art that other accompanying drawings can be obtained from these accompanying drawings without creative effort.

[0025] Figure 1 The present invention is a system block diagram of a CAN bus message sending system according to an exemplary embodiment.

[0026] Figure 2 The figure is a flow chart of a method for sending a CAN bus message according to an exemplary embodiment.

[0027] Figure 3 The figure is a flow chart of a method for sending a CAN bus message according to another exemplary embodiment.

[0028] Figure 4 The diagram is a schematic diagram of a CAN bus message sending method according to another exemplary embodiment.

[0029] Figure 5 It is a block diagram of an electronic device according to an exemplary embodiment.

[0030] Figure 6 It is a block diagram of a computer-readable medium according to an exemplary embodiment. DETAILED DESCRIPTION

[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0032] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0033] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0034] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0035] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the concepts of the present application. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more.

[0036] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present application, and therefore cannot be used to limit the scope of protection of the present application.

[0037] Figure 1 The present invention is a system block diagram of a CAN bus message sending system according to an exemplary embodiment.

[0038] like Figure 1As shown, the system architecture 10 may include the following components: a host computer, a programmable logic device (FPGA) and a static access memory (SRAM). In order to more clearly illustrate the sending structure of the CAN bus message, Figure 1 The communication connection relationship between the CAN controller and the FPGA, and between the CAN transceiver and the CAN controller is also described by way of example.

[0039] Among them, the host computer and the programmable logic device exchange data through a communication connection, and the communication method can be diverse, such as through network communication or USB communication. During data transmission, the FPGA maintains real-time communication with the host computer to ensure efficient transmission and reception of CAN bus data. In addition, the programmable logic device (FPGA) and the static access memory (SRAM) are connected through a bus, which can specifically include a control bus and a data / address bus to achieve efficient reading and writing of data. The communication connection between the FPGA and the CAN controller can also be achieved through network communication or USB communication to ensure that the linked list message is stable and reliable during the transmission process.

[0040] In the CAN bus message sending system of the present application, the programmable logic device (FPGA) is responsible for data interaction with the host computer. It can send the received CAN bus data back to the host computer and receive the linked list message issued by the host computer. For the data receiving part, the method adopted by the present application is consistent with the common CAN bus communication method, so it will not be repeated here.

[0041] More specifically, in this application:

[0042] The host computer is used to send a linked list message to the programmable logic device, wherein the linked list message includes a CAN bus message; and is also used to generate a CAN bus message sending command;

[0043] In a specific embodiment, the host computer can be used to generate and send a linked list message and control the entire message sending process. The host computer sends the generated linked list message to a programmable logic device (FPGA), and the linked list message contains multiple message data and scheduling information that need to be sent on the CAN bus. In addition, the host computer is also responsible for generating a CAN bus message sending command to start the FPGA to execute the message sending task.

[0044] A programmable logic device is used to store the linked list message in a static access memory; after obtaining a CAN bus message sending command, read the linked list message in the static access memory; parse the linked list message to generate a parsing result; and perform corresponding operations according to the parsing result to realize the sending of the CAN bus message;

[0045] In a specific embodiment, as the core processing unit of the entire system, after receiving the linked list messages sent by the host computer, the FPGA stores these messages in the static access memory (SRAM), and after receiving the send command from the host computer, it starts to read the linked list messages from the SRAM. The FPGA can parse the linked list messages, including parsing the frame format, frame type, number of valid bytes and other information, and generate corresponding parsing results. Based on these parsing results, the FPGA can perform corresponding operations and finally send the CAN bus messages at precise time intervals.

[0046] Static access memory is used to store the linked list messages. After receiving the linked list messages sent by the host computer, the FPGA will save these message data in the SRAM. After the send command is triggered, the FPGA will read the linked list messages from the SRAM in sequence for parsing and processing. In this way, SRAM not only serves as a medium for data storage, but also plays an important supporting role in message scheduling and sending.

[0047] More specifically, after receiving the linked list message sent by the host computer, the programmable logic device (FPGA) stores it in the static random access memory (SRAM). After receiving the start sending command sent by the host computer, it starts to read the linked list from the static random access memory (SRAM) and sends it periodically according to the content of the linked list.

[0048] Figure 2 2 is a flow chart showing a method for sending a CAN bus message according to an exemplary embodiment. The CAN bus message sending method 20 at least includes steps S202 to S210.

[0049] like Figure 2 As shown, in S202, the host computer sends a linked list message to the programmable logic device, wherein the linked list message includes a CAN bus message. For example, the data structure of the linked list message can be determined; the data to be sent can be determined; the host computer assembles the data to be sent according to the data structure to generate the linked list message; and the linked list message can be sent to the programmable logic device.

[0050] More specifically, the host computer can determine the data structure of the linked list message, such as the data format, control bit, address, and time interval of each frame. It can also determine the data to be sent, that is, the specific message to be sent through the CAN bus. The host computer assembles the data to be sent according to the predetermined data structure and finally generates a linked list message. After the linked list message is constructed, the host computer sends the linked list message to the programmable logic device (FPGA) through network communication or USB communication.

[0051] In S204, the programmable logic device stores the linked list message in a static access memory.

[0052] In one embodiment, the method further includes: determining the data width and data depth of the static access memory according to the data structure of the linked list message.

[0053] After receiving the linked list message, the FPGA stores it in a static access memory (SRAM). In a certain embodiment, the data width and data depth of the SRAM can also be determined based on the data structure of the linked list message. For example, the address space occupied by the frame data of the linked list message and the size of each frame message will determine the storage format and resource allocation of the SRAM. This ensures that the data is efficiently stored and subsequently read.

[0054] In a specific embodiment, when the host computer communicates with the programmable logic device (FPGA), each frame message consists of 6 32-bit data. In order to match this data structure, a static random access memory (SRAM) with a data width of 32 bits can be used. In the actual storage process, one frame of data will occupy 6 address spaces of the SRAM, that is, each address position corresponds to 32 bits of data, so 6 consecutive addresses can store a complete frame of messages.

[0055] During the data storage phase, the hardware does not process or interfere with the specific content of the message, that is, the hardware layer does not care about the actual content of the data. The address allocation and specific content of the data are controlled by the host computer, which decides how to arrange the data into different address spaces in the SRAM. Only when it is necessary to read the data and perform operations, the FPGA will parse the read data according to the linked list structure and extract the necessary control information, frame attributes and sending schedule.

[0056] More specifically, in the data structure, each frame of data has a 16-bit field that indicates the address of the next message. Since this field can represent an address range of 0x0000 to 0xFFFF, a linked list message can support up to 65536 messages. Each message will occupy 6 address spaces, so in order to store such a large number of messages, the capacity of the SRAM needs to be large enough.

[0057] To meet these requirements, the depth of the SRAM used in the present invention is calculated as follows: each frame message requires 6 address spaces to store data, and a maximum of 65536 messages need to be supported. Therefore, the minimum depth of the SRAM should be 393216 address spaces, that is, a minimum storage space of 384K is required.

[0058] Through this design, FPGA can flexibly process large amounts of message data, realize large-scale message scheduling, and ensure real-time and accuracy through efficient storage management and parsing mechanisms.

[0059] In S206, after obtaining the CAN bus message sending command, the programmable logic device reads the linked list message in the static access memory. More specifically, the CAN bus message sending command sent by the host computer can be obtained.

[0060] When the host computer issues a CAN bus message sending command, the FPGA reads the stored linked list message from the SRAM. In a more specific implementation process, the programmable logic device obtains and responds to the sending command from the host computer to trigger the read operation. This process ensures that the linked list message can be extracted and prepared for sending at the appropriate time.

[0061] In S208, the linked list message is parsed to generate a parsing result. The parsed content includes key information such as the message type, sending time interval, frame attributes, etc. in the linked list message. By parsing these data fields, the FPGA can be fully prepared for message sending and ensure that the message is sent according to the expected scheduling plan.

[0062] In S210, a corresponding operation is performed according to the analysis result to implement the sending of the CAN bus message. The message time interval and the CAN bus message can be obtained from the analysis result; and an external clock is called based on the message time interval to send the CAN bus message.

[0063] According to the CAN bus message sending method of the present application, through a programmable logic device (FPGA) and a linked list message design, precise time interval control for sending messages can be achieved, and the sending interval time can be controlled to within 1 millisecond. Flexible message sending scheduling can be achieved through the linked list message design.

[0064] More specifically, calling an external clock to send the CAN bus message based on the message time interval includes: sending the CAN bus message in the current linked list message; obtaining the address of the next message from the parsing result; and obtaining subsequent linked list messages from the next message address based on the message time interval to perform corresponding operations.

[0065] In a specific embodiment, the CAN bus message in the current linked list message is sent; then, the address of the next message is obtained from the parsing result, and based on the set message time interval, the external clock is called for timed sending. Timed sending can be specifically, for example, after the FPGA sends the current message, it waits for the external clock signal to reach the set time point, and then obtains the subsequent linked list message from the address of the next message, and continues to execute the message sending operation.

[0066] The CAN bus message sending method based on FPGA and linked list messages of the present application can not only significantly improve the time accuracy of message sending, but also effectively reduce the burden on the host computer and improve the real-time performance and flexibility of the entire system.

[0067] In one embodiment, the control data is obtained from the analysis result; when the state of the control data is valid, the programmable logic device sends an interrupt instruction to the host computer; the host computer sends a new linked list message according to the interrupt instruction. When the state of the control data is valid, the FPGA sends an interrupt instruction to the host computer, prompting the host computer to send a new linked list message. According to the prompt of the interrupt instruction, the host computer sends a new linked list message to supplement the message queue, thereby ensuring that subsequent messages can be sent in time.

[0068] In one embodiment, frame attribute data is obtained from the parsing result, the frame attribute data including frame format, frame type, frame identifier, and number of valid bytes; and a CAN bus message is sent according to the frame attribute data.

[0069] In a specific embodiment, the FPGA can obtain frame attribute data through the parsing result, including frame format, frame type, frame identifier and valid byte number. Based on these frame attribute data, the FPGA determines the type and format of the CAN bus message, and then sends the message to the CAN bus according to the correct protocol. For example, if the frame type is a data frame, the FPGA will send the actual data; if the frame type is a request frame, it will send a specific request command.

[0070] According to the CAN bus message sending method of the present application, a linked list message is sent to a programmable logic device through a host computer, and the linked list message includes a CAN bus message; the programmable logic device stores the linked list message in a static access memory; after obtaining a CAN bus message sending command, the programmable logic device reads the linked list message in the static access memory; the linked list message is parsed to generate a parsing result; and corresponding operations are performed according to the parsing result to realize the sending of the CAN bus message. This method can realize precise time control, flexible message scheduling and efficient message transmission, and has the advantages of strong real-time performance, high stability, flexible scheduling and low burden on the host computer.

[0071] It should be clearly understood that the present application describes how to form and use specific examples, but the principles of the present application are not limited to any details of these examples. On the contrary, based on the teaching of the content disclosed in the present application, these principles can be applied to many other embodiments.

[0072] Figure 3 The figure is a flow chart of a method for sending a CAN bus message according to another exemplary embodiment. Figure 3 The process 30 shown is for Figure 2 A detailed description of S202 “the host computer sends the linked list message to the programmable logic device” in the process shown.

[0073] like Figure 3 As shown, in S302, the data structure of the linked list message is determined. The linked list message contains the necessary information for sending the CAN bus message. Figure 4 As described in the description, messages are stored in different address spaces in the static random access memory (SRAM). For example, the interrupt status bit and the next message number address of each frame occupy the address space 0 of the SRAM. Bytes 0 to byte 3 in the frame data occupy the address space 5 of the SRAM. The data of other frames will be stored in the corresponding address space in sequence according to the same rules.

[0074] More specifically, in the data structure of actual application, it can be set as follows:

[0075] In the first frame: [D31:D17] is an invalid bit, D16 is the interrupt status bit, and [D15:D0] is the address of the next message number;

[0076] In the second frame: [D31:D10] is the time interval between the next message, the unit can be 1us;

[0077] In the third frame: D31 is an invalid bit, D30 is the frame format, D29 is the frame type, and [D28:D0] is the frame identifier;

[0078] In the fourth frame: [D31:D4] is an invalid bit, [D3:D0] is the number of valid bytes in the frame;

[0079] In the fifth frame: [D31:D0] is the frame data, from high to low, it is byte 7 to byte 4;

[0080] In the sixth frame: [D31:D0] is the frame data, from high to low, it is byte 3 to byte 0.

[0081] Among them, the main function of the interrupt status bit is to indicate when the host computer needs to send a new message. Whenever the programmable logic device (FPGA) reads a linked list message from the SRAM, it detects whether the interrupt status bit of the current frame is 1. If it is 1, the FPGA will send an interrupt command to the host computer to notify the host computer to prepare a new message. After receiving the command, the host computer sends a new linked list message to the FPGA according to the predetermined data structure.

[0082] The next message number address is used to determine the storage location of the next message in the linked list. The address starts from 0 and ends at 0xFFFE in hexadecimal, which is a valid message address. Whenever a message is sent, the system will parse the next message number address to determine the location of the next message in the linked list. If the next message number address is 0xFFFF, it means that the current frame is the last message and will not be sent any more.

[0083] The frame format defines the type of message: if the frame format is 1, the frame is an extended frame, and 29 bits are used as the frame identifier. If the frame format is 0, the frame is a standard frame, and only 11 bits are used as the valid frame identifier.

[0084] The frame type defines the content of the frame: a frame type of 1 indicates that the frame is a request frame, and a frame type of 0 indicates that the frame is a data frame.

[0085] The number of valid bytes in the frame determines the valid data actually carried in the data frame. For example, if the number of valid bytes in the frame is 2, then byte 0 and byte 1 are valid data, while byte 2 to byte 7 are padding data and are invalid.

[0086] In S304, the data to be sent is determined, for example, the message time interval is determined, for example, the control data is determined, and for example, the CAN bus message to be sent is determined.

[0087] More specifically, the message time interval is used to determine the interval between two messages. The control data can be an interrupt state, which is used to control the order of message transmission and the communication with the host computer. The CAN bus message to be sent is the actual data frame that needs to be transmitted.

[0088] In S306, the host computer assembles the data to be sent according to the data structure to generate the linked list message. For example, the message scheduling order can be determined; the next message address is generated based on the message scheduling order; the host computer generates the linked list message based on the data structure by assembling the data to be sent and the corresponding next message address.

[0089] In S308, the linked list message is sent to the programmable logic device. The host computer sends the generated linked list message to the programmable logic device (FPGA) through a preset communication channel (such as USB or network communication). After receiving the linked list message, the FPGA will store it in a static random access memory (SRAM) and wait for instructions to be sent or for the next step of parsing and scheduling.

[0090] More specifically, the time interval for the next message in the present application is timed by the programmable logic device (FPGA) hardware. Compared with the software timing of the traditional real-time operating system, the programmable logic device (FPGA) is timed according to the external clock input, starting from the start of sending the current message until the next message starts to be sent, and can achieve precise timing in units of 1us, avoiding slow message sending caused by the host computer jam.

[0091] In the actual operation process, the message can be written into the static random access memory (SRAM) in advance, and the time interval between messages can be specified. The host computer will send new data after receiving the interruption, which also reduces the burden on the host computer software. The total length is 32 bits, so the maximum time interval with the next message is (232-1)us.

[0092] The method in the present application cleverly applies the linked list data structure to the communication between the host computer and the programmable logic device (FPGA). The host computer sends data to the programmable logic device (FPGA) according to the linked list data structure. The programmable logic device (FPGA) stores the linked list data in a static random access memory (SRAM). The programmable logic device (FPGA) implements interrupt triggering and timed message sending functions according to key fields such as the interrupt status bit and the next message number address in the linked list data structure, which not only improves the communication efficiency, but also reduces the burden on the host computer and realizes flexible scheduling of messages.

[0093] Those skilled in the art will appreciate that all or part of the steps for implementing the above embodiments are implemented as a computer program executed by a CPU. When the computer program is executed by the CPU, the above functions defined by the above method provided in the present application are executed. The program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0094] In addition, it should be noted that the above figures are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It is easy to understand that the processes shown in the above figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0095] Figure 5 It is a block diagram of an electronic device according to an exemplary embodiment.

[0096] Refer to the following Figure 5 The electronic device 500 according to this embodiment of the present application is described. Figure 5 The electronic device 500 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0097] like Figure 5 As shown, the electronic device 500 is in the form of a general computing device. The components of the electronic device 500 may include, but are not limited to: at least one processing unit 510, at least one storage unit 520, a bus 530 connecting different system components (including the storage unit 520 and the processing unit 510), a display unit 540, etc.

[0098] The storage unit stores a program code, which can be executed by the processing unit 510, so that the processing unit 510 performs the steps described in this specification according to various exemplary embodiments of the present application. For example, the processing unit 510 can perform the following steps: Figure 2 , Figure 3 Follow the steps shown in .

[0099] The storage unit 520 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 5201 and / or a cache memory unit 5202 , and may further include a read-only memory unit (ROM) 5203 .

[0100] The storage unit 520 may also include a program / utility 5204 having a set (at least one) of program modules 5206, such program modules 5206 including but not limited to: an operating system, one or more application programs, other program modules and program data, each of which or some combination may include the implementation of a network environment.

[0101] Bus 530 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0102] The electronic device 500 may also communicate with one or more external devices 500' (e.g., keyboards, pointing devices, Bluetooth devices, etc.) to enable a user to interact with the electronic device 500, and / or any device (e.g., routers, modems, etc.) that the electronic device 500 can communicate with one or more other computing devices. Such communication may be performed via an input / output (I / O) interface 550. In addition, the electronic device 500 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 550. The network adapter 550 may communicate with other modules of the electronic device 500 via a bus 530. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 500, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0103] Through the above description of the implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by combining software with necessary hardware. Figure 6 As shown, the technical solution according to the implementation mode of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, or a network device, etc.) to execute the above method according to the implementation mode of the present application.

[0104] The software product may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, a system, device or component of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0105] The computer readable storage medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The readable storage medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by an instruction execution system, an apparatus, or a device or used in combination with it. The program code contained on the readable storage medium may be transmitted with any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the above.

[0106] Program code for performing the operations of the present application may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., using an Internet service provider to connect through the Internet).

[0107] The above-mentioned computer-readable medium carries one or more programs. When the above-mentioned one or more programs are executed by a device, the computer-readable medium realizes the following functions: the host computer sends a linked list message to the programmable logic device, and the linked list message includes a CAN bus message; the programmable logic device stores the linked list message in a static access memory; after obtaining a CAN bus message sending command, the programmable logic device reads the linked list message in the static access memory; parses the linked list message to generate a parsing result; and executes corresponding operations according to the parsing result to realize the sending of the CAN bus message.

[0108] Those skilled in the art will appreciate that the above modules can be distributed in the device according to the description of the embodiment, or can be changed accordingly and only used in one or more devices different from the embodiment. The modules of the above embodiments can be combined into one module, or further divided into multiple sub-modules.

[0109] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the embodiment of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiment of the present application.

[0110] The exemplary embodiments of the present application are specifically shown and described above. It should be understood that the present application is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present application is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended claims.

Claims

1. A CAN bus message sending method, comprising: The host computer sends a linked list message to the programmable logic device, wherein the linked list message includes a CAN bus message; The programmable logic device stores the linked list message in a static access memory; After obtaining the CAN bus message sending command, the programmable logic device reads the linked list message in the static access memory; Parsing the linked list message to generate a parsing result; The corresponding operation is performed according to the analysis result to realize the sending of the CAN bus message.

2. The method according to claim 1, characterized in that The host computer sends the linked list message to the programmable logic device, including: Determine the data structure of the linked list message; Determine the data to be sent; The host computer assembles the data to be sent according to the data structure to generate the linked list message; The linked list message is sent to a programmable logic device.

3. The method according to claim 2, characterized in that Determine the data to be sent, including: Determine the message interval; and / or determine control data; and / or Identify the CAN bus message to be sent.

4. The method according to claim 2, characterized in that The host computer assembles the data to be sent according to the data structure to generate the linked list message, including: Determine the order of message dispatch; Generate a next message address based on the message scheduling order; The host computer generates the linked list message based on the data structure by combining the data to be sent and the corresponding next message address.

5. The method according to claim 1, characterized in that Before the programmable logic device stores the linked list message in the static access memory, the programmable logic device further includes: The data width and data depth of the static access memory are determined according to the data structure of the linked list message.

6. The method according to claim 1, characterized in that Executing corresponding operations according to the analysis results to implement the sending of CAN bus messages, including: Obtaining the message time interval and the CAN bus message from the analysis result; An external clock is called based on the message time interval to send the CAN bus message.

7. The method according to claim 6, characterized in that Calling an external clock based on the message time interval to send the CAN bus message includes: Send the CAN bus message in the current linked list message; Obtaining the next message address from the parsing result; Based on the message time interval, the subsequent linked list message is obtained from the next message address to perform a corresponding operation.

8. The method according to claim 1, characterized in that Executing corresponding operations according to the analysis results to implement the sending of CAN bus messages, including: Obtaining control data from the analysis result; When the state of the control data is valid, the programmable logic device sends an interrupt instruction to the host computer; The host computer sends a new linked list message according to the interrupt instruction.

9. The method according to claim 1, characterized in that Executing corresponding operations according to the analysis results to implement the sending of CAN bus messages, including: Acquire frame attribute data from the parsing result, wherein the frame attribute data includes frame format, frame type, frame identifier, and valid byte number; The CAN bus message is sent according to the frame attribute data.

10. A CAN bus message sending system, characterized in that: include: The host computer is used to send a linked list message to the programmable logic device, wherein the linked list message includes a CAN bus message; and is also used to generate a CAN bus message sending command; A programmable logic device, used for storing the linked list message in a static access memory; After obtaining a CAN bus message sending command, reading the linked list message in the static access memory; Parsing the linked list message to generate a parsing result; performing corresponding operations according to the parsing result to realize the sending of the CAN bus message; The static access memory is used to store the linked list message.

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