Chip self-test system and test method

Abstract

The invention discloses a chip self-test system and a test method, the chip self-test system comprises a test machine and a tested chip, the test machine is coupled with the tested chip and is suitable for burning a test program to the tested chip and obtaining a temperature sensing voltage conversion code fed back by the tested chip so as to judge whether the tested chip is abnormal or not; the tested chip comprises a power management module, a memory, a microcontroller core, an analog-to-digital converter and a temperature sensor, wherein the power management module provides working voltage and reference voltage for the tested chip; the memory stores a test program; the microcontroller core reads and operates the test program; the temperature sensor collects the real-time temperature of the tested chip, converts the real-time temperature into temperature sensing voltage and outputs the temperature sensing voltage to the analog-to-digital converter; the analog-to-digital converter converts the temperature sensing voltage into a corresponding temperature sensing voltage conversion code and outputs the temperature sensing voltage conversion code to a test machine through the microcontroller core. By adopting the scheme, more testing machine resources do not need to be occupied when the MCU chip is tested.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a chip self-testing system and a testing method. Background Art

[0002] With the development of semiconductor technology and market demand, the application scenarios of microcontroller unit (MCU) chips are becoming more and more extensive, and the types of peripheral devices integrated with MCU chips are also richer.

[0003] In order to ensure that the MCU chip can work normally at different temperatures and achieve consistency of performance indicators at different temperatures, it is necessary to accurately obtain the internal temperature of the MCU chip when it is working. Some existing MCU chips are integrated with temperature sensors, which measure the internal temperature and ambient temperature of the MCU chip. The internal temperature and ambient temperature of the MCU chip can be used to determine whether the MCU chip is in a stable working state.

[0004] In the prior art, the MCU chip includes modules such as a temperature sensor and an analog to digital converter (ADC). The temperature sensor converts the collected temperature into a voltage V that changes linearly with the temperature. TS , the voltage V TS Converted into a corresponding digital signal. The ADC includes two reference input terminals: the positive reference input terminal ADC_VREFP and the negative reference input terminal ADC_VREFN.

[0005] When the MCU chip is tested by the test machine, the positive reference input terminal ADC_VREFP can be configured to be short-circuited to the power supply internally, and the negative reference input terminal ADC_VREFN can be configured to be connected to the ground terminal (AVSS) of the MCU chip internally through the test program, and AVSS is coupled to the ground terminal (GND) of the test machine. Alternatively, the test machine can configure the positive reference input terminal ADC_VREFP to be short-circuited to the power supply internally, and configure the negative reference input terminal ADC_VREFN to be connected to the input / output (IO) port of the MCU chip internally through the test program, and the IO port is connected to the test machine resources.

[0006] It can be seen that in the prior art, when the tester tests the MCU chip, the tester controls the chip pins such as the negative reference input terminal ADC_VREFN of the chip, which requires more channel resources of the tester and is not easy to be tested and expanded at multiple stations. Summary of the invention

[0007] The technical problem solved by the present invention is that testing an MCU chip requires occupying test machine resources.

[0008] To solve the above problems, the present invention provides a chip self-test system, comprising: a tester and a chip under test, wherein: the tester is coupled to the chip under test, suitable for burning a test program into the chip under test, and obtaining a temperature-sensitive voltage conversion code fed back by the chip under test, and judging whether the chip under test has an abnormality based on the temperature-sensitive voltage conversion code; the chip under test comprises a power management module, a memory, a microcontroller core, an analog-to-digital converter and a temperature sensor, wherein: the power management module is suitable for providing an operating voltage and a reference voltage for the chip under test; the memory is suitable for storing the test program; the microcontroller The core is coupled to the memory and is suitable for reading and running the test program; the temperature sensor is coupled to the analog-to-digital converter and is suitable for collecting the real-time temperature of the chip under test, converting the real-time temperature into a temperature-sensitive voltage and outputting it to the analog-to-digital converter; the analog-to-digital converter is suitable for converting the temperature-sensitive voltage into a corresponding temperature-sensitive voltage conversion code, and outputting the temperature-sensitive voltage conversion code to the tester through the microcontroller core, the analog-to-digital converter includes a positive reference input terminal and a negative reference input terminal, the positive reference input terminal is coupled to the power supply terminal of the chip under test, and the negative reference input terminal is coupled to the ground terminal inside the chip under test.

[0009] Optionally, the microcontroller core is adapted to select a connection method of a positive reference input terminal and a negative reference input terminal of the analog-to-digital converter based on the test program.

[0010] Optionally, the positive reference input terminal of the analog-to-digital converter is coupled to the power supply pin of the chip under test, and the power supply pin of the chip under test is coupled to the power supply terminal of the tester; or, the positive reference input terminal of the analog-to-digital converter is coupled to the reference voltage output terminal of the power management module.

[0011] Optionally, the negative reference input terminal of the analog-to-digital converter is coupled to the ground pin of the chip under test, and the ground pin of the chip under test is coupled to the ground terminal of the test machine; or, the negative reference input terminal of the analog-to-digital converter is coupled to the output terminal of the universal input-output port of the chip under test, and the output terminal voltage of the universal input-output port is set to 0V; or, the negative reference input terminal of the analog-to-digital converter is coupled to the input terminal of the universal input-output port, and the input terminal of the universal input-output port is coupled to the first end of the pull-down resistor, and the second end of the pull-down resistor is grounded.

[0012] Optionally, the chip under test also includes an internal register coupled to the test machine and the analog-to-digital converter, suitable for storing the temperature-sensitive voltage conversion code, and the temperature-sensitive voltage conversion code is output to the test machine through the microcontroller core.

[0013] The present invention also provides a chip self-test method, which is executed by a microcontroller core of a chip under test in any one of the chip self-test systems described above, and the chip self-test method includes: determining a positive reference input terminal and a negative reference input terminal of an analog-to-digital converter, wherein the negative reference input terminal of the analog-to-digital converter is coupled to a ground terminal inside the chip under test; obtaining a temperature-sensitive voltage conversion code output by the analog-to-digital converter, and outputting the temperature-sensitive voltage conversion code to a tester; the temperature-sensitive voltage conversion code is generated by the analog-to-digital converter based on a temperature-sensitive voltage, and the temperature-sensitive voltage is obtained by the temperature sensor based on the real-time temperature of the chip under test collected.

[0014] Optionally, the chip self-test method further includes: determining whether the chip under test is abnormal based on the temperature-sensitive voltage conversion code.

[0015] Optionally, determining whether the chip under test is abnormal based on the temperature-sensitive voltage conversion code includes: coupling the positive reference input terminal of the analog-to-digital converter to the power supply pin of the chip under test, and coupling the negative reference input terminal of the analog-to-digital converter to the ground pin of the chip under test; obtaining the temperature-sensitive voltage conversion code output by the analog-to-digital converter; and detecting that the value of the temperature-sensitive voltage conversion code exceeds a preset first threshold, and determining that the chip under test is abnormal.

[0016] Optionally, the chip self-test method also includes: detecting that the value of the temperature-sensitive voltage code does not exceed the first threshold, coupling the positive reference input terminal of the analog-to-digital converter to the reference voltage output terminal of the power management module, and coupling the negative reference input terminal of the analog-to-digital converter to the output terminal of the general input and output port of the chip under test; obtaining the temperature-sensitive voltage conversion code output by the analog-to-digital converter; detecting that the value of the temperature-sensitive voltage conversion code exceeds a preset second threshold, and determining that the chip under test is abnormal; the second threshold is less than the first threshold; and the output terminal of the general input and output port is set to 0V.

[0017] Optionally, the chip self-test method also includes: detecting that the value of the temperature-sensitive voltage code does not exceed the second threshold, coupling the positive reference input terminal of the analog-to-digital converter to the reference voltage output terminal of the power management module, and coupling the negative reference input terminal of the analog-to-digital converter to the output terminal of the universal input-output port of the chip under test; detecting that the value of the temperature-sensitive voltage conversion code exceeds a preset third threshold, determining that the chip under test is abnormal; the third threshold is less than the second threshold; the input terminal of the universal input-output port is coupled to the first end of the pull-down resistor, and the second end of the pull-down resistor is grounded.

[0018] Optionally, the chip self-test method further includes: detecting that the value of the temperature-sensing voltage code does not exceed the third threshold, obtaining a deviation value between a theoretical value and a measured value of the temperature-sensing voltage conversion code, and using the deviation value as a compensation value and saving it.

[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0020] The chip under test includes an analog-to-digital converter, which includes a positive reference input terminal and a negative reference input terminal, wherein the positive reference input terminal is coupled to a power supply terminal of the chip under test, and the negative reference input terminal is coupled to a ground terminal inside the chip under test. Thus, the potential of the negative reference input terminal of the analog-to-digital converter is provided by the inside of the chip under test, and does not need to be provided by the tester, so that the tester resources used in the test process can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic structural diagram of a chip self-test system in an embodiment of the present invention;

[0022] Figure 2 is a schematic structural diagram of another chip self-test system in an embodiment of the present invention;

[0023] Figure 3 is a flow chart of a chip self-test method in an embodiment of the present invention;

[0024] Figure 4 This is a flow chart for determining whether a chip under test is abnormal in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In the prior art, the MCU chip includes modules such as a temperature sensor and an analog to digital converter (ADC). The temperature sensor converts the collected temperature into a voltage V that changes linearly with the temperature. TS , the voltage V TS Converted into a corresponding digital signal. The ADC includes two reference input terminals: the positive reference input terminal ADC_VREFP and the negative reference input terminal ADC_VREFN.

[0026] In the prior art, when the test machine tests the MCU chip, the positive reference input terminal ADC_VREFP can be configured to be short-circuited to the power supply internally, and the negative reference input terminal ADC_VREFN can be configured to be connected to the ground terminal (AVSS) of the MCU chip internally through the test program, and the AVSS is coupled to the ground terminal (GND) of the test machine. Alternatively, the test machine can configure the positive reference input terminal ADC_VREFP to be short-circuited to the power supply internally, and configure the negative reference input terminal ADC_VREFN to be connected to the input / output (IO) port of the MCU chip internally through the test program, and the IO port is connected to the test machine resources.

[0027] It can be seen that in the prior art, when the tester tests the MCU chip, the tester controls the chip pins such as the negative reference input terminal ADC_VREFN of the chip, which requires more channel resources of the tester and is not easy to be tested and expanded at multiple stations.

[0028] In an embodiment of the present invention, the analog-to-digital converter includes a positive reference input terminal and a negative reference input terminal, the positive reference input terminal is coupled to the power supply terminal of the chip under test, and the negative reference input terminal is coupled to the ground terminal inside the chip under test. The negative reference input terminal of the analog-to-digital converter is grounded through the input pull-down of the universal input / output port of the chip under test, or the negative reference input terminal of the analog-to-digital converter outputs 0V through the universal input / output port of the chip under test. Thus, the potential of the negative reference input terminal of the analog-to-digital converter is provided by the inside of the chip under test, and does not need to be provided by the tester, so the tester resources used in the test process can be reduced.

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] Reference Figure 1 , a schematic diagram of the structure of a chip self-test system in an embodiment of the present invention is given.

[0031] In an embodiment of the present invention, the chip self-test system may include a tester (Automatic Testing Equipment, ATE) and a chip under test. The chip under test may be electrically connected to the tester through a test hardware interface (such as a load test board, etc.). During the test process, the tester may communicate with the chip under test and may provide power to the chip under test.

[0032] In a specific implementation, the chip self-test system may further include a host computer, which may communicate with the tester, and the tester may control the tester through the host computer. For example, the tester may input a test instruction through the human-computer interaction interface of the host computer to control the tester to test the chip under test. Alternatively, the tester may input a test program through the human-computer interaction interface of the host computer, and the tester may then write the test program into the chip under test.

[0033] In a specific implementation, the chip under test may be integrated with functional modules such as a microcontroller core, a power management module, a memory, an analog-to-digital converter, etc. The chip under test may also be integrated with a temperature sensor.

[0034] In some embodiments, the chip under test may be a microcontroller unit (MCU) chip.

[0035] like Figure 1 As shown, the chip under test includes a power management module, a memory, a microcontroller core, an analog-to-digital converter, and a temperature sensor. The tester can be coupled to the power management module and the memory of the chip under test. The tester can burn the test program into the memory of the chip under test. The power management module can provide the internal circuit operating voltage and the reference voltage for the chip under test.

[0036] In a specific implementation, the chip under test receives a test program sent by a tester and stores the test program in a memory.

[0037] In some embodiments, the memory may be eFlash, or other types of storage modules / units capable of storing test programs, etc. The analog-to-digital converter may include a positive reference input terminal and a negative reference input terminal.

[0038] The microcontroller core (Core) can be coupled to the memory, and can read the test program from the memory and run it. When the microcontroller core (Core) runs the test program, it can control the temperature sensor to obtain the real-time temperature of the chip under test, and control the positive reference input terminal of the analog-to-digital converter to be coupled to the power terminal of the chip under test, and control the negative reference input terminal of the analog-to-digital converter to be coupled to the ground terminal inside the chip under test.

[0039] The temperature sensor can be coupled to the analog-to-digital converter to collect the real-time temperature of the chip under test, convert the real-time temperature into a temperature-sensing voltage, and output the temperature-sensing voltage to the analog-to-digital converter.

[0040] In some embodiments, the real-time temperature of the chip under test and the temperature sensing voltage may be linearly negatively correlated. That is, the higher the real-time temperature of the chip under test, the smaller the corresponding temperature sensing voltage; conversely, the lower the real-time temperature of the chip under test, the higher the corresponding temperature sensing voltage.

[0041] In other embodiments, the real-time temperature of the chip under test and the temperature sensing voltage may be linearly positively correlated. That is, the higher the real-time temperature of the chip under test, the higher the corresponding temperature sensing voltage; conversely, the lower the real-time temperature of the chip under test, the lower the corresponding temperature sensing voltage.

[0042] The analog-to-digital converter receives the temperature sensing voltage, can convert the temperature sensing voltage into a corresponding temperature sensing voltage conversion code, and send the temperature sensing voltage conversion code to the microcontroller core, and the microcontroller core outputs the received temperature sensing voltage conversion code to the test machine.

[0043] In an embodiment of the present invention, the microcontroller core can determine the connection relationship between the positive reference input terminal and the negative reference input terminal of the analog-to-digital converter based on the test program. That is to say, in an embodiment of the present invention, the connection mode of the positive reference input terminal and the connection mode of the negative reference input terminal of the analog-to-digital converter may not be fixed. In the test program, the internal state of the chip under test can be pre-configured, and the internal state of the chip under test can include the state of the general input and output ports or the internal ground terminal in the chip under test. Based on the internal state of the chip under test, the connection relationship of the positive reference input terminal and the connection relationship of the negative reference input terminal of the analog-to-digital converter can be determined.

[0044] In a specific implementation, the positive reference input terminal of the analog-to-digital converter can be coupled to the power supply pin of the chip under test to input the power supply voltage; or, the positive reference input terminal of the analog-to-digital converter can be coupled to the reference voltage output terminal of the power management module to input the reference voltage.

[0045] The negative reference input terminal of the analog-to-digital converter can be coupled to the ground pin of the chip under test, and the ground pin of the chip under test is coupled to the ground terminal of the tester; or, the negative reference input terminal of the analog-to-digital converter can be coupled to the output terminal of the universal input-output port in the chip under test, and the voltage output terminal voltage of the universal input-output port in the chip under test is set to 0V; or, the negative reference input terminal of the analog-to-digital converter can be coupled to the input terminal of the universal input-output port in the chip under test, and the input terminal of the universal input-output port is coupled to the first end of the pull-down resistor, and the second end of the pull-down resistor is grounded.

[0046] Specifically, the microcontroller core can determine whether the positive reference input terminal of the analog-to-digital converter inputs the power supply voltage or the reference voltage based on the test program. The connection relationship of the negative reference input terminal of the analog-to-digital converter can also be selected by the microcontroller core based on the test program.

[0047] Reference Figure 2 , a schematic diagram of the structure of another chip self-test system in an embodiment of the present invention is given.

[0048] Figure 2In the test, the test machine is coupled to the memory of the chip under test. In the chip under test, the temperature sensor generates a corresponding temperature sensing voltage V based on the real-time temperature of the chip under test. TS , and input to the input of ADC. ADC is based on temperature sensing voltage V TS Generate temperature-sensing voltage conversion code and output it to the microcontroller core.

[0049] The positive reference input of the ADC is coupled to the output of the gate MUX1. The first input of the gate MUX1 inputs VREF, and the second input of the gate MUX1 inputs VDD. The VREF is the reference voltage output by the power management module, and the VDD is the power supply voltage of the chip under test.

[0050] The power supply voltage mentioned above can be outputted by the power supply pin of the chip under test. The reference voltage mentioned above can be coupled by the reference voltage output terminal of the power management module.

[0051] The microcontroller core can output a first control signal to the gate MUX1 through a test program to control the gate MUX1 to output VREF or VDD. When the microcontroller core selects the gate MUX1 to output VDD through the first control signal, the positive reference voltage input terminal of the ADC is coupled to the power supply pin of the chip under test; when the microcontroller core selects the gate MUX1 to output VREF through the first control signal, the positive reference voltage input terminal of the ADC is coupled to the reference voltage output terminal of the power management module.

[0052] The negative reference input terminal of the ADC is coupled to the output terminal of the gate MUX2. The first input terminal of the gate MUX2 is coupled to the ground pin of the chip under test, and the ground pin of the chip under test is coupled to the ground terminal of the tester. In this scenario, the first input terminal of the gate MUX2 inputs VSS;

[0053] The second input terminal of the selector MUX2 is coupled to the output terminal of the general purpose input and output port, and the output terminal of the general purpose input and output port is set to 0 V. In this scenario, the second input terminal of the selector MUX2 inputs GPIO_OUTPUT_0V;

[0054] The third input terminal of the selector MUX2 is coupled to the input terminal of the general input output port, and the input terminal of the general input output port is coupled to the first terminal of the pull-down resistor, and the second terminal of the pull-down resistor is grounded. In this scenario, the third input terminal of the selector MUX2 inputs GPIO_INPUT_0V.

[0055] The microcontroller core can output a second control signal to the selector MUX2 through a test program to control the selector MUX2 to output VSS, or output GPIO_OUTPUT_0V, or output GPIO_INPUT_0V.

[0056] In summary, in the embodiment of the present invention, the positive reference input terminal of the analog-to-digital converter is coupled to the power supply terminal of the chip under test, and the negative reference input terminal is coupled to the ground terminal inside the chip under test. Therefore, the potential of the negative reference input terminal of the analog-to-digital converter is provided by the inside of the chip under test, and does not need to be provided by the tester, so the tester resources used in the test process can be reduced.

[0057] The chip self-test method provided in the embodiment of the present invention is described in detail below. Figure 3 , a flow chart of a chip self-test method in an embodiment of the present invention is given.

[0058] In an embodiment of the present invention, the following chip self-test method can be combined with Figure 1 and Figure 2 Provide explanation.

[0059] Step 301: The tester supplies power to the chip under test.

[0060] In a specific implementation, before the test starts, a wired cable connection can be established between the chip under test and the tester. The tester can power the chip under test through the wired cable and communicate with the chip under test through the wired cable.

[0061] Step 302: The test machine burns the test program into the eFlash of the chip under test.

[0062] In a specific implementation, a tester can trigger a test machine so that the test machine burns a test program into the eFlash of the chip under test. The test program is pre-written by the tester and stored in the test machine.

[0063] Step 303: the test machine triggers the chip under test to run the test program.

[0064] In a specific implementation, the test machine may trigger the chip under test to run a test program.

[0065] For example, the tester can send a reset signal to the chip under test. After receiving the reset signal, the chip under test can run the test program.

[0066] For another example, the tester can control the chip under test to power off, and then control the chip under test to power on again after the chip under test is powered off. The chip under test detects that it is powered on again and runs the test program.

[0067] Step 304 : The microcontroller core selects a connection method for the positive reference input terminal and the negative reference input terminal of the analog-to-digital converter.

[0068] In a specific implementation, the microcontroller core can select the connection mode of the positive reference input terminal and the connection mode of the negative reference input terminal of the analog-to-digital converter based on the test program. The positive reference input terminal of the analog-to-digital converter can be coupled to the power terminal of the chip under test, and the negative reference input terminal of the analog-to-digital converter can be coupled to the ground terminal inside the chip under test.

[0069] Step 305, obtaining the temperature-sensing voltage conversion code output by the analog-to-digital converter to determine whether the chip under test is abnormal.

[0070] In a specific implementation, the analog-to-digital converter inside the chip under test can obtain the temperature inside the chip under test, and convert the obtained temperature into a corresponding temperature-sensitive voltage conversion code.

[0071] The microcontroller core can determine whether the chip under test is abnormal based on the temperature-sensing voltage transcoding.

[0072] Refer to the following Figure 4 , the specific execution process of steps 304 to 305 is explained. Figure 4 A flow chart for determining whether a chip under test is abnormal is provided in an embodiment of the present invention.

[0073] Step 401 , coupling the positive reference input terminal to the power supply pin of the chip under test, and coupling the negative reference input terminal to the ground pin of the chip under test.

[0074] Step 402: Obtain a first temperature-sensitive voltage conversion code.

[0075] Step 403: Detect that the value of the first temperature-sensitive voltage conversion code exceeds a preset first threshold, and determine that the chip under test is abnormal.

[0076] In a specific implementation, if the value of the first temperature-sensitive voltage conversion code exceeds the first threshold, it means that the temperature of the chip under test exceeds the maximum temperature under normal operating conditions, so it can be determined that the temperature of the chip under test is abnormal, and then the chip under test is abnormal.

[0077] Step 404 , when it is detected that the value of the first temperature-sensing voltage conversion code does not exceed the first threshold, the positive reference input terminal is coupled to the reference voltage output terminal of the power management module, and the negative reference input terminal is coupled to the output terminal of the general input / output port.

[0078] In a specific implementation, the output end of the general input and output port of the chip under test is set to 0V.

[0079] Step 405: Obtain a second temperature-sensitive voltage conversion code.

[0080] Step 406: Detect that the value of the second temperature-sensitive voltage conversion code exceeds a preset second threshold, and determine that the chip under test is abnormal.

[0081] In a specific implementation, the second threshold mentioned above may be smaller than the first threshold.

[0082] Step 407 , when it is detected that the value of the second temperature-sensing voltage conversion code does not exceed the second threshold, the positive reference input terminal is coupled to the reference voltage output terminal of the power management module, and the negative reference input terminal is coupled to the input terminal of the general input / output port.

[0083] In a specific implementation, the input terminal of the general input / output port is coupled to a first terminal of a pull-down resistor, and a second terminal of the pull-down resistor is grounded.

[0084] Step 408: Obtain a third temperature-sensitive voltage conversion code.

[0085] Step 409: If it is detected that the value of the third temperature-sensitive voltage conversion code does not exceed the third threshold, it is determined that the chip under test has no abnormality.

[0086] In the embodiment of the present invention, after executing step 403 and / or step 406 and determining that the chip under test is abnormal, step 410 may be executed: determining that the chip under test is a defective product and screening out the chip under test.

[0087] In a specific implementation, if it is detected that the value of the third temperature-sensitive voltage code exceeds the third threshold, it is determined that the chip under test is abnormal.

[0088] Step 306 , determining that the chip under test has no abnormality, obtaining the deviation value between the theoretical value and the measured value of the temperature sensing voltage conversion code, and taking the deviation value as a compensation value and saving it.

[0089] In the embodiment of the present invention, after determining that the chip under test has no abnormality through steps 304 to 305, the deviation value between the theoretical value and the measured value of the temperature-sensitive voltage conversion code can also be obtained, and the deviation value can be used as a compensation value and saved. In subsequent applications, the compensation value can be used to compensate the obtained temperature-sensitive voltage conversion code.

[0090] In the embodiment of the present invention, after step 306 is completed, steps 307 to 308 may also be executed.

[0091] Specifically, steps 307 to 308 may be used in subsequent practical application scenarios to compensate for the acquired temperature-sensitive voltage conversion code.

[0092] In a specific implementation, the chip under test can be tested in different test temperature scenarios (high temperature scenario, normal temperature scenario, low temperature scenario), and the corresponding compensation values ​​under different temperature scenarios can be obtained and saved. In subsequent applications, the corresponding compensation values ​​can be obtained based on the test temperature range of the chip under test to compensate for the temperature-sensitive voltage conversion code.

[0093] Step 307: When the compensation result after compensating the measured value with the compensation value meets the expected value, it is determined that the chip under test is a good product.

[0094] Step 308: When the compensation result after compensating the measured value with the compensation value does not meet the expected value, it is determined that the chip under test is a defective product.

[0095] Step 309: Screen out the chips to be tested.

[0096] In a specific implementation, when it is determined that the chip under test is abnormal, the chip under test can be determined to be a defective product and the chip under test is screened out.

[0097] In actual applications, in order to save testing costs, MCU chips with embedded eFlash are usually tested in modules and stages during production testing. Since the test content and test process of embedded eFlash are relatively complex and the test time is long, in order to ensure test coverage and improve test efficiency, eFlash is usually tested independently with CP for software and hardware development and production batch testing. Therefore, MCU chip testing usually includes two test stages: eFlash CP test and Logic CP test.

[0098] The Logic CP test is a functional parameter test of each module in the MCU chip, which requires a hardware test interface (probe card) with full pad output to complete the test. For the eFlash CP test, the number of hardware test interfaces required is relatively small, and the pads required for the eFlash test are distributed on a single side or opposite sides. Under normal circumstances, based on a test machine with 1024 test channels, the maximum number of simultaneous tests of eFlash CP can reach 128. Integrating the process of testing the temperature sensor into the eFlash CP test process can improve the test efficiency. However, when testing the temperature sensor, the test machine is required to control the positive reference input terminal ADC_VREFP and the negative reference input terminal ADC_VREFN of the analog-to-digital converter, which occupies part of the interface resources of the test machine, resulting in a decrease in the number of simultaneous tests.

[0099] By adopting the solution provided in the embodiment of the present invention, the test machine does not need to control the two reference input terminals of the analog-to-digital converter, which can reduce the used test machine resources.

[0100] The eFlash CP test process needs to be performed at different ambient temperatures (such as high temperature 85°C, normal temperature 30°C, etc.) to meet the test requirements and ensure the quality of eFlash. Logic CP testing is usually performed at room temperature.

[0101] The temperature sensor in the MCU chip needs to be tested and adjusted at different temperatures to ensure the accuracy of temperature sensing. Integrating the temperature sensor test into the eFlash CP test process can avoid adding another Logic CP test to introduce pad puncture, which can reduce damage to the MCU chip pad, reduce test costs, improve test efficiency, and shorten test cycles.

[0102] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A chip self-test system, characterized in that: include: A tester and a chip under test, wherein: the tester is coupled to the chip under test, and is suitable for burning a test program into the chip under test, and obtaining a temperature-sensitive voltage conversion code fed back by the chip under test, and judging whether the chip under test is abnormal based on the temperature-sensitive voltage conversion code; The chip under test includes a power management module, a memory, a microcontroller core, an analog-to-digital converter, and a temperature sensor, wherein: The power management module is adapted to provide an operating voltage and a reference voltage for the chip under test; The memory is adapted to store the test program; The microcontroller core is coupled to the memory and is suitable for reading and running the test program; The temperature sensor is coupled to the analog-to-digital converter and is suitable for collecting the real-time temperature of the chip under test, converting the real-time temperature into a temperature-sensing voltage and outputting it to the analog-to-digital converter; The analog-to-digital converter is suitable for converting the temperature-sensitive voltage into a corresponding temperature-sensitive voltage conversion code, and outputting the temperature-sensitive voltage conversion code to the tester through the microcontroller core; the analog-to-digital converter includes a positive reference input terminal and a negative reference input terminal, the positive reference input terminal is coupled to the power supply terminal of the chip under test, and the negative reference input terminal is coupled to the ground terminal inside the chip under test.

2. The chip self-test system as claimed in claim 1, characterized in that: The microcontroller core is adapted to select a connection mode of the positive reference input terminal and the negative reference input terminal of the analog-to-digital converter based on the test program.

3. The chip self-test system as claimed in claim 2, characterized in that: The positive reference input terminal of the analog-to-digital converter is coupled to the power supply pin of the chip under test, and the power supply pin of the chip under test is coupled to the power supply terminal of the tester; Alternatively, the positive reference input terminal of the analog-to-digital converter is coupled to the reference voltage output terminal of the power management module.

4. The chip self-test system according to claim 2 or 3, characterized in that: The negative reference input terminal of the analog-to-digital converter is coupled to the ground pin of the chip under test, and the ground pin of the chip under test is coupled to the ground terminal of the tester; or, The negative reference input terminal of the analog-to-digital converter is coupled to the output terminal of the universal input-output port of the chip under test, and the output terminal voltage of the universal input-output port is set to 0V; or, The negative reference input terminal of the analog-to-digital converter is coupled to the input terminal of the universal input-output port, and the input terminal of the universal input-output port is coupled to the first terminal of the pull-down resistor, and the second terminal of the pull-down resistor is grounded.

5. The chip self-test system as claimed in claim 1, characterized in that: The chip under test also includes an internal register coupled to the test machine and the analog-to-digital converter, suitable for storing the temperature-sensitive voltage conversion code, and the temperature-sensitive voltage conversion code is output to the test machine through the microcontroller core.

6. A chip self-test method, characterized in that: The chip self-test method is executed by a microcontroller core of a chip under test in a chip self-test system according to any one of claims 1 to 5, and the chip self-test method comprises: Determine a connection mode of a positive reference input terminal and a negative reference input terminal of an analog-to-digital converter, wherein the positive reference input terminal of the analog-to-digital converter is coupled to a power supply terminal of the chip under test, and the negative reference input terminal of the analog-to-digital converter is coupled to a ground terminal inside the chip under test; The temperature-sensitive voltage conversion code output by the analog-to-digital converter is obtained, and the temperature-sensitive voltage conversion code is output to the test machine; the temperature-sensitive voltage conversion code is generated by the analog-to-digital converter based on the temperature-sensitive voltage, and the temperature-sensitive voltage is obtained by the temperature sensor based on the real-time temperature of the chip under test collected.

7. The chip self-test method according to claim 6, characterized in that: Also includes: Based on the temperature-sensitive voltage conversion code, it is determined whether the chip under test is abnormal.

8. The chip self-test method according to claim 7, characterized in that: The determining whether the chip under test is abnormal based on the temperature-sensitive voltage conversion code includes: The positive reference input terminal of the analog-to-digital converter is coupled to the power supply pin of the chip under test, and the negative reference input terminal of the analog-to-digital converter is coupled to the ground pin of the chip under test; Obtaining a temperature sensing voltage conversion code output by the analog-to-digital converter; It is detected that the value of the temperature-sensing voltage conversion code exceeds a preset first threshold, and it is determined that the chip under test is abnormal.

9. The chip self-test method according to claim 8, characterized in that: Also includes: When it is detected that the value of the temperature sensing voltage code does not exceed the first threshold, the positive reference input terminal of the analog-to-digital converter is coupled to the reference voltage output terminal of the power management module, and the negative reference input terminal of the analog-to-digital converter is coupled to the output terminal of the general input-output port of the chip under test; Obtaining a temperature sensing voltage conversion code output by the analog-to-digital converter; Detecting that the value of the temperature-sensing voltage conversion code exceeds a preset second threshold, determining that the chip under test is abnormal; The second threshold is less than the first threshold; The output terminal of the general input / output port is set to 0V.

10. The chip self-test method according to claim 9, characterized in that: Also includes: When it is detected that the value of the temperature sensing voltage code does not exceed the second threshold, the positive reference input terminal of the analog-to-digital converter is coupled to the reference voltage output terminal of the power management module, and the negative reference input terminal of the analog-to-digital converter is coupled to the output terminal of the general input-output port of the chip under test; Detecting that the value of the temperature sensing voltage conversion code exceeds a preset third threshold, determining that the chip under test is abnormal; The third threshold is less than the second threshold; An input terminal of the general purpose input / output port is coupled to a first terminal of a pull-down resistor, and a second terminal of the pull-down resistor is grounded.

11. The chip self-test method according to claim 10, characterized in that: Also includes: It is detected that the value of the temperature-sensitive voltage code does not exceed the third threshold, a deviation value between a theoretical value and a measured value of the temperature-sensitive voltage conversion code is obtained, and the deviation value is used as a compensation value and saved.

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