LDO (Low Dropout Regulator) circuit, LDO chip, LDO and electronic equipment

Abstract

The invention discloses a low dropout regulator (LDO) circuit, an LDO chip, an LDO and an electronic device. The circuit comprises a power device, a low dropout regulator (LDO) chip and a low dropout regulator (LDO) chip, the feedback unit is suitable for generating feedback voltage according to the output voltage of the LDO circuit; the first input end of the comparison unit is suitable for being connected with a reference voltage, the second input end of the comparison unit is connected with the output end of the feedback unit, the output end of the comparison unit is connected with the control end of the power device, and the comparison unit is suitable for comparing the feedback voltage with the reference voltage and outputting a comparison signal; the comparison signal is used for controlling on or off of the power device; the load capacitor and the shunt control unit are respectively arranged corresponding to the output end of the LDO circuit, and the shunt control unit is suitable for carrying out shunt control on current passing through the load capacitor. According to the circuit, the current passing through the load capacitor is shunted through the shunting control unit, so that the capacitance value requirement on the load capacitor is reduced and the area of the LDO circuit is reduced on the premise of keeping the performance of the LDO.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment, and in particular to a low dropout linear regulator (LDO) circuit, an LDO chip, an LDO and an electronic equipment. Background Art

[0002] In the related art, for LDO design without external capacitors, most of the area is on the load capacitor. At the same time, in order to maintain the performance similar to that of the external capacitor, internal load capacitors with larger capacitance values ​​are generally placed to meet the performance requirements of power supply ripple rejection ratio, load transient response, etc. However, the application of internal load capacitors with larger capacitance values ​​also increases the module area of ​​the LDO. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first object of the present invention is to provide a low dropout linear regulator LDO circuit, which shunts the current passing through the load capacitor by a shunt control unit, thereby reducing the capacitance value requirement of the load capacitor while maintaining the LDO performance, thereby reducing the application area of ​​the LDO circuit.

[0004] The second objective of the present invention is to provide an LDO chip.

[0005] The third objective of the present invention is to provide an LDO.

[0006] A fourth objective of the present invention is to provide an electronic device.

[0007] To achieve the above-mentioned purpose, the first embodiment of the present invention proposes a low-dropout linear regulator LDO circuit comprising: a power device, wherein the first end of the power device is suitable for connecting to a first reference power supply, and the second end of the power device is suitable for connecting to the output end of the LDO circuit; a feedback unit, wherein the feedback unit is connected to the second end of the power device and is suitable for generating a feedback voltage according to the output voltage of the LDO circuit; a comparison unit, wherein the first input end of the comparison unit is suitable for connecting to a reference voltage, the second input end of the comparison unit is connected to the output end of the feedback unit, and the output end of the comparison unit is connected to the control end of the power device, and is suitable for comparing the feedback voltage with the reference voltage and outputting a comparison signal, wherein the comparison signal is used to control the on or off of the power device; a load capacitor and a shunt control unit, wherein the load capacitor and the shunt control unit are respectively arranged corresponding to the output end of the LDO circuit, and the shunt control unit is suitable for shunt control of the current passing through the load capacitor.

[0008] According to the low-dropout linear regulator LDO circuit of the embodiment of the present invention, the first end of the power device is suitable for connecting to the first reference power supply, the second end of the power device is suitable for connecting to the output end of the LDO circuit, the feedback unit is connected to the second end of the power device, the feedback unit generates a feedback voltage according to the output voltage of the LDO circuit, the first input end of the comparison unit is suitable for connecting to the reference voltage, the second input end of the comparison unit is connected to the output end of the feedback unit, the output end of the comparison unit is connected to the control end of the power device, the comparison unit compares the feedback voltage with the reference voltage, and outputs a comparison signal, wherein the comparison signal is used to control the opening or closing of the power device, the load capacitor and the shunt control unit are respectively set corresponding to the output end of the LDO circuit, and the shunt control unit performs shunt control on the current passing through the load capacitor. Thus, the circuit shunts the current passing through the load capacitor through the shunt control unit, and reduces the capacitance value requirement of the load capacitor while maintaining the LDO performance, thereby reducing the application area of ​​the LDO circuit.

[0009] In addition, the low dropout linear regulator LDO circuit according to the above embodiment of the present invention may also have the following additional technical features:

[0010] According to one embodiment of the present invention, the shunt control unit includes: a voltage-dividing resistor, one end of which is connected to the output end of the LDO circuit, the other end of which is connected to one end of the load capacitor, and the other end of the load capacitor is grounded; a VI converter, suitable for converting the voltage difference on the voltage-dividing resistor into a shunt current; and a current mirror, suitable for mirroring the shunt current to draw away the shunt current.

[0011] According to an embodiment of the present invention, the current mirror ratio of the current mirror is adjustable.

[0012] According to one embodiment of the present invention, a VI converter includes: a first comparator, wherein a negative input terminal of the first comparator is connected to one end of a voltage-dividing resistor, and a positive input terminal of the first comparator is connected to the other end of the voltage-dividing resistor; a pull-up resistor, wherein one end of the pull-up resistor is suitable for connecting to a second reference power supply; and a first switch tube, wherein a control end of the first switch tube is connected to an output end of the first comparator, a first end of the first switch tube is connected to the other end of the pull-up resistor, and a second end of the first switch tube is suitable for providing a control current to a current mirror.

[0013] According to an embodiment of the present invention, the first switch tube is a PMOS (P-Metal-Oxide-Semiconductor) tube.

[0014] According to one embodiment of the present invention, the current mirror includes: a second switch tube, a first end of the second switch tube is connected to the other end of the voltage divider resistor, and a second end of the second switch tube is grounded; a third switch tube, a control end of the third switch tube is connected to the control end of the second switch tube, a first end of the third switch tube is respectively connected to the control end of the third switch tube and the second end of the first switch tube, and a second end of the third switch tube is grounded.

[0015] According to an embodiment of the present invention, the number of the second switch tubes is determined according to the current mirror ratio of the current mirror.

[0016] According to an embodiment of the present invention, the second switch tube and the third switch tube are respectively NMOS (N-Metal-Oxide-Semiconductor) tubes.

[0017] According to an embodiment of the present invention, the power device is an NMOS tube.

[0018] According to one embodiment of the present invention, the comparison unit includes a second comparator, the positive input terminal of the second comparator is suitable for connecting to a reference voltage, the negative input terminal of the second comparator is connected to the output terminal of the feedback unit, and the output terminal of the second comparator is connected to the control terminal of the power device.

[0019] According to one embodiment of the present invention, the feedback unit includes: a first resistor, one end of which is connected to the second end of the power device; a second resistor, one end of which is connected to the other end of the first resistor and has a first node, the other end of the second resistor is grounded, and the first node serves as the output end of the feedback unit.

[0020] To achieve the above object, a second embodiment of the present invention provides an LDO chip, including the above LDO circuit.

[0021] According to the LDO chip of the embodiment of the present invention, based on the above-mentioned low dropout linear regulator LDO circuit, the chip area of ​​the LDO is reduced while maintaining the performance of the LDO chip.

[0022] To achieve the above object, a third aspect of the present invention provides an LDO, including the above LDO chip.

[0023] According to the LDO of the embodiment of the present invention, based on the above-mentioned LDO chip, the area of ​​the LDO is reduced and the application cost is reduced while maintaining the LDO performance.

[0024] To achieve the above-mentioned purpose, a fourth aspect of the present invention provides an electronic device, including the above-mentioned LDO.

[0025] The electronic device according to the embodiment of the present invention is based on the above LDO, which reduces the area of ​​the electronic device and reduces the device cost while maintaining the performance of the electronic device.

[0026] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A connection diagram of a low dropout linear regulator LDO circuit according to an embodiment of the present invention;

[0028] Figure 2 is a schematic diagram of a capacitance multiplier according to an embodiment of the present invention;

[0029] Figure 3 A circuit diagram of a low dropout linear regulator LDO circuit in the related art;

[0030] Figure 4 A circuit diagram of a low dropout linear regulator LDO circuit according to a specific embodiment of the present invention;

[0031] Figure 5 A schematic diagram of a startup simulation according to a specific embodiment of the present invention;

[0032] Figure 6 A schematic diagram of a power supply ripple rejection ratio simulation according to a specific embodiment of the present invention;

[0033] Figure 7 A schematic diagram of load transient response simulation according to a specific embodiment of the present invention;

[0034] Figure 8 is a block diagram of an LDO chip according to an embodiment of the present invention;

[0035] Fig. 9 is a block diagram of an LDO according to an embodiment of the present invention;

[0036] Fig.10 FIG. 4 is a block diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0038] The following describes a low dropout linear regulator LDO circuit, an LDO chip, an LDO and an electronic device proposed in embodiments of the present invention with reference to the accompanying drawings.

[0039] Figure 1 FIG. 4 is a connection diagram of a low dropout linear regulator LDO circuit according to an embodiment of the present invention.

[0040] like Figure 1 As shown, the low dropout linear regulator LDO circuit of the present invention may include: a power device Q, a feedback unit 10, a comparison unit 20, a load capacitor C and a shunt control unit 30.

[0041] The first end of the power device Q is suitable for connecting to the first reference power supply VCC1, and the second end of the power device Q is suitable for connecting to the output end of the LDO circuit. The feedback unit 10 is connected to the second end of the power device Q, and the feedback unit 10 is suitable for generating a feedback voltage V0 according to the output voltage Vout of the LDO circuit. The first input end of the comparison unit 20 is suitable for connecting to the reference voltage Vref, the second input end of the comparison unit 20 is connected to the output end of the feedback unit 10, and the output end of the comparison unit 20 is connected to the control end of the power device Q. The comparison unit 20 is suitable for comparing the feedback voltage V0 with the reference voltage Vref and outputting a comparison signal, wherein the comparison signal is used to control the opening or closing of the power device Q. The load capacitor C and the shunt control unit 30 are respectively set corresponding to the output end of the LDO circuit, and the shunt control unit 30 is suitable for shunt control of the current passing through the load capacitor C.

[0042] Specifically, the output voltage Vout of the output end of the LDO circuit is collected by the feedback unit 10, and a feedback voltage V0 is generated and sent to the comparison unit 20. The comparison unit 20 compares the feedback voltage V0 with the reference voltage Vref, and the comparison unit 20 generates a corresponding comparison signal according to the comparison result to control the on or off of the power device Q. Assuming that when the feedback voltage V0 is greater than the reference voltage Vref, the comparison signal output by the comparison unit 20 can control the power device Q to be turned on, and the first reference power supply VCC1 is connected to the output end of the LDO circuit through the turned-on power device Q. At this time, the output voltage Vout of the LDO circuit is the first reference power supply VCC1 minus the on-state voltage of the power device Q.

[0043] When the power device Q is turned on, the output voltage Vout of the LDO circuit charges the load capacitor C, and the current flowing into the load capacitor C is shunted and controlled by the shunting control unit 30. Figure 2 As shown, a resistor R is connected in series at the upper end of the load capacitor C, where the sinking current refers to the current received by the resistor R, and the pumping current refers to the partial current drawn from the bottom of the resistor R. The drawn partial current, i.e., the pumping current, does not pass through the load capacitor C, and satisfies the following formula:

[0044] Q=CV=IT

[0045] C=IT / V

[0046] Among them, Q is the charge of the load capacitor, T is the charge and discharge time of the load capacitor, I is the current passing through the load capacitor, V is the voltage difference across the load capacitor, and C is the capacitance value of the load capacitor.

[0047] From the above formula, we can see that if the current through the load capacitor C decreases, the corresponding capacitance value will also decrease. Assuming the sink current is 5x and the draw current is 4x, then the current through the load capacitor C is only x, and the corresponding capacitance value of the load capacitor C can also be reduced by 5 times. At the same time, since the sink current into the resistor R remains unchanged, the effective capacitance value corresponding to the output of the LDO circuit also remains unchanged.

[0048] Therefore, this application is based on Figure 2 The capacitance multiplier concept shown in FIG. 1 controls the current flowing into the load capacitor C through the shunt control unit 30, thereby reducing the current flowing into the load capacitor C. Under the condition that the effective capacitance value corresponding to the output of the LDO circuit remains unchanged, the capacitance value requirement of the load capacitor C is reduced. In other words, under the premise of ensuring the working performance of the LDO circuit, relative to Figure 3 The present application can use a load capacitor C with a smaller capacitance value to reduce the area of ​​the LDO circuit. Furthermore, if a load capacitor C with the same capacitance value is used, the present application can improve the performance of the LDO circuit, such as the power supply ripple rejection ratio and load transient response.

[0049] It should be noted that the power device Q can be applied according to actual conditions. For example, in one embodiment of the present invention, the power device Q is an NMOS transistor. It is understandable that the power device Q can also be a PMOS transistor, which is not limited here.

[0050] In addition, the feedback unit 10 generates a feedback voltage V0 based on the output voltage Vout. Specifically, a voltage divider circuit can be used to divide the received output voltage Vout in real time, and the obtained divided voltage is used as the feedback voltage V0. In addition, after the output voltage Vout exceeds a preset voltage threshold or is less than a preset voltage threshold, a corresponding feedback voltage V0 can be output according to the output voltage Vout. There is no limitation here.

[0051] The following uses the power device Q and NMOS tube as an example to illustrate the low dropout linear regulator LDO circuit of the present application.

[0052] Combination Figure 4As shown, in one embodiment of the present invention, the feedback unit 10 includes: a first resistor R1, one end of the first resistor R1 is connected to the second end of the power device Q; a second resistor R2, one end of the second resistor R2 is connected to the other end of the first resistor R1, and has a first node a, the other end of the second resistor R2 is grounded, and the first node a serves as the output end of the feedback unit 10.

[0053] That is, the first resistor R1 and the second resistor R2 form a voltage divider circuit to divide the output voltage Vout, and output the divided voltage as the feedback voltage V0 to the comparison unit 20 through the first node a. The feedback voltage V0 satisfies the formula Wherein, R1 is the resistance value of the first resistor R2, R2 is the resistance value of the second resistor R2, and Vout is the output voltage of the LDO circuit.

[0054] In one embodiment of the present invention, the comparison unit 20 includes a second comparator A2, the positive input terminal of the second comparator A2 is suitable for connecting the reference voltage Vref, the negative input terminal of the second comparator A2 is connected to the output terminal of the feedback unit 10, and the output terminal of the second comparator A2 is connected to the control terminal of the power device Q.

[0055] When the power device Q is an NMOS tube, the on-voltage is the voltage difference between the gate g and the drain d of the NMOS tube.

[0056] Specifically, in the comparison unit 20, the feedback voltage V0 is compared with the reference voltage Vref, and then amplified in the second comparator A2, and then a comparison signal is output to control the gate g of the NMOS tube to control the opening or closing of the NMOS tube.

[0057] In one embodiment of the present invention, the shunt control unit 30 includes: a voltage divider resistor R3, a VI converter 31, and a current mirror 32. One end of the voltage divider resistor R3 is connected to the output end of the LDO circuit, the other end of the voltage divider resistor R3 is connected to one end of the load capacitor C, and the other end of the load capacitor C is grounded. The VI converter 31 is suitable for converting the voltage difference on the voltage divider resistor R3 into a shunt current. The current mirror 32 is suitable for mirroring the shunt current to draw away the shunt current.

[0058] Specifically, combined Figure 2 As shown, when the LDO circuit is started, the load capacitor C is charged. When the current passes through the voltage-dividing resistor R3, a voltage difference is generated between the two electrodes of the voltage-dividing resistor R3. The voltage difference of the voltage-dividing resistor R3 passes through the VI converter 31 to form a shunt current. The shunt current is mirrored by the current mirror 32 and part of the current is drawn away, that is, forming Figure 2 The current draw shown here is to reduce the current flowing through the load capacitor C.

[0059] In one embodiment of the present invention, the current mirror ratio of the current mirror 32 is adjustable. For example, the current mirror 32 can be adjusted through a register to change the magnitude of the drawn current to adapt to load capacitances of different capacitance values.

[0060] In one embodiment of the present invention, the VI converter 31 includes: a first comparator A1, wherein the negative input terminal of the first comparator A1 is connected to one end of the voltage-dividing resistor R3, and the positive input terminal of the first comparator A1 is connected to the other end of the voltage-dividing resistor R3; a pull-up resistor R4, wherein one end of the pull-up resistor R4 is suitable for connecting to the second reference power supply VCC2; a first switch tube Q1, wherein the control end of the first switch tube Q1 is connected to the output end of the first comparator A1, the first end of the first switch tube Q1 is connected to the other end of the pull-up resistor R4, and the second end of the first switch tube Q1 is suitable for providing a control current to the current mirror 32. The second reference power supply VCC2 can be set at the same potential as the first reference power supply VCC1, that is, the second reference power supply VCC2 and the first reference power supply VCC are the same reference power supply.

[0061] In one embodiment of the present invention, the first switch tube Q1 is a PMOS tube.

[0062] Specifically, when the LDO circuit starts working, the output voltage Vout is output through the output end of the LDO circuit, and the load capacitor C is charged through the voltage-dividing resistor R3. The voltage difference between the two electrodes of the voltage-dividing resistor R3 is positive, that is, the voltage of the upper end (the end away from the load capacitor C) of the voltage-dividing resistor R3 is greater than the voltage of the lower end (the end connected to the load capacitor C) of the voltage-dividing resistor R3, that is, the voltage of the positive input end of the first comparator A1 is less than the voltage of the negative input end. At this time, the first comparator A1 generates a comparison signal based on the comparison result, and controls the PMOS tube, that is, the first switch tube Q1 to be turned on. The second reference power supply VCC2 and the pull-up resistor R4 are connected to the current mirror 32 through the turned-on first switch tube Q1 to provide a control current to the current mirror 32.

[0063] In the process of providing the control current to the current mirror 32, if the voltage difference between the two electrodes of the voltage-dividing resistor R3 is large, that is, the current flowing through is large, at this time, the voltage at the positive input terminal of the first comparator A1 is greatly different from the voltage at the negative input terminal, the output signal of the first comparator A1 becomes stronger, and the on-state voltage of the PMOS tube, that is, the voltage drop, becomes smaller, and the output control current increases.

[0064] In one embodiment of the present invention, the current mirror 32 includes: a second switch tube Q2, a first end of the second switch tube Q2 is connected to the other end of the voltage-dividing resistor R3, and a second end of the second switch tube Q2 is grounded; a third switch tube Q3, a control end of the third switch tube Q3 is connected to the control end of the second switch tube Q2, a first end of the third switch tube Q3 is respectively connected to the control end of the third switch tube Q3 and the second end of the first switch tube Q2, and a second end of the third switch tube Q3 is grounded.

[0065] In one embodiment of the present invention, the number of second switch tubes Q2 is determined according to the current mirror ratio of the current mirror 32. That is, the current extraction ratio is controlled by adjusting the current mirror ratio, such as 4:5, 9:10, etc., so as to adjust the current ratio flowing into the load capacitor, and then adjust the capacitance value requirement of the load capacitor. Therefore, there is no limit to reducing the area of ​​the LDO circuit, which can be achieved by adjusting the current mirror ratio.

[0066] In one embodiment of the present invention, the second switch tube Q2 and the third switch tube Q3 are NMOS tubes respectively.

[0067] Specifically, the control current output by the VI converter 31 flows into the second switch tube Q2 and is mirrored to the third switch tube Q3 through the mirroring effect. The current flowing through the third switch tube Q3 is the mirror current of the control current and changes with the change of the control current. The current flowing through the third switch tube Q3 is the extraction current, thereby realizing the shunt control of the load capacitor C.

[0068] Furthermore, the following describes the circuit performance of the present application by simulating the output of three embodiments. Figure 3 As shown, the capacitance value of the load capacitor C is 50pF, and the large capacitor occupies about 70% of the entire circuit area; in the second embodiment, the LDO circuit is as follows Figure 3 As shown, the capacitance value of the load capacitor C is 10pF, and its circuit area is the smallest; in the third embodiment, the LDO circuit is as follows Figure 4 As shown, the capacitance value of the load capacitor C is 10 pF. The circuit is designed based on a capacitance multiplier. The circuit area is slightly larger than that of the second embodiment, but much smaller than that of the first embodiment.

[0069] The effective capacitance value of the low dropout linear regulator LDO circuit will affect the transient current I when the LDO circuit output is started. Figure 5 As shown, the simulation waveforms of the starting currents of Example 1 and Example 3 are close to or even overlap with the simulation waveform of the starting current of Example 2. Compared with the simulation waveform of the starting current of Example 2, under the premise of the same starting voltage, the starting currents of Example 1 and Example 3 are about 5 times larger than the starting current of Example 2.

[0070] The effective capacitance value of the low dropout linear regulator LDO circuit will affect the power supply ripple rejection ratio at high frequencies. Figure 6 As shown, the simulation waveforms of the first embodiment and the third embodiment are close to or even overlap, and taking the power supply ripple rejection ratio at 10MHz as an example, the first embodiment and the third embodiment are about 10dB smaller than the second embodiment. In addition, the effective capacitance values ​​of the first embodiment and the third embodiment are also similar.

[0071] Figure 7 The figure is a comparative simulation diagram of load transient response. When the load current output by the LDO circuit changes, the output voltage of the LDO circuit will have ripples. The larger the effective capacitance value, the smaller the ripple will be, and the better the output voltage quality of the LDO circuit will be. Figure 7 Taking the load current changing within the range of 0-12mA as an example, the simulation waveforms of Example 1 and Example 3 are close to or even overlap. It can be seen from the ripple simulation results that Example 1 and Example 3 jitter at 20mV, while Example 2 has a small effective capacitance value, so the ripple is around 70mV.

[0072] Thus, through Figure 5 , Figure 6 and Figure 7 Based on the simulation results of the first and third embodiments, it can be seen that the low-voltage dropout linear regulator LDO circuit provided by the present application can make the capacitance value of the load capacitor smaller while maintaining the effective capacitance value and performance, and save circuit area. Based on the simulation results of the second and third embodiments, it can be seen that while maintaining the same capacitance value, the low-voltage dropout linear regulator LDO circuit proposed in the present application makes the performance of the LDO circuit better, such as lower power supply ripple suppression ratio, better load transient response, and smaller ripple.

[0073] The low-dropout linear regulator LDO circuit proposed in the present application uses a shunt control unit 30 to shunt the current flowing into the load capacitor C while reducing the occupied area of ​​the load capacitor C, thereby maintaining the characteristics of the same large capacitor and maintaining the three important indicators of the LDO without external capacitors, namely, LDO load stability, power supply ripple suppression ratio and load transient response.

[0074] In summary, according to the low-dropout linear regulator LDO circuit of the embodiment of the present invention, the first end of the power device is suitable for connecting to the first reference power supply, the second end of the power device is suitable for connecting to the output end of the LDO circuit, the feedback unit is connected to the second end of the power device, the feedback unit generates a feedback voltage according to the output voltage of the LDO circuit, the first input end of the comparison unit is suitable for connecting to the reference voltage, the second input end of the comparison unit is connected to the output end of the feedback unit, the output end of the comparison unit is connected to the control end of the power device, the comparison unit compares the feedback voltage with the reference voltage, and outputs a comparison signal, wherein the comparison signal is used to control the opening or closing of the power device, the load capacitor and the shunt control unit are respectively set corresponding to the output end of the LDO circuit, and the shunt control unit shunts the current passing through the load capacitor. Thus, the circuit shunts the current passing through the load capacitor through the shunt control unit, and reduces the capacitance value requirement of the load capacitor under the premise of maintaining the LDO performance, thereby reducing the application area of ​​the LDO circuit. In addition, the technical solution proposed in this application can not only reduce the size of the capacitor area, but also achieve better LDO performance effects, including power supply ripple suppression ratio and load transient response, while keeping the capacitor area unchanged.

[0075] Corresponding to the above embodiment, the present invention further proposes an LDO chip.

[0076] like Figure 8 As shown, the LDO chip 100 according to the embodiment of the present invention includes the above-mentioned LDO circuit 110 .

[0077] According to the LDO chip of the embodiment of the present invention, based on the above-mentioned low dropout linear regulator LDO circuit, the chip area of ​​the LDO is reduced while maintaining the performance of the LDO chip.

[0078] Corresponding to the above embodiment, the present invention further proposes an LDO.

[0079] like Fig. 9 As shown, the LDO 200 according to the embodiment of the present invention includes the above-mentioned LDO chip 100 .

[0080] According to the LDO of the embodiment of the present invention, based on the above-mentioned LDO chip, the area of ​​the LDO is reduced and the application cost is reduced while maintaining the LDO performance.

[0081] Corresponding to the above embodiment, the present invention further provides an electronic device.

[0082] like Fig.10As shown, the electronic device 300 of the embodiment of the present invention includes the above-mentioned LDO 200. The electronic device 300 is an electrical device, and the LDO 200 can be applied to the power consumption scenarios of digital circuits and low-voltage analog circuits in the electrical device. The circuit layout can be carried out according to actual conditions, and no limitation is made here.

[0083] The electronic device according to the embodiment of the present invention is based on the above LDO, which reduces the area of ​​the electronic device and reduces the device cost while maintaining the performance of the electronic device.

[0084] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0085] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0086] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0087] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A low dropout linear regulator LDO circuit, characterized in that: include: A power device, wherein a first end of the power device is suitable for connecting to a first reference power source, and a second end of the power device is suitable for connecting to an output end of the LDO circuit; a feedback unit, the feedback unit being connected to the second end of the power device and being adapted to generate a feedback voltage according to the output voltage of the LDO circuit; A comparison unit, wherein a first input terminal of the comparison unit is suitable for connecting a reference voltage, a second input terminal of the comparison unit is connected to an output terminal of the feedback unit, an output terminal of the comparison unit is connected to a control terminal of the power device, and the comparison unit is suitable for comparing the feedback voltage with the reference voltage and outputting a comparison signal, wherein the comparison signal is used to control the on or off of the power device; A load capacitor and a shunt control unit, wherein the load capacitor and the shunt control unit are respectively arranged corresponding to the output end of the LDO circuit, and the shunt control unit is suitable for shunt control of the current passing through the load capacitor.

2. The LDO circuit according to claim 1, characterized in that: The shunt control unit comprises: A voltage-dividing resistor, one end of which is connected to the output end of the LDO circuit, the other end of which is connected to one end of the load capacitor, and the other end of which is grounded; A VI converter, adapted to convert the voltage difference across the voltage divider resistor into a shunt current; The current mirror is adapted to mirror the shunt current so as to draw away the shunt current.

3. The LDO circuit according to claim 2, characterized in that: The current mirror ratio of the current mirror is adjustable.

4. The LDO circuit according to claim 2, characterized in that: The VI converter comprises: A first comparator, wherein a negative input terminal of the first comparator is connected to one end of the voltage-dividing resistor, and a positive input terminal of the first comparator is connected to the other end of the voltage-dividing resistor; A pull-up resistor, one end of which is suitable for connecting to a second reference power supply; A first switch tube, wherein the control end of the first switch tube is connected to the output end of the first comparator, the first end of the first switch tube is connected to the other end of the pull-up resistor, and the second end of the first switch tube is suitable for providing a control current to the current mirror.

5. The LDO circuit according to claim 4, characterized in that: The first switch tube is a PMOS tube.

6. The LDO circuit according to claim 4, characterized in that: The current mirror comprises: A second switch tube, wherein a first end of the second switch tube is connected to the other end of the voltage-dividing resistor, and a second end of the second switch tube is grounded; A third switch tube, wherein the control end of the third switch tube is connected to the control end of the second switch tube, the first end of the third switch tube is respectively connected to the control end of the third switch tube and the second end of the first switch tube, and the second end of the third switch tube is grounded.

7. The LDO circuit according to claim 6, characterized in that: The number of the second switch tubes is determined according to the current mirror ratio of the current mirror.

8. The LDO circuit according to claim 6, characterized in that: The second switch tube and the third switch tube are NMOS tubes respectively.

9. The LDO circuit according to any one of claims 1 to 8, characterized in that: The power device is an NMOS tube.

10. The LDO circuit according to claim 9, characterized in that: The comparison unit comprises a second comparator, a positive input terminal of the second comparator is suitable for connecting the reference voltage, a negative input terminal of the second comparator is connected to the output terminal of the feedback unit, and an output terminal of the second comparator is connected to the control terminal of the power device.

11. The LDO circuit according to any one of claims 1 to 8, characterized in that: The feedback unit comprises: a first resistor, one end of the first resistor being connected to the second end of the power device; A second resistor, one end of the second resistor is connected to the other end of the first resistor and has a first node, the other end of the second resistor is grounded, and the first node serves as an output end of the feedback unit.

12. An LDO chip, characterized in that: The method comprises the LDO circuit according to any one of claims 1 to 11.

13. An LDO, characterized in that: The invention comprises the LDO chip according to claim 12.

14. An electronic device, characterized in that: Comprising the LDO according to claim 13.

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