Low dropout regulator circuit and system on chip

Abstract

The invention relates to the technical field of integrated circuit design, and discloses a low-dropout linear voltage regulator circuit and a system on chip, and the low-dropout linear voltage regulator circuit comprises a reference voltage generation circuit, a linear adjustment loop and an overshoot elimination circuit; the reference voltage generation circuit is configured to generate a reference voltage in a current-to-voltage mode; the linear adjustment loop is connected with the reference voltage generation circuit and is configured to generate an output voltage according to the reference voltage; the overshoot elimination circuit is connected with the linear adjustment loop and is configured to eliminate the overshoot phenomenon possibly occurring in the output voltage. The reference voltage is generated in a current-to-voltage mode, so that the noise of the reference voltage caused by mutual interference between different ground of each circuit module and the circuit in the system on chip can be reduced. The reference voltage can be controlled through the current in the reference voltage generation circuit, and the output trimming resistance is optimized, so that the output noise of the low dropout linear regulator circuit is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, for example, to a low voltage dropout linear regulator circuit and a system on chip. Background Art

[0002] With the rapid development of electronic technology, more and more SoC applications are replacing the original large and complex discrete electronic devices. In the field of consumer electronics, people's pursuit of multifunctional, high-performance, compact, flexible and low-cost electronic products has driven more and more SoCs to integrate more functional circuits. In order to ensure the performance of each functional circuit and reduce the crosstalk between each circuit, it has become a common practice to use separate power supplies for each functional circuit. Due to the linear feedback characteristics of its circuit structure, LDO (Low Dropout Regulator) can filter out the noise on the external power line and provide a "clean" power supply voltage for the circuit. Since a large number of LDO circuits will be used in SoCs, LDOs without external capacitors will be well used to reduce the cost of use. Switching circuits such as DCDC are generally integrated in SoCs, and SoC LDO circuits have a higher power supply rejection ratio requirement.

[0003] In the related technology, combined Figure 1 As shown in FIG. 1 , the LDO circuit structure includes an amplifier A, a PMOS tube PM, and a trimming resistor string. The trimming resistor string includes sampling resistors Rm and Rn. The sampling resistors Rm and Rn divide the output voltage Vo, and apply the divided voltage to the positive input terminal of the amplifier A to compare it with the reference voltage Vref applied to the negative input terminal. The difference between the two is amplified by the amplifier A to control the voltage drop of the PMOS tube PM, thereby stabilizing the output voltage Vo.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The trimming resistor string will introduce a lot of noise to the output voltage of the LDO.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] Embodiments of the present disclosure provide a low voltage dropout linear regulator circuit and a system on chip to reduce output noise of the low voltage dropout linear regulator circuit.

[0009] In some embodiments, a low voltage difference linear regulator circuit includes: a reference voltage generating circuit, a linear adjustment loop, and an overshoot elimination circuit; the reference voltage generating circuit is configured to generate a reference voltage by converting current into voltage; the linear adjustment loop is connected to the reference voltage generating circuit and is configured to generate an output voltage according to the reference voltage; the overshoot elimination circuit is connected to the linear adjustment loop and is configured to eliminate possible overshoot of the output voltage.

[0010] Optionally, the reference voltage generating circuit includes: a conversion circuit, a filtering circuit, and a starting circuit; the conversion circuit is configured to convert current into a starting voltage; the filtering circuit is connected to the conversion circuit and is configured to filter the starting voltage and output a reference voltage; the starting circuit is connected to both the conversion circuit and the filtering circuit and is configured to accelerate the establishment of the reference voltage.

[0011] Optionally, the conversion circuit includes: multiple current sources, a first resistor, and a second resistor; the multiple current sources are connected in parallel, the first parallel end is connected to the first power supply voltage, the second parallel end is connected to the first end of the first resistor, and a starting voltage is generated at the first end of the first resistor; the second end of the first resistor is connected to the first end of the second resistor; the second end of the second resistor is connected to the second power supply voltage.

[0012] Optionally, the filtering circuit includes: a third resistor and a first capacitor; the first end of the third resistor is connected to the first end of the first resistor; the second end of the third resistor is connected to the first end of the first capacitor and outputs a reference voltage; the second end of the first capacitor is connected to the second power supply voltage.

[0013] Optionally, the startup circuit includes: a switch, a comparator, and a second capacitor; the first end of the switch is connected to the first end of the third resistor; the second end of the switch is connected to the second end of the third resistor; the negative input end of the comparator is connected to the second end of the first resistor; the positive input end of the comparator is connected to the output voltage; the output end of the comparator is connected to the first end of the second capacitor; the second end of the second capacitor is connected to the second power supply voltage; the output end of the comparator outputs a control signal of the switch; wherein, when the output voltage is lower than a preset voltage, the comparator outputs a first level signal to control the switch to be closed; when the output voltage is higher than the preset voltage, the comparator outputs a second level signal to control the switch to be opened.

[0014] Optionally, the comparator includes: a first current source, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, and a sixth NMOS tube; a first end of the first current source is connected to a first power supply voltage; a second end of the first current source is connected to a drain of the first NMOS tube, a gate of the first NMOS tube, and a gate of the fifth NMOS tube; a source of the first PMOS tube, a source of the second PMOS tube, a source of the third PMOS tube, a source of the fourth PMOS tube, a source of the fifth PMOS tube, and a source of the sixth PMOS tube are all connected to the first power supply voltage; a gate of the first PMOS tube is connected to a gate of the second PMOS tube, a drain of the second PMOS tube, a drain of the third PMOS tube, a drain of the fourth PMOS tube, a drain of the fifth PMOS tube, and a drain of the fifth PMOS tube. The gate of the S tube and the drain of the third NMOS tube are all connected; the drain of the first PMOS tube is connected to the drain of the second NMOS tube, the gate of the second NMOS tube, and the gate of the sixth NMOS tube; the gate of the third PMOS tube is connected to the drain of the fourth PMOS tube, the drain of the fourth NMOS tube, the drain of the fifth PMOS tube, the gate of the fifth PMOS tube, and the gate of the sixth PMOS tube; the drain of the sixth PMOS tube is connected to the drain of the sixth NMOS tube as the output end of the comparator; the source of the first NMOS tube, the source of the second NMOS tube, the source of the fifth NMOS tube, and the source of the sixth NMOS tube are all connected to the second power supply voltage; the gate of the third NMOS tube serves as the negative input end of the comparator; the source of the third NMOS tube and the source of the fourth NMOS tube are connected to the drain of the fifth NMOS tube; the gate of the fourth NMOS tube serves as the positive input end of the comparator.

[0015] Optionally, the linear adjustment loop includes: an amplifier, a seventh PMOS tube, a third capacitor, and a current source load; the negative input terminal of the amplifier is connected to a reference voltage generating circuit to receive a reference voltage; the positive input terminal of the amplifier is connected to an output voltage; the output terminal of the amplifier is connected to a gate of the seventh PMOS tube; the source of the seventh PMOS tube is connected to a first power supply voltage; the drain of the seventh PMOS tube is connected to both a first end of the third capacitor and a first end of the current source load to generate an output voltage; the second end of the third capacitor is connected to the amplifier to provide loop phase margin compensation; and the second end of the current source load is connected to a second power supply voltage.

[0016] Optionally, the overshoot elimination circuit includes: a fourth capacitor, a fourth resistor, and a seventh NMOS tube; the first end of the fourth capacitor is connected to the output end of the amplifier; the second end of the fourth capacitor is connected to the first end of the fourth resistor and the gate of the seventh NMOS tube; the second end of the fourth resistor is connected to the reference voltage; the drain of the seventh NMOS tube is connected to the drain of the seventh PMOS tube; and the source of the seventh NMOS tube is connected to the second power supply voltage.

[0017] Optionally, the amplifier includes: a second current source, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, and a seventeenth NMOS tube; a first end of the second current source is connected to the first power supply voltage; a second end of the second current source is connected to the drain of the eighth NMOS tube, the gate of the eighth NMOS tube, the gate of the ninth NMOS tube, the gate of the tenth NMOS tube, and the gate of the fourteenth NMOS tube; a source of the eighth PMOS tube, a source of the ninth PMOS tube, a source of the tenth PMOS tube, a source of the eleventh PMOS tube, and a source of the twelfth PMOS tube are all connected to the first power supply voltage; a gate of the eighth PMOS tube is connected to the drain of the eighth PMOS tube, the drain of the ninth NMOS tube, the drain of the thirteenth NMOS tube, and the drain of the eighth PMOS tube. The gate of the first PMOS tube and the gate of the fourteenth PMOS tube are all connected; the gate of the ninth PMOS tube is connected to the drain of the ninth PMOS tube, the drain of the tenth NMOS tube, the gate of the tenth PMOS tube, the gate of the eleventh PMOS tube, and the gate of the twelfth PMOS tube; the drain of the tenth PMOS tube is connected to the drain of the eleventh NMOS tube, the gate of the eleventh NMOS tube, and the gate of the fifteenth NMOS tube; the drain of the eleventh PMOS tube is connected to the source of the thirteenth PMOS tube, the source of the twelfth NMOS tube, and the gate of the twelfth NMOS tube. The drain of the 12th PMOS tube is connected to the source of the 14th PMOS tube and the drain of the 13th NMOS tube; the drain of the 13th PMOS tube is connected to the drain of the 16th NMOS tube, the gate of the 16th NMOS tube, and the gate of the 17th NMOS tube; the drain of the 14th PMOS tube is connected to the drain of the 15th NMOS tube as the output end of the amplifier; the source of the 8th NMOS tube, the source of the 9th NMOS tube, the source of the 10th NMOS tube, and the source of the 11th NMOS tube. The source of the 14th NMOS tube, the source of the 16th NMOS tube, and the source of the 17th NMOS tube are all connected to the second power supply voltage; the gate of the 12th NMOS tube serves as the negative input end of the amplifier; the gate of the 13th NMOS tube serves as the positive input end of the amplifier; the source of the 12th NMOS tube, the source of the 13th NMOS tube, and the drain of the 14th NMOS tube are connected; the source of the 15th NMOS tube is connected to the drain of the 17th NMOS tube, and is connected to the second end of the third capacitor.

[0018] In some embodiments, a system on chip includes: a low dropout linear regulator circuit as described above.

[0019] The low voltage dropout linear regulator circuit and system on chip provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] In the disclosed embodiment, the low-voltage difference linear regulator circuit includes a reference voltage generating circuit, a linear adjustment loop, and an overshoot elimination circuit. Among them, the reference voltage generating circuit is configured to generate a reference voltage by converting current into voltage, which can reduce the noise caused by the mutual interference between the circuit modules and the circuits in the on-chip system. The overshoot elimination circuit can eliminate the overshoot phenomenon that may occur in the output voltage and improve the stability of the circuit. By controlling the reference voltage through the current in the reference voltage generating circuit, the output trimming resistor is optimized, and the LDO output noise contributed by the trimming resistor string in the related art can be removed. In addition, the low-voltage difference linear regulator circuit provided in the disclosed embodiment has a high power supply rejection ratio, can filter out the ripple interference generated by the on-chip DCDC converter, and provide a cleaner power supply voltage for the on-chip system. Designing the LDO circuit as a structure without external capacitors can also save space and reduce the circuit area.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 is a circuit diagram of an LDO circuit in the related art;

[0024] Figure 2 is a circuit block diagram of a low voltage dropout linear regulator circuit provided by an embodiment of the present disclosure;

[0025] Figure 3 is a circuit block diagram of another low voltage dropout linear regulator circuit provided by an embodiment of the present disclosure;

[0026] Figure 4 is a circuit diagram of a low voltage dropout linear regulator circuit provided by an embodiment of the present disclosure;

[0027] Figure 5 is a circuit diagram of a comparator in a low voltage dropout linear regulator circuit provided by an embodiment of the present disclosure;

[0028] Figure 6 It is a circuit diagram of an amplifier in a low voltage difference linear regulator circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0030] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0031] Unless otherwise stated, the term "plurality" means two or more.

[0032] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0033] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0034] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0035] Combination Figure 2 As shown, the embodiment of the present disclosure provides a low voltage drop linear regulator circuit, including: a reference voltage generating circuit 10, a linear adjustment loop 20, and an overshoot elimination circuit 30. The reference voltage generating circuit 10 is configured to generate a reference voltage VREF by converting current into voltage. The linear adjustment loop 20 is connected to the reference voltage generating circuit 10 and is configured to generate an output voltage VOUT according to the reference voltage. The overshoot elimination circuit 30 is connected to the linear adjustment loop 20 and is configured to eliminate the overshoot phenomenon that may occur in the output voltage VOUT.

[0036] The reference voltage generating circuit 10 is configured to generate a reference voltage VREF by converting current into voltage, which can reduce the noise caused by the mutual interference between the circuit modules and the circuits in the on-chip system. The overshoot elimination circuit 30 can eliminate the overshoot phenomenon that may occur in the output voltage VOUT and improve the stability of the circuit. By controlling the reference voltage VREF by the current in the reference voltage generating circuit 10, the output trimming resistor is optimized, and the LDO output noise contributed by the trimming resistor string in the related art can be removed. In addition, the low-voltage difference linear regulator circuit provided in the embodiment of the present disclosure has a high power supply rejection ratio, can filter out the ripple interference generated by the on-chip DCDC converter, and provide a cleaner power supply voltage for the on-chip system. Designing the LDO circuit as a structure without external capacitors can also save space and reduce the circuit area.

[0037] Optionally, combined Figure 3 As shown, the reference voltage generating circuit 10 includes: a conversion circuit 11, a filter circuit 12, and a startup circuit 13. The conversion circuit 11 is configured to convert the current into a startup voltage VREF_S. The filter circuit 12 is connected to the conversion circuit 11 and is configured to filter the startup voltage VREF_S and output the reference voltage VREF. The startup circuit 13 is connected to both the conversion circuit 11 and the filter circuit 12 and is configured to accelerate the establishment of the reference voltage VREF.

[0038] In this embodiment, the reference voltage VREF realizes the current-to-voltage function through the conversion circuit 11 to obtain the startup voltage VREF_S. The filter circuit 12 can filter the startup voltage VREF_S to filter out noise and obtain the reference voltage VREF. Since the filter circuit 12 requires a long establishment time during the circuit power-on process, a startup circuit 13 is provided in the reference voltage generation circuit 10 to accelerate the establishment of the reference voltage VREF after the circuit is started.

[0039] Optionally, combined Figure 4 As shown, the conversion circuit 11 includes: a plurality of current sources (1I, I2, ..., IN), a first resistor R1, and a second resistor R2. The plurality of current sources are connected in parallel, the first parallel end is connected to the first power supply voltage VCC, the second parallel end is connected to the first end of the first resistor R1, and the start voltage VREF_S is generated at the first end of the first resistor R1; the second end of the first resistor R1 is connected to the first end of the second resistor R2; and the second end of the second resistor R2 is connected to the second power supply voltage VSS.

[0040] Optionally, the first power supply voltage VCC is an external power supply terminal; the second power supply voltage VSS is a ground terminal.

[0041] In this embodiment, the conversion circuit 11 uses a plurality of current sources connected in parallel to generate a current flowing through the first resistor R1 and the second resistor R2 to generate a startup voltage VREF_S. Each current source branch is provided with a control switch (S1, S2, ..., SN). Therefore, by controlling the switch to adjust the number and size of the current source, the startup voltage VREF_S can be accurately controlled, thereby achieving control of the reference voltage VREF. By converting current to voltage, the noise caused by the mutual interference between the circuit modules and the circuits in the on-chip system to the reference voltage VREF can be reduced.

[0042] Optionally, combined Figure 4 As shown, the filter circuit 12 includes: a third resistor R3 and a first capacitor C1. The first end of the third resistor R3 is connected to the first end of the first resistor R1; the second end of the third resistor R3 is connected to the first end of the first capacitor C1 and outputs a reference voltage VREF; the second end of the first capacitor C1 is connected to the second power supply voltage VSS.

[0043] In this embodiment, the filter circuit 12 uses a low-pass filter composed of a third resistor R3 and a first capacitor C1 to perform low-pass filtering on the start-up voltage VREF_S to remove unnecessary high-frequency noise, thereby obtaining a reference voltage VREF.

[0044] Optionally, combined Figure 4 As shown, the startup circuit 13 includes: a switch S, a comparator COMP, and a second capacitor C2. The first end of the switch S is connected to the first end of the third resistor R3; the second end of the switch S is connected to the second end of the third resistor R3; the negative input end of the comparator COMP is connected to the second end of the first resistor R1; the positive input end of the comparator COMP is connected to the output voltage VOUT; the output end of the comparator COMP is connected to the first end of the second capacitor C2; the second end of the second capacitor C2 is connected to the second power supply voltage VSS; the output end VOUT_COMP of the comparator COMP outputs the control signal of the switch S. Wherein, when the output voltage VOUT is lower than the preset voltage, the comparator COMP outputs a first level signal to control the switch S to close; when the output voltage VOUT is higher than the preset voltage, the comparator COMP outputs a second level signal to control the switch S to open.

[0045] Optionally, the preset voltage is a divided voltage of the first resistor R1 and the second resistor R2; the first level signal is a low level signal, and the second level signal is a high level signal.

[0046] In this embodiment, a switch S is connected in parallel at both ends of the third resistor R3. When the switch S is closed, the third resistor R3 is short-circuited, and a low-resistance path is formed between the start-up voltage VREF_S and the reference voltage VREF through the switch S, and the reference voltage VREF can be quickly increased. When the switch S is disconnected, the reference voltage VREF is formed by filtering the start-up voltage VREF_S through the filter circuit 12. The control signal of the switch S is the output signal of the comparator COMP. The negative input terminal of the comparator COMP is the divided voltage of the first resistor R1 and the second resistor R2, and the positive input terminal is the output voltage VOUT. When the circuit is just started, the output voltage VOUT is low, lower than the divided voltage of the first resistor R1 and the second resistor R2. At this time, the comparator COMP outputs a low-level signal, the switch S is closed, and the reference voltage VREF can be quickly increased. As the reference voltage VREF increases, the output voltage VOUT also increases. When the output voltage VOUT is higher than the divided voltage of the first resistor R1 and the second resistor R2, the comparator COMP outputs a high level signal and the control switch S is turned on. At this time, the reference voltage VREF is the start-up voltage VREF_S formed after filtering by the filter circuit 12.

[0047] Optionally, combined Figure 5 As shown, the comparator COMP includes: a first current source I_REF1, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, and a sixth NMOS tube NM6.

[0048] The first end of the first current source I_REF1 is connected to the first power supply voltage VCC; the second end of the first current source I_REF1 is connected to the drain of the first NMOS tube NM1, the gate of the first NMOS tube NM1, and the gate of the fifth NMOS tube NM5; the source of the first PMOS tube PM1, the source of the second PMOS tube PM2, the source of the third PMOS tube PM3, the source of the fourth PMOS tube PM4, the source of the fifth PMOS tube PM5, and the source of the sixth PMOS tube PM6 are all connected to the first power supply voltage VCC; the gate of the first PMOS tube PM1 is connected to the gate of the second PMOS tube PM2, the drain of the second PMOS tube PM2, the drain of the third PMOS tube PM3, the gate of the fourth PMOS tube PM4, and the drain of the third NMOS tube NM3; the drain of the first PMOS tube PM1 is connected to the drain of the second NMOS tube NM2, the gate of the second NMOS tube NM2, the gate of the sixth NMOS tube PM6, and the drain of the third PMOS tube PM4. The gates of the third PMOS tube PM3 are all connected to the drain of the fourth PMOS tube PM4, the drain of the fourth NMOS tube NM4, the drain of the fifth PMOS tube PM5, the gate of the fifth PMOS tube PM5, and the gate of the sixth PMOS tube PM6; the drain of the sixth PMOS tube PM6 is connected to the drain of the sixth NMOS tube NM6 as the output terminal VOUT_COMP of the comparator COMP; the source of the first NMOS tube NM1, the source of the second NMOS tube NM2, the source of the fifth NMOS tube NM5, and the source of the sixth NMOS tube NM6 are all connected to the second power supply voltage VSS; the gate of the third NMOS tube NM3 serves as the negative input terminal of the comparator COMP; the source of the third NMOS tube NM3 and the source of the fourth NMOS tube NM4 are all connected to the drain of the fifth NMOS tube NM5; the gate of the fourth NMOS tube NM4 serves as the positive input terminal of the comparator COMP.

[0049] Optionally, combined Figure 4 As shown, the linear adjustment loop 20 includes: an amplifier AMP, a seventh PMOS transistor PM7, a third capacitor C3, and a current source load I_LOAD. The negative input terminal of the amplifier AMP is connected to the reference voltage generating circuit 10 to receive the reference voltage VREF; the positive input terminal of the amplifier AMP is connected to the output voltage VOUT; the output terminal VOUT_AMP of the amplifier AMP is connected to the gate of the seventh PMOS transistor PM7; the source of the seventh PMOS transistor PM7 is connected to the first power supply voltage VCC; the drain of the seventh PMOS transistor PM7 is connected to the first end of the third capacitor C3 and the first end of the current source load I_LOAD to generate the output voltage VOUT; the second end of the third capacitor C3 is connected to the amplifier AMP to provide loop phase margin compensation; the second end of the current source load I_LOAD is connected to the second power supply voltage VSS.

[0050] In this embodiment, the trimming resistor string at the output end of the amplifier AMP is removed, thereby removing the output noise provided by the trimming resistor string. By adding a current source load I_LOAD at the output end, the linear adjustment loop 20 can provide a stable output voltage VOUT within a wide load range. The third capacitor C3 is connected to the FB_AMP port of the amplifier to provide loop phase margin compensation for the circuit. The phase margin refers to the difference between the output and input phase difference and -180 degrees when the open-loop gain is 1. The third capacitor C3 introduces additional phase delay and adjusts the phase characteristics of the circuit through a compensation network, which can increase the phase margin of the circuit, thereby improving the stability and robustness of the circuit and enabling the circuit to have a good transient response.

[0051] Optionally, combined Figure 4 As shown, the overshoot elimination circuit 30 includes: a fourth capacitor C4, a fourth resistor R4, and a seventh NMOS transistor NM7. The first end of the fourth capacitor C4 is connected to the output end of the amplifier AMP; the second end of the fourth capacitor C4 is connected to the first end of the fourth resistor R4 and the gate of the seventh NMOS transistor NM7; the second end of the fourth resistor R4 is connected to the reference voltage V_BIAS; the drain of the seventh NMOS transistor NM7 is connected to the drain of the seventh PMOS transistor PM7; and the source of the seventh NMOS transistor NM7 is connected to the second power supply voltage VSS.

[0052] In this embodiment, the overshoot elimination circuit 30 can ensure that the circuit can quickly stabilize when starting or when the load changes, and avoid overshoot of the output voltage VOUT. When the LDO circuit starts, the overshoot elimination circuit 30 can help the circuit quickly reach a stable working state and reduce the startup time. When the load changes suddenly or the circuit parameters change, the overshoot elimination circuit 30 can prevent the output voltage VOUT from exceeding the expected maximum value, thereby protecting the subsequent circuit from damage. By controlling the output voltage VOUT, the overshoot elimination circuit 30 ensures that the LDO can provide a stable voltage output under different working conditions. The overshoot elimination circuit 30 also helps to improve the power supply rejection ratio of the LDO, thereby reducing power supply ripple and noise and improving circuit performance.

[0053] Optionally, combined Figure 6As shown, the amplifier AMP includes: a second current source I_REF2, an eighth PMOS tube PM8, a ninth PMOS tube PM9, a tenth PMOS tube PM10, an eleventh PMOS tube PM11, a twelfth PMOS tube PM12, a thirteenth PMOS tube PM13, a fourteenth PMOS tube PM14, an eighth NMOS tube NM8, a ninth NMOS tube NM9, a tenth NMOS tube NM10, an eleventh NMOS tube NM11, a twelfth NMOS tube NM12, a thirteenth NMOS tube NM13, a fourteenth NMOS tube NM14, a fifteenth NMOS tube NM15, a sixteenth NMOS tube NM16, and a seventeenth NMOS tube NM17.

[0054] The first end of the second current source I_REF2 is connected to the first power supply voltage VCC; the second end of the second current source I_REF2 is connected to the drain of the eighth NMOS tube NM8, the gate of the eighth NMOS tube NM8, the gate of the ninth NMOS tube NM9, the gate of the tenth NMOS tube NM10, and the gate of the fourteenth NMOS tube NM14; the source of the eighth PMOS tube PM8, the source of the ninth PMOS tube PM9, the source of the tenth PMOS tube PM10, the source of the eleventh PMOS tube PM11, the source of the twelfth PMOS tube PM12, the source of the twelfth PMOS tube PM13, the source of the twelfth PMOS tube PM14, the source of the twelfth PMOS tube PM15, the source of the twelfth PMOS tube PM16, the source of the twelfth PMOS tube PM17, the source of the twelfth PMOS tube PM18, the source of the twelfth PMOS tube PM19, the source of the twelfth PMOS tube PM20, the source of the twelfth PMOS tube PM21, the source of the twelfth PMOS tube PM22, the source of the twelfth PMOS tube PM23, the source of the twelfth PMOS tube PM24, the source of the twelfth PMOS tube PM25, the source of the twelfth PMOS tube PM26, the source of the twelfth PMOS tube PM27, the source of the twelfth PMOS tube PM28, the source of the twelfth PMOS tube PM29, the source of the twelfth PMOS tube PM21, the source of the twelfth The source of the PMOS tube PM12 is connected to the first power supply voltage VCC; the gate of the eighth PMOS tube PM8 is connected to the drain of the eighth PMOS tube PM8, the drain of the ninth NMOS tube NM9, the gate of the thirteenth PMOS tube PM13, and the gate of the fourteenth PMOS tube PM14; the gate of the ninth PMOS tube PM9 is connected to the drain of the ninth PMOS tube PM9, the drain of the tenth NMOS tube NM10, the gate of the tenth PMOS tube PM10, the gate of the eleventh PMOS tube PM11, the gate of the twelfth PMOS tube PM12, and the gate of the twelfth PMOS tube PM13. The gate of the 11th PMOS tube PM10 is connected to the drain of the 12th PMOS tube PM14 and the drain of the 13th NMOS tube NM15; the drain of the 14th PMOS tube PM14 is connected to the drain of the 15th NMOS tube NM16; the drain of the 16th PMOS tube PM11 is connected to the source of the 17th PMOS tube PM13 and the drain of the 18th NMOS tube NM17; the drain of the 19th PMOS tube PM12 is connected to the source of the 14th PMOS tube PM14 and the drain of the 18th NMOS tube NM16. the drain of the thirteenth PMOS tube PM13 is connected to the drain of the sixteenth NMOS tube NM16, the gate of the sixteenth NMOS tube NM16, and the gate of the seventeenth NMOS tube NM17; the drain of the fourteenth PMOS tube PM14 is connected to the drain of the fifteenth NMOS tube NM15, as the output terminal VOUT_AMP of the amplifier AMP; the source of the eighth NMOS tube NM8, the source of the ninth NMOS tube NM9, the source of the tenth NMOS tube NM10, and the source of the eleventh NMOS tube NM11. The source of the fourteenth NMOS tube NM14, the source of the sixteenth NMOS tube NM16, and the source of the seventeenth NMOS tube NM17 are all connected to the second power supply voltage VSS; the gate of the twelfth NMOS tube NM12 serves as the negative input terminal of the amplifier AMP; the gate of the thirteenth NMOS tube NM13 serves as the positive input terminal of the amplifier AMP; the source of the twelfth NMOS tube NM12, the source of the thirteenth NMOS tube NM13 and the drain of the fourteenth NMOS tube NM14 are connected; the source of the fifteenth NMOS tube NM15 is connected to the drain of the seventeenth NMOS tube NM17 as the FB_AMP terminal of the amplifier, and is connected to the second end of the third capacitor C3.

[0055] In this embodiment, the amplifier AMP adopts a folded unipolar operational amplifier structure, which provides a larger bandwidth while ensuring the loop gain, thereby meeting the requirement of the LDO circuit to provide a higher power supply rejection ratio.

[0056] In some embodiments, the present disclosure also provides a system on chip, including the low voltage dropout linear regulator circuit as described above.

[0057] The low-dropout linear regulator circuit provided by the embodiment of the present disclosure reduces the LDO reference voltage VREF input noise caused by different grounds and crosstalk between different circuits by changing the voltage reference input of the traditional LDO to a current-to-voltage input and optimizing the output adjustment resistor string, thereby effectively reducing the output noise of the LDO. The LDO circuit provided by the embodiment of the present disclosure also has a high power supply rejection ratio, which can filter out the ripple interference generated by the on-chip DCDC converter and provide a cleaner power supply voltage for the on-chip system. The LDO circuit is designed as a structure without external capacitors, which reduces the demand for external components, reduces costs, saves space, is suitable for integration into the SOC chip, and helps to reduce the size of the chip. Through optimized design, the LDO circuit can respond quickly to load changes and provide a stable voltage output. The use of the LDO circuit makes the internal power supply of the SOC chip more flexible and efficient, and reduces the mutual interference problem between the functional circuits.

[0058] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

Claims

1. A low voltage dropout linear regulator circuit, characterized in that: include: Reference voltage generation circuit, linear adjustment loop, overshoot elimination circuit; The reference voltage generating circuit is configured to generate a reference voltage by converting current into voltage; The linear adjustment loop is connected to the reference voltage generating circuit and is configured to generate an output voltage according to the reference voltage; The overshoot elimination circuit is connected to the linear regulation loop and is configured to eliminate possible overshoot phenomenon of the output voltage.

2. The low voltage dropout linear regulator circuit according to claim 1, characterized in that: The reference voltage generating circuit includes: a conversion circuit, a filtering circuit, and a starting circuit; The conversion circuit is configured to convert the current into a starting voltage; The filter circuit is connected to the conversion circuit and is configured to filter the start-up voltage and output a reference voltage; The startup circuit is connected to both the conversion circuit and the filtering circuit and is configured to accelerate the establishment of the reference voltage.

3. The low voltage dropout linear regulator circuit according to claim 2, characterized in that: The conversion circuit includes: a plurality of current sources, a first resistor, and a second resistor; Multiple current sources are connected in parallel, the first parallel end is connected to the first power supply voltage, the second parallel end is connected to the first end of the first resistor, and a starting voltage is generated at the first end of the first resistor; the second end of the first resistor is connected to the first end of the second resistor; and the second end of the second resistor is connected to the second power supply voltage.

4. The low voltage dropout linear regulator circuit according to claim 3, characterized in that: The filter circuit includes: a third resistor and a first capacitor; The first end of the third resistor is connected to the first end of the first resistor; the second end of the third resistor is connected to the first end of the first capacitor and outputs a reference voltage; the second end of the first capacitor is connected to the second power supply voltage.

5. The low voltage dropout linear regulator circuit according to claim 4, characterized in that: The startup circuit includes: a switch, a comparator, and a second capacitor; The first end of the switch is connected to the first end of the third resistor; the second end of the switch is connected to the second end of the third resistor; the negative input end of the comparator is connected to the second end of the first resistor; the positive input end of the comparator is connected to the output voltage; the output end of the comparator is connected to the first end of the second capacitor; the second end of the second capacitor is connected to the second power supply voltage; the output end of the comparator outputs a control signal of the switch; When the output voltage is lower than the preset voltage, the comparator outputs a first level signal to control the switch to be closed; when the output voltage is higher than the preset voltage, the comparator outputs a second level signal to control the switch to be opened.

6. The low voltage dropout linear regulator circuit according to claim 5, characterized in that: The comparators include: A first current source, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, and a sixth NMOS tube; The first end of the first current source is connected to the first power supply voltage; the second end of the first current source is connected to the drain of the first NMOS tube, the gate of the first NMOS tube, and the gate of the fifth NMOS tube; the source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube, the source of the fourth PMOS tube, the source of the fifth PMOS tube, and the source of the sixth PMOS tube are all connected to the first power supply voltage; the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the drain of the second PMOS tube, the drain of the third PMOS tube, the gate of the fourth PMOS tube, and the drain of the third NMOS tube; the drain of the first PMOS tube is connected to the drain of the second NMOS tube, the gate of the second NMOS tube, the gate of the sixth NMOS tube, and the drain of the third PMOS tube. The gates of the MOS tubes are all connected; the gate of the third PMOS tube is connected to the drain of the fourth PMOS tube, the drain of the fourth NMOS tube, the drain of the fifth PMOS tube, the gate of the fifth PMOS tube, and the gate of the sixth PMOS tube; the drain of the sixth PMOS tube is connected to the drain of the sixth NMOS tube as the output end of the comparator; the source of the first NMOS tube, the source of the second NMOS tube, the source of the fifth NMOS tube, and the source of the sixth NMOS tube are all connected to the second power supply voltage; the gate of the third NMOS tube serves as the negative input end of the comparator; the source of the third NMOS tube and the source of the fourth NMOS tube are all connected to the drain of the fifth NMOS tube; the gate of the fourth NMOS tube serves as the positive input end of the comparator.

7. The low voltage dropout linear regulator circuit according to any one of claims 1 to 6, characterized in that: The linear adjustment loop includes: an amplifier, a seventh PMOS tube, a third capacitor, and a current source load; The negative input terminal of the amplifier is connected to the reference voltage generating circuit to receive the reference voltage; the positive input terminal of the amplifier is connected to the output voltage; the output terminal of the amplifier is connected to the gate of the seventh PMOS tube; the source of the seventh PMOS tube is connected to the first power supply voltage; the drain of the seventh PMOS tube is connected to the first end of the third capacitor and the first end of the current source load to generate an output voltage; the second end of the third capacitor is connected to the amplifier to provide loop phase margin compensation; the second end of the current source load is connected to the second power supply voltage.

8. The low voltage dropout linear regulator circuit according to claim 7, characterized in that: The overshoot elimination circuit comprises: a fourth capacitor, a fourth resistor, and a seventh NMOS tube; The first end of the fourth capacitor is connected to the output end of the amplifier; the second end of the fourth capacitor is connected to the first end of the fourth resistor and the gate of the seventh NMOS tube; the second end of the fourth resistor is connected to the reference voltage; the drain of the seventh NMOS tube is connected to the drain of the seventh PMOS tube; and the source of the seventh NMOS tube is connected to the second power supply voltage.

9. The low voltage dropout linear regulator circuit according to claim 7, characterized in that: The amplifier includes: a second current source, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, and a seventeenth NMOS tube; The first end of the second current source is connected to the first power supply voltage; the second end of the second current source is connected to the drain of the eighth NMOS tube, the gate of the eighth NMOS tube, the gate of the ninth NMOS tube, the gate of the tenth NMOS tube, and the gate of the fourteenth NMOS tube; the source of the eighth PMOS tube, the source of the ninth PMOS tube, the source of the tenth PMOS tube, the source of the eleventh PMOS tube, and the source of the twelfth PMOS tube are all connected to the first power supply voltage; the gate of the eighth PMOS tube is connected to the drain of the eighth PMOS tube, the drain of the ninth NMOS tube, the gate of the thirteenth PMOS tube, and the gate of the fourteenth PMOS tube; the gate of the ninth PMOS tube is connected to the drain of the ninth PMOS tube, the drain of the tenth NMOS tube, the gate of the tenth PMOS tube, the gate of the eleventh PMOS tube, the gate of the tenth The gates of the second PMOS tube are all connected; the drain of the tenth PMOS tube is connected to the drain of the eleventh NMOS tube, the gate of the eleventh NMOS tube, and the gate of the fifteenth NMOS tube; the drain of the eleventh PMOS tube is connected to the source of the thirteenth PMOS tube and the drain of the twelfth NMOS tube; the drain of the twelfth PMOS tube is connected to the source of the fourteenth PMOS tube and the drain of the thirteenth NMOS tube; the drain of the thirteenth PMOS tube is connected to the drain of the sixteenth NMOS tube, the gate of the sixteenth NMOS tube, and the gate of the seventeenth NMOS tube; the drain of the fourteenth PMOS tube is connected to the drain of the fifteenth NMOS tube as the output end of the amplifier; the source of the eighth NMOS tube, the source of the ninth NMOS tube, the source of the tenth NMOS tube, and the source of the eleventh NMOS tube. The source of the fourteenth NMOS tube, the source of the sixteenth NMOS tube, and the source of the seventeenth NMOS tube are all connected to the second power supply voltage; the gate of the twelfth NMOS tube serves as the negative input terminal of the amplifier; the gate of the thirteenth NMOS tube serves as the positive input terminal of the amplifier; the source of the twelfth NMOS tube, the source of the thirteenth NMOS tube and the drain of the fourteenth NMOS tube are connected; the source of the fifteenth NMOS tube is connected to the drain of the seventeenth NMOS tube, and is connected to the second end of the third capacitor.

10. A system on chip, characterized in that: include: A low voltage dropout linear regulator circuit as claimed in any one of claims 1 to 9.

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