Low dropout regulator circuit, electronic chip and automobile

Abstract

The invention relates to the technical field of automobile electronic chips, and discloses a low-dropout linear regulator circuit, an electronic chip and an automobile, and the low-dropout linear regulator circuit comprises an inverter amplifier, a driving circuit and a high-bandwidth loop; the inverter amplifier is implemented based on an inverter and is configured to generate an amplified voltage according to a reference voltage and a feedback voltage of an output voltage; the driving circuit is connected with the inverter amplifier and is configured to generate an output voltage and a feedback voltage of the output voltage according to the amplified voltage; and the high-bandwidth loop is connected with the inverter amplifier and the driving circuit, and is configured to adjust the output voltage through a negative feedback loop formed by the inverter amplifier and the driving circuit. The low-dropout linear regulator circuit provided by the invention has a higher power supply rejection ratio and a larger voltage input range while having a high transient response characteristic.

Description

Technical Field

[0001] The present application relates to the technical field of automotive electronic chips, for example, to a low voltage drop linear regulator circuit, an electronic chip and an automobile. Background Art

[0002] At present, with the continuous advancement of automobile intelligence and electrification, LDO (Low Dropout Regulator) is becoming more and more important in the design of automotive chips, especially in applications such as power systems, chassis systems, domain control systems and body systems. LDO usually has large AC disturbances in places such as chip load ends and power supplies, so more new requirements are put forward for the transient response, voltage input range and PSRR (Power Supply Rejection Ratio) of LDO in the chip.

[0003] In the related technology, combined Figure 1 As shown in the figure, the LDO circuit connects the voltage generated by the output voltage division to the error amplifier EA through two resistors r1 and r2. The error amplifier EA compares the voltage with the bandgap reference voltage and outputs the error value. The power tube PM uses the error value output by the error amplifier EA to adjust the output voltage to achieve a stable output.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The LDO circuit in the related art is lacking in characteristics such as transient response, PSRR and voltage input range, and is unable to have a larger PSRR and voltage input range while having high transient response characteristics.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a low dropout linear regulator circuit, an electronic chip, and a car, so that the LDO circuit has a higher transient response characteristic while having a larger PSRR and a voltage input range.

[0009] In some embodiments, a low voltage difference linear regulator circuit includes: an inverter amplifier, a drive circuit and a high bandwidth loop; the inverter amplifier is implemented based on an inverter and is configured to generate an amplified voltage based on a reference voltage and a feedback voltage of the output voltage; the drive circuit is connected to the inverter amplifier and is configured to generate an output voltage and a feedback voltage of the output voltage based on the amplified voltage; the high bandwidth loop is connected to both the inverter amplifier and the drive circuit and is configured to adjust the output voltage through a negative feedback loop formed by the inverter amplifier and the drive circuit.

[0010] Optionally, the inverter amplifier includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter and an auxiliary amplifier; the input end of the first inverter is connected to the feedback voltage; the input end of the second inverter is connected to the reference voltage; the output end of the second inverter and the output end of the fourth inverter are both connected to the input end of the auxiliary amplifier; the output end of the auxiliary amplifier is connected to the input end of the fourth inverter and the input end of the third inverter; the output end of the third inverter, the output end of the first inverter and the input end of the fifth inverter are all connected; the output end of the fifth inverter outputs the amplified voltage.

[0011] Optionally, the fourth inverter is configured to match the gain of the reference voltage and the feedback voltage and serve as a transimpedance load for the second inverter.

[0012] Optionally, the auxiliary amplifier is configured to maintain a stable loop gain, widen the reference voltage input range, and improve the power supply rejection ratio when the reference voltage deviates from the target voltage.

[0013] Optionally, the driving circuit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a first capacitor, a second capacitor, a first resistor, a second resistor and a third resistor;

[0014] The source of the first PMOS tube and the source of the second PMOS tube are connected to the power supply; the gate of the first PMOS tube, the gate of the second PMOS tube, and the drain of the first PMOS tube are all connected to the drain of the first NMOS tube; the gate of the first NMOS tube and the first end of the first capacitor are all connected to the amplified voltage; the source of the first NMOS tube and the second end of the first capacitor are all grounded; the drain of the second PMOS tube generates an output voltage; the drain of the second PMOS tube is connected to the first end of the first resistor, the first end of the second capacitor, and the first end of the third resistor; the second end of the first resistor is connected to the first end of the second resistor and generates a feedback voltage of the output voltage; the second end of the second resistor, the second end of the second capacitor, and the second end of the third resistor are all grounded.

[0015] Optionally, the high bandwidth loop includes: a third PMOS tube, a fourth PMOS tube, a sixth inverter, a third capacitor, a second NMOS tube and a third NMOS tube;

[0016] The source of the third PMOS tube and the source of the fourth PMOS tube are both connected to the power supply; the gate of the third PMOS tube, the gate of the fourth PMOS tube, and the drain of the fourth PMOS tube are all connected to the drain of the third NMOS tube; the drain of the third PMOS tube is connected to the drain of the first NMOS tube; the input end of the sixth inverter is connected to the amplified voltage; the output end of the sixth inverter is connected to the first end of the third capacitor, the gate of the second NMOS tube, and the gate of the third NMOS tube; the second end of the third capacitor is grounded; the drain of the second NMOS tube is connected to the output voltage; the source of the second NMOS tube and the source of the third NMOS tube are both grounded.

[0017] Optionally, when the output voltage exceeds the preset voltage, through the negative feedback loop, the input terminal voltage of the sixth inverter is low level, the output terminal voltage of the sixth inverter, the gate voltages of the second NMOS tube and the third NMOS tube are high level, the second NMOS tube and the third NMOS tube are turned on, and the output voltage is pulled down;

[0018] When the output voltage is close to the preset voltage, through the negative feedback loop, the input voltage of the sixth inverter is high, the output voltage of the sixth inverter and the gate voltages of the second NMOS tube and the third NMOS tube are low, the second NMOS tube and the third NMOS tube are cut off, and the output voltage is not affected.

[0019] Optionally, the capacitance of the third capacitor is smaller than the preset capacitance.

[0020] In some embodiments, an electronic chip includes a low dropout linear regulator circuit as described above.

[0021] In some embodiments, a car includes an electronic chip as described above.

[0022] The low voltage difference linear regulator circuit, electronic chip and automobile provided by the embodiments of the present disclosure can achieve the following technical effects:

[0023] The low-dropout linear regulator circuit provided by the embodiment of the present disclosure includes an inverter amplifier, a drive circuit and a high-bandwidth loop. Among them, the inverter amplifier is implemented based on an inverter, and the inverter can provide negative resistance enhancement, reduce the impact of input voltage fluctuations on the output voltage, and provide greater driving force when the output voltage undergoes transient changes, quickly recover to a stable state, and help maintain a stable output within a wide voltage range. The LDO circuit can operate within a wider voltage input range while improving the PSRR. The design of the high-bandwidth loop enables the LDO circuit to respond quickly when the output voltage deviates from the normal range, and restores to the normal range by quickly pulling down the output voltage, thereby improving the transient response speed and safety of the LDO circuit. Therefore, the low-dropout linear regulator circuit provided by the embodiment of the present disclosure has a larger PSRR and voltage input range while having high transient response characteristics.

[0024] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0026] Figure 1 is a circuit diagram of an LDO circuit in the related art;

[0027] Figure 2 is a circuit block diagram of a low voltage dropout linear regulator circuit provided by an embodiment of the present disclosure;

[0028] Figure 3 is a circuit diagram of an inverter amplifier in a low voltage difference linear regulator circuit provided by an embodiment of the present disclosure;

[0029] Figure 4 is a circuit diagram of a driving circuit in a low voltage dropout linear regulator circuit provided by an embodiment of the present disclosure;

[0030] Figure 5 is a circuit diagram of a high-bandwidth loop in a low-dropout linear regulator circuit provided by an embodiment of the present disclosure;

[0031] Figure 6 is a circuit diagram of a low voltage dropout linear regulator circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0033] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0034] Unless otherwise stated, the term "plurality" means two or more.

[0035] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0036] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0037] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0038] Combination Figure 2 As shown, an embodiment of the present disclosure provides a low voltage dropout linear regulator circuit, including an inverter amplifier 10 , a drive circuit 20 and a high bandwidth loop 30 .

[0039] The inverter amplifier 10 is implemented based on an inverter and is configured to generate an amplified voltage VG according to a reference voltage Vref and a feedback voltage Vfb of an output voltage VOUT. The drive circuit 20 is connected to the inverter amplifier 10 and is configured to generate an output voltage VOUT and a feedback voltage Vfb of the output voltage VOUT according to the amplified voltage VG. The high-bandwidth loop 30 is connected to both the inverter amplifier 10 and the drive circuit 20 and is configured to adjust the output voltage VOUT through a negative feedback loop formed by the inverter amplifier 10 and the drive circuit 20.

[0040] In the embodiment of the present disclosure, the inverter amplifier 10 is implemented based on an inverter, which can provide negative resistance enhancement, reduce the impact of input voltage fluctuations on the output voltage VOUT, and provide greater driving force when the output voltage VOUT undergoes transient changes, quickly recover to a stable state, and help maintain a stable output within a wide voltage range. The LDO circuit can operate within a wider voltage input range while improving the PSRR. The design of the high-bandwidth loop 30 enables the LDO circuit to respond quickly when the output voltage VOUT deviates from the normal range, and restores to the normal range by quickly pulling down the output voltage VOUT, thereby improving the transient response speed and safety of the LDO circuit. Therefore, the low-voltage difference linear regulator circuit provided in the embodiment of the present disclosure has a larger PSRR and voltage input range while having high transient response characteristics.

[0041] Optionally, combined Figure 3 As shown, the inverter amplifier 10 includes: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5 and an auxiliary amplifier AUX. The input end of the first inverter INV1 is connected to the feedback voltage Vfb; the input end of the second inverter INV2 is connected to the reference voltage Vref; the output end of the second inverter INV2 and the output end of the fourth inverter INV4 are both connected to the input end of the auxiliary amplifier AUX; the output end of the auxiliary amplifier AUX is connected to the input end of the fourth inverter INV4 and the input end of the third inverter INV3; the output end of the third inverter INV3 and the output end of the first inverter INV1 are all connected to the input end of the fifth inverter INV5; the output end of the fifth inverter INV5 outputs the amplified voltage VG.

[0042] In this embodiment, the inverter amplifier 10 receives the feedback voltage Vfb through the first inverter INV1, and the second inverter INV2 receives the reference voltage Vref. The output of the second inverter INV2 passes through the auxiliary amplifier AUX, and then is inverted by the third inverter INV3, and the difference is calculated with the output of the first inverter INV1. The fifth inverter INV5 inverts the difference and provides it to the drive circuit 20 as the amplified voltage VG. Therefore, the inverter amplifier 10 can obtain the amplified voltage VG by comparing the reference voltage Vref and the feedback voltage Vfb, and the amplified voltage VG acts on the drive circuit 20 to obtain a stable output voltage VOUT.

[0043] Optionally, the fourth inverter INV4 is configured to match the gains of the reference voltage Vref and the feedback voltage Vfb, and serves as a transimpedance load of the second inverter INV2.

[0044] In this embodiment, the fourth inverter INV4 is used to match the gain of the reference voltage Vref and the feedback voltage Vfb, ensuring that the signal in the inverter amplifier 10 can be correctly processed and compared, which helps to maintain the stability and responsiveness of the circuit. In addition, the fourth inverter INV4 also serves as a transimpedance load of the second inverter INV2 to help manage the impedance matching in the circuit to improve the integrity of the signal and the stability of the circuit.

[0045] Optionally, the auxiliary amplifier AUX is configured to maintain a stable loop gain, widen the input range of the reference voltage Vref, and improve the power supply rejection ratio when the reference voltage Vref deviates from the target voltage.

[0046] Optionally, the target voltage is an optimal voltage of the reference voltage Vref.

[0047] In this embodiment, the auxiliary amplifier AUX can help stabilize the loop gain of the entire LDO circuit, especially when the reference voltage Vref deviates from the optimal operating point, by providing additional gain to ensure that the circuit remains stable under different operating conditions. When the input voltage is low or high, the auxiliary amplifier AUX can ensure that the inverter amplifier 10 can generate enough amplified voltage VG to adjust the output voltage VOUT by providing the necessary gain, thereby widening the voltage input range of the LDO. The auxiliary amplifier AUX also helps to improve the PSRR of the LDO circuit. By amplifying the error signal, the auxiliary amplifier AUX can more effectively combat power supply noise and reduce the impact of input power supply noise on the output voltage VOUT. In addition, when the load changes or the input voltage changes, the auxiliary amplifier AUX can respond quickly and provide the necessary gain to help the LDO circuit quickly adjust the output voltage VOUT, thereby improving the transient response.

[0048] Optionally, combined Figure 4 and Figure 6As shown, the driving circuit 20 includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2 and a third resistor R3. The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are connected to the power supply VDD; the gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, and the drain of the first PMOS transistor PM1 are all connected to the drain of the first NMOS transistor NM1, and a voltage signal V1 is generated at the drain of the first NMOS transistor NM1; the gate of the first NMOS transistor NM1 and the first end of the first capacitor C1 are all connected to the amplified voltage VG; the source of the first NMOS transistor NM1 and the second end of the first capacitor C1 are all grounded; the drain of the second PMOS transistor PM2 generates an output voltage VOUT; the drain of the second PMOS transistor PM2 is all connected to the first end of the first resistor R1, the first end of the second capacitor C2, and the first end of the third resistor R3; the second end of the first resistor R1 is connected to the first end of the second resistor R2, and a feedback voltage Vfb of the output voltage VOUT is generated; the second end of the second resistor R2, the second end of the second capacitor C2, and the second end of the third resistor R3 are all grounded.

[0049] In this embodiment, the drive circuit 20 can convert the amplified voltage VG generated by the inverter amplifier 10 into control of the MOS tube to adjust the output voltage VOUT. The output voltage VOUT is divided by the first resistor R1 and the second resistor R2 to generate a feedback voltage Vfb, thereby forming a feedback loop of the inverter amplifier 10 and the drive circuit 20.

[0050] Optionally, combined Figure 5 and Figure 6 As shown, the high bandwidth loop 30 includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a sixth inverter INV6, a third capacitor C3, a second NMOS transistor NM2 and a third NMOS transistor NM3. The source of the third PMOS tube PM3 and the source of the fourth PMOS tube PM4 are both connected to the power supply VDD; the gate of the third PMOS tube PM3, the gate of the fourth PMOS tube PM4, and the drain of the fourth PMOS tube PM4 are all connected to the drain of the third NMOS tube NM3; the drain of the third PMOS tube PM3 is connected to the drain of the first NMOS tube NM1, that is, the drain of the third PMOS tube PM3 is connected to the voltage signal V1; the input end of the sixth inverter INV6 is connected to the amplified voltage VG; the output end of the sixth inverter INV6 is connected to the first end of the third capacitor C3, the gate of the second NMOS tube NM2, and the gate of the third NMOS tube NM3; the second end of the third capacitor C3 is grounded; the drain of the second NMOS tube NM2 is connected to the output voltage VOUT; the source of the second NMOS tube NM2 and the source of the third NMOS tube NM3 are both grounded.

[0051] In this embodiment, the high bandwidth loop 30 can quickly respond to transient changes in the output voltage VOUT, such as sudden load changes or power supply noise, and quickly adjust the output to maintain voltage stability.

[0052] Optionally, when the output voltage VOUT exceeds the preset voltage, through the negative feedback loop, the input terminal voltage of the sixth inverter INV6 is low level, the output terminal voltage of the sixth inverter INV6 and the gate voltages of the second NMOS tube NM2 and the third NMOS tube NM3 are high level, the second NMOS tube NM2 and the third NMOS tube NM3 are turned on, and the output voltage VOUT is pulled down; when the output voltage VOUT is close to the preset voltage, through the negative feedback loop, the input terminal voltage of the sixth inverter INV6 is high level, the output terminal voltage of the sixth inverter INV6 and the gate voltages of the second NMOS tube NM2 and the third NMOS tube NM3 are low level, the second NMOS tube NM2 and the third NMOS tube NM3 are turned off, and the output voltage VOUT is not affected.

[0053] Optionally, the preset voltage is an output voltage value when the circuit works normally.

[0054] In this embodiment, when the output voltage VOUT exceeds the preset voltage, the inverter amplifier 10 compares the feedback voltage Vfb with the reference voltage Vref through a negative feedback loop, and outputs a low-level amplified voltage VG. The amplified voltage VG acts on the sixth inverter INV6, and the input voltage of the sixth inverter INV6 is low-level, and the output voltage is high-level. At this time, the gate voltages of the second NMOS tube NM2 and the third NMOS tube NM3 are high-level, so that the second NMOS tube NM2 and the third NMOS tube NM3 are turned on, showing a strong pull-down, thereby rapidly reducing the output voltage VOUT until the output voltage VOUT returns to the normal range. When the output voltage VOUT is close to the preset voltage, the inverter amplifier 10 outputs a high-level amplified voltage VG through a negative feedback loop. At this time, the input terminal voltage of the sixth inverter INV6 is high level, the output terminal voltage is low level, and the gate voltages of the second NMOS tube NM2 and the third NMOS tube NM3 are low level, so that the second NMOS tube NM2 and the third NMOS tube NM3 are cut off, and have no effect on the output voltage VOUT, thereby achieving the goal of maintaining the stability of the output voltage VOUT.

[0055] Optionally, the capacitance of the third capacitor C3 is smaller than a preset capacitance.

[0056] In this embodiment, when the LDO circuit works normally and works in a large load current state, there is no need to additionally pull down the output voltage VOUT, and the second NMOS tube NM2 and the third NMOS tube NM3 are cut off. When the LDO circuit works normally and works in a small load current state, since the capacitance of the third capacitor C3 is very small, that is, the attenuation effect of the third capacitor C3 on the high-frequency signal is small. Therefore, the pole generated at the output end of the sixth inverter INV6 is located in a higher frequency range, so that the high-bandwidth loop 30 exhibits a high-bandwidth gain stage in most operating frequencies. Since the high-bandwidth gain stage can provide better transient response without causing oscillation, the negative impact on the stability of the loop is reduced. Therefore, the LDO circuit can maintain stable operation under different load conditions, and can quickly adjust the output voltage VOUT even when the load changes, maintaining the stability of the circuit. Therefore, the high-bandwidth loop 30 achieves precise control of the output voltage VOUT of the LDO circuit by intelligently adjusting the conduction state of the second NMOS tube NM2 and the third NMOS tube NM3, and utilizing the characteristics of the third capacitor C3 under different load conditions, ensuring the stability and responsiveness of the circuit under various working conditions.

[0057] Optionally, the preset capacitance value is in the range of picofarad (pF) level to femtofarad (fF) level.

[0058] In this embodiment, the third capacitor C3 works with the sixth inverter INV6 in the high-bandwidth loop 30 to achieve a high-bandwidth gain stage, affecting the frequency response and stability of the LDO circuit. In this application, the capacitance of the third capacitor C3 needs to be small enough to ensure that the third capacitor C3 does not have a significant impact on the stability of the circuit within the frequency range of interest. Therefore, according to the specific design requirements and operating frequency, a suitable third capacitor C3 is selected to ensure that at high frequencies, the impact of the third capacitor C3 on the stability of the circuit is minimized, while allowing the sixth inverter INV6 to provide sufficient gain within the frequency range of interest.

[0059] An embodiment of the present disclosure provides an electronic chip, comprising the low voltage dropout linear regulator circuit as described above.

[0060] The low-dropout linear regulator circuit provided by the embodiment of the present disclosure can effectively suppress the input power supply noise and ensure the stability of the output voltage. It has a wide input voltage range and can work within a wide voltage range to adapt to different power supply conditions. It has a fast transient response characteristic and can quickly respond to load changes and power supply fluctuations to keep the output voltage stable. The high-bandwidth loop can provide fast feedback regulation capabilities, optimize the dynamic performance of the circuit, and quickly pull down the output voltage when the output voltage deviates from the normal range to improve safety. The inverter amplifier based on the inverter can widen the voltage input range, improve the PSRR, and speed up the transient response speed. Through the auxiliary amplifier, it can also maintain a stable loop gain when the reference voltage deviates from the optimal value. The electronic chip integrates the low-dropout linear regulator circuit as described above, so that the electronic chip has a larger PSRR and voltage input range while having a high transient response characteristic, and can provide a stable and efficient power management solution, which is suitable for electronic devices that require high stability and fast response.

[0061] An embodiment of the present disclosure provides a car, comprising the electronic chip as described above.

[0062] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

Claims

1. A low voltage dropout linear regulator circuit, characterized in that: include: Inverter amplifiers, drive circuits, and high-bandwidth loops; The inverter amplifier is implemented based on an inverter and is configured to generate an amplified voltage according to a reference voltage and a feedback voltage of an output voltage; The driving circuit is connected to the inverter amplifier and is configured to generate an output voltage and a feedback voltage of the output voltage according to the amplified voltage; The high bandwidth loop is connected to both the inverter amplifier and the drive circuit, and is configured to adjust the output voltage through a negative feedback loop formed by the inverter amplifier and the drive circuit.

2. The low voltage dropout linear regulator circuit according to claim 1, characterized in that: The inverter amplifier includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter and an auxiliary amplifier; The input end of the first inverter is connected to the feedback voltage; the input end of the second inverter is connected to the reference voltage; the output end of the second inverter and the output end of the fourth inverter are both connected to the input end of the auxiliary amplifier; the output end of the auxiliary amplifier is connected to the input end of the fourth inverter and the input end of the third inverter; the output end of the third inverter, the output end of the first inverter and the input end of the fifth inverter are all connected; the output end of the fifth inverter outputs the amplified voltage.

3. The low voltage dropout linear regulator circuit according to claim 2, characterized in that: The fourth inverter is configured to match the gain of the reference voltage and the feedback voltage and serve as a transimpedance load for the second inverter.

4. The low voltage dropout linear regulator circuit according to claim 2, characterized in that: The auxiliary amplifier is configured to maintain a stable loop gain, widen the reference voltage input range, and improve the power supply rejection ratio when the reference voltage deviates from the target voltage.

5. The low voltage dropout linear regulator circuit according to any one of claims 1 to 4, characterized in that: The driving circuit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a first capacitor, a second capacitor, a first resistor, a second resistor and a third resistor; The source of the first PMOS tube and the source of the second PMOS tube are connected to the power supply; the gate of the first PMOS tube, the gate of the second PMOS tube, and the drain of the first PMOS tube are all connected to the drain of the first NMOS tube; the gate of the first NMOS tube and the first end of the first capacitor are all connected to the amplified voltage; the source of the first NMOS tube and the second end of the first capacitor are all grounded; the drain of the second PMOS tube generates an output voltage; the drain of the second PMOS tube is connected to the first end of the first resistor, the first end of the second capacitor, and the first end of the third resistor; the second end of the first resistor is connected to the first end of the second resistor and generates a feedback voltage of the output voltage; the second end of the second resistor, the second end of the second capacitor, and the second end of the third resistor are all grounded.

6. The low voltage dropout linear regulator circuit according to claim 5, characterized in that: The high bandwidth loop includes: a third PMOS tube, a fourth PMOS tube, a sixth inverter, a third capacitor, a second NMOS tube and a third NMOS tube; The source of the third PMOS tube and the source of the fourth PMOS tube are both connected to the power supply; the gate of the third PMOS tube, the gate of the fourth PMOS tube, and the drain of the fourth PMOS tube are all connected to the drain of the third NMOS tube; the drain of the third PMOS tube is connected to the drain of the first NMOS tube; the input end of the sixth inverter is connected to the amplified voltage; the output end of the sixth inverter is connected to the first end of the third capacitor, the gate of the second NMOS tube, and the gate of the third NMOS tube; the second end of the third capacitor is grounded; the drain of the second NMOS tube is connected to the output voltage; the source of the second NMOS tube and the source of the third NMOS tube are both grounded.

7. The low voltage dropout linear regulator circuit according to claim 6, characterized in that: When the output voltage exceeds the preset voltage, through the negative feedback loop, the input terminal voltage of the sixth inverter is low level, the output terminal voltage of the sixth inverter, the gate voltages of the second NMOS tube and the third NMOS tube are high level, the second NMOS tube and the third NMOS tube are turned on, and the output voltage is pulled down; When the output voltage is close to the preset voltage, through the negative feedback loop, the input voltage of the sixth inverter is high, the output voltage of the sixth inverter and the gate voltages of the second NMOS tube and the third NMOS tube are low, the second NMOS tube and the third NMOS tube are cut off, and the output voltage is not affected.

8. The low voltage dropout linear regulator circuit according to claim 6, characterized in that: The capacitance of the third capacitor is smaller than the preset capacitance.

9. An electronic chip, characterized in that: The invention comprises the low voltage drop linear regulator circuit as claimed in any one of claims 1 to 8.

10. An automobile, characterized in that: Comprising the electronic chip as claimed in claim 9.

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