A Clock Holding Method for a Step-Down Power Supply System

Abstract

The present invention provides a clock holding method for a step-down power supply system, belonging to the technical field of power supply systems, including: Step 1: Detect whether there is a voltage output of VIO_1.8V inside the 4G Android module; Step 2: If there is no voltage output, it is determined that the 4G Android module is in a shutdown state. At this time, based on the clock holding circuit, the RTC clock is controlled to be in a holding state; Step 3: When the power-on button of the 4G Android module is pressed, a VIO_1.8V voltage will be output inside the 4G Android module. At this time, it is determined that the 4G Android module has switched from the shutdown state to the power-on state; wherein, the clock holding circuit includes: a first diode D1, a second diode D2, a 4V / 3ADC-DC1 module, a 4V / 0.3ADC-DC2 module, a first resistor R1, a sixth resistor R6, and a triode Q1. It solves the problem of large static current of the large-current step-down DCDC, and at the same time enables the RTC clock inside the 4G Android module to work properly.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply systems, and particularly to a clock holding method for a step-down power supply system. Background Art

[0002] Some devices powered by an 8.7V high-voltage battery (such as detonators and DMR walkie-talkie devices often used outdoors) generally step down the high current through a large-current DC-DC to 4V to power a 4G Android module system. However, the static current of the large-current DC-DC step-down is generally large (usually reaching 0.8 mA), which will significantly reduce the standby time of the device. Since the internal RTC clock of the 4G Android module is still working when it is in the shutdown state (the current is very small, 0.04 mA), in order to maintain the RTC clock, the DC-DC cannot be turned off at this time. However, the static current of the large-current DC-DC is too large. If the device is powered on with the battery installed and then shut down, it will cause the battery to be over-discharged and damage the battery. Another approach is to directly turn off the step-down DCDC after the device is shut down, but this approach will cause the device to restore to the default value when it is powered on again.

[0003] Therefore, the present invention proposes a clock holding method for a step-down power supply system. Summary of the Invention

[0004] The present invention provides a clock holding method for a step-down power supply system, which is used to solve the problem of large static current of the large-current step-down DCDC, and at the same time enable the internal RTC clock of the 4G Android module to work properly.

[0005] The present invention provides a clock holding method for a step-down power supply system, including:

[0006] Step 1: Detect whether there is a voltage output of VIO_1.8V inside the 4G Android module;

[0007] Step 2: If there is no voltage output, it is determined that the 4G Android module is in the shutdown state. At this time, based on the clock holding circuit, the RTC clock is controlled to be in the holding state;

[0008] Step 3: When the power-on button of the 4G Android module is pressed, the 4G Android module will output a VIO_1.8V voltage inside. At this time, it is determined that the 4G Android module has switched from the shutdown state to the power-on state;

[0009] Wherein, the clock holding circuit includes: a first diode D1, a second diode D2, a 4V / 3A DC-DC1 module, a 4V / 0.3A DC-DC2 module, a first resistor R1, a sixth resistor R6, and a triode Q1;

[0010] The cathodes of the first diode D1 and the second diode D2 are respectively connected to the output end of the 4G Android module, and the anode of the first diode D1 is connected to the voltage output end of the 4V / 3ADC-DC1 module, and the anode of the second diode D2 is connected to the voltage output end of the 4V / 0.3ADC-DC2 module;

[0011] The 8.7V high-voltage battery is respectively connected to the voltage input ends of the 4V / 3ADC-DC1 module and the 4V / 0.3ADC-DC2 module, and one end of the first resistor R1;

[0012] The VIO_1.8V inside the 4G Android module is connected to the enable EN end of the 4V / 3ADC-DC1 module;

[0013] The other end of the first resistor R1 is respectively connected to the enable EN end of the 4V / 0.3ADC-DC2 module and the collector of the triode Q1;

[0014] The base of the triode Q1 is connected to one end of the sixth resistor R6;

[0015] The other end of the sixth resistor R6 and the emitter of the triode Q1 are respectively connected to the ground.

[0016] Preferably, the 4V / 3ADC-DC1 module includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a second resistor R2, a third resistor R3, a third inductor L3, a first DC-DC module U1;

[0017] Among them, the 8.7V high-voltage battery is respectively connected to the first capacitor C1, the second capacitor C2, and the VIN port of the first DC-DC module U1. The VBST port of the first DC-DC module U1 is connected to one end of the third capacitor C3. The SW port of the first DC-DC module U1 is respectively connected to the other end of the third capacitor C3 and one end of the third inductor L3. The other end of the third inductor L3 is respectively connected to one end of the second resistor R2, one end of the fourth capacitor C4, and the anode of the second diode D2. The VFB end of the first DC-DC module U1 is respectively connected to the other end of the second resistor R2 and one end of the third resistor R3. The other ends of the first capacitor C1, the second capacitor C2, the third resistor R3, and the fourth capacitor C4 are respectively connected to the ground.

[0018] Preferably, the 4V / 0.3ADC-DC2 module includes: a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a fourth resistor R4, a fifth resistor R5, a sixteenth resistor R16, a second inductor L2, a second DC-DC module U2;

[0019] Among them, the 8.7V high-voltage battery is respectively connected to one end of the fourth resistor R4 and one end of the sixth capacitor C6. The other end of the fourth resistor R4 is respectively connected to the collector of the triode Q1 and the EN end of the second DC-DC module U2. The BST end of the second DC-DC module U2 is connected to one end of the seventh capacitor C7. The SW end of the second DC-DC module U2 is respectively connected to the other end of the seventh capacitor C7 and one end of the second inductor L2. The other end of the second inductor L2 is respectively connected to one end of the fifth resistor R5, one end of the eighth capacitor C8, and the positive pole of the first diode D1. The FB end of the second DC-DC module U2 is respectively connected to the other end of the fifth resistor R5 and one end of the sixteenth resistor R16;

[0020] The other end of the sixth capacitor C6, the other end of the sixteenth resistor R16, and the other end of the eighth capacitor C8 are respectively connected to the ground.

[0021] Preferably, after determining that the 4G Android module is switched from the shutdown state to the startup state, it further includes:

[0022] When the 4G Android module is in the startup state, if the 4G Android module works to a specified temperature, at this time, measure the first current at several consecutive time nodes, and construct a first measurement vector corresponding to the specified temperature;

[0023] According to the factory standard of the 4G Android module, sequentially obtain the set current when the 4G working module works to each specified temperature, and construct a standard vector;

[0024] Respectively obtain the average current and current variance of each first measurement vector, and when the current variance is greater than the variance threshold, retain the sum of the average current and the current variance as the first calculation result;

[0025] When the current variance is not greater than the variance threshold, retain the difference between the average current and the current variance as the second calculation result;

[0026] Construct an actual vector based on the retained results;

[0027] Compare and analyze the actual vector with the standard vector, construct a difference vector, and input it into the temperature compensation model to obtain a first compensation circuit for the 4G Android module.

[0028] Preferably, it further includes: determining the number of several consecutive time nodes corresponding to the specified temperature, specifically including:

[0029] ;

[0030] Among them, Indicates the number of time nodes required to measure the 4G Android module to reach the specified temperature; ceiling() represents the ceiling function; Indicates the theoretical duration of the 4G Android module from the normal operating temperature to the specified temperature; Indicates the actual duration of the 4G Android module from the normal operating temperature to the specified temperature; Indicates the corresponding specified temperature; Indicates the normal operating temperature of the 4G Android module; Indicates the maximum operating temperature of the 4G Android module; Indicates N1 clock operating frequencies randomly collected before the 4G Android module reaches the specified temperature; Indicates the set operating frequency of the 4G Android module.

[0031] Preferably, after determining that the 4G Android module is converted from the shutdown state to the startup state, it further includes:

[0032] When the 4G Android module is in the startup state, construct the first frequency curve of the RTC clock within the time period from the starting operating temperature to the first specified temperature of the 4G Android module;

[0033] Construct the second frequency curve of the RCT clock within the time period from the first specified temperature to the next specified temperature until the last frequency curve is constructed;

[0034] Determine whether there is a mutation frequency in each frequency curve. If so, locate the points corresponding to the mutation frequency to obtain the actual mutation time and the mutation frequency amount, and calculate the mutation reliability of the mutation frequency;

[0035] If all mutation reliabilities are greater than or equal to the preset reliability, it is determined that no compensation is required for the 4G Android module;

[0036] Otherwise, lock the temperature stage with a mutation reliability less than the preset reliability and the first quantity of the positioning points involved in the corresponding temperature stage with a mutation reliability less than the preset reliability;

[0037] Based on the temperature stage, the first quantity, and the mutation frequency amount of each positioning point in the first quantity, construct a compensation vector;

[0038] Input the compensation vector into the circuit compensation model to obtain the second compensation circuit of the 4G Android module.

[0039] Preferably, calculating the mutation reliability of the mutation frequency includes:

[0040] ;

[0041] Wherein, Indicates the corresponding actual mutation time; Indicates the theoretical mutation time of the corresponding positioning point; Indicates the mutation frequency quantity of the corresponding positioning point, and , ln represents the logarithmic function symbol; Respectively represent the frequencies at the first 2 time points based on the positioning point d, the frequency at the first 1 time point based on the positioning point d, the frequency of the d-th positioning point, the frequency at the next 1 time point based on the positioning point d, and the frequencies at the next 2 time points based on the positioning point d, and the value of d is 2, 3, 4,... Indicates based on the specified temperature And the next specified temperature The number of time points involved in the obtained frequency curve; when i = 1, , represents the starting working temperature of the 4G Android module; Indicates the mutation reliability of the corresponding mutation frequency.

[0042] Preferably, after obtaining the first compensation circuit and the second compensation circuit, it further includes:

[0043] Performing compensation simulation on the first compensation circuit and the second compensation circuit simulation platform, and respectively obtaining the first compensation qualification coefficient and the second compensation qualification coefficient for the RTC clock;

[0044] Selecting the compensation circuit corresponding to the maximum coefficient from the first compensation qualification coefficient and the second compensation qualification coefficient and applying it to the 4G Android module.

[0045] Compared with the prior art, the beneficial effects of the present application are as follows:

[0046] Effectively achieve that when the device is in the shutdown state, the RTC of its 4G Android module can work normally, and at the same time, the current only increases by 1 μA, greatly enhancing the standby time of the device in the shutdown state.

[0047] Other features and advantages of the present invention will be described in the subsequent description, and part of them will become obvious from the description, or will be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained through the structures specifically pointed out in the written description and the drawings.

[0048] The technical solutions of the present invention will be further described in detail below through the drawings and embodiments. Description of the Drawings

[0049] The drawings are used to provide a further understanding of the present invention, and constitute a part of the description. They are used together with the embodiments of the present invention to explain the present invention, and do not constitute a limitation to the present invention. In the drawings:

[0050] Figure 1 Flow chart of a clock holding method for a step-down power supply system in an embodiment of the present invention;

[0051] Figure 2 Clock holding circuit diagram in an embodiment of the present invention;

[0052] Figure 3 Circuit diagram of the 4V / 3ADC-DC1 module in an embodiment of the present invention;

[0053] Figure 4 Circuit diagram of the 4V / 0.3ADC-DC2 module in an embodiment of the present invention. Detailed implementation manners

[0054] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0055] The present invention provides a clock holding method for a step-down power supply system, as Figure 1 shown, including:

[0056] Step 1: Detect whether there is a voltage output at VIO_1.8V inside the 4G Android module;

[0057] Step 2: If there is no voltage output, determine that the 4G Android module is in the shutdown state. At this time, control the RTC clock to be in the holding state based on the clock holding circuit;

[0058] Step 3: When the power-on button of the 4G Android module is pressed, a VIO_1.8V voltage will be output inside the 4G Android module. At this time, determine that the 4G Android module has switched from the shutdown state to the power-on state;

[0059] Among them, as Figure 2 shown, the clock holding circuit includes: a first diode D1, a second diode D2, a 4V / 3ADC-DC1 module, a 4V / 0.3ADC-DC2 module, a first resistor R1, a sixth resistor R6, and a triode Q1;

[0060] The cathodes of the first diode D1 and the second diode D2 are respectively connected to the output terminal of the 4G Android module, and the anode of the first diode D1 is connected to the voltage output terminal of the 4V / 3ADC-DC1 module, and the anode of the second diode D2 is connected to the voltage output terminal of the 4V / 0.3ADC-DC2 module;

[0061] The 8.7V high-voltage battery is respectively connected to the voltage input terminals of the 4V / 3ADC-DC1 module and the 4V / 0.3ADC-DC2 module, and one end of the first resistor R1;

[0062] The EN enable terminal of the 4V / 3ADC-DC1 module inside the 4G Android module is connected to VIO_1.8V;

[0063] The other end of the first resistor R1 is respectively connected to the EN enable terminal of the 4V / 0.3ADC-DC2 module and the collector of the triode Q1;

[0064] The base of the triode Q1 is connected to one end of the sixth resistor R6;

[0065] The other end of the sixth resistor R6 and the emitter of the triode Q1 are respectively connected to the ground.

[0066] Preferably, as Figure 3 shown, the 4V / 3ADC-DC1 module includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a second resistor R2, a third resistor R3, a third inductor L3, and a first DC-DC module U1;

[0067] Among them, the 8.7V high-voltage battery is respectively connected to the VIN port of the first capacitor C1, the second capacitor C2, and the first DC-DC module U1. The VBST port of the first DC-DC module U1 is connected to one end of the third capacitor C3. The SW port of the first DC-DC module U1 is respectively connected to the other end of the third capacitor C3 and one end of the third inductor L3. The other end of the third inductor L3 is respectively connected to one end of the second resistor R2, one end of the fourth capacitor C4, and the positive pole of the second diode D2. The VFB end of the first DC-DC module U1 is respectively connected to the other end of the second resistor R2 and one end of the third resistor R3. The other ends of the first capacitor C1, the second capacitor C2, the third resistor R3, and the fourth capacitor C4 are respectively connected to the ground.

[0068] Preferably, as Figure 4 shown, the 4V / 0.3ADC-DC2 module includes: a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a fourth resistor R4, a fifth resistor R5, a sixteenth resistor R16, a second inductor L2, and a second DC-DC module U2;

[0069] Among them, the 8.7V high-voltage battery is respectively connected to one end of the fourth resistor R4 and one end of the sixth capacitor C6. The other end of the fourth resistor R4 is respectively connected to the collector of the triode Q1 and the EN terminal of the second DC-DC module U2. The BST terminal of the second DC-DC module U2 is connected to one end of the seventh capacitor C7. The SW terminal of the second DC-DC module U2 is respectively connected to the other end of the seventh capacitor C7 and one end of the second inductor L2. The other end of the second inductor L2 is respectively connected to one end of the fifth resistor R5, one end of the eighth capacitor C8, and the positive electrode of the first diode D1. The FB terminal of the second DC-DC module U2 is respectively connected to the other end of the fifth resistor R5 and one end of the sixteenth resistor R16;

[0070] The other end of the sixth capacitor C6, the other end of the sixteenth resistor R16, and the other end of the eighth capacitor C8 are respectively connected to the ground.

[0071] Working principle of the above clock holding circuit: When the 4G Android module is in the shutdown state, there is no voltage output at VIO_1.8V inside the 4G Android module. At this time, the enable EN pin of the first DC-DC module U1 is pulled low through the first resistor R1, and the first DC-DC module U1 is turned off (3A high-current buck DCDC). The first capacitor C1 and the second capacitor C2 are the input energy storage and filtering capacitors of the first DC-DC module. The third inductor L3 is the energy storage inductor of the first DC-DC module. The second resistor R2 and the third resistor R3 are the feedback resistors of the first DC-DC module to adjust the output voltage. The fourth capacitor C4 is the output filtering capacitor of the first DC-DC module. The second diode D2 is to prevent the 4V voltage output by the 4V / 0.3A DC-DC2 module U2 from being back-fed to the first DC-DC module U1 and leaking current through the second resistor R2 and the third resistor R3. The 4V / 0.3A DC-DC2 module U2 is a low-current buck DCDC (current 0.3A) with a small static current (only 1uA). The enable EN pin of the 4V / 0.3A DC-DC2 module U2 is connected to the 8.7V voltage through the fourth resistor R4, and the 4V / 0.3A DC-DC2 module U2 works normally and outputs 4V to power the 4G Android module. At this time, the 4G Android module is not powered on. The sixth capacitor C6 is the input filtering capacitor of the 4V / 0.3A DC-DC2 module U2. The seventh capacitor C7 at this time is the bootstrap capacitor of the 4V / 0.3A DC-DC2 module U2. The second inductor L2 is the energy storage inductor of the 4V / 0.3A DC-DC2 module U2. The fifth resistor R5 and the sixteenth resistor R16 are the output feedback resistors of the 4V / 0.3A DC-DC2 module U2 to adjust the output voltage. The eighth capacitor C8 is the output filtering capacitor of the 4V / 0.3A DC-DC2 module U2. The first diode D1 is to prevent the output voltage of the first DC-DC module U1 from leaking current through the fifth resistor R5 and the sixteenth resistor R16 after the power-on is completed. However, the internal RTC of the module can work normally, enabling the RTC of the 4G Android module to work normally when the device is in the shutdown state, and at the same time, the current only increases by 1uA, greatly enhancing the standby time of the device in the shutdown state.

[0072] The specific startup process of the 4G Android module is as follows: Since the 4V / 0.3A DC-DC2 module U2 step-down DCDC is also turned on when the 4G Android module is shut down and outputs 4V voltage to supply power to the 4G Android module. When the power-on button of the 4G Android module is pressed, the 4G Android module will output VIO_1.8V voltage internally, and the 4G Android module starts to boot. Since the 4V / 0.3A DC-DC2 module U2 is a small-current DCDC, the 4G Android module cannot start up. However, the VIO_1.8V voltage output internally by the 4G Android module will pull up and turn on the enable EN of the large-current DCDC of the first DC-DC module U1. At this time, the large-current DCDC of the first DC-DC module U1 outputs 4V voltage to supply power to the 4G Android module, and the 4G Android module boots up normally. In addition, during the startup process of the 4G module, the output VIO_1.8V makes the Q1 NPN transistor conduct through the resistor R6, pulling down the enable EN pin of the 4V / 0.3A DC-DC2 module U2 to turn off the 4V / 0.3A DC-DC2 module U2 and reduce power consumption.

[0073] The beneficial effects of the above technical solution are as follows: It can effectively ensure that the RTC of the 4G Android module of the device can work normally when the device is in the shutdown state, and at the same time, the current only increases by 1uA, greatly enhancing the standby time of the device in the shutdown state.

[0074] The present invention provides a clock holding method for a step-down power supply system. After determining that the 4G Android module is switched from the shutdown state to the startup state, it further includes:

[0075] When the 4G Android module is in the startup state, if the 4G Android module works to a specified temperature, at this time, measure the first current at several consecutive time nodes to construct a first measurement vector corresponding to the specified temperature;

[0076] According to the factory standard of the 4G Android module, sequentially obtain the set current of the 4G working module when it works to each specified temperature, and construct a standard vector;

[0077] Respectively obtain the average current and current variance of each first measurement vector, and when the current variance is greater than the variance threshold, retain the sum of the average current and the current variance as the first calculation result;

[0078] When the current variance is not greater than the variance threshold, retain the difference between the average current and the current variance as the second calculation result;

[0079] Construct an actual vector based on the retained results;

[0080] Compare and analyze the actual vector with the standard vector, construct a difference vector, and input it into the temperature compensation model to obtain the first compensation circuit for the 4G Android module.

[0081] Preferably, it further includes: determining the number of several consecutive time nodes corresponding to a specified temperature, specifically including:

[0082] ;

[0083] wherein, represents the number of time nodes required to measure when the 4G Android module works to the specified temperature; ceiling() represents the ceiling function; represents the theoretical duration of the 4G Android module from the normal operating temperature to the specified temperature; represents the actual duration of the 4G Android module from the normal operating temperature to the specified temperature; represents the corresponding specified temperature; represents the normal operating temperature of the 4G Android module; represents the maximum operating temperature of the 4G Android module; represents N1 clock operating frequencies randomly collected before the 4G Android module works to the specified temperature; represents the set operating frequency of the 4G Android module.

[0084] In this embodiment, the specified temperatures are all preset, for example, 30 degrees Celsius, 35 degrees Celsius, 40 degrees Celsius, 45 degrees Celsius, etc. Since there will be changes in the module temperature during the power-on and use process of the 4G Android module, therefore, by measuring the current of the 4G Android module at different specified temperatures, the corresponding first measurement vector can be obtained.

[0085] In this embodiment, for example, after the 4G Android module reaches 40 degrees Celsius, at this time, taking the reaching point of 40 degrees Celsius as the initial time reaching point, continuous time points are measured to obtain the first current at each time point, and the measured first current can be the output current of the 4G Android module. At this time, the obtained first measurement vector is: {the first current at different time nodes}.

[0086] In this embodiment, the factory standard refers to the standard set before the 4G Android module leaves the factory, that is, the set current output by the 4G Android module corresponding to the specified temperature can be directly obtained, and the constructed standard vector: {the set current at different specified temperatures}.

[0087] In this embodiment, the value of the variance threshold is 0.1.

[0088] In this embodiment, the actual vector = {the retained current at different time nodes}.

[0089] In this embodiment, the difference vector = {the current difference between the retained current and the set current at each time node}.

[0090] In this embodiment, the temperature compensation model is trained by a neural network model with the difference vector of the current based on temperature and the compensation scheme for the difference vector as sample pairs. Therefore, the corresponding compensation scheme can be directly obtained, and the compensation scheme is the compensation circuit.

[0091] In this embodiment, the theoretical duration of the 4G Android module at different specified temperatures is known, and the maximum temperature and the normal operating temperature are both known.

[0092] The beneficial effect of the above technical solution is that by measuring the current of the 4G Android module at different specified temperatures, the compensation circuit is obtained, which effectively ensures the retention of the RTC clock when the 4G Android module is in the shutdown state.

[0093] The present invention provides a method for maintaining the clock of a step-down power supply system. After determining that the 4G Android module is switched from the shutdown state to the startup state, it further includes:

[0094] When the 4G Android module is in the startup state, construct the first frequency curve of the RTC clock within the time period from the starting working temperature to the first specified temperature of the 4G Android module;

[0095] Construct the second frequency curve of the RCT clock within the time period from the first specified temperature to the next specified temperature until the last frequency curve is constructed;

[0096] Judge whether there is a mutation frequency in each frequency curve. If so, locate the points corresponding to the mutation frequency to obtain the actual mutation time and the mutation frequency amount, and calculate the mutation reliability of the mutation frequency;

[0097] If all mutation reliabilities are greater than or equal to the preset reliability, it is determined that the 4G Android module does not need to be compensated;

[0098] Otherwise, lock the temperature stage with a mutation reliability less than the preset reliability and the first quantity of the positioning points involved in the corresponding temperature stage with a mutation reliability less than the preset reliability;

[0099] Based on the temperature stage, the first quantity, and the mutation frequency amount of each positioning point in the first quantity, construct a compensation vector;

[0100] Input the compensation vector into the circuit compensation model to obtain the second compensation circuit of the 4G Android module.

[0101] Preferably, calculating the mutation reliability of the mutation frequency includes:

[0102] ;

[0103] Wherein, represents the corresponding actual mutation time; Indicates the theoretical mutation time of the corresponding positioning point; Indicates the mutation frequency quantity of the corresponding positioning point, and , where ln represents the logarithmic function symbol; respectively represent the frequency at the first 2 time points based on the positioning point d, the frequency at the first 1 time point based on the positioning point d, the frequency of the d-th positioning point, the frequency at the next 1 time point based on the positioning point d, and the frequency at the next 2 time points based on the positioning point d, and the value of d is 2, 3, 4,... Indicates based on the specified temperature and the next specified temperature the number of time points involved in the obtained frequency curve; when i = 1, , represents the starting working temperature of the 4G Android module; keep.

[0104] The present invention provides a clock holding method for a step-down power supply system. After obtaining the first compensation circuit and the second compensation circuit, it further includes:

[0105] Performing compensation simulation on the simulation platforms of the first compensation circuit and the second compensation circuit, and respectively obtaining a first compensation qualification coefficient and a second compensation qualification coefficient for the RTC clock;

[0106] Selecting the compensation circuit corresponding to the maximum coefficient from the first compensation qualification coefficient and the second compensation qualification coefficient and applying it to the 4G Android module.

[0107] In this embodiment, the simulation platform refers to a circuit simulation platform. By performing compensation simulation, the frequency offset of the clock under different compensation circuits is determined, and then the most effective circuit is selected.

[0108] In this embodiment, the first compensation qualification coefficient = 1 - the clock deviation frequency obtained based on the compensation simulation result / the set working frequency.

[0109] The beneficial effect of the above technical solution is: By performing compensation simulation on the compensation circuit to obtain the compensation qualification coefficients of different circuits, and then selecting the circuit with the most effective coefficient for compensation, the clock RTC is effectively held.

[0110] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations. Represents the mutation reliability corresponding to the mutation frequency.

[0111] In this embodiment, during the process of temperature change, the frequency curve within the corresponding time period is respectively constructed by capturing the clock frequency.

[0112] In this embodiment, if the absolute value of the difference between the actual operating frequency of the corresponding point and the set operating frequency of the 4G Android module / the value of the set operating frequency is greater than 0.05, then at this time, the corresponding point is regarded as the point corresponding to the mutation frequency.

[0113] In this embodiment, the preset reliability takes a value of 0.5.

[0114] In this embodiment, the temperature stage is the stage corresponding to two specified temperatures corresponding to the frequency curve.

[0115] In this embodiment, the compensation vector: {the temperature stage involved, the first quantity under each temperature stage, the mutation frequency quantity of each positioning point in the first quantity}.

[0116] In this embodiment, the circuit compensation model is obtained by training a neural network model with different compensation vectors and the compensation setting circuits for the compensation vectors as samples. Therefore, the compensation circuit for the compensation vector can be directly obtained.

[0117] The beneficial effects of the above technical solution are: by determining the frequency curve based on the temperature stage to lock the mutation points in the curve, and then calculating the mutation reliability, and constructing the compensation vector through comparative analysis, which provides a basis for obtaining the compensation circuit and facilitates the subsequent retention of the RTC clock when the 4G Android module is in the shutdown state.

[0118] The present invention provides a method for maintaining the clock of a step-down power supply system. After obtaining the first compensation circuit and the second compensation circuit, it further includes:

[0119] Performing compensation simulation on the first compensation circuit and the second compensation circuit in the simulation platform, and respectively obtaining the first compensation qualification coefficient and the second compensation qualification coefficient for the RTC clock;

[0120] Selecting the compensation circuit corresponding to the maximum coefficient from the first compensation qualification coefficient and the second compensation qualification coefficient and applying it to the 4G Android module.

[0121] In this embodiment, the simulation platform refers to a circuit simulation platform. By performing compensation simulation, the frequency offset of the clock under different compensation circuits is determined, and then the most effective circuit is selected.

[0122] In this embodiment, the first compensation qualification coefficient = 1 - the clock deviation frequency obtained based on the compensation simulation result / the set operating frequency.

[0123] The beneficial effects of the above technical solution are: by performing compensation simulation on the compensation circuit to obtain the compensation qualification coefficients of different circuits, and then selecting the circuit with the most effective coefficient for compensation, effectively maintaining the retention of the RTC clock.

[0124] Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A clock holding method for a step-down power supply system, characterized in that Including: Step 1: Detect whether there is a voltage output at VIO_1.8V inside the 4G Android module; Step 2: If there is no voltage output, determine that the 4G Android module is in the shutdown state. At this time, control the RTC clock to be in the hold state based on the clock hold circuit; Step 3: When the power-on button of the 4G Android module is pressed, a VIO_1.8V voltage will be output inside the 4G Android module. At this time, determine that the 4G Android module has switched from the shutdown state to the power-on state; Among them, the clock hold circuit includes: a first diode D1, a second diode D2, a 4V / 3ADC-DC1 module, a 4V / 0.3ADC-DC2 module, a first resistor R1, a sixth resistor R6, and a triode Q1; The cathodes of the first diode D1 and the second diode D2 are respectively connected to the output terminal of the 4G Android module, and the anode of the first diode D1 is connected to the voltage output terminal of the 4V / 3ADC-DC1 module, and the anode of the second diode D2 is connected to the voltage output terminal of the 4V / 0.3ADC-DC2 module; The 8.7V high-voltage battery is respectively connected to the voltage input terminals of the 4V / 3ADC-DC1 module and the 4V / 0.3ADC-DC2 module, and one end of the first resistor R1; The internal VIO_1.8V of the 4G Android module is connected to the enable EN terminal of the 4V / 3ADC-DC1 module; The other end of the first resistor R1 is respectively connected to the enable EN terminal of the 4V / 0.3ADC-DC2 module and the collector of the triode Q1; The base of the triode Q1 is connected to one end of the sixth resistor R6; The other end of the sixth resistor R6 is connected to VIO_1.8V, and the emitter of the triode Q1 is connected to the ground.

2. The clock hold method of the step-down power supply system according to claim 1, characterized in that The 4V / 3ADC-DC1 module includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a second resistor R2, a third resistor R3, a third inductor L3, and a first DC-DC module U1; Among them, the 8.7V high-voltage battery is respectively connected to one end of the first capacitor C1, one end of the second capacitor C2, and the VIN port of the first DC-DC module U1. The VBST port of the first DC-DC module U1 is connected to one end of the third capacitor C3. The SW port of the first DC-DC module U1 is respectively connected to the other end of the third capacitor C3 and one end of the third inductor L3. The other end of the third inductor L3 is respectively connected to one end of the second resistor R2, one end of the fourth capacitor C4, and the anode of the second diode D2. The VFB end of the first DC-DC module U1 is respectively connected to the other end of the second resistor R2 and one end of the third resistor R3. The other ends of the first capacitor C1, the second capacitor C2, the third resistor R3, and the fourth capacitor C4 are respectively connected to the ground.

3. The clock hold method of the step-down power supply system according to claim 2, characterized in that The 4V / 0.3A DC-DC2 module includes: a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a fourth resistor R4, a fifth resistor R5, a sixteenth resistor R16, a second inductor L2, and a second DC-DC module U2; Among them, the 8.7V high-voltage battery is respectively connected to one end of the fourth resistor R4 and one end of the sixth capacitor C6. The other end of the fourth resistor R4 is respectively connected to the collector of the triode Q1 and the EN end of the second DC-DC module U2. The BST end of the second DC-DC module U2 is connected to one end of the seventh capacitor C7. The SW end of the second DC-DC module U2 is respectively connected to the other end of the seventh capacitor C7 and one end of the second inductor L2. The other end of the second inductor L2 is respectively connected to one end of the fifth resistor R5, one end of the eighth capacitor C8, and the positive electrode of the first diode D1. The FB end of the second DC-DC module U2 is respectively connected to the other end of the fifth resistor R5 and one end of the sixteenth resistor R16; The other ends of the sixth capacitor C6, the sixteenth resistor R16, and the eighth capacitor C8 are respectively connected to the ground.

4. The clock holding method of the step-down power supply system according to claim 3, characterized in that, After determining that the 4G Android module is switched from the shutdown state to the startup state, it further includes: When the 4G Android module is in the startup state, if the 4G Android module works to the specified temperature, at this time, measure the first current at several consecutive time nodes, and construct a first measurement vector corresponding to the specified temperature; According to the factory standard of the 4G Android module, sequentially obtain the set current of the 4G Android module when it works to each specified temperature, and construct a standard vector; Respectively obtain the average current and current variance of each first measurement vector, and when the current variance is greater than the variance threshold, retain the sum of the average current and the current variance as the first calculation result; When the current variance is not greater than the variance threshold, retain the difference between the average current and the current variance as the second calculation result; Construct an actual vector based on the retained results; Compare and analyze the actual vector with the standard vector, construct a difference vector, and input it into the temperature compensation model to obtain a first compensation circuit for the 4G Android module.

5. The clock holding method of the step-down power supply system according to claim 4, characterized in that, After determining that the 4G Android module is switched from the shutdown state to the startup state, it further includes: When the 4G Android module is in the startup state, construct a first frequency curve of the RTC clock during the period from the starting working temperature of the 4G Android module to the first specified temperature; Construct a second frequency curve of the RCT clock during the period from the first specified temperature to the next specified temperature until the last frequency curve is constructed; Judge whether there is a mutation frequency in each frequency curve. If so, locate the point corresponding to the mutation frequency to obtain the actual mutation time and the mutation frequency amount, and calculate the mutation reliability of the mutation frequency; If all mutation reliabilities are greater than or equal to the preset reliability, it is determined that no compensation is required for the 4G Android module; Otherwise, lock the temperature stage where the mutation reliability is less than the preset reliability and the first quantity of the positioning points involved in the corresponding temperature stage where the mutation reliability is less than the preset reliability; Based on the temperature stage, the first quantity, and the mutation frequency quantity of each positioning point in the first quantity, construct a compensation vector; Input the compensation vector into the circuit compensation model to obtain the second compensation circuit of the 4G Android module.

6. The clock holding method of the step-down power supply system according to claim 5, characterized in that, After obtaining the first compensation circuit and the second compensation circuit, it further includes: Perform compensation simulation on the first compensation circuit and the second compensation circuit simulation platform, and respectively obtain the first compensation qualification coefficient and the second compensation qualification coefficient for the RTC clock; Select the compensation circuit corresponding to the maximum coefficient from the first compensation qualification coefficient and the second compensation qualification coefficient and apply it to the 4G Android module.

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