Acceleration unit, control unit, special data processor, host and data read-write method

Abstract

The embodiment of the invention provides an acceleration unit, a control unit, a special data processor, a host and a data read-write method, the acceleration unit is arranged on the special data processor connected with the host, and the acceleration unit comprises a receiving subunit, an analysis subunit and a verification subunit; the receiving subunit is used for receiving a first read-write request sent by the host and sending the first read-write request to the analysis subunit; the parsing subunit is used for parsing the first read-write request, determining a target queue address and a target process identifier included in the first read-write request, and sending the target queue address and the target process identifier to the verification subunit; and the verification subunit is used for reading a target queue identifier in the target queue according to the target queue address, and establishing a read-write channel between the host and the target queue when the target process identifier and the target queue identifier meet a matching rule, so that the host reads and writes the target queue. The acceleration unit provided by the scheme can improve the data security.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to an acceleration unit, a control unit, a dedicated data processor, a host, and a data reading and writing method. Background Art

[0002] Accelerators such as network cards map hardware registers to user mode through memory mapped input and output (MMIO). User mode programs can determine the real address of registers through page table mapping and virtual addresses within the process, so that user mode can directly access registers, thus avoiding the need to enter the kernel and reducing the time required to access registers.

[0003] Currently, queue registers corresponding to multiple processes in a host are set in the same physical page.

[0004] However, since the queue registers corresponding to multiple processes are set in the same physical page, when a process needs to read or write registers, it can read the queue registers corresponding to other processes stored in the same physical page, which poses a risk of data leakage. Summary of the invention

[0005] In view of this, an embodiment of the present application provides an acceleration unit, a control unit, a dedicated data processor, a host and a data reading and writing method to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of an embodiment of the present application, an acceleration unit is provided, which is arranged in a dedicated data processor connected to a host, and the acceleration unit includes: a receiving subunit, a parsing subunit and a checking subunit; the receiving subunit is used to receive a first read-write request sent by the host, and send the first read-write request to the parsing subunit; the parsing subunit is used to parse the first read-write request, determine the target queue address and target process identifier included in the first read-write request, and send the target queue address and the target process identifier to the checking subunit; the checking subunit is used to read the target queue identifier in the target queue according to the target queue address, and when the target process identifier and the target queue identifier meet the matching rule, establish a read-write channel between the host and the target queue based on the first read-write request, so that the host reads and writes the target queue.

[0007] In a possible implementation, the matching rule includes: the target process identifier is the same as the target queue identifier, the target process identifier is less than or equal to the target queue identifier, and the target process identifier is greater than or equal to the target queue identifier.

[0008] In one possible implementation, the verification subunit is used to write the target queue address and the target process identifier into the alarm queue when the target process identifier and the target queue identifier do not satisfy the matching rule, and send an alarm signal to the host, so that the host reads the target queue address and the target process identifier from the alarm queue, and generates an alarm log based on the target queue address and the target process identifier.

[0009] According to a second aspect of an embodiment of the present application, a control unit is provided, which is arranged in a host, and the control unit is used to receive a second read-write request generated by a target process, determine a target process identifier corresponding to the target process according to the target process, and generate a first read-write request according to the target process identifier and the second read-write request, and send the first read-write request to the acceleration unit, so that after the acceleration unit establishes a read-write channel between the host and the target queue according to the first read-write request, the host reads and writes the target queue, wherein the target process is any process running in the host.

[0010] In one possible implementation, the control unit is used to obtain the target process identifier of the target process when the target process is generated, and after writing the target process identifier into a register in the host, associate the register address written with the target process identifier with the process number corresponding to the target process and save it.

[0011] In a possible implementation, the control unit is used to determine the register address corresponding to the process number according to the process number of the target process after the target process sends the second read / write request, and read the target process identifier stored in the register according to the register address.

[0012] In a possible implementation, the control unit is used to delete the target process identifier stored in the register according to the process number of the target process when the target process ends.

[0013] According to a third aspect of an embodiment of the present application, a data reading and writing method is provided, which is applied to a dedicated data processor, including: receiving a first read and write request sent by a host; parsing the first read and write request to determine a target queue address and a target process identifier included in the first read and write request; reading a target queue identifier in the target queue according to the target queue address, and when the target process identifier and the target queue identifier meet a matching rule, establishing a read and write channel between the host and the target queue based on the first read and write request, so that the host reads and writes the target queue.

[0014] According to a fourth aspect of an embodiment of the present application, a dedicated data processor is provided, comprising an acceleration unit as described in the first aspect of the embodiment of the present application.

[0015] According to a fifth aspect of the embodiments of the present application, a host is provided, comprising: a control unit as described in the second aspect of the embodiments of the present application, wherein the host is connected to a dedicated data processor as described in the fourth aspect of the embodiments of the present application.

[0016] According to the scheme provided in the embodiment of the present application, the acceleration unit in the dedicated data processor connected to the host includes a receiving subunit, a parsing subunit and a checking subunit. The receiving subunit can receive a first read and write request sent by the host. The parsing subunit can parse the first read and write request to determine the target queue address and the target process identifier. The checking subunit can read the target queue identifier of the target queue according to the target queue address, and establish a read and write channel between the host and the target queue when the target queue identifier and the target process identifier meet the matching rule, thereby enabling the host to read and write the target queue. Since the host is allowed to read and write the target queue only when the target queue identifier and the target process identifier meet the matching rule, the process in the host can only read the target queue that meets the requirements. Since the checking subunit can determine whether the process in the host has the authority to access the target queue by determining whether the target process identifier and the target queue identifier meet the matching rule, compared with the prior art, it can prevent the dedicated data processor from illegally accessing the queues corresponding to other processes after mapping the memory to the user state through MMIO, and can prevent data leakage, and the data security is relatively high. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic diagram of a queue register in the prior art provided by an embodiment of the present application;

[0019] Figure 2 is a schematic diagram of an acceleration unit provided in an embodiment of the present application;

[0020] Figure 3 is a schematic diagram of a host provided in an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of a queue register provided in an embodiment of the present application;

[0022] Figure 5It is a flow chart of a data reading and writing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0024] As mentioned above, accelerators such as network cards map hardware registers to user mode through memory mapped input and output (MMIO). User mode programs can determine the real address of registers through page table mapping and virtual addresses within the process, so that user mode can directly access registers, thereby avoiding the need to enter the kernel and reducing the time required to access registers. Currently, the queue registers corresponding to multiple processes in the host are set in the same physical page, for example: Figure 1 is a schematic diagram of a queue register in the prior art provided by an embodiment of the present application, such as Figure 1 As shown, different processes in current technology ( Figure 1 The queue registers corresponding to process A and process B in the above example are set in the same physical page, for example, queue_0, queue_1, queue_2, queue_3, ..., queue_n, which are set in a 4K or 4096-byte physical page. However, since the queue registers corresponding to multiple processes are set in the same physical page, when a process needs to read or write registers, it can read the queue registers corresponding to other processes stored in the same physical page, which may lead to data leakage risks. For example: Figure 1 In the figure, queue_0, queue_1, and queue_2 are queue registers of process A, and queue_3 is queue register of process B. When process B accesses the queue register, the physical page is mapped to user state through MMIO, so process B can illegally access queue_0, queue_1, and queue_2, resulting in data leakage.

[0025] The present application provides an acceleration unit, which includes a receiving subunit, a parsing subunit and a checking subunit. The receiving subunit can receive a first read-write request sent by a host. The parsing subunit can parse the first read-write request to determine a target queue address and a target process identifier. The checking subunit can read the target queue identifier of the target queue according to the target queue address, and establish a read-write channel between the host and the target queue when the target queue identifier and the target process identifier meet the matching rule, thereby enabling the host to read and write the target queue. Since the host is allowed to read and write the target queue only when the target queue identifier and the target process identifier meet the matching rule, the process in the host can only read the target queue that meets the requirements. Since the checking subunit can determine whether the process in the host has the authority to access the target queue by determining whether the target process identifier and the target queue identifier meet the matching rule, compared with the prior art, it can prevent the dedicated data processor from illegally accessing the queues corresponding to other processes after mapping the memory to the user state through MMIO, and can prevent data leakage, with high data security.

[0026] The specific implementation of the embodiment of the present application is further explained below in conjunction with the accompanying drawings of the embodiment of the present application.

[0027] Figure 2 Schematic diagram of an acceleration unit provided in an embodiment of the present application. The acceleration unit 200 is provided in a dedicated data processor connected to a host, such as Figure 2 As shown, the acceleration unit 200 includes: a receiving subunit 201, a parsing subunit 202 and a checking subunit 203. The receiving subunit 201 can receive a first read-write request sent by the host, and send the first read-write request to the parsing subunit 202. The parsing subunit 202 can parse the first read-write request, determine the target queue address and target process identifier included in the first read-write request, and send the target queue address and target process identifier to the checking subunit 203. The checking subunit 203 can read the target queue identifier in the target queue according to the target queue address, and when the target process identifier and the target queue identifier meet the matching rule, establish a read-write channel between the host and the target queue based on the target queue address, so that the host reads and writes the target queue.

[0028] The receiving sub-unit 201 can receive a first read-write request sent by the host. The first read-write request can indicate that the target process in the host requests to read and write memory, the process requests to read and write queue registers, etc. After receiving the first read-write request, the receiving unit sends the first read-write request to the parsing sub-unit 202. The parsing sub-unit 202 parses the first read-write request and determines that the first read-write request includes a target queue address and a target process identifier. The target queue address is the register address of the queue register that the host needs to read and write. The target queue can be any queue register in the physical page of the memory. The target process identifier is the process identifier corresponding to the process that needs to perform read and write operations in the host. The process identifier is a unique identifier generated by the process when the process is created in the host. Different processes in the host correspond to different process identifiers.

[0029] After parsing the target queue address and the target process identifier from the first read-write request, the parsing subunit 202 sends the target queue address and the target process identifier to the checking subunit 203. The checking subunit 203 reads the target queue identifier stored in the target queue according to the target queue address. In one example, the target queue may include a data bit and an identifier, the data bit may store data, and the identifier may store a queue identifier. The checking subunit 203 may read the target queue identifier of the target queue from the identifier of the target queue. The checking subunit 203 compares the target process identifier with the target queue identifier. When the target process identifier and the target queue identifier meet the matching rule, a read-write channel between the host and the target queue is established based on the target queue address, so that the process in the host can read and write the target queue through a dedicated data processor. It should be understood that the target process identifier and the target queue identifier meet the matching rule, which can be a rule set manually.

[0030] In an embodiment of the present application, an acceleration unit 200 in a dedicated data processor connected to a host includes a receiving subunit 201, a parsing subunit 202, and a checking subunit 203. The receiving subunit 201 can receive a first read / write request sent by the host, the parsing subunit 202 can parse the first read / write request to determine a target queue address and a target process identifier, the checking subunit 203 can read the target queue identifier of the target queue according to the target queue address, and establish a read / write channel between the host and the target queue when the target queue identifier and the target process identifier meet a matching rule, thereby enabling the host to read / write the target queue. Since the host is allowed to read / write the target queue only when the target queue identifier and the target process identifier meet a matching rule, the process in the host can only read the target queue that meets the requirements. Since the checking subunit 203 can determine whether the process in the host has the authority to access the target queue by determining whether the target process identifier and the target queue identifier meet a matching rule, compared with the prior art, the dedicated data processor can be prevented from illegally accessing queues corresponding to other processes after mapping memory to user mode through MMIO, data leakage can be prevented, and data security is high.

[0031] In a possible implementation, the matching rule includes one of the following: the target process identifier is the same as the target queue identifier, the target process identifier is less than or equal to the target queue identifier, and the target process identifier is greater than or equal to the target queue identifier.

[0032] The matching rule can be a single rule, for example: the target process identifier is an identifier number, and the target queue identifier is also an identifier number. The matching rule may include: the target process identifier is the same as the target queue identifier, the target process identifier is less than or equal to the target queue identifier, and the target process identifier is greater than or equal to the target queue identifier. For example: the host process is only allowed to read and write the target queue when the target process identifier is equal to the target queue identifier.

[0033] It should be noted that the matching rule may also be other rules, and the specific rules may be set manually. For example, the target queue identifier may be a range, and when the target process identifier is within the range, the process may read and write the target queue.

[0034] In an embodiment of the present application, the matching rules include one of the target process identifier being the same as the target queue identifier, the target process identifier being less than or equal to the target queue identifier, and the target process identifier being greater than or equal to the target queue identifier. The matching rules can be set so that the verification subunit 203 can determine whether the process in the host has the authority to access the target queue by judging whether the target process identifier and the target queue identifier meet the matching rules, thereby improving data security.

[0035] In one possible implementation, when the target process identifier and the target queue identifier do not satisfy the matching rule, the verification sub-unit 203 can write the target queue address and the target process identifier into the alarm queue and send an alarm signal to the host, so that the host reads the target queue address and the target process identifier from the alarm queue and generates an alarm log based on the target queue address and the target process identifier.

[0036] When the target process identifier and the target queue identifier do not satisfy the matching rules, the verification sub-unit 203 associates the target process identifier and the target queue address and writes them into the alarm queue. The alarm queue can be a register inside the host and sends an alarm signal to the processor in the host. In one example, the alarm signal can be an interrupt signal. After the host processor receives the interrupt signal, it reads the target queue address and the target process identifier from the alarm queue. It should be understood that when the target process identifier and the target queue address do not satisfy the matching rules, it proves that the target process illegally accesses the queues of other processes. At this time, the host processor determines the target process that illegally requests to read and write based on the read target process identifier, and determines the target queue based on the target queue address. Therefore, an alarm log can be generated based on the process and target queue that illegally requests to read and write.

[0037] In an embodiment of the present application, the verification sub-unit 203 can write the target queue address and the target process identifier into the alarm queue and send an alarm signal to the host when the target process identifier and the target queue identifier do not satisfy the matching rules. The host can thereby be alarmed to inform the process in the host of illegal requests to read and write queues, and the host generates an alarm log, thereby informing the staff of the illegal request event, so that the staff can perform security debugging based on the alarm log.

[0038] Figure 3 is a schematic diagram of a host provided in an embodiment of the present application, such as Figure 3 As shown, a control unit 301 is provided in the host 300, and the control unit 301 can receive a second read-write request generated by a target process, determine a target process identifier corresponding to the target process according to the target process, and generate a first read-write request according to the target process identifier and the second read-write request, and send the first read-write request to the acceleration unit 200, so that after the acceleration unit 200 establishes a read-write channel between the host 300 and the target queue according to the first read-write request, the host 300 reads and writes the target queue, wherein the target process is any process running in the host 300.

[0039] The control unit 301 is arranged in the host 300. In one example, the control unit 301 may be a processing unit with read and write functions. In another example, the control unit 301 may be a bus controller (Root Complex, RC). When the target process in the host 300 requests to read and write the target queue, the target process issues a second read and write request. The second read and write request may include the register address of the queue register to be accessed. After receiving the second read and write request, the control unit 301 determines the target process ID of the target process according to the target process that issues the second read and write request, and generates a first read and write request according to the second read and write request and the target process ID. The first read and write request includes the target queue address of the target queue and the target process ID of the target process requesting to read and write the target queue.

[0040] After the control unit 301 generates the first read-write request, it sends the first read-write request to the acceleration unit 200, which may be the acceleration unit 200 in any of the above-mentioned embodiments. The receiving subunit 201 in the acceleration unit 200 receives the first read-write request, and sends the first read-write request to the parsing subunit 202. The parsing subunit 202 may parse the first read-write request, determine the target queue address and target process identifier included in the first read-write request, and send the target queue address and target process identifier to the verification subunit 203. The verification subunit 203 may read the target queue identifier in the target queue according to the target queue address, and when the target process identifier and the target queue identifier meet the matching rules, establish a read-write channel between the host 300 and the target queue based on the target queue address, so that the target process can read and write the target queue.

[0041] Figure 4 is a schematic diagram of a queue register provided in an embodiment of the present application, such as Figure 4 As shown, the control unit 301 writes the process ID into the Model Specific Register (MSR), and the host 300 writes the queue ID into the queue register when the process is generated. Figure 4 In the MSR, process identifier A corresponding to process A and process identifier B corresponding to process B are stored. The queue register stores queue identifier 0 corresponding to queue_0, queue identifier 1 corresponding to queue_1, queue identifier 2 corresponding to queue_2, queue identifier 3 corresponding to queue_3, and so on, and queue identifier n corresponding to queue_n.

[0042] In an embodiment of the present application, after the control unit 301 in the host 300 receives the second read-write request of the target process, it generates a first read-write request based on the target process identifier of the target process and the second read-write request, and sends the first read-write request to the acceleration unit 200. The receiving subunit 201 in the acceleration unit 200 can receive the first read-write request, the parsing subunit 202 can parse the first read-write request to determine the target queue address and the target process identifier, the verification subunit 203 can read the target queue identifier of the target queue according to the target queue address, and establish a read-write connection between the host 300 and the target queue when the target queue identifier and the target process identifier meet the matching rule. Channel, whereby the target process in the host 300 can read and write the target queue. Since the target process is allowed to read and write the target queue only when the target queue identifier and the target process identifier satisfy the matching rule, the target process in the host 300 can read only the target queue that meets the requirement. Since the inspection subunit in the acceleration unit 200 can determine whether the process in the host 300 has the authority to access the target queue by determining whether the target process identifier and the target queue identifier satisfy the matching rule, compared with the prior art, it can prevent the process from illegally accessing the queues corresponding to other processes after the network card maps the memory to the user state through MMIO, and can prevent data leakage, with higher data security.

[0043] In one possible implementation, the control unit 301 can obtain the target process identifier of the target process when the target process is generated, and after writing the target process identifier into the register in the host 300, associate the register address written with the target process identifier with the process number corresponding to the target process and save it.

[0044] When the target process in the host 300 is generated, the driver will simultaneously generate the target process and the target process identifier corresponding to the target process. The control unit 301 obtains the target process identifier of the target process. In one example, the control unit 301 can actively obtain the target process identifier when the target process is generated. In another example, the control unit 301 can receive the target process identifier sent by the driver when the target process is generated, and return the target process identifier. After the control unit 301 obtains the target process identifier, it writes the target process identifier into a register in the host 300. In one example, the register for storing the process identifier can be an MSR set in the processor.

[0045] After the control unit 301 writes the target process identifier into the register, it associates the register address of the register to which the target process identifier is written with the target process number of the target process corresponding to the target process identifier and saves the address. Thus, after the target process issues a read or write operation request, the control unit 301 can query the target process identifier corresponding to the target process in the register according to the target process number of the target process.

[0046] In an embodiment of the present application, the control unit 301 can obtain the target process identifier of the target process when the target process is generated, and write the target process identifier into a register in the host 300, thereby saving the target identifier corresponding to the target process, and associating the register address written with the target process identifier with the process number corresponding to the target process and saving it, so that after the target process issues a read or write request, the control unit 301 can query the target process identifier according to the process number corresponding to the target process, thereby realizing control over the read and write permissions of the target process.

[0047] In a possible implementation, after the target process sends the second read / write request, the control unit 301 may determine the register address corresponding to the process number according to the process number of the target process, and read the target process identifier stored in the register according to the register address.

[0048] When the target process is generated, the control unit 301 associates the register address written with the target process identifier and the process number corresponding to the target process and saves them. After receiving the second read-write request sent by the target process, the control unit 301 parses the second read-write request and determines the process number of the target process. The target process identifier corresponding to the target process can be read from the register according to the process number of the target process, and a first read-write request is generated according to the second read-write request and the target process identifier, and the first read-write request is sent to the acceleration unit 200.

[0049] In an embodiment of the present application, the control unit 301 can determine the register address corresponding to the process number according to the process number of the target process after the target process sends the second read and write request, thereby reading the target process identifier of the corresponding target process stored in the register according to the register address, thereby realizing the acquisition of the target process identifier.

[0050] In a possible implementation, the control unit 301 may delete the target process identifier stored in the register according to the process number of the target process when the target process ends.

[0051] In an embodiment of the present application, the control unit 301 can delete the target process identifier stored in the register according to the process number of the target process when the target process ends, thereby deleting the process identifier corresponding to the ended process, preventing the process identifier corresponding to the ended process from occupying the register space, thereby ensuring that the process identifier corresponding to the new process can be written into the register when a new process is generated.

[0052] The specific application of the dedicated data processor is described below through a specific embodiment.

[0053] Figure 5is a flow chart of a data reading and writing method provided in an embodiment of the present application, and the data reading and writing method is applied to a dedicated data processor, such as Figure 5 As shown, the data reading and writing method includes the following steps 501 to 503:

[0054] Step 501: Receive a first read / write request sent by a host.

[0055] Step 502: parse the first read / write request to determine the target queue address and target process identifier included in the first read / write request.

[0056] Step 503: read the target queue identifier in the target queue according to the target queue address, and when the target process identifier and the target queue identifier meet the matching rule, establish a read / write channel between the host and the target queue based on the first read / write request, so that the host can read and write the target queue.

[0057] The specific description of each step in the embodiments of the present application can be found in the description of any of the above-mentioned acceleration unit 200 embodiments, and will not be repeated here.

[0058] In an embodiment of the present application, a first read / write request sent by a host is received, the first read / write request is parsed, a target queue address and a target process identifier are determined, the target queue identifier of the target queue is read according to the target queue address, and when the target queue identifier and the target process identifier satisfy a matching rule, a read / write channel between the host and the target queue is established, thereby enabling the host to read / write the target queue. Since the host is allowed to read / write the target queue only when the target queue identifier and the target process identifier satisfy a matching rule, the process in the host can only read the target queue that meets the requirements. Since the check subunit 203 can determine whether the process in the host has the authority to access the target queue by determining whether the target process identifier and the target queue identifier satisfy the matching rule, compared with the prior art, it can prevent the dedicated data processor from mapping the memory to the user state through MMIO, and the process can be prevented from illegally accessing the queues corresponding to other processes, thereby preventing data leakage and achieving high data security.

[0059] In a possible implementation, the matching rule includes: the target process identifier is the same as the target queue identifier, the target process identifier is less than or equal to the target queue identifier, and the target process identifier is greater than or equal to the target queue identifier.

[0060] In one possible implementation, when the target process identifier and the target queue identifier do not satisfy the matching rules, the target queue address and the target process identifier are written into the alarm queue, and an alarm signal is sent to the host, so that the host reads the target queue address and the target process identifier from the alarm queue, and generates an alarm log based on the target queue address and the target process identifier.

[0061] The embodiment of the present application further provides a dedicated data processor, which may be a smart network card connected to a host, for example, the dedicated data processor may be a data processing unit (DPU), and the dedicated data processor includes the acceleration unit 200 in any of the above embodiments. The operation in any of the above embodiments may be implemented by the acceleration unit 200.

[0062] The present application also provides a host, such as Figure 3 As shown, the host includes the control unit 301 in any of the above embodiments, and the host is connected to the dedicated data processor in the above embodiments. The host in the embodiment of the present application can implement the operations performed by the control unit 301 in any of the above embodiments through the control unit 301, and can implement interaction with the dedicated data processor through the connection channel with the dedicated data processor.

[0063] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the method described in the device and system embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of other embodiments.

[0064] It should be understood that the above is a description of a specific embodiment of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0065] It should be understood that an element described in singular form herein or shown in the drawings as only one does not limit the number of the element to one. In addition, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be split into multiple modules or elements.

[0066] It should also be understood that the terms and expressions used herein are for description only, and one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

Claims

1. An acceleration unit, the acceleration unit being arranged in a dedicated data processor connected to a host, characterized in that: The acceleration unit includes: a receiving subunit, a parsing subunit and a checking subunit; The receiving subunit is used to receive a first read / write request sent by the host, and send the first read / write request to the parsing subunit; The parsing subunit is used to parse the first read / write request, determine the target queue address and the target process identifier included in the first read / write request, and send the target queue address and the target process identifier to the verification subunit; The check subunit is used to read the target queue identifier in the target queue according to the target queue address, and when the target process identifier and the target queue identifier meet the matching rule, establish a read / write channel between the host and the target queue based on the first read / write request, so that the host reads and writes the target queue.

2. The acceleration unit according to claim 1, characterized in that: The matching rule includes one of: the target process identifier is the same as the target queue identifier, the target process identifier is less than or equal to the target queue identifier, and the target process identifier is greater than or equal to the target queue identifier.

3. The acceleration unit according to claim 1, characterized in that: The verification subunit is used to write the target queue address and the target process identifier into the alarm queue when the target process identifier and the target queue identifier do not satisfy the matching rule, and send an alarm signal to the host, so that the host reads the target queue address and the target process identifier from the alarm queue, and generates an alarm log according to the target queue address and the target process identifier.

4. A control unit, arranged in a host, characterized in that: The control unit is used to receive a second read-write request generated by a target process, determine a target process identifier corresponding to the target process according to the target process, generate a first read-write request according to the target process identifier and the second read-write request, and send the first read-write request to the acceleration unit, so that after the acceleration unit establishes a read-write channel between the host and the target queue according to the first read-write request, the host reads and writes the target queue, wherein the target process is any process running in the host.

5. The control unit according to claim 4, characterized in that: The control unit is used to obtain the target process identifier of the target process when the target process is generated, and after writing the target process identifier into the register in the host, associate the register address written with the target process identifier with the process number corresponding to the target process and save it.

6. The control unit according to claim 5, characterized in that The control unit is used to determine the register address corresponding to the process number according to the process number of the target process after the target process sends the second read / write request, and read the target process identifier stored in the register according to the register address.

7. The control unit according to claim 5, characterized in that: The control unit is used to delete the target process identifier stored in the register according to the process number of the target process when the target process ends.

8. A data reading and writing method, applied to a dedicated data processor, characterized in that: include: Receiving a first read / write request sent by a host; Parsing the first read / write request to determine a target queue address and a target process identifier included in the first read / write request; The target queue identifier in the target queue is read according to the target queue address, and when the target process identifier and the target queue identifier satisfy a matching rule, a read / write channel between the host and the target queue is established based on the first read / write request, so that the host reads and writes the target queue.

9. A special data processor, characterized in that: The invention comprises an acceleration unit as claimed in any one of claims 1 to 3.

10. A host, characterized in that: comprising a control unit as claimed in any one of claims 4 to 7; The host is connected to the dedicated data processor as claimed in claim 9.

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