Described data operations based on integrated memory regions

Abstract

The invention relates to operations for describing data based on integrated memory regions. Various embodiments enable a memory subsystem to perform a read operation based on integrated memory region description data, which may be generated based on memory region description data (e.g., SGL) provided by a host system for the read operation.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the original Chinese invention patent application entitled “Operation based on integrated memory area description data”. The application number of the original Chinese invention patent application is 202210216809.2 and the application date is March 7, 2022. Technical Field

[0003] Embodiments of the present disclosure relate generally to memory devices, and more particularly, to memory operations, such as read operations, performed based on consolidated memory region description data. Background Art

[0004] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, a host system may utilize a memory subsystem to store data at the memory devices and retrieve data from the memory devices.

[0005] Non-Volatile Memory Express (NVMe) is an example of a memory protocol that supports interaction between a memory subsystem and a host system. The current version of the NVMe protocol supports a scatter list (SGL), which is a mechanism for transmitting commands and data between a host system and a memory subsystem. The SGL can help the memory subsystem process a read or write request, wherein the SGL can describe a list of memory regions on the host system, which the memory subsystem uses in conjunction with a read request to send data back to the host system (e.g., via a peripheral component interconnect express (PCIe) interface), or the memory subsystem uses the list of memory regions in conjunction with a write request to obtain (e.g., read) data from the host system. Each of the memory regions on the host system can act as a buffer (e.g., an SGL buffer) for the memory subsystem to send data back to the host system. The SGL typically includes a linked list of connected buffers, and each buffer size can be different (e.g., as small as 32 bytes). In some cases, the host system establishes a large number of buffers on the host system, which can cause the buffers to be distributed around the local memory of the host system (e.g., based on space availability). This may result in the memory subsystem having to frequently and repeatedly traverse (eg, walk through) the SGL in conjunction with a single SGL-based operation. Summary of the invention

[0006] On the one hand, the present disclosure provides a memory system, which includes: a memory device; and a processing device, which is operatively coupled to the memory device and configured to perform operations including the following: receiving a first request from a host system to read requested first data stored on the memory system, the first request specifying first memory area description data associated with the first request, the first memory area description data describing a first group of individual memory areas of the host system to which the requested first data will be sent; and in response to the first request: based on the first memory area description data, generating first integrated memory area description data by identifying a first group of continuous memory areas, the first group of continuous memory areas each including two or more sequentially adjacent memory areas in the first group of individual memory areas, the first integrated memory area description data including: a single descriptor for each continuous memory area in the first group of continuous memory areas; and a single descriptor for each individual memory area in the first group of individual memory areas, the each individual memory area being excluded from the first group of continuous memory areas; and performing a first read operation on the memory device based on the first integrated memory area description data generated on the memory system.

[0007] On the other hand, the present disclosure provides a method, which includes: receiving a request at a memory system from a host system to read requested data stored on the memory system, the request specifying host memory area description data associated with the request, the host memory area description data describing a group of individual memory areas of the host system to which the requested data will be sent; and in response to the request: accessing the host memory area description data from the host system; generating integrated memory area description data by identifying a group of continuous memory areas, each of the group of continuous memory areas including two or more sequentially adjacent memory areas in the group of individual memory areas, the integrated memory area description data including: a single descriptor for each continuous memory area in the group of continuous memory areas; and a single descriptor for each individual memory area in the group of individual memory areas, the each individual memory area being excluded from the group of continuous memory areas; and storing the integrated memory area description data on a buffer of the memory system.

[0008] On the other hand, the present disclosure provides at least one non-temporary machine-readable storage medium including instructions, which, when executed by a processing device of a memory system, causes the processing device to perform operations including the following: receiving a request from a host system to read requested data stored on the memory system, the request specifying host memory area description data associated with the request, the host memory area description data describing a group of individual memory areas of the host system to which the requested data will be sent; and in response to the request: based on the host memory area description data, generating integrated memory area description data by identifying a group of continuous memory areas, each of the group of continuous memory areas including two or more sequentially adjacent memory areas in the group of individual memory areas, the integrated memory area description data including: a single descriptor for each continuous memory area in the group of continuous memory areas; and a single descriptor for each individual memory area in the group of individual memory areas, wherein each individual memory area is excluded from the group of continuous memory areas; and storing the integrated memory area description data on a buffer of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure will be more fully understood according to the embodiments given below and the accompanying drawings according to various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0010] Figure 1 is a block diagram illustrating an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0011] Figure 2 and 3 Flowchart of an example method for performing memory operations based on consolidated data describing one or more memory regions on a host system according to some embodiments of the present disclosure.

[0012] Figure 4 and 5 A diagram illustrating an example of generating integrated memory region description data according to some embodiments of the present disclosure.

[0013] Figure 6 An interaction diagram is provided that illustrates interactions between components of a computing environment in the context of some embodiments, in which a method for performing a memory read operation based on consolidated data describing one or more memory regions on a host system as described herein is performed.

[0014] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0015] Various aspects of the present disclosure relate to memory operations performed based on consolidated memory region data. Specifically, various embodiments enable a memory subsystem to perform memory read operations based on consolidated data describing one or more memory regions on a host system (e.g., data including a consolidated list of memory regions), wherein the one or more memory regions are used by the memory subsystem as one or more buffers for sending read data to the host system. The memory subsystem may be a storage device, a memory module, or a mixture of storage devices and memory modules. Figure 1 Examples of storage devices and memory modules are described. Generally speaking, a host system can utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system can send access requests to the memory subsystem to store data at the memory subsystem and read data from the memory subsystem.

[0016] The host system may send an access request (e.g., a write command, a read command) to the memory subsystem to store data on a memory device at the memory subsystem, read data from a memory device on the memory subsystem, or write / read structures (e.g., submission and completion queues) relative to a memory device on the memory subsystem. The data to be read or written as specified by the host request is referred to as "host data" hereinafter. The host request may include logical address information (e.g., logical block address (LBA), name space) of the host data, which is the location associated with the host data by the host system. The logical address information (e.g., LBA, name space) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., error correction code (ECC) codeword, parity check code), data version (e.g., for distinguishing the period of written data), valid bitmap (which LBAs or logical transfer units contain valid data), etc.

[0017] As used herein, a memory device may be a non-volatile memory device.

[0018] Currently, a memory subsystem may facilitate data transfers by pushing or pulling data from one or more memory regions of a host system (e.g., on local memory) using conventional techniques. For example, as described herein, Non-Volatile Memory Express (NVMe) is an example of a memory protocol that supports interaction between a memory subsystem and a host system. Current versions of the NVMe protocol support scatter lists (SGLs), which are mechanisms for transferring commands and data between a host system and a memory subsystem. A host system may use scatter lists (SGLs) to facilitate a memory subsystem to perform a read request, wherein the SGL may describe a list of memory regions on the host system, which the memory subsystem uses to send (e.g., transfer) the requested data back to the host system (e.g., via a peripheral component interconnect express (PCIe) interface). Each of the memory regions on the host system may act as a buffer (e.g., an SGL buffer) for the memory subsystem to send data back to the host system. The SGL typically includes a linked list of connected buffers, and each buffer size may be different (e.g., as small as 1 byte, according to the NVMe standard). In some cases, the host system establishes a large number of buffers on the host system, which may distribute the buffers around the local memory of the host system (e.g., based on space availability). This may result in the memory subsystem having to frequently and repeatedly traverse (e.g., walk through) the SGL in conjunction with a single SGL-based operation.

[0019] In general, each individual memory request (e.g., a read or write request) generated by a host system may have a corresponding SGL stored on the host system, which the memory system may access and use in response to the individual requests. In addition, each of the memory regions described by the SGL may be sized differently (e.g., variably) and located at different locations (e.g., logical or physical locations) on the local memory of the host system. A given SGL typically includes a list of descriptors that each describe a different memory region on the host system, and the size of a given SGL may vary based on its associated request. For example, the host system may generate or establish a large number of small memory regions on the local memory of the host system in conjunction with a given read request (e.g., a read request based on the SGL) sent by the host system to the memory system. The size and / or number of SGLs handled by a conventional memory system at a given time may make it impossible or impractical for the memory system to store all portions of the SGL on the memory system at the same time (e.g., at least without increasing the memory space used to store the SGL on the memory system). Therefore, when performing memory operations in conjunction with a given SGL, a conventional memory system typically accesses (e.g., reads and traverses or walks) the associated SGL from the host system multiple times (e.g., when buffer space permits). The conventional memory system's repeated accesses to the associated SGL (and other SGLs used for other memory operations) can generate a large amount of overhead for the conventional memory system when performing the associated read operations, which in turn can reduce the operating efficiency of the conventional memory system.

[0020] Various aspects of the present disclosure solve the above and other deficiencies by performing a read or write operation on a memory subsystem based on integrated memory region description data, which can be generated based on memory region description data (e.g., SGL) provided by a host system for the read or write operation. For example, when a host system sends a request (e.g., a command) to read data from a memory subsystem, the host system can: create or establish a set of memory regions (e.g., buffers) on the host system to facilitate sending the read data from the memory subsystem to the host system in response to the request; and generate host memory region description data (e.g., SGL for the request, where the SGL is stored on the host system) describing a set of memory regions created / established on the host system. In response to the request, various embodiments access the host memory region description data (e.g., SGL) from the host system. The host memory region description data can be separated from the request stored on the host system, buffered on the memory subsystem when accessed from the host system, and accessed by the memory subsystem via a data bus (e.g., PCIe bus) between the host system and the memory subsystem. For various embodiments, the data size of the host memory region description data is larger than a buffer on the memory subsystem used to store such data in conjunction with a read request. Based on the host memory region description data, various embodiments identify one or more contiguous memory regions in a set of memory regions, wherein each contiguous memory region is formed by two or more memory regions in a set of memory regions that are sequentially adjacently located on the host system (e.g., its local memory). Various embodiments generate (and store on the memory subsystem) integrated memory region description data, the integrated memory region description data including a single memory region descriptor for each contiguous memory region identified in the list of memory regions described by the host memory region description data, and including a single memory descriptor for each memory region in a set of memory regions that is not part of one of the identified contiguous memory regions. In this way, the integrated memory region description data can represent a simplified version of the host memory region description data provided by the host system.

[0021] Although various embodiments are described herein with respect to read requests from a host system or device, various embodiments support write requests in a similar manner. Typically, for write requests, the memory subsystem may retrieve data from the host system in sequence, so the memory subsystem typically does not have to traverse (e.g., walk through) the host memory region description data (e.g., SGL) as frequently as for read requests. Nevertheless, consolidating the memory region description data as described herein may be beneficial to the memory subsystem performing both read and write requests because consolidating the memory region description data may reduce storage used on the memory subsystem and may facilitate data bus optimization (e.g., better use of transaction layer packets (TLPs) sent via the PCIe bus).

[0022] The generated integrated memory region description data may be smaller in data size than the host memory region description data provided by the host system, which may enable the integrated memory region description data to be traversed faster than the host memory region description data. In addition, when the host memory region description data cannot be completely stored on the memory subsystem, the smaller data size may permit the integrated memory region description data to be completely stored on the memory subsystem (e.g., its designated buffer), thereby avoiding the need for the memory subsystem to repeatedly access (e.g., read and traverse) the host memory region description data (e.g., via a PCIe data bus between the host system and the memory subsystem). In addition, by identifying contiguous memory regions, embodiments may enable larger data transfers that improve data bus efficiency between the host system and the memory subsystem.

[0023] As used herein, a memory zone may include a memory zone space on a memory device (e.g., local memory) of a host system. A memory zone may be used as a buffer space on a host system for receiving requested read data from a memory subsystem, or a buffer space on a host system for providing data to be written to a memory subsystem. As used herein, memory zone description data may describe one or more memory zones on a host system in conjunction with a request from a host system to a memory subsystem (e.g., as a list). For example, the memory zone description data may include entries or descriptors for each memory zone. Each entry / descriptor may define a separate memory zone by a memory address corresponding to a memory address space (for individual memory zones) on a memory (e.g., local memory) of the host system and a memory size (e.g., size value) of the memory address space. The size of the individual memory zones described by the memory zone description data may vary. The memory zone description data may be implemented as a linked list of memory zone descriptors. An example of memory zone description data may include (but not limited to) an SGL associated with a request sent by a host system to a memory subsystem.

[0024] Disclosed herein are some examples of performing memory operations based on consolidated data describing one or more memory regions on a host system, as described herein.

[0025] Figure 1 An example computing environment 100 is shown that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0026] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, secure digital (SD) cards, embedded multimedia controllers (eMMC) drives, universal flash memory (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0027] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0028] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical connections, optical connections, magnetic connections, etc.

[0029] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0030] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a SATA interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a Fibre Channel, a serial attached SCSI (SAS), a small computer system interface (SCSI), a double data rate (DDR) memory bus, a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting double data rate (DDR)), an open NAND flash interface (ONFI), a double data rate (DDR), a low power double data rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple independent communication connections, and / or a combination of communication connections.

[0031] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0033] Each memory device 130 may include one or more memory cell arrays. One type of memory cell, such as SLC, may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), TLC, quad-level cells (QLC), and penta-level cells (PLC) may store multiple bits per cell. In some embodiments, each memory device 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0034] Although nonvolatile memory components such as NAND-type flash memory (e.g., 2D NAND, 3D NAND) and a 3D cross-point array of nonvolatile memory cells are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations performed at the memory device 130. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0036] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0037] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), name spaces) and physical memory addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system 120 into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0039] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0040] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] The memory subsystem controller 115 includes a memory region description data integrator 113 that implements or facilitates the various methods described herein with respect to the memory subsystem 110. For example, the memory region description data integrator 113 may enable the memory subsystem controller 115 to generate integrated memory region description data on the memory subsystem 110 based on host memory region description data provided by the host system 120 in conjunction with a request to read data from or write data to the memory subsystem 110. In addition, the memory region description data integrator 113 may enable the memory subsystem controller 115 to perform a read operation or a write operation in response to a request based on the generated integrated memory region description data.

[0042] For some embodiments, the host system 120 sends a request (e.g., a command) to the memory subsystem 110 to read the requested data from a memory location corresponding to a memory address (e.g., a logical block address) on the memory subsystem 110, or to write the data to a memory location corresponding to a memory address on the memory subsystem 110. In conjunction with the request, the host system 120 may create or establish a set of memory regions (e.g., buffers) on the host system 120, such as on a local memory of the host system 120, to facilitate sending (e.g., transferring) the requested data from the memory subsystem 110 to the host system 120 in response to the request. Additionally, in conjunction with the request, the host system 120 may generate host memory region description data (e.g., an SGL for the request) that describes a set of memory regions created / established on the host system 120. For various embodiments, the host memory region description data is generated and stored on a memory (e.g., a local memory) of the host system 120. After receiving the request, the memory subsystem 110 may access the host memory region description data directly from the host system 120 (e.g., via a data bus, such as a PCIe bus) as needed to execute the request by the memory subsystem 110. Generally speaking, the data size of the host memory region description data may make it infeasible for the memory subsystem 110 to locally store all of the host memory region description data on a buffer of the memory subsystem 110 at one time, especially when the memory subsystem 110 is handling multiple requests each having associated host memory region description data simultaneously.

[0043] In response to the request, the memory region description data integrator 113 may enable the memory subsystem controller 115 to access the host memory region description data (e.g., SGL) from the host system 120. When the host memory region description data is accessed by the memory subsystem 110 from the host system 120, the host memory region description data may be separated from the request received by the memory subsystem 110, stored on a host-side memory (e.g., local memory) of the host system 120, and buffered on the memory subsystem 110. The host memory region description data may be accessed by the memory subsystem 110 via a data bus (e.g., PCIe bus) between the host system 120 and the memory subsystem 110.

[0044] The memory region description data integrator 113 may cause the memory subsystem controller 115 to generate integrated memory region description data based on the host memory region description data accessed by the memory subsystem 110 from the host system 120. As described herein, the data size of the host memory region description data may be larger than a buffer on the memory subsystem 110 used to store such data on the memory subsystem 110. Specifically, the memory region description data integrator 113 may cause the memory subsystem controller 115 to identify one or more contiguous memory regions in a set of memory regions described by the host memory region description data, wherein each contiguous memory region includes two or more memory regions in the set of memory regions that are sequentially adjacently located on the host system 120 (e.g., its local memory). For some embodiments, the integrated memory region description data includes a single descriptor (e.g., a memory region descriptor) for each contiguous memory region identified in the memory region list described by the host memory region description data, and includes a single memory descriptor for each memory region in the set of memory regions that is not part of one of the identified contiguous memory regions. In this way, the consolidated memory region description data may represent a simplified version of the host memory region description data provided by the host system.

[0045] According to various embodiments, the data size of the generated consolidated memory region description data is smaller than that of the host memory region description data, and may have a data size that permits it to be completely stored on the buffer of the memory subsystem 110. By having the consolidated memory region description data completely stored on the memory subsystem 110, the memory subsystem 110 may access the consolidated memory region description data locally when the memory subsystem 110 sends a portion of the requested data to the memory region described by the consolidated memory region description data on the host system 120. This may enable the memory subsystem controller 115 to traverse the consolidated memory region description data faster than the host memory region description data. In the case of locally accessing the consolidated memory region description data, the memory subsystem 110 may avoid the overhead of repeatedly accessing (and buffering) the host memory region description data from the host system 120 when the memory subsystem 110 sends a portion of the requested data to the memory region on the host system 120. Additionally, by identifying contiguous memory regions, consolidating memory region description data may enable the memory subsystem controller 115 to perform larger data transmissions that improve data bus efficiency between the host system 120 and the memory subsystem 110 (e.g., better use of transaction layer packets (TLPs) sent via the PCIe bus).

[0046] For some embodiments, the memory region description data integrator 113 causes the memory subsystem controller 115 to perform a read operation or a write operation in response to a request based on the generated integrated memory region description data. Specifically, the memory region description data integrator 113 causes the memory subsystem controller 115 to send a set of read commands for a set of logical block addresses, where the requested data is stored on the memory subsystem 110, or a set of write commands for a set of logical block addresses, where data (e.g., provided by the host system 120) is to be stored on the memory subsystem 110, to one or more of the memory devices 130, 140. With respect to the read request, the memory subsystem controller 115 may receive selected data from one of the memory devices 130, 140 in response to one of the read commands (in the set of read commands) associated with the selected logical block address in the set of logical addresses. In response to receiving the selected data, the memory subsystem controller 115 may determine that one or more selected memory regions described in the integrated memory region description data in the host system 120 will receive the selected data from the memory subsystem 110. Regarding write requests, the memory subsystem controller 115 may determine that one or more selected memory regions described in the consolidated memory region description data in the host system 120 will provide selected data to be written to one or more of the memory devices 130 , 140 via a set of write commands.

[0047] Determining one or more selected memory regions of the host system 120 may include determining (e.g., calculating) one or more ranges of host memory addresses corresponding to the one or more selected memory regions based on the consolidated memory region description data. The consolidated memory regions may be stored, for example, in a buffer or local memory of the memory subsystem 110, such as the local memory 119 of the memory subsystem controller 115. The consolidated memory region description data may include a set of memory region descriptors describing the starting address and memory size of each memory region, which the memory subsystem controller 115 may use to calculate one or more host memory addresses in view of the selected logical block address associated with the selected data received from one of the memory devices 130, 140. Specifically, the consolidated memory region description data may be indexed by the logical block address, which may help determine the host memory address. Ultimately, the memory subsystem controller 115 may send the selected data to a location on the local memory corresponding to the host memory address. The location on the local memory may correspond to a location within the memory region described by the consolidated memory region description data. The memory subsystem controller 115 may receive selected data (representing a portion of the requested data) in response to each read command sent to the one or more memory devices 130, 140, and for each of those selected data received, the memory subsystem controller 115 may determine a host memory address and send the selected data to a location (on the local memory of the host system 120) corresponding to the determined host memory address. The selected data may be sent to the location on the local memory, for example, using a single transaction layer packet (TLP) including the selected data, where the single TLP may be in accordance with the Peripheral Component Interconnect Express (PCIe) standard.

[0048] Figure 2 and 3 Flowchart of an example method for performing memory operations based on aggregated data describing one or more memory regions on a host system according to some embodiments of the present disclosure. Methods 200 and 300 may be performed by processing logic that may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, at least one of methods 200 and 300 is performed by Figure 1 The memory subsystem controller 115 is executed based on the memory region description data integrator 113. Additionally or alternatively, for some embodiments, at least one of the methods 200, 300 is at least partially performed by Figure 1The local media controller 135 of the memory device 130 of the memory device 130 is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the processes can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0049] View now Figure 2 In the method 200 of the present invention, at operation 202, a processing device (e.g., a processor 117 of a memory subsystem controller 115) receives a request at a memory system (e.g., 130) from a host system (e.g., 120) to read requested data stored on a memory system (e.g., 110) or to write data to the memory system. The request may be a specific type of read or write request using a memory region, such as an SGL read command / request. For some embodiments, the request from the host system specifies host memory region description data associated with the request. For example, the request may specify (e.g., via a pointer to a memory location) where the host memory region description data is stored on the host system or from which the host memory region description data may be accessed. For some embodiments, each request to a memory system (e.g., 110) may be associated with its own host memory region description data. According to various embodiments, the host memory region description data describes a set of individual memory regions of a local memory of a host system that will be used by the memory system (e.g., as a buffer) to send the requested data to the host system. In this way, each of the memory regions can be used as a host-side buffer on a host system (e.g., 120) to receive requested data from a memory system (e.g., 110). The host memory region description data may include a linked list of memory region descriptors, wherein each memory region descriptor includes a memory address (e.g., a pointer to a memory address) corresponding to a memory address space on a local memory of the host system. As described herein, the host memory region description data may include an SGL associated with the request, wherein the SGL is in accordance with a non-volatile memory express (NVMe) protocol. The host memory region description data may be generated by the host system (e.g., 120) in conjunction with the request, and the generated host memory region description data may be stored on a memory local to the host system (e.g., a local memory of the host system 120), wherein the memory may be accessed by the memory system (e.g., 110).

[0050] In response to the request, at operation 204, the processing device (e.g., 117) generates the integrated memory region description data based on the host memory region description data provided by the host system (e.g., 120) to the memory system (e.g., 110). For some embodiments, the integrated memory region description data is generated by identifying a group of continuous memory regions (in a group of individual memory regions), wherein each continuous memory region includes two or more sequentially adjacent memory regions in a group of individual memory regions described by the host memory region description data. For some embodiments, the individual continuous memory regions in a group of individual memory regions are identified as the host memory region description data accessed from the host system. Each continuous memory region may represent a maximum sequence of adjacent memory regions. Two or more sequentially adjacent memory regions may be considered as continuous memory regions. For various embodiments, the integrated memory region description data includes a single descriptor for each continuous memory region in a group of continuous memory regions, a single descriptor for each individual memory region in a group of individual memory regions, and each individual memory region is excluded from a group of continuous memory regions (e.g., not part of any continuous memory region therein). For some embodiments, a new descriptor is generated in the consolidated memory region description data for each contiguous memory region in the identified set of contiguous memory regions, while each of the other individual descriptors in the consolidated memory region description data (for other memory regions that are not part of any contiguous memory region) may be copied from the host memory region description data. For some embodiments, the consolidated memory region description data is indexed by a logical block address, which may help determine the host memory address. Each memory region described in the consolidated memory region description data may be defined by a starting memory address corresponding to an individual memory address space (on the local memory of the host system) and a memory size of the individual memory address space. In the consolidated memory region description data, each starting memory address may effectively indicate a break between a previous memory region and the starting memory address. After the consolidated memory region description data has been generated on the memory system (e.g., 110), the processing device may rely on the consolidated memory region description data (instead of the host memory region description data) to process a request from the host system, thereby avoiding the need for the processing device to repeatedly access the host memory region description data when portions of the requested data are sent back to the host system (e.g., 120).

[0051] At operation 206, the processing device (e.g., 117) performs a memory operation, such as a read operation or a write operation, on one or more memory devices (e.g., 130, 140) of the memory system (e.g., 110) based on the consolidated memory region description data generated on the memory system (e.g., 110). For some embodiments, performing a read operation on one or more memory devices (e.g., 130, 140) based on the consolidated memory region description data includes: sending (e.g., issuing) a set of read commands (e.g., ten read commands) for a set of logical block addresses (e.g., ten LBAs) to the memory device, where the requested data is stored on the memory system (e.g., 110); and receiving selected data (e.g., data from the selected LBA) from the memory device in response to a selected read command (e.g., in a set of read commands) for a selected logical block address in the set of logical addresses.

[0052] A set of read commands is generated based on the request and associated memory address received from the host system (e.g., 120) by operation 202. A set of read commands may include one or more read commands to two or more memory devices of the memory system, and a set of read commands may be sent to the one or more memory devices via one or more memory channels. One or more memory devices (e.g., 130, 140) may provide a response or result for each of the read commands sent. Responses / results may be received randomly and out of order from the one or more memory devices. In response to a set of read commands, the processing device may receive a corresponding set of responses from the one or more memory devices, wherein each response includes a selected data portion of the requested data. Each of the responses may indicate a logical block address to which the selected portion of the requested data corresponds. Each logical block corresponding to the logical block address may include a size of, for example, 512 bytes (512B) or 528 bytes (528B) (e.g., with extended protection information or metadata).

[0053] In response to receiving selected data from one of the memory devices (e.g., 130, 140), the processing device may determine that one or more selected memory regions described in the integrated memory region description data in the host system 120 receive the selected data from the memory subsystem 110. For example, the processing device may determine that the selected data (e.g., LBA) received from one of the memory devices will be sent and saved (e.g., transferred) across two or more memory regions, wherein one of the memory regions may receive a portion (e.g., a starting portion, a middle portion, or an ending portion) of the selected data. Therefore, based on the integrated memory region description data, the memory system may determine (e.g., calculate) one or more ranges of host memory addresses corresponding to the one or more selected memory regions that will receive the selected data. The host memory address may correspond to a memory location (on the local memory of the host system) within one of a set of individual memory regions created / established on the host system and initially described by the host memory region description data. Ultimately, the processing device may send the selected data to one or more memory locations on the local memory corresponding to the range of host memory addresses. The selected data may be sent to a location on a local memory using a single TLP including the selected data, wherein the single TLP is in accordance with the PCIe standard. To achieve more efficient use of the data bus between the memory system and the host system, for some embodiments, a single TLP includes selected data and additional data received from one or more memory devices in response to another read command sent to the one or more memory devices, the other read command being associated with a second read operation performed on the one or more memory devices in response to a second request received by the memory system from the host system. The selected data and the additional data may go to sequentially adjacent memory areas on the host system. In this way, various embodiments may optimize PCIe transfers from the memory system to the host system, and may maximize the use of TLPs whenever possible.

[0054] For some embodiments, performing a write operation on one or more memory devices (e.g., 130, 140) based on the consolidated memory region description data includes: determining one or more selected memory regions described in the consolidated memory region description data in a host system (e.g., 120), wherein the one or more selected memory regions are storing data to be written to one or more memory devices (e.g., 130, 140) of a memory system (e.g., 110); retrieving data from the one or more selected memory regions; and writing the retrieved data to the one or more memory devices according to a request from the host system (e.g., 120). For example, the processing device may write the retrieved data to the one or more memory devices by sending (e.g., issuing) a set of write commands (e.g., two write commands) for a set of logical block addresses (e.g., two LBAs) to one or more of the memory devices, the set of logical block addresses corresponding to physical locations to which a portion of the retrieved data is to be written.

[0055] View now Figure 3 In the method 300, at operation 302, a processing device (e.g., processor 117 of memory subsystem controller 115) receives a request to read requested data stored on a memory system (e.g., 110) or to write data to the memory system from a host system (e.g., 120) at a memory system (e.g., 130). For some embodiments, operation 302 is similar to the method described above with respect to Figure 2 Operation 202 of method 200 is described.

[0056] In response to receiving the request at operation 302, at operation 304, the processing device (e.g., 117) accesses the host memory region description data from the host system (e.g., 120). For various embodiments, the processing device (e.g., 117) accesses the host memory region description data from the host system (e.g., 120) via a data bus (e.g., a PCIe bus), which enables the processing device to pull, read, and traverse the host memory region description data as needed. According to some embodiments, the processing device (e.g., 117) accesses the host memory region description data only once to facilitate operation 306.

[0057] At operation 306, the processing device (e.g., 117) generates the integrated memory region description data based on the host memory region description data provided by the host system (e.g., 120) to the memory system (e.g., 110). For some embodiments, operation 306 is similar to the operation described with respect to Figure 2 Operation 204 of the described method 200. When the integrated memory region description data is generated through operation 306, the processing device may store the integrated memory region description data on a buffer (eg, 119) of the memory system (eg, 110) at operation 308.

[0058] At operation 310, a processing device (e.g., 117) performs a memory operation, such as a read operation or a write operation, on one or more memory devices (e.g., 130, 140) of a memory system (e.g., 110) based on the integrated memory region description data generated on the memory system (e.g., 110). For some embodiments, operation 310 is similar to that described with respect to Figure 2 Operation 206 of method 200 is described.

[0059] Figure 4 and 5 FIG. 1 is a diagram showing an example of generating integrated memory region description data according to some embodiments of the present disclosure. Figure 4 and 5 While described with respect to performing read operations, various embodiments support performing write operations using the consolidated memory region description data in a similar manner. Figure 4 Example host memory region description data 402 generated by a host system in conjunction with a request to read data from a memory system is shown, where the request to read data may include multiple LBAs of the memory system (eight LBAs, 1-8), and where each logical block has a size of 512 bytes (512B). The host memory region description data 402 may represent an SGL generated by the host system, where each memory region (e.g., an SGL buffer) has a separate entry or descriptor in the SGL. As shown, the host memory region description data 402 describes eight memory regions, and each individual memory region is described by a starting address (A) of the individual memory region and a memory size (LEN) of the individual memory region. Specifically, the host memory area description data 402 describes the following list of individual memory areas: a first memory area (A=0, LEN=32B); a second memory area (A=32, LEN=128B); a third memory area (A=100, LEN=96B); a fourth memory area (A=196, LEN=256B); a fifth memory area (A=500, LEN=512B); a sixth memory area (A=1012, LEN=2048B); a seventh memory area (A=2036, LEN=1000B); and an eighth memory area (A=3036, LEN=24B).

[0060] The host memory region description data 404 illustrates the host memory region description data 402 after one or more contiguous memory regions have been identified according to some embodiments. Specifically, the following contiguous memory regions are identified in the memory region list described by the host memory region description data 402: a first contiguous memory region including a first memory region (A=0, LEN=32B) and a second memory region (A=32, LEN=128B); a second contiguous memory region including a third memory region (A=100, LEN=96B) and a fourth memory region (A=196, LEN=256B); and a third contiguous memory region including a fifth memory region (A=500, LEN=512B), a sixth memory region (A=1012, LEN=2048B) and a seventh memory region (A=2036, LEN=1000B).

[0061] Based on the host memory region description data 404 and the one or more identified contiguous memory regions, the memory system may generate consolidated memory region description data 406. Specifically, the memory system may generate consolidated memory region description data 406 such that there is a single entry / descriptor for each of the first, second, and third contiguous memory regions, and there is a single entry / descriptor for the remaining memory region (the eighth memory region) that is not part of any of the identified contiguous memory regions. As shown, the integrated memory region description data 406 includes a single entry / descriptor for each of the following: a first contiguous memory region, whose starting address is 0 (A=0) and whose memory size is 160B (LEN=160B); a second contiguous memory region, whose starting address is 100 (A=100) and whose memory size is 352B (LEN=352B); a third contiguous memory region, whose starting address is 500 (A=500) and whose memory size is 4072B (LEN=4072B); and an eighth memory region, whose starting address is still 3036 (A=3036) and whose memory size is 24B (LEN=24B), which is the same as described by the host memory region description data 402.

[0062] As described herein, based on the consolidated memory region description data 406, the memory system may determine (e.g., calculate) one or more selected memory regions for sending (e.g., transmitting) LBAs (received / returned from one of the memory devices) to the host system in response to a request to read data. For example, in response to the request, eight read commands for eight different LBAs may be sent to one or more memory devices of the memory system to retrieve the read data requested by the host system, where each logical block may have a size of 512B. As described herein, responses / results may be received out of order (e.g., randomly) from the one or more memory devices. In the event that the one or more memory devices return eight LBAs (LBA 8), the memory system may determine one or more selected memory regions of the host system that will receive LBA 8. As described herein, the consolidated memory region description data 406 may be indexed by the ordinal numbers of the LBAs returned by the one or more memory devices. For example, based on the consolidated memory region description data 406, the memory system may determine the starting host memory address of LBA 8 as follows:

[0063] 500+(8-1)×512B=4084,

[0064] Where 8 represents the eighth LBA (LBA 8). In addition, based on the integrated memory region description data 406, the memory system can determine that the host memory address of 4084 belongs to the third continuous memory region, the starting memory address of the third continuous memory region is 500 and the ending memory address is 4572, and LBA 8 will be sent and saved (e.g., transferred) across the third continuous memory region (starting at the host memory address of 4084 and ending at the host memory address of 4572) and the eighth memory region (starting at the host memory address 4572 and ending at the host memory address of 4596). As a result, the memory system can send (e.g., transfer or move) 488B of LBA 8 from the memory system to the memory space on the host system, the 488B starting at the memory location corresponding to the host memory address 4084 and ending at the memory location corresponding to the host memory address 4572. In addition, the memory system will send (e.g., transfer or move) the remaining 24B of LBA 8 from the memory system to the memory space on the host system, where the 24B starts at the memory location corresponding to host memory address 4572 and ends at the memory location corresponding to host memory address 4596.

[0065] Continuing with this example, where one or more memory devices return a first LBA (LBA 1), the memory system can determine that the first contiguous memory region of the host system (starting at a host memory address of 0 and ending at a host memory address of 512) will receive LBA 1. Specifically, based on the consolidated memory region description data 406, the memory system can determine the starting host memory address of LBA 1 as follows:

[0066] 500+(1-1)×512B=0,

[0067] Where 1 represents the first LBA (LBA 1). Thus, the memory system can send (e.g., transfer or move) 512B of LBA 1 from the memory system to the memory space on the host system, starting at a memory location corresponding to host memory address 0 and ending at a memory location corresponding to host memory address 512. As shown, the sending of LBA 1 does not cross into another memory zone (i.e., LBA 1 is within the first contiguous memory zone).

[0068] Figure 5 Example host memory region description data 502 generated by a host system in conjunction with a request to read data from a memory system is shown, where the request to read data may include multiple LBAs (three LBAs, 1-3) of the memory system, and where each logical block has a size of 528 bytes (528B). Figure 4 Host memory region description data 402 of the host system, host memory region description data 502 may represent an SGL generated by the host system, where each memory region (e.g., SGL buffer) has a separate entry or descriptor in the SGL. As shown, host memory region description data 502 describes the following individual memory region lists: first memory region (A=5000, LEN=512B); second memory region (A=5512, LEN=16B); third memory region (A=6000, LEN=512B); fourth memory region (A=6512, LEN=16B); fifth memory region (A=7000, LEN=512B); sixth memory region (A=7512, LEN=512B).

[0069] The host memory region description data 504 (illustrating the host memory region description data 502 after one or more continuous memory regions have been identified according to some embodiments) identifies the following continuous memory regions: a first continuous memory region, which includes a first memory region (A=5000, LEN=512B) and a second memory region (A=5512, LEN=16B); a second continuous memory region, which includes a third memory region (A=6000, LEN=512B) and a fourth memory region (A=6512, LEN=16B); and a third continuous memory region, which includes a fifth memory region (A=7000, LEN=512B) and a sixth memory region (A=7512, LEN=512B).

[0070] Based on the host memory region description data 504 and the one or more identified contiguous memory regions, the memory system may generate consolidated memory region description data 506. Specifically, the memory system may generate consolidated memory region description data 506 such that there is a single entry / descriptor for each of the first, second, and third contiguous memory regions. As shown, the consolidated memory region description data 506 includes a single entry / descriptor for each of: a first contiguous memory region having a starting address of 5000 (A=5000) and a memory size of 528B (LEN=528B); a second contiguous memory region having a starting address of 6000 (A=6000) and a memory size of 528B (LEN=528B); and a third contiguous memory region having a starting address of 7000 (A=7000) and a memory size of 528B (LEN=528B).

[0071] Figure 6 An interaction diagram is provided that illustrates interactions between components of a computing environment in the context of some embodiments, wherein a method for performing a memory read operation based on consolidated data describing one or more memory regions on a host system as described herein is performed. Figure 6Memory reads are shown as being performed according to various embodiments, but some embodiments support performing memory writes in a similar manner based on integrated data (describing one or more memory areas on a host system). The operations of the method may be performed by processing logic that may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method is performed by a host system (e.g., 120), a memory subsystem controller (e.g., 115), a memory device (e.g., 130 or 140), or some combination thereof. Although the operations are shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the embodiments shown should be understood only as examples, and the processes shown may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. In Figure 6 In the context of the illustrated example, the host system may include host system 120 , the memory subsystem controller may include memory subsystem controller 115 , and the memory device may include memory device 140 .

[0072] like Figure 6 As shown, at operation 602, the memory subsystem controller 115 sends a request to read requested data from the memory subsystem 110, wherein the request specifies host memory region description data associated with the request, wherein the host memory region description data describes a set of individual memory regions of a local memory of the host system 120 to be used to send (e.g., transfer) the requested data to the host system 120. At operation 610, the memory subsystem controller 115 receives the request from the host system, and in response, the memory subsystem controller 115 accesses the host memory region description data from the host system 120 (e.g., via a PCIe bus) at operation 612. At operation 604, the host system 120 provides the memory subsystem 110 with access to the host memory region description data stored on the host system 120.

[0073] Based on the accessed host memory region description data, at operation 614, the memory subsystem controller 115 generates consolidated memory region description data by identifying a group of contiguous memory regions, each of which includes two or more sequentially adjacent memory regions in a group of individual memory regions (described by the accessed host memory region description data). At operation 616, the memory subsystem controller 115 performs a read operation on the memory device 140 based on the consolidated memory region description data generated by the memory subsystem controller 115. At operation 630, the memory device 140 facilitates the memory subsystem controller 115 to perform the read operation, wherein the memory device 140 may execute one or more read commands issued by the memory subsystem controller 115 to the memory device 140 in conjunction with the read operation. Additionally, at operation 606, the host system 120 provides access to one or more memory regions on the host system 120 to facilitate the receipt of the requested data (via the memory subsystem controller 115) from the memory subsystem 110 to the host system 120.

[0074] Figure 7 An example machine is shown in the form of a computer system 700 within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 700 may be coupled to a host system (e.g., Figure 1 1) corresponding to a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a peer-to-peer (or distributed) network environment, or in the capacity of a server or a client machine in a client-server network environment.

[0075] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is shown, the term "machine" should also be construed to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0076] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 718 that communicate with each other via a bus 730.

[0077] The processing device 702 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device 702 can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 702 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 may further include a network interface device 708 to communicate via a network 720.

[0078] The data storage device 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 726 or software embodying any one or more of the methods or functions described herein. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage device 718, and / or the main memory 704 may correspond to Figure 1 Memory subsystem 110.

[0079] In one embodiment, instructions 726 include instructions to implement functionality corresponding to performing a memory read operation based on consolidated data describing one or more memory regions on a host system as described herein (e.g., Figure 1113). Although the machine-readable storage medium 724 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executed by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0080] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally considered to be a self-consistent sequence of operations that produce a desired result. Operations are those that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Mainly for common reasons, it has proven convenient at times to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0081] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0082] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, each coupled to a computer system bus, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions.

[0083] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with the program according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the method. The structures for various of these systems will be presented as set forth in the description below. In addition, the embodiments of the present disclosure are not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0084] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0085] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A memory system, comprising: Memory device; as well as a processing device operatively coupled to the memory device, configured to perform operations comprising: In response to a request from a host system to write requested data to the memory device of the memory system: Aggregate memory region description data is generated by identifying a set of contiguous memory regions in a set of individual memory regions of the host system that provide the requested data for writing, the set of individual memory regions of the host system being described by the memory region description data specified by the request, the aggregate memory region description data comprising: A single descriptor for each contiguous memory region in the set of contiguous memory regions; and a single descriptor for each individual memory region in the set of individual memory regions, the each individual memory region being excluded from the set of contiguous memory regions; and A write operation is performed on the memory device based on the integrated memory region description data generated on the memory system.

2. The memory system according to claim 1, wherein the generating the integrated memory region description data comprises: The single descriptor is generated for each contiguous memory region in the set of contiguous memory regions of the host system.

3. The memory system of claim 1 , wherein the set of individual memory regions of the host system are described by memory region description data stored on the host system and specified by the request, the operations comprising: The memory region description data is accessed from the host system.

4. The memory system of claim 3, wherein the memory region description data comprises a linked list of memory region descriptors, each memory region descriptor comprising a memory address corresponding to a memory address space on a local memory of the host system.

5. The memory system according to claim 3, wherein the memory region description data comprises a scatter gather list (SGL) according to a non-volatile memory express (NVMe) protocol.

6. The memory system of claim 1 , wherein each individual memory region of the set of individual memory regions of the host system is defined by: memory addresses corresponding to individual memory address spaces on a local memory of the host system; and The memory size of the individual memory address space.

7. The memory system of claim 1, wherein each individual memory region of the set of individual memory regions comprises an individual memory address space on a local memory of the host system.

8. The memory system of claim 1 , wherein performing the write operation on the memory device based on the consolidated memory region description data stored on the memory system for the host system comprises: determining, based on the consolidated memory region description data for the host system, a selected set of memory regions on the host system storing the requested data to be written to the memory device; retrieving the requested data from the selected set of memory areas on the host system; as well as A set of write commands for a set of logical block addresses are sent to the memory device, wherein the requested data is to be written to the set of logical block addresses according to the request.

9. The memory system of claim 8, wherein the requested data is retrieved from the set of selected memory regions on the local memory of the host system using a single transaction layer packet (TLP), the single transaction layer packet being in accordance with the Peripheral Component Interconnect Express (PCIe) standard.

10. The memory system of claim 1, wherein the identifying the set of contiguous memory regions of the host system comprises identifying individual contiguous memory regions of the set of individual memory regions of the host system when the memory region description data is accessed from the host system.

11. The memory system according to claim 1, comprising: A buffer is used to store the integrated memory area description data generated by the memory system.

12. The memory system according to claim 11, comprising: A memory controller includes the processing device and the buffer.

13. A method for performing a memory operation, comprising: In response to a request from the host system to write requested data to the memory system: Aggregate memory region description data for the host system is generated by identifying a set of contiguous memory regions in a set of individual memory regions of the host system that provide the requested data for writing, the set of individual memory regions of the host system being described by the memory region description data specified by the request, the aggregate memory region description data for the host system comprising: a single descriptor for each contiguous memory region in the set of contiguous memory regions of the host system; and a single descriptor for each individual memory region of the set of individual memory regions of the host system, the each individual memory region being excluded from the set of contiguous memory regions of the host system; and The consolidated memory region description data for the host system is stored on a buffer of the memory system.

14. The method of claim 13, comprising, in response to the request: A write operation is performed on a memory device of the memory system based on the consolidated memory region description data for the host system stored on the buffer.

15. The method of claim 14, wherein performing the write operation on the memory device based on the consolidated memory region description data stored on the memory system for the host system comprises: determining, based on the consolidated memory region description data for the host system, a selected set of memory regions on the host system storing the requested data to be written to the memory device; retrieving the requested data from the selected set of memory areas on the host system; as well as A set of write commands for a set of logical block addresses are sent to the memory device, wherein the requested data is to be written to the set of logical block addresses according to the request.

16. The method of claim 15, wherein the requested data is retrieved from the set of selected memory regions on the local memory of the host system using a single transaction layer packet (TLP), the single transaction layer packet being in accordance with the Peripheral Component Interconnect Express (PCIe) standard.

17. A method according to claim 13, wherein the set of individual memory regions of the host system is described by host memory region description data specified by the request, the host memory region description data comprising a linked list of memory region descriptors, each memory region descriptor comprising a memory address corresponding to a memory address space on a local memory of the host system.

18. The method of claim 13, wherein the set of individual memory regions of the host system are described by host memory region description data specified by the request, wherein the host memory region description data comprises a scatter gather list (SGL) according to a Non-Volatile Memory Express (NVMe) protocol.

19. The method of claim 13, wherein each individual memory area of ​​the set of individual memory areas of the host system is defined by: memory addresses corresponding to individual memory address spaces on a local memory of the host system; and The memory size of the individual memory address space.

20. At least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processing device of a memory system, cause the processing device to perform operations comprising: In response to a request from a host system to write requested data to the memory system: Aggregate memory region description data is generated by identifying a set of contiguous memory regions in a set of individual memory regions of the host system that provide the requested data for writing, the aggregate memory region description data for the host system comprising: a single descriptor for each contiguous memory region of the set of contiguous memory regions of the host system; as well as a single descriptor for each individual memory region of the set of individual memory regions of the host system, the each individual memory region being excluded from the set of contiguous memory regions; as well as The consolidated memory region description data for the host system is stored on a buffer of the memory system.

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