Memory management method and memory controller

Abstract

A memory management method and a memory controller, the memory management method is suitable for a storage device configured with a rewritable nonvolatile memory module, and the memory management method comprises: obtaining respective effective counts of a plurality of virtual blocks, each virtual block comprising one or more physical blocks of the rewritable nonvolatile memory module; according to the effective count of each virtual block, obtaining a pre-recovery state of each virtual block; according to the pre-recovery state of each virtual block, determining an updating sequence of the effective data bitmaps of each virtual block; a target virtual block is selected to update a target valid data bitmap of the target virtual block using a logical-to-physical index list corresponding to the target virtual block and a logical-to-physical mapping table corresponding to the logical-to-physical index list according to an update order of the valid data bitmap for each virtual block. According to the method, the effective data bitmap is updated in advance, and the pre-recovery state mechanism is combined, so that the foreground garbage recovery efficiency is obviously improved, and the performance of the storage equipment is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a memory management method and a memory controller. Background Art

[0002] Non-volatile memory refers to computer memory in which the stored data does not disappear when the current is cut off. It has the advantages of non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] Common non-volatile memory is a memory configured with NAND Flash (such as a solid-state drive), which has the characteristics of high read and write speed and does not require a mechanical structure to access data.

[0004] In NAND flash storage devices, with the frequent writing and updating of data, a large amount of invalid data will be generated in the storage space. In order to optimize the utilization efficiency of storage space, storage devices need to organize valid data in storage blocks through the garbage collection (GC) mechanism. The garbage collection process can be divided into foreground garbage collection (Foreground GC) and background garbage collection (Background GC). Among them, foreground garbage collection is a garbage collection operation that is forced to be performed due to insufficient remaining storage space during the host data writing process. Since foreground garbage collection and host writing are carried out simultaneously, it is necessary to frequently search and update the mapping table during the garbage collection process, which not only consumes a lot of system resources, but also significantly affects the performance of the storage device. Therefore, how to improve the efficiency of foreground garbage collection is a technical problem that current storage devices urgently need to solve. Summary of the invention

[0005] In view of the above problems, the present disclosure provides a memory management method and a memory controller, which significantly improve the efficiency of foreground garbage collection by introducing a valid data bitmap and combining a pre-collection state mechanism.

[0006] One or more embodiments of the present disclosure provide a memory management method, which is applicable to a storage device equipped with a rewritable non-volatile memory module. The method includes: obtaining valid counts of each of a plurality of virtual blocks, wherein each virtual block includes one or more physical blocks of the rewritable non-volatile memory module; obtaining a pre-reclaim status of each virtual block according to the valid count of each virtual block; determining an update order of a valid data bitmap of each virtual block according to the pre-reclaim status of each virtual block; selecting a target virtual block from the plurality of virtual blocks according to the update order of the valid data bitmap of each virtual block, so as to update a target valid data bitmap of the target virtual block using a logical-to-physical index list corresponding to the target virtual block and a logical-to-physical mapping table corresponding to the logical-to-physical index list.

[0007] In one or more embodiments of the present disclosure, the method further includes: determining a garbage collection order of each virtual block according to the pre-collection status of each virtual block.

[0008] In one or more embodiments of the present disclosure, the step of obtaining the pre-recycling state of each virtual block includes: comparing the valid count of each virtual block with multiple thresholds of different sizes based on the valid count of each virtual block to determine the threshold interval in which the valid count of each virtual block is located; determining the pre-recycling state of each virtual block based on the threshold interval, if the valid count of a virtual block is greater than the maximum threshold among the multiple thresholds, determining the pre-recycling state of the virtual block to be the minimum pre-recycling state; if the valid count of a virtual block is less than the minimum threshold among the multiple thresholds, determining the pre-recycling state of the virtual block to be the maximum pre-recycling state; wherein the first virtual block corresponding to the minimum pre-recycling state is determined not to need to update the corresponding first valid data bitmap, and the second virtual block corresponding to the maximum pre-recycling state is determined to need to prioritize updating the corresponding second valid data bitmap.

[0009] In one or more embodiments of the present disclosure, the number of the multiple thresholds is 3, and the pre-recycling state includes a first pre-recycling state, a second pre-recycling state, a third pre-recycling state, and a fourth pre-recycling state, wherein the valid count corresponding to the first pre-recycling state is greater than the first threshold, the valid count corresponding to the second pre-recycling state is greater than the second threshold and less than the first threshold, the valid count corresponding to the third pre-recycling state is greater than the third threshold and less than the second threshold, and the valid count corresponding to the fourth pre-recycling state is less than the third threshold, wherein the first threshold is the maximum threshold, the third threshold is the minimum threshold, the first threshold is greater than the second threshold, and the second threshold is greater than the third threshold.

[0010] In one or more embodiments of the present disclosure, the logical-to-physical index list is used to record identification codes of one or more logical-to-physical mapping tables associated with the corresponding virtual block, wherein the physical address of the valid data stored in the corresponding virtual block will be recorded in one of the one or more logical-to-physical mapping tables.

[0011] In one or more embodiments of the present disclosure, the valid data bitmap includes a plurality of bits, each of which corresponds to a data area of ​​a preset size in the virtual block, and is used to indicate whether the data in the data area is valid data.

[0012] In one or more embodiments of the present disclosure, the method further includes: updating the target virtual block when the storage device is in an idle period, wherein the step of updating the target valid data bitmap of the target virtual block includes: determining one or more target logical-to-physical mapping tables associated with the target virtual block through the logical-to-physical index list of the target virtual block; checking whether the physical address of each data area of ​​the target virtual block exists in the one or more target logical-to-physical mapping tables; and updating the multiple bits of the target valid data bitmap according to the checking result of each data area, wherein the updated target valid data bitmap is stored in the rewritable non-volatile memory module.

[0013] In one or more embodiments of the present disclosure, the step of updating the multiple bits of the target valid data bitmap includes: if the first physical address of the first data area of ​​the target virtual block exists in one of the one or more target logical-to-physical mapping tables, setting the first bit corresponding to the first data area in the multiple bits of the target valid data bitmap to a first value; and if the second physical address of the second data area of ​​the target virtual block does not exist in any of the one or more target logical-to-physical mapping tables, setting the second bit corresponding to the second data area in the multiple bits of the target valid data bitmap to a second value.

[0014] In one or more embodiments of the present disclosure, the garbage collection order of each virtual block is determined including: when performing foreground garbage collection during a host write operation, preferentially selecting a virtual block with the largest pre-collection status as the garbage collection virtual block for garbage collection; and secondly selecting a virtual block with the second largest pre-collection status as the garbage collection virtual block for garbage collection.

[0015] In one or more embodiments of the present disclosure, the step of performing garbage collection includes: obtaining the valid data bitmap of the selected garbage collection virtual block; based on multiple first bits in the valid data bitmap of the selected virtual block, copying the first data of each of the multiple first data areas corresponding to the multiple first bits in the garbage collection virtual block to a data block; and performing an erase operation on the garbage collection virtual block.

[0016] One or more embodiments of the present disclosure provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module; a data management circuit for electrically connecting to a connection interface circuit of the storage device for receiving data and instructions from a host system via the connection interface circuit; a buffer memory for caching data; and a processor for electrically connecting to the memory interface control circuit, the data management circuit, and the buffer memory. Wherein, the processor is configured to: obtain the valid counts of each of a plurality of virtual blocks, wherein each of the virtual blocks includes one or more physical blocks of the rewritable non-volatile memory module; obtain the pre-reclaim status of each virtual block based on the valid count of each virtual block; determine the update order of the valid data bitmap of each virtual block based on the pre-reclaim status of each virtual block; and select a target virtual block from the plurality of virtual blocks based on the update order of the valid data bitmap of each virtual block to update the target valid data bitmap of the target virtual block using the logical-to-physical index list corresponding to the target virtual block and the logical-to-physical mapping table corresponding to the logical-to-physical index list.

[0017] Based on the above, the memory management method and memory controller provided by the embodiments of the present disclosure can significantly reduce the mapping table query overhead during foreground garbage collection by pre-establishing and updating the valid data bitmap; utilize the pre-recovery state mechanism to perform hierarchical management of virtual blocks, so that garbage collection can give priority to virtual blocks with a higher proportion of invalid data, thereby improving the recovery efficiency of storage space; and pre-update the valid data bitmap when the storage device is idle, thereby avoiding the real-time update overhead when performing garbage collection, and effectively improving the response speed of the storage device under high load conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0019] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention;

[0020] Figure 2 is a flow chart of a memory management method according to an embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of updating a logical-to-physical index list of written data according to an embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of updating a valid data bitmap according to an embodiment of the present invention;

[0023] Figure 5 is a schematic diagram of a pre-recycling state classification mechanism according to an embodiment of the present invention;

[0024] Figure 6 is a schematic diagram of a virtual block pre-reclaiming state table according to an embodiment of the present invention;

[0025] Figure 7 is a flowchart of a memory management method according to another embodiment of the present invention.

[0026] Description of Figure Numbers

[0027] 10: Host system

[0028] 20: Storage device

[0029] 211: First processor

[0030] 110: Second processor

[0031] 120: Host memory

[0032] 130: Data transmission interface circuit

[0033] 210: Memory Controller

[0034] 212: Data management circuit

[0035] 213: Memory interface control circuit

[0036] 214: Buffer memory

[0037] 220: Rewritable non-volatile memory module

[0038] 230: Connecting interface circuit

[0039] BM1: Valid data bitmap

[0040] IDX1: Logical to physical index list

[0041] L2P1, L2P2: Logical to physical mapping table

[0042] TB61: Virtual block pre-reclaim status table

[0043] VB1: Virtual Block

[0044] PG1, PG2, PG3: Data area

[0045] LBA1, LBA11, LBA12, LBA21, LBA22: logical addresses PBA1, PBA11, PBA12, PBA13, PBA21, PBA22: physical addresses C1, C2, C3: first threshold

[0046] CT5: Graphs

[0047] S210-S240: Process steps of the memory management method

[0048] S710-S740: Process steps of the memory management method

[0049] A31, A32, A41, A42, A43, A44, A45: First arrow DETAILED DESCRIPTION

[0050] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0051] Figure 1 FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present disclosure. Figure 1 , the host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In the present embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In the present embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0052] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0053] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0054] In this embodiment, the number of the data transmission interface circuit 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless manner. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device or a low power consumption Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.

[0055] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use the fast non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol to transmit data.

[0056] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0057] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present disclosure is not limited thereto, and the host memory 120 may also be other suitable memories.

[0058] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10 .

[0059] In more detail, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the storage device 20 operates, these control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in this embodiment, the control instructions / program codes can be further executed to implement the memory management method provided by the present disclosure. The control instructions / program codes corresponding to the memory management can be further implemented as a circuit unit in the form of hardware to implement the memory management method provided by the present disclosure.

[0060] It is worth mentioning that in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present disclosure is not limited thereto.

[0061] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0062] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation (also called a host write operation) is performed according to a write instruction (also called a host write instruction) from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (data can be read from one or more storage units in one or more physical units), and the read data is written to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211 .

[0063] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also called programming) operation, a read operation or an erase operation (also called an erasure operation) on the rewritable non-volatile memory module 220 .

[0064] In addition, the data to be written to the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will transmit a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, and a physical address may be included.

[0065] In the present disclosure, the memory controller 210 establishes a logical to physical address mapping table (Logical To Physical address mapping table, also called L2P mapping table) and a physical to logical address mapping table (Physical To Logical address mapping tablee, also called P2L mapping table) to record the mapping relationship between the logical address of the logical unit (e.g., logical block, logical page or logical column) configured for the rewritable non-volatile memory module 220 and the physical address (physical address) of the physical unit (e.g., physical erase unit / physical block, physical page, physical column). In other words, the memory controller 210 can search for the physical unit mapped by a logical unit (e.g., search for the physical page mapped by a logical page; search for the physical address mapped by a logical address) through the logical to physical address mapping table (also called logical to physical mapping table), and the memory controller 210 can search for the logical unit mapped by a physical unit (e.g., search for the logical page mapped by a physical page; search for the logical address mapped by a physical address) through the physical to logical address mapping table (also called physical to logical mapping table).

[0066] The memory controller 210 also establishes a data structure to record various mapping relationships, including: a virtual block mapping list that records the physical blocks corresponding to each virtual block, an L2P index list that records the L2P mapping table associated with each virtual block, and a virtual block pre-reclaim status table that records all virtual blocks.

[0067] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20 (e.g., various mapping tables, index tables, virtual block mapping lists, L2P index lists, virtual block pre-reclaim status tables, etc., system data related to the present disclosure), so that the processor 211 can quickly access the data, instructions or system data from the buffer memory 214.

[0068] In one embodiment, the memory controller 210 reserves a specific area in the buffer memory 214 for storing various types of mapping tables and index information. The memory controller 210 caches these data hierarchically according to access frequency and importance: frequently accessed mapping table information is stored in a fast access area, while less frequently used information is stored in a normal area. When the buffer memory 214 is insufficient, the memory controller 210 gives priority to writing less frequently used information back to the rewritable non-volatile memory module 220. In order to improve data reliability, the memory controller 210 also periodically synchronizes important mapping information in the buffer memory 214 to the rewritable non-volatile memory module 220, and records the synchronization timestamp so that it can be restored to the most recent valid state in the event of a system anomaly.

[0069] In one embodiment, the memory controller 210 establishes multiple data structures to record various mapping relationships. Specifically, the memory controller 210 establishes a virtual block mapping list (VB mapping list) to record the identification information of one or more physical blocks corresponding to each virtual block. In some embodiments, the virtual block mapping list may also include the location information of the physical block in the corresponding virtual block, the number of erasures of each physical block, and the valid count of each virtual block. The memory controller 210 also establishes an L2P index list (L2P index list) to record the identification codes of one or more logical to physical mapping tables associated with each virtual block. In addition, the memory controller 210 also establishes a virtual block pre-recycling state table (VBPre-GC state table) to record the pre-recycling status of all virtual blocks. In one embodiment, each entry in the virtual block pre-recycling state table includes: virtual block identification code, current valid count value and other information.

[0070] In another embodiment, the memory controller 210 stores these data structures in a preset area in the buffer memory, and periodically synchronizes their update status to the rewritable non-volatile memory module to ensure data persistence and consistency. In some embodiments, when the memory controller 210 is restarted, the latest status of these data structures can be restored from the rewritable non-volatile memory module to ensure that the system can continue the previous storage management operation.

[0071] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213 ) and is used to store data written by the host system 10 .

[0072] In the present embodiment, the rewritable non-volatile memory module 220 has a plurality of word lines, wherein each of the plurality of word lines is electrically connected to a plurality of storage cells, also known as columns (also known as physical columns). The plurality of columns on the same word line constitute a physical programming unit (also known as a physical page or physical page). Each physical page corresponds to a physical address for recording the location of the data stored in the physical page. In addition, the plurality of physical pages may constitute a physical block (also known as a physical erase unit or physical block). Each memory grain (chip) of the plurality of memory grains of the rewritable non-volatile memory module has a plurality of planes, and each plane has a plurality of physical blocks. It should be noted that the present disclosure is not limited to the size of each physical page and logical page.

[0073] The memory cell type (also known as storage mode) can be used to indicate the number of bits that each memory cell (also known as storage unit) can store. Common types include SLC (single-layer storage cell, each storage cell stores 1 bit), MLC (multi-layer storage cell, each storage cell stores 2 bits), TLC (triple-layer storage cell, each storage cell stores 3 bits), etc. Different storage modes vary in storage density, read / write speed, and durability, which affects the overall performance and characteristics of flash memory.

[0074] Figure 2 is a flowchart of a memory management method according to an embodiment of the present disclosure.

[0075] Reference Figure 2 In one embodiment, the memory controller 210 performs a memory management method. Specifically, in step S210 , the memory controller 210 obtains valid counts of each of a plurality of virtual blocks, wherein each virtual block includes one or more physical blocks of the rewritable non-volatile memory module 220 .

[0076] In one embodiment, the memory controller 210 may obtain the valid count of the virtual block in a variety of ways. When the storage device 20 performs a write operation, the memory controller 210 maintains a valid count counter for real-time counting of the number of valid data in each virtual block. Specifically, when performing a write operation, the memory controller 210 performs one of the following operations:

[0077] When the written data is new data, the memory controller 210 increases the valid count counter of the target virtual block by 1; when the written data overwrites the original data, the memory controller 210 first determines the source virtual block where the overwritten data is located according to the logical-to-physical mapping table, reduces the valid count counter of the source virtual block by 1, and then increases the valid count counter of the target virtual block by 1; when deleting data, the memory controller 210 reduces the valid count counter of the corresponding virtual block by 1.

[0078] In another embodiment, the memory controller 210 can periodically scan the logical-to-physical mapping table in the background, and update the valid count by counting the number of times each virtual block appears in the mapping table. Although this method has a large computational overhead, it can correct the counting error caused by system abnormalities.

[0079] In step S220 , the memory controller 210 obtains the pre-reclaim status of each virtual block according to the valid count of each virtual block.

[0080] In one embodiment, when obtaining the pre-reclaim status of each virtual block, the memory controller 210 first compares the effective count of each virtual block with a plurality of preset thresholds to determine the threshold interval in which the effective count of the virtual block is located. Specifically, the memory controller 210 presets a plurality of thresholds of different sizes, and arranges the thresholds in descending order to divide the plurality of threshold intervals.

[0081] The memory controller 210 then determines the pre-reclaim state of each virtual block according to the threshold interval in which the valid count of each virtual block is located. When the valid count of a certain virtual block is greater than the maximum threshold value among the multiple threshold values, the memory controller 210 sets the pre-reclaim state of the virtual block to the minimum pre-reclaim state value. Conversely, when the valid count of a certain virtual block is less than the minimum threshold value among the multiple threshold values, the memory controller 210 sets the pre-reclaim state of the virtual block to the maximum pre-reclaim state value.

[0082] For example, when a first virtual block is determined to have the minimum pre-reclaim state, the memory controller 210 marks the first virtual block as not needing to update its corresponding first valid data bitmap. This is because the virtual block with the minimum pre-reclaim state usually has a higher proportion of valid data and does not need to be garbage collected temporarily. On the contrary, when a second virtual block is determined to have the maximum pre-reclaim state, the memory controller 210 marks the second virtual block as needing to update its corresponding second valid data bitmap first, because such virtual blocks have a higher proportion of invalid data and are more likely to be selected as targets for garbage collection.

[0083] Figure 5 is a schematic diagram of a pre-recycling state classification mechanism according to an embodiment of the present invention.

[0084] Reference Figure 5 In one embodiment, the memory controller 210 implements a pre-reclaim state classification mechanism. As shown in the graph CT5, the coordinate axis represents the valid count (Valid Count), and the memory controller 210 divides the virtual block into different pre-reclaim states based on the valid count value of the virtual block.

[0085] In this embodiment, the memory controller 210 presets three thresholds, namely, a first threshold (C1), a second threshold (C2), and a third threshold (C3), and satisfies that C1 is greater than C2 and C2 is greater than C3. The memory controller 210 uses these three thresholds to divide the value range of the valid count into four intervals, and corresponds these four intervals to four different pre-reclaim states.

[0086] Specifically, when the memory controller 210 detects that the valid count of a virtual block is greater than the first threshold C1, the pre-reclaim state of the virtual block is set to "state 1" and marked as "no need to update". This means that the proportion of valid data in the virtual block is high, and it is temporarily unnecessary to update its valid data bitmap or perform garbage collection.

[0087] When the memory controller 210 detects that the valid count of a virtual block is less than the first threshold C1 but greater than the second threshold C2, the pre-reclaim state of the virtual block is set to "state 2" and marked as "low priority". This means that the virtual block can update its valid data bitmap when system resources are sufficient.

[0088] When the memory controller 210 detects that the valid count of a virtual block is less than the second threshold C2 but greater than the third threshold C3, the pre-reclaim state of the virtual block is set to "state 3" and marked as "second highest priority", which means that the virtual block has a relatively high update priority.

[0089] When the memory controller 210 detects that the valid count of a certain virtual block is less than the third threshold value C3, the pre-reclaim state of the virtual block is set to "state 4" and marked as "highest priority". This means that the proportion of invalid data in the virtual block is high, and its valid data bitmap needs to be updated first, and it may be selected for garbage collection operation first.

[0090] In one embodiment, in a specific implementation, the memory controller 210 may dynamically adjust the specific values ​​of these thresholds according to the performance requirements and workload characteristics of the storage device 20. For example, in a high performance requirement scenario, the values ​​of these thresholds may be increased so that more virtual blocks are classified into a high priority pre-recycling state, thereby performing garbage collection more actively; in a low power consumption scenario, the values ​​of these thresholds may be reduced to reduce unnecessary garbage collection operations.

[0091] In addition, although the above example uses three thresholds to manage the classification of pre-reclaim states, the present disclosure is not limited thereto. For example, the memory controller 210 may use more or fewer thresholds to manage the classification of pre-reclaim states.

[0092] Back to Figure 2Then, in step S230, the memory controller 210 determines the update order of the valid data bitmap of each virtual block according to the pre-reclaim status of each virtual block.

[0093] In one embodiment, the memory controller 210 gives priority to updating the valid data bitmap of the virtual block with a larger pre-reclaim status value. For example, when it is detected that the storage device 20 is in an idle state, the memory controller 210 first updates the valid data bitmap of the virtual block with the fourth pre-reclaim status, and then updates the valid data bitmap of the virtual block with the third pre-reclaim status and the second pre-reclaim status in sequence. For the virtual block with the first pre-reclaim status, since its valid data ratio is relatively high, its valid data bitmap may not be updated temporarily.

[0094] In step S240, the memory controller 210 selects a target virtual block from the multiple virtual blocks according to the update order of the valid data bitmap of each virtual block, so as to update the target valid data bitmap of the target virtual block by using the logical-to-physical index list corresponding to the target virtual block and the logical-to-physical mapping table corresponding to the logical-to-physical index list.

[0095] In one embodiment, specifically, the memory controller 210 first finds all logical-to-physical mapping tables associated with the target virtual block through the logical-to-physical index list of the target virtual block. Then, the memory controller 210 checks whether the physical address of each data area in the target virtual block still exists in these mapping tables. If the physical address of a data area still exists in the mapping table, the bit corresponding to the data area in the target valid data bitmap is set to the first value (eg, 1); if the physical address of a data area does not exist in any mapping table, the corresponding bit is set to the second value (eg, 0). After the update is completed, the memory controller 210 stores the target valid data bitmap in the rewritable non-volatile memory module 220.

[0096] In one embodiment, when predetermined conditions are met (for example, when the storage device 20 is idle), the memory controller 210 can pre-update the valid data bitmap of each virtual block to provide a quick data validity judgment basis for subsequent foreground garbage collection operations, thereby improving the efficiency of garbage collection.

[0097] Figure 3 4 is a schematic diagram of updating a logical-to-physical index list of written data according to an embodiment of the present invention.

[0098] Reference Figure 3 In one embodiment, when writing the write data TD to the virtual block VB1, the memory controller 210 updates the logical-to-physical index list.

[0099] In detail, as shown by arrow A31, when the virtual block VB1 of the storage device 20 receives the write data, the data is assigned a physical address "PBA1" and stored in the virtual block VB1. At the same time, the memory controller 210 needs to establish a mapping relationship from the logical address "LBA1" of the data to the physical address "PBA1" in the logical-to-physical mapping table L2P1. Specifically, the memory controller 210 creates a new table entry in the logical-to-physical mapping table L2P1, which contains a logical address field and a physical address field, recording "LBA1" and "PBA1" respectively.

[0100] Next, as shown by arrow A32, the memory controller 210 also needs to update the logical-to-physical index list IDX1. The logical-to-physical index list IDX1 is used to record the identification codes of one or more logical-to-physical mapping tables associated with the virtual block. In this embodiment, the memory controller 210 records the identification code "L2P1" of the logical-to-physical mapping table L2P1 in the index list IDX1, indicating that the physical address information of the valid data stored in the virtual block VB1 can be found in the mapping table L2P1. It also means that the valid data of the virtual block VB1 will be associated with the logical-to-physical mapping table L2P1 recorded in the logical-to-physical index list IDX1.

[0101] In one embodiment, the memory controller 210 uses a hierarchical index structure when establishing a logical-to-physical index list. The first layer is a virtual block identifier, which is used to quickly locate the target virtual block; the second layer is a list of identifiers of all L2P mapping tables related to the virtual block. This hierarchical structure enables the memory controller 210 to quickly find all mapping information related to a specific virtual block.

[0102] The memory controller 210 updates the L2P index list by the following steps: When writing new data, the memory controller 210 first checks whether the target virtual block of the data already has a corresponding entry in the index list. If not, a new index entry is created; if it already exists, it checks whether the L2P mapping table corresponding to the new data is already in the mapping table list of the virtual block. For new mapping tables that are not in the list, the memory controller 210 adds its identifier to the list.

[0103] When the data mapping relationship of the same virtual block is scattered in multiple logical-to-physical mapping tables, the memory controller 210 will record the identification codes of all related mapping tables in the index list corresponding to the virtual block. This design enables the memory controller 210 to quickly locate and load all mapping tables that need to be queried (loaded into the cache memory 214) when performing garbage collection, thereby improving the efficiency of data validity judgment.

[0104] By maintaining this index list mechanism, the memory controller 210 can quickly determine which logical-to-physical mapping tables need to be checked in the subsequent garbage collection process, thereby improving the update efficiency of the valid data bitmap. When the memory controller 210 needs to update the valid data bitmap of a virtual block, it only needs to find the index list corresponding to the virtual block to obtain the identification codes of all mapping tables that need to be checked, avoiding the overhead of traversing all mapping tables, thereby speeding up the update of the valid data bitmap.

[0105] Figure 4 is a schematic diagram of updating a valid data bitmap according to an embodiment of the present invention.

[0106] Reference Figure 4 In one embodiment, the memory controller 210 establishes and maintains a valid data bitmap BM1, which includes multiple bits. Each bit corresponds to a data area of ​​a preset size (eg, PG1, PG2, PG3) in the virtual block VB1, which is used to indicate whether the data in the data area is valid data. Specifically, when the data stored in a data area is still valid (valid data), the memory controller 210 sets the bit corresponding to the area to the first value (eg, "1"); when the data stored in a data area is invalid (not valid data), the memory controller 210 sets the bit corresponding to the area to the second value (eg, "0").

[0107] In one embodiment, when the storage device 20 is in an idle period (for example, when no host command needs to be processed), the memory controller 210 performs a valid data bitmap update operation of the target virtual block VB1. First, the memory controller 210 accesses the logical-to-physical index list IDX1 corresponding to the target virtual block VB1, which records the identifiers of all logical-to-physical mapping tables associated with the target virtual block VB1, including "L2P1" and "L2P2".

[0108] The memory controller 210 accesses the logical-to-physical index list IDX1, which records the identifiers of the logical-to-physical mapping tables associated with the virtual block VB1, including "L2P1" and "L2P2". The memory controller 210 thus determines that it needs to load and check the mapping tables L2P1 and L2P2 to verify the validity of the data in the virtual block VB1.

[0109] After loading the mapping tables L2P1 and L2P2 into the cache memory 214 , the memory controller 210 checks whether the physical address of each storage area of ​​the virtual block exists in the physical addresses recorded in the mapping tables L2P1 and L2P2 .

[0110] The memory controller 210 loads the relevant logical to physical mapping tables L2P1 and L2P2 according to the identifier in the index list IDX1. As shown by arrow A41, the memory controller 210 checks that the first physical address "PBA11" of the first data area PG1 exists in the mapping table L2P1 and is associated with the logical address "LBA11". Therefore, the memory controller 210 determines that the first physical address "PBA11" of the first data area PG1 stores valid data. Then, as shown by arrow A42, the memory controller 210 sets the first bit corresponding to the first data area in the valid data bitmap BM1 to "1" (also called the first value).

[0111] As indicated by arrow A43, the memory controller 210 detects that the second physical address "PBA12" of the second data region PG2 does not exist in any logical-to-physical mapping table (indicated by an "×" mark in the figure). This indicates that the data stored at the physical address has expired (e.g., the physical address corresponds to invalid data), so the memory controller 210 sets the second bit corresponding to the second data region in the valid data bitmap BM1 to "0" (also called the second value).

[0112] For another example, as shown by arrows A44 and A45, for the physical address "PBA13" of the third data region PG3, the memory controller 210 finds its corresponding valid mapping relationship in the mapping table L2P2, where the physical address is associated with the logical address "LBA22". This indicates that the data is still valid, so the memory controller 210 sets the bit corresponding to the third data region in the valid data bitmap BM1 to "1".

[0113] By analogy, the memory controller 210 can update the valid data bitmap BM1 corresponding to the virtual block VB1. In this way, the memory controller 210 completes the update of the valid data bitmap BM1 of the virtual block VB1. The updated bitmap accurately reflects the validity status of each data area in the virtual block VB1, providing a reliable reference for subsequent garbage collection operations.

[0114] After completing the validity check of all data areas, the memory controller 210 stores the updated target valid data bitmap BM1 in the rewritable non-volatile memory module 220 for subsequent garbage collection operations. In this way, the storage device 20 can complete the update of the valid data bitmap in advance during idle time, thereby reducing the overhead during garbage collection operations.

[0115] In one embodiment, in actual implementation, the memory controller 210 can use a batch processing method to simultaneously check the validity of multiple physical addresses and update multiple bits in the valid data bitmap at one time, thereby improving the update efficiency. In addition, the memory controller 210 can also maintain a checksum during the update process to verify the integrity of the updated valid data bitmap.

[0116] Figure 6 4 is a schematic diagram of a virtual block pre-reclaiming status table according to an embodiment of the present invention.

[0117] Reference Figure 6 In one embodiment, the memory controller 210 maintains a virtual block pre-reclaiming status table TB61 for recording status information of multiple virtual blocks and guiding garbage collection operations.

[0118] The virtual block pre-recycling state table TB61 includes multiple fields: a virtual block number / identification code field, which is used to uniquely identify each virtual block; a valid count field, which records the amount of valid data in each virtual block; a pre-recycling state field, which indicates the pre-recycling state value of the virtual block; and a "need to update" field, which is used to mark whether the valid data bitmap of the virtual block needs to be updated. In this embodiment, a pre-recycling state of 1 will be determined as the total amount of valid data exceeds a certain value, and the corresponding valid data bitmap does not need to be updated, thereby reducing resource overhead.

[0119] In this embodiment, the memory controller 210 presets three thresholds: a first threshold C1 (45000), a second threshold C2 (35000) and a third threshold C3 (20000). According to the comparison results between the effective count value and these thresholds, the memory controller 210 assigns a corresponding pre-reclaim state to each virtual block. For example, Figure 6 The effective count of the virtual block numbered "0" in C1 is 65536, which is greater than C1, so its pre-reclaim state is set to "1"; the effective count of the virtual block numbered "1" is 16000, which is less than C3, so its pre-reclaim state is set to "4", and so on.

[0120] The memory controller 210 determines whether it is necessary to update the valid data bitmap of the virtual block according to the pre-reclaim status value. Specifically, when the pre-reclaim status value is "1", due to the high proportion of valid data, it is marked as "no", indicating that it does not need to be updated temporarily; when the pre-reclaim status value is greater than "1", it is marked as "yes", indicating that it is necessary to update its valid data bitmap when the storage device 20 is idle.

[0121] When foreground garbage collection needs to be performed during a host write operation, the memory controller 210 preferentially selects a virtual block with a maximum pre-collection status value (ie, a status value of "4") as a garbage collection target. Figure 6As shown, the pre-reclaim status of virtual block "1" and virtual block "5" is "4", wherein virtual block "1" has a smaller valid count (16000), and is therefore selected first. If these virtual blocks have been processed, the memory controller 210 will select a virtual block with the next largest pre-reclaim status value (i.e., the status value is "3"), such as virtual block "6" and virtual block "7" in the figure, and so on. In other words, the memory controller 210 can determine the garbage collection order of each virtual block according to the pre-reclaim status of each virtual block.

[0122] by Figure 6 For example, when it is necessary to perform foreground garbage collection, the memory controller 210 first selects virtual block "1" (valid count 16000, pre-recovery state "4") as the garbage collection virtual block; then selects virtual block "5" (valid count 15000, pre-recovery state "4"); and then selects virtual block "6" and virtual block "7" (pre-recovery state "3"). This selection strategy based on the pre-recovery state ensures that the garbage collection operation can give priority to processing virtual blocks with a higher proportion of invalid data, thereby improving the recovery efficiency of the storage space.

[0123] Through this pre-reclaim status table mechanism, the memory controller 210 can quickly identify and prioritize the most suitable virtual blocks for recycling during foreground garbage collection, which significantly improves the efficiency of garbage collection.

[0124] Figure 7 is a flowchart of a memory management method according to another embodiment of the present invention.

[0125] Reference Figure 7 In one embodiment, the storage device 20 performs a memory management method combined with foreground garbage collection.

[0126] In step S710, the memory controller 210 obtains a write instruction sent by the host system 10. After obtaining the write instruction, the memory controller 210 needs to ensure that the storage device 20 has enough available space to complete the data write operation.

[0127] In step S720, in response to determining that a foreground garbage collection operation needs to be performed, the memory controller 210 selects a target virtual block according to the pre-collection state of each virtual block, and obtains a target valid data bitmap corresponding to the target virtual block. Specifically, the memory controller 210 preferentially selects a virtual block with the largest pre-collection state value as a garbage collection virtual block. If there are multiple virtual blocks with the same pre-collection state value, the processing order is further determined according to the size of the valid count.

[0128] In one embodiment, the memory controller 210 may determine whether to perform a foreground garbage collection operation in a variety of ways.

[0129] In a preferred embodiment, the memory controller 210 determines whether to perform foreground garbage collection by monitoring the available space of the storage device 20. Specifically, the memory controller 210 presets a free space threshold, and triggers a foreground garbage collection operation when it is detected that the available space of the storage device 20 is less than the preset threshold. The free space threshold can be set according to the percentage of the total capacity of the storage device 20, for example, garbage collection is triggered when the available space is less than 10% of the total capacity.

[0130] In another embodiment, the memory controller 210 determines whether to perform foreground garbage collection based on the comparison result of the data amount of the write request and the current available space. When the memory controller 210 receives a write request from the host system 10, the amount of data to be written is calculated and compared with the current available space. If the current available space is not enough to accommodate the data to be written, the foreground garbage collection operation is started.

[0131] In another embodiment, the memory controller 210 determines whether garbage collection needs to be performed by evaluating the state distribution of virtual blocks. Specifically, the memory controller 210 counts the number of virtual blocks whose pre-collection state is the fourth pre-collection state (maximum state value). When the number exceeds a preset threshold, it indicates that there are more blocks that need to be collected, and the foreground garbage collection operation is triggered.

[0132] In another embodiment, the memory controller 210 determines whether garbage collection needs to be performed by monitoring the write performance of the storage device 20. When the write speed is detected to be lower than the expected performance threshold, it may indicate that the storage space is severely fragmented, and a foreground garbage collection operation is triggered to organize the storage space.

[0133] The memory controller 210 may also adjust the garbage collection strategy according to different triggering conditions, for example, in an emergency, giving priority to reclaiming virtual blocks with larger pre-reclaim status values ​​to quickly release storage space.

[0134] Next, the memory controller 210 divides the processing into two branches that are executed in parallel:

[0135] In step S730 , the memory controller 210 executes the host write instruction to write the data sent by the host system 10 into the valid storage space in the storage device 20 .

[0136] At the same time, in step S740, the memory controller 210 performs a foreground garbage collection operation. Specifically, the memory controller 210 first obtains a valid data bitmap of the selected garbage collection virtual block. Then, the memory controller 210 scans all bits in the valid data bitmap and identifies a plurality of first bits having a first value (eg, "1"), which indicates that valid data is stored in the corresponding data area.

[0137] The memory controller 210 locates a plurality of first data regions corresponding to the first bits in the garbage collection virtual block according to the identified plurality of first bits. Subsequently, the memory controller 210 sequentially copies the valid data in the first data regions to the pre-allocated data blocks.

[0138] During the data copying process, the memory controller 210 may simultaneously update the corresponding logical-to-physical mapping table and record the new physical addresses of the valid data into the mapping table.

[0139] After completing the copying of valid data, the memory controller 210 performs an erase operation on the garbage collection virtual block to restore it to a usable state. At this time, all storage units in the virtual block are reset to preset values ​​and can be used for subsequent data write operations. The corresponding virtual block mapping table, logical to physical index list, and virtual block pre-recovery status table will be updated / reset accordingly.

[0140] In this way, the memory controller 210 can efficiently complete the garbage collection operation while executing the host write instruction, effectively improving the overall performance of the storage device 20. In particular, when the storage device 20 is close to being full, this garbage collection method based on the pre-collection state can quickly release storage space and ensure the smooth progress of the host write operation.

[0141] Finally, this embodiment also provides a computer program product, including a computer readable code, or a non-volatile computer readable storage medium carrying the computer readable code. When the computer readable code runs in the processor of the host system, the processor executes the process steps of the above-mentioned memory management method and realizes the function of the memory controller. The computer program product can be implemented in hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium. In another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0142] Based on the above, the memory management method and memory controller provided by the embodiments of the present disclosure can achieve the following technical effects:

[0143] First, the present disclosure adopts a virtual block pre-recycling state classification mechanism, which divides virtual blocks into different pre-recycling states according to valid counts, and pre-updates the valid data bitmap of high-priority virtual blocks when the storage device is idle. This pre-processing mechanism significantly reduces the mapping table query overhead during foreground garbage collection and improves garbage collection efficiency.

[0144] Second, the present disclosure designs a multi-level garbage collection triggering mechanism, which realizes precise control of garbage collection operations by monitoring multiple dimensions of indicators such as available space, write load, block status distribution, etc. of the storage device. This mechanism can start foreground garbage collection at the appropriate time, which not only ensures the timely release of storage space, but also avoids unnecessary garbage collection operations.

[0145] Third, the present disclosure establishes a fast index relationship between a virtual block and its associated logical-to-physical mapping table through a logical-to-physical index list mechanism. This design significantly reduces the overhead of searching the mapping table when updating the valid data bitmap, and improves the efficiency of bitmap updates.

[0146] Fourth, when performing foreground garbage collection, the present disclosure preferentially selects virtual blocks with the largest pre-collection status value for processing, and quickly identifies and copies valid data based on the valid data bitmap. This method minimizes the amount of data migration and improves the speed of garbage collection.

[0147] In summary, the memory management method provided by the present disclosure significantly improves the performance of the storage device under high load conditions, and is particularly suitable for application scenarios that require frequent data writing. By pre-updating the valid data bitmap and combining the pre-recycling state classification mechanism, this solution effectively solves the problem of low efficiency of traditional foreground garbage collection and improves the overall operating efficiency of the storage device.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A memory management method, applicable to a storage device equipped with a rewritable non-volatile memory module, characterized in that: The method comprises: Obtaining a valid count of each of a plurality of virtual blocks, wherein each virtual block includes one or more physical blocks of the rewritable non-volatile memory module; According to the valid count of each virtual block, obtaining the pre-recycling state of each virtual block; Determining an update order of a valid data bitmap of each virtual block according to the pre-reclaim status of each virtual block; and According to the update order of the valid data bitmap of each virtual block, a target virtual block is selected from the multiple virtual blocks to update the target valid data bitmap of the target virtual block using the logical-to-physical index list corresponding to the target virtual block and the logical-to-physical mapping table corresponding to the logical-to-physical index list.

2. The memory management method according to claim 1, characterized in that: Also includes: The garbage collection order of each virtual block is determined according to the pre-collection state of each virtual block.

3. The memory management method according to claim 1, characterized in that: The step of obtaining the pre-reclaim status of each virtual block includes: According to the valid count of each virtual block, compare the valid count of each virtual block with a plurality of thresholds of different sizes to determine a threshold interval in which the valid count of each virtual block is located; Determining the pre-reclaim state of each virtual block according to the threshold interval of each virtual block, If the valid count of a virtual block is greater than a maximum threshold value among the multiple threshold values, determining the pre-recycling state of the virtual block to be the minimum pre-recycling state; If the valid count of a virtual block is less than a minimum threshold value among the multiple threshold values, determining the pre-recycling state of the virtual block to be the maximum pre-recycling state; The first virtual block corresponding to the smallest pre-recycling state is determined not to need to update the corresponding first valid data bitmap, and the second virtual block corresponding to the largest pre-recycling state is determined to need to prioritize updating the corresponding second valid data bitmap.

4. The memory management method according to claim 3, characterized in that: The number of the multiple thresholds is 3, the pre-recycling state includes a first pre-recycling state, a second pre-recycling state, a third pre-recycling state and a fourth pre-recycling state, The valid count corresponding to the first pre-recycling state is greater than a first threshold value, The valid count corresponding to the second pre-recycling state is greater than the second threshold and less than the first threshold, The valid count corresponding to the third pre-recycling state is greater than the third threshold and less than the second threshold, The valid count corresponding to the fourth pre-recycling state is less than the third threshold, wherein the first threshold is the maximum threshold, the third threshold is the minimum threshold, the first threshold is greater than the second threshold, and the second threshold is greater than the third threshold.

5. The memory management method according to claim 1, characterized in that: The logical-to-physical index list is used to record identification codes of one or more logical-to-physical mapping tables associated with the corresponding virtual block, wherein the physical address of valid data stored in the corresponding virtual block is recorded in one of the one or more logical-to-physical mapping tables.

6. The memory management method according to claim 1, characterized in that: The valid data bitmap includes a plurality of bits, each of which corresponds to a data region of a preset size in the virtual block and is used to indicate whether the data in the data region is valid data.

7. The memory management method according to claim 6, characterized in that: The method further comprises: updating the target virtual block when the storage device is idle, The step of updating the target valid data bitmap of the target virtual block comprises: Determining one or more target logical-to-physical mapping tables associated with the target virtual block through the logical-to-physical index list of the target virtual block; checking whether a physical address of each data region of the target virtual block exists in the one or more target logical-to-physical mapping tables; and The plurality of bits of the target valid data bitmap are updated according to the checking result of each data region, wherein the updated target valid data bitmap is stored in the rewritable non-volatile memory module.

8. The memory management method according to claim 7, characterized in that: The step of updating the plurality of bits of the target valid data bitmap comprises: If a first physical address of a first data region of the target virtual block exists in one of the one or more target logical-to-physical mapping tables, setting a first bit of the plurality of bits of the target valid data bitmap corresponding to the first data region to a first value; and If the second physical address of the second data area of ​​the target virtual block does not exist in any of the one or more target logical-to-physical mapping tables, the second bit corresponding to the second data area among the multiple bits of the target valid data bitmap is set to a second value.

9. The memory management method according to claim 2, characterized in that: Determining the garbage collection order of each virtual block includes: When performing foreground garbage collection during a host write operation, preferentially selecting a virtual block with the largest pre-collection state as a garbage collection virtual block for garbage collection; and Secondly, a virtual block with the next largest pre-recycling state is selected as the garbage collection virtual block for garbage collection.

10. The memory management method according to claim 9, characterized in that: The steps to perform garbage collection include: Obtaining the valid data bitmap of the selected garbage collection virtual block; According to the plurality of first bits in the valid data bitmap of the selected virtual block, copying first data of each of the plurality of first data areas corresponding to the plurality of first bits in the garbage collection virtual block to the data block; and An erase operation is performed on the garbage collection virtual block.

11. A memory controller for controlling a storage device equipped with a rewritable non-volatile memory module, characterized in that: The memory controller comprises: A memory interface control circuit, used for electrically connecting to the rewritable non-volatile memory module; a data management circuit electrically connected to the connection interface circuit of the storage device, for receiving data and instructions from a host system via the connection interface circuit; A buffer memory for caching data; and a processor electrically connected to the memory interface control circuit, the data management circuit and the buffer memory, wherein the processor is configured to: Obtaining a valid count of each of a plurality of virtual blocks, wherein each of the virtual blocks includes one or more physical blocks of the rewritable non-volatile memory module; According to the valid count of each virtual block, obtaining the pre-recycling state of each virtual block; Determining an update order of a valid data bitmap of each virtual block according to the pre-reclaim status of each virtual block; and According to the update order of the valid data bitmap of each virtual block, a target virtual block is selected from the multiple virtual blocks to update the target valid data bitmap of the target virtual block using the logical-to-physical index list corresponding to the target virtual block and the logical-to-physical mapping table corresponding to the logical-to-physical index list.

12. The memory controller according to claim 11, wherein: The processor is also configured to: The garbage collection order of each virtual block is determined according to the pre-collection state of each virtual block.

13. The memory controller according to claim 11, wherein: When obtaining the pre-reclamation status of each virtual block, the processor is configured to: According to the valid count of each virtual block, compare the valid count of each virtual block with a plurality of thresholds of different sizes to determine a threshold interval in which the valid count of each virtual block is located; Determining the pre-reclaim state of each virtual block according to the threshold interval of each virtual block, If the valid count of a virtual block is greater than a maximum threshold value among the multiple threshold values, determining the pre-recycling state of the virtual block to be the minimum pre-recycling state; If the valid count of a virtual block is less than a minimum threshold value among the multiple threshold values, determining the pre-recycling state of the virtual block to be the maximum pre-recycling state; The first virtual block corresponding to the smallest pre-recycling state is determined not to need to update the corresponding first valid data bitmap, and the second virtual block corresponding to the largest pre-recycling state is determined to need to prioritize updating the corresponding second valid data bitmap.

14. The memory controller according to claim 13, wherein: The number of the multiple thresholds is 3, the pre-recycling state includes a first pre-recycling state, a second pre-recycling state, a third pre-recycling state and a fourth pre-recycling state, The valid count corresponding to the first pre-recycling state is greater than a first threshold value, The valid count corresponding to the second pre-recycling state is greater than the second threshold and less than the first threshold, The valid count corresponding to the third pre-recycling state is greater than the third threshold and less than the second threshold, The valid count corresponding to the fourth pre-recycling state is less than the third threshold, wherein the first threshold is the maximum threshold, the third threshold is the minimum threshold, the first threshold is greater than the second threshold, and the second threshold is greater than the third threshold.

15. The memory controller according to claim 11, wherein: The logical-to-physical index list is used to record identification codes of one or more logical-to-physical mapping tables associated with the corresponding virtual block, wherein the physical address of valid data stored in the corresponding virtual block is recorded in one of the one or more logical-to-physical mapping tables.

16. The memory controller according to claim 11, wherein: The valid data bitmap includes a plurality of bits, each of which corresponds to a data region of a preset size in the virtual block and is used to indicate whether the data in the data region is valid data.

17. The memory controller according to claim 16, wherein: The processor is also configured to updating the target virtual block when the storage device is idle, The step of updating the target valid data bitmap of the target virtual block comprises: Determining one or more target logical-to-physical mapping tables associated with the target virtual block through the logical-to-physical index list of the target virtual block; checking whether a physical address of each data region of the target virtual block exists in the one or more target logical-to-physical mapping tables; and The plurality of bits of the target valid data bitmap are updated according to the checking result of each data region, wherein the updated target valid data bitmap is stored in the rewritable non-volatile memory module.

18. The memory controller according to claim 17, wherein: When updating the plurality of bits of the target valid data bitmap, the processor is configured to: If a first physical address of a first data region of the target virtual block exists in one of the one or more target logical-to-physical mapping tables, setting a first bit of the plurality of bits of the target valid data bitmap corresponding to the first data region to a first value; and If the second physical address of the second data area of ​​the target virtual block does not exist in any of the one or more target logical-to-physical mapping tables, the second bit corresponding to the second data area among the multiple bits of the target valid data bitmap is set to a second value.

19. The memory controller according to claim 12, wherein: In determining the garbage collection order of each virtual block, the processor is configured to: When performing foreground garbage collection during a host write operation, preferentially selecting a virtual block with the largest pre-collection state as a garbage collection virtual block for garbage collection; and Secondly, a virtual block with the next largest pre-recycling state is selected as the garbage collection virtual block for garbage collection.

20. The memory controller according to claim 19, wherein: When performing garbage collection, the processor is configured to: Obtaining the valid data bitmap of the selected garbage collection virtual block; According to the plurality of first bits in the valid data bitmap of the selected virtual block, copying first data of each of the plurality of first data areas corresponding to the plurality of first bits in the garbage collection virtual block to the data block; as well as An erase operation is performed on the garbage collection virtual block.

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