Memory management method and memory controller

Abstract

A memory management method and a memory controller, the memory management method is suitable for a storage device configured with a rewritable non-volatile memory module, comprising: obtaining the valid count of each virtual block, each virtual block comprising one or more physical blocks of the rewritable non-volatile memory module; obtaining the pre-recycle state of each virtual block according to the valid count of each virtual block; determining the update order of the valid data bitmap of each virtual block according to the pre-recycle state of each virtual block; and selecting a target virtual block according to the update order of the valid data bitmap of each virtual block, and updating the target valid data bitmap of the target virtual block by using the logical-to-physical index list corresponding to the target virtual block and the logical-to-physical mapping table corresponding to the logical-to-physical index list. The method significantly improves the efficiency of foreground garbage collection and improves the performance of the storage device by pre-updating the valid data bitmap and combining the pre-recycle state mechanism.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of memory, in particular to a memory management method and a memory controller. BACKGROUND

[0002] Non-volatile memory refers to computer storage that does not lose stored data when the current is cut off, has the advantages of data non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] The common non-volatile memory is a memory (such as a solid state disk) configured with NAND flash, which has the characteristics of high read-write speed and does not require a mechanical structure for data access.

[0004] In a NAND flash storage device, a large amount of invalid data will be generated in the storage space as the data is frequently written and updated. In order to optimize the utilization efficiency of the storage space, the storage device needs to arrange the valid data in the storage block through the garbage collection (GC) mechanism. The garbage collection process can be divided into foreground garbage collection and background garbage collection. Among them, the foreground garbage collection is a garbage collection operation forced to be performed due to insufficient remaining storage space during the host data writing process. Since the foreground garbage collection is performed simultaneously with the host writing, it is necessary to frequently search and update the mapping table during the garbage collection process, which not only consumes a large amount of system resources, but also significantly affects the performance of the storage device. Therefore, how to improve the efficiency of foreground garbage collection is a technical problem that needs to be solved for current storage devices. SUMMARY

[0005] In view of the above problems, the present disclosure provides a memory management method and a memory controller, which significantly improves the efficiency of foreground garbage collection by introducing an effective data bitmap and combining a pre-recycling state mechanism.

[0006] One or more embodiments of this disclosure provide a memory management method applicable to a storage device configured with a rewritable non-volatile memory module. The method includes: obtaining valid counts for a plurality of virtual blocks, wherein each virtual block includes one or more physical blocks of the rewritable non-volatile memory module; obtaining a pre-reclaim status for each virtual block based on the valid counts; determining an update order for the valid data bitmap of each virtual block based on the pre-reclaim status; and selecting a target virtual block from the plurality of virtual blocks based on the update order of the valid data bitmap, to update the target valid data bitmap of the target virtual block using a logical-to-physical index list corresponding to the target virtual block and a logical-to-physical mapping table corresponding to the logical-to-physical index list.

[0007] In one or more embodiments of this disclosure, the method further includes: determining the garbage collection order of each virtual block based on the pre-collection state of each virtual block.

[0008] In one or more embodiments of this disclosure, the step of obtaining the pre-reclaim state of each virtual block includes: comparing the effective count of each virtual block with multiple thresholds of different sizes based on the effective count of each virtual block to determine the threshold interval in which the effective count of each virtual block is located; determining the pre-reclaim state of each virtual block based on the threshold interval of each virtual block; if the effective count of a virtual block is greater than the largest threshold among the multiple thresholds, determining the pre-reclaim state of the virtual block as the minimum pre-reclaim state; if the effective count of a virtual block is less than the smallest threshold among the multiple thresholds, determining the pre-reclaim state of the virtual block as the maximum pre-reclaim state; wherein the first virtual block corresponding to the minimum pre-reclaim state is determined not to need to update the corresponding first valid data bitmap, and the second virtual block corresponding to the maximum pre-reclaim state is determined to need to prioritize updating the corresponding second valid data bitmap.

[0009] In one or more embodiments of this disclosure, the number of the plurality of thresholds is 3, the pre-recovery state includes a first pre-recovery state, a second pre-recovery state, a third pre-recovery state, and a fourth pre-recovery state, wherein the effective count corresponding to the first pre-recovery state is greater than the first threshold, the effective count corresponding to the second pre-recovery state is greater than the second threshold and less than the first threshold, the effective count corresponding to the third pre-recovery state is greater than the third threshold and less than the second threshold, and the effective count corresponding to the fourth pre-recovery state is less than the third threshold, wherein the first threshold is the maximum threshold, the third threshold is the minimum threshold, the first threshold is greater than the second threshold, and the second threshold is greater than the third threshold.

[0010] In one or more embodiments of this disclosure, the logical-to-physical index list is used to record the identification codes of one or more logical-to-physical mapping tables associated with the corresponding virtual block, wherein the physical address of the valid data stored in the corresponding virtual block is recorded in one of the one or more logical-to-physical mapping tables.

[0011] In one or more embodiments of this disclosure, the valid data bitmap includes a plurality of bits, each bit corresponding to a data area of ​​a preset size in the virtual block, used to indicate whether the data in the data area is valid data.

[0012] In one or more embodiments of this disclosure, the method further includes: updating the target virtual block during a period when the storage device is idle, wherein the step of updating the target valid data bitmap of the target virtual block includes: determining one or more target logical-to-physical mapping tables associated with the target virtual block through the logical-to-physical index list of the target virtual block; checking whether the physical address of each data region of the target virtual block exists in the one or more target logical-to-physical mapping tables; and updating the plurality of bits of the target valid data bitmap according to the check result of each data region, wherein the updated target valid data bitmap is stored in the rewritable non-volatile memory module.

[0013] In one or more embodiments of this disclosure, the step of updating the plurality of bits of the target valid data bitmap includes: if the first physical address of the first data region of the target virtual block exists in one of the one or more target logical-to-physical mapping tables, setting the first bit of the plurality of bits of the target valid data bitmap corresponding to the first data region to a first value; and if the second physical address of the second data region of the target virtual block does not exist in any of the one or more target logical-to-physical mapping tables, setting the second bit of the plurality of bits of the target valid data bitmap corresponding to the second data region to a second value.

[0014] In one or more embodiments of this disclosure, determining the garbage collection order for each virtual block includes: when performing foreground garbage collection during a host write operation, preferentially selecting the virtual block with the largest pre-collection state as the garbage collection virtual block for garbage collection; and subsequently selecting the virtual block with the second largest pre-collection state as the garbage collection virtual block for garbage collection.

[0015] In one or more embodiments of this disclosure, the step of performing garbage collection includes: obtaining the valid data bitmap of the selected garbage collection virtual block; copying first data of each of a plurality of first data regions corresponding to the plurality of first bits in the valid data bitmap of the selected virtual block to a data block according to a plurality of first bits; and performing an erase operation on the garbage collection virtual block.

[0016] One or more embodiments of this disclosure provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit electrically connected to the rewritable non-volatile memory module; a data management circuit electrically connected to a connection interface circuit of the storage device for receiving data and instructions from a host system via the connection interface circuit; a buffer memory for buffering data; and a processor electrically connected to the memory interface control circuit, the data management circuit, and the buffer memory. The processor is configured to: acquire valid counts of a plurality of virtual blocks, each virtual block comprising one or more physical blocks of the rewritable nonvolatile memory module; acquire a pre-reclaim status of each virtual block based on the valid count of each virtual block; determine an update order of the valid data bitmap of each virtual block based on the pre-reclaim status of each virtual block; and select a target virtual block from the plurality of virtual blocks based on the update order of the valid data bitmap of each virtual block, so as to update the target valid data bitmap of the target virtual block using a logical-to-physical index list corresponding to the target virtual block and a logical-to-physical mapping table corresponding to the logical-to-physical index list.

[0017] Based on the above, the memory management method and memory controller provided in this disclosure can significantly reduce the mapping table lookup overhead during foreground garbage collection by pre-establishing and updating the valid data bitmap; by using a pre-collection state mechanism to hierarchically manage virtual blocks, garbage collection can prioritize processing virtual blocks with a high proportion of invalid data, thereby improving the efficiency of storage space reclamation; and by pre-updating the valid data bitmap when the storage device is idle, the real-time update overhead during garbage collection is avoided, effectively improving the response speed of the storage device under high load conditions. Attached Figure Description

[0018] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0019] Figure 1 This is a block diagram of a host system and storage device according to an embodiment of the present invention;

[0020] Figure 2 This is a flowchart of a memory management method according to an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram illustrating the logical-to-physical index list update of written data according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of an updated valid data bitmap according to an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of a pre-recovery status grading mechanism according to an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of a virtual block pre-reclaim status table according to an embodiment of the present invention;

[0025] Figure 7 This is a flowchart of a memory management method according to another embodiment of the present invention.

[0026] Explanation of icon numbers

[0027] 10: Host System

[0028] 20: Storage device

[0029] 211: First Processor

[0030] 110: Second Processor

[0031] 120: Host memory

[0032] 130: Data transmission interface circuit

[0033] 210: Memory controller

[0034] 212: Data Management Circuit

[0035] 213: Memory Interface Control Circuit

[0036] 214: Buffer memory

[0037] 220: Rewritable Non-volatile Memory Module

[0038] 230: Connection interface circuit

[0039] BM1: Valid Data Bitmap

[0040] IDX1: Logical to Physical Index List

[0041] L2P1, L2P2: Logical-to-Physical Mapping Tables

[0042] TB61: Virtual Block Pre-Reclamation Status Table

[0043] VB1: Virtual Blocks

[0044] PG1, PG2, PG3: Data Area

[0045] LBA1, LBA11, LBA12, LBA21, LBA22: Logical addresses; PBA1, PBA11, PBA12, PBA13, PBA21, PBA22: Physical addresses; C1, C2, C3: First threshold.

[0046] CT5: Chart

[0047] S210-S240: Flowchart of memory management method

[0048] S710-S740: Flowchart of Memory Management Method

[0049] A31, A32, A41, A42, A43, A44, A45: First arrow Detailed Implementation

[0050] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0051] Figure 1 This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be located on the motherboard of the host system 10.

[0052] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0053] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0054] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0055] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0056] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0057] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0058] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to the instructions of the host system 10.

[0059] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data. Furthermore, in this embodiment, the control instructions / program codes can also be executed to implement the memory management method provided in this disclosure. The control instructions / program codes corresponding to memory management can also be implemented as hardware circuit units to implement the memory management method provided in this disclosure.

[0060] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0061] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0062] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., performing a write operation based on a write instruction from the host system 10, also called a host write operation). Another example is reading data from one or more physical units of the rewritable non-volatile memory module 220 (data can be read from one or more memory cells in one or more physical units) via the memory interface control circuit 213 and writing the read data to the host system 10 (e.g., host memory 120) via the connection interface circuit 230 (e.g., performing a read operation based on a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0063] The memory interface control circuit 213 is used to receive instructions from the processor 211 and, in conjunction with the data management circuit 212, perform write (also known as programming), read, or erase operations (also known as erasure) on the rewritable non-volatile memory module 220.

[0064] Furthermore, data to be written to the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 needs to access the rewritable non-volatile memory module 220, the processor 211 will send a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0065] In this disclosure, the memory controller 210 establishes a Logical to Physical address mapping table (L2P mapping table) and a Physical to Logical address mapping table (P2L mapping table) to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages, or logical columns) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages, physical columns) configured for the rewritable non-volatile memory module 220. In other words, the memory controller 210 can use the L2P mapping table (also called the logical to physical mapping table) to look up the physical unit mapped to a logical unit (e.g., look up the physical page mapped to a logical page; look up the physical address mapped to a logical address), and the memory controller 210 can use the P2L mapping table (also called the physical to logical mapping table) to look up the logical unit mapped to a physical unit (e.g., look up the logical page mapped to a physical page; look up the logical address mapped to a physical address).

[0066] The memory controller 210 also establishes data structures to record various mapping relationships, including: a virtual block mapping list that records the physical blocks corresponding to each virtual block, an L2P index list that records the L2P mapping table associated with each virtual block, and a virtual block pre-reclaim status table that records all virtual blocks.

[0067] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20 (e.g., various mapping tables, index tables, virtual block mapping lists, L2P index lists, virtual block pre-reclamation status tables, and other system data related to this disclosure) so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 214.

[0068] In one embodiment, the memory controller 210 reserves a specific area in the buffer memory 214 for storing various mapping tables and index information. The memory controller 210 performs hierarchical caching of this data based on access frequency and importance: frequently accessed mapping table information is stored in a fast-access area, while less frequently used information is stored in a normal area. When the buffer memory 214 is insufficient, the memory controller 210 prioritizes writing less frequently used information back to the rewritable non-volatile memory module 220. To improve data reliability, the memory controller 210 also periodically synchronizes important mapping information from the buffer memory 214 to the rewritable non-volatile memory module 220 and records the synchronization timestamp so that the system can be restored to the most recent valid state in case of an anomaly.

[0069] In one embodiment, the memory controller 210 establishes multiple data structures to record various mapping relationships. Specifically, the memory controller 210 establishes a Virtual Block Mapping List (VB mapping list) to record the identification information of one or more physical blocks corresponding to each virtual block. In some embodiments, the VB mapping list may also include the location information of the physical block within the corresponding virtual block, the erase count information of each physical block, and the effective count of each virtual block. The memory controller 210 also establishes an L2P index list to record the identification code of one or more logical-to-physical mapping tables associated with each virtual block. In addition, the memory controller 210 establishes a Virtual Block Pre-GC state table to record the pre-GC state of all corresponding virtual blocks. In one embodiment, each entry in the Virtual Block Pre-GC state table includes information such as: virtual block identification code, current effective count value, etc.

[0070] In another embodiment, the memory controller 210 stores these data structures in a preset area of ​​the buffer memory and periodically synchronizes their updated state to the rewritable non-volatile memory module to ensure data persistence and consistency. In some embodiments, when the memory controller 210 restarts, the latest state of these data structures can be restored from the rewritable non-volatile memory module, ensuring that the system can continue previous storage management operations.

[0071] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store data written by the host system 10.

[0072] In this embodiment, the rewritable non-volatile memory module 220 has multiple word lines, each of which is electrically connected to multiple memory cells, also called columns (or physical columns). Multiple columns on the same word line form a physical programming unit (also called a physical page or physical page). Each physical page corresponds to a physical address to record the location of the data stored in the physical page. Furthermore, multiple physical pages can form a physical block (also called a physical erase unit or physical block). Each memory die (chip) in the multiple memory dies of the rewritable non-volatile memory module has multiple planes, and each plane has multiple physical blocks. It should be noted that this disclosure is not limited to the size of each physical page and logical page.

[0073] Memory cell type (also known as storage mode) represents the number of bits that each memory cell (or storage unit) can store. Common types include SLC (Single-level cell, 1 bit per cell), MLC (Multi-level cell, 2 bits per cell), and TLC (Triple-level cell, 3 bits per cell). Different storage modes vary in storage density, read / write speed, and endurance, affecting the overall performance and characteristics of flash memory.

[0074] Figure 2 This is a flowchart of a memory management method according to an embodiment of the present disclosure.

[0075] Reference Figure 2 In one embodiment, the memory controller 210 performs a memory management method. Specifically, in step S210, the memory controller 210 acquires valid counts for each of a plurality of virtual blocks, wherein each virtual block includes one or more physical blocks of the rewritable nonvolatile memory module 220.

[0076] In one embodiment, the memory controller 210 can obtain the valid count of virtual blocks in a variety of ways. When the storage device 20 performs a write operation, the memory controller 210 maintains a valid count counter to count the number of valid data in each virtual block in real time. Specifically, when performing a write operation, the memory controller 210 performs one of the following operations:

[0077] When new data is written, the memory controller 210 increments the effective counter of the target virtual block by 1; when the written data overwrites the original data, the memory controller 210 first determines the source virtual block where the overwritten data is located according to the logical-to-physical mapping table, decrements the effective counter of the source virtual block by 1, and then increments the effective counter of the target virtual block by 1; when data is deleted, the memory controller 210 decrements the effective counter of the corresponding virtual block by 1.

[0078] In another embodiment, the memory controller 210 can periodically scan the logical-to-physical mapping table in the background, updating the valid count by counting the number of times each virtual block appears in the mapping table. Although this method has a higher computational cost, it can correct for counting errors caused by system anomalies.

[0079] In step S220, the memory controller 210 obtains the pre-reclaim status of each virtual block based on the effective count of each virtual block.

[0080] In one embodiment, when the memory controller 210 acquires the pre-reclaim status of each virtual block, it first compares the effective count of each virtual block with a plurality of preset thresholds to determine the threshold interval in which the effective count of the virtual block falls. Specifically, the memory controller 210 presets a plurality of thresholds of different sizes and arranges these thresholds in descending order to divide the multiple threshold intervals.

[0081] The memory controller 210 then determines the pre-reclaim status of each virtual block based on the threshold range in which the valid count of each virtual block falls. When the valid count of a virtual block is greater than the maximum threshold among the plurality of thresholds, the memory controller 210 sets the pre-reclaim status of that virtual block to the minimum pre-reclaim status value. Conversely, when the valid count of a virtual block is less than the minimum threshold among the plurality of thresholds, the memory controller 210 sets the pre-reclaim status of that virtual block to the maximum pre-reclaim status value.

[0082] For example, when a first virtual block is determined to have the minimum pre-reclaim status, the memory controller 210 marks the first virtual block as not requiring an update to its corresponding first valid data bitmap. This is because virtual blocks with the minimum pre-reclaim status typically have a high proportion of valid data and do not require garbage collection at this time. Conversely, when a second virtual block is determined to have the maximum pre-reclaim status, the memory controller 210 marks the second virtual block as requiring a priority update to its corresponding second valid data bitmap, because such virtual blocks have a higher proportion of invalid data and are more likely to be selected as targets for garbage collection.

[0083] Figure 5 This is a schematic diagram of a pre-recycling status grading mechanism according to an embodiment of the present invention.

[0084] Reference Figure 5 In one embodiment, the memory controller 210 implements a pre-reclaiming state hierarchy mechanism. As shown in Figure CT5, the coordinate axes represent valid counts, and the memory controller 210 divides virtual blocks into different pre-reclaiming states based on the valid count values.

[0085] In this embodiment, the memory controller 210 presets three thresholds, namely a first threshold (C1), a second threshold (C2), and a third threshold (C3), wherein C1 is greater than C2 and C2 is greater than C3. The memory controller 210 uses these three thresholds to divide the effective count range into four intervals, and assigns these four intervals to four different pre-recycling states.

[0086] Specifically, when the memory controller 210 detects that the effective count of a virtual block is greater than the first threshold C1, it sets the pre-reclamation state of the virtual block to "state 1" and marks it as "no need to update". This means that the proportion of effective data in the virtual block is high, and there is no need to update its effective data bitmap or perform garbage collection for the time being.

[0087] When the memory controller 210 detects that the valid count of a virtual block is less than the first threshold C1 but greater than the second threshold C2, it sets the pre-reclamation state of the virtual block to "state 2" and marks it as "low priority". This means that the virtual block can update its valid data bitmap when system resources are sufficient.

[0088] When the memory controller 210 detects that the effective count of a virtual block is less than the second threshold C2 but greater than the third threshold C3, it sets the pre-reclamation state of the virtual block to "state 3" and marks it as "second highest priority". This indicates that the virtual block has a relatively high update priority.

[0089] When the memory controller 210 detects that the valid count of a virtual block is less than the third threshold C3, it sets the pre-reclaim status of the virtual block to "state 4" and marks it as "highest priority". This indicates that the proportion of invalid data in the virtual block is high, its valid data bitmap needs to be updated first, and it may be given priority for garbage collection.

[0090] In one embodiment, the memory controller 210 can dynamically adjust the specific values ​​of these thresholds based on the performance requirements and workload characteristics of the storage device 20. For example, in high-performance scenarios, the values ​​of these thresholds can be increased, causing more virtual blocks to be allocated to a high-priority pre-reclaim state, thereby enabling more aggressive garbage collection; in low-power scenarios, the values ​​of these thresholds can be decreased to reduce unnecessary garbage collection operations.

[0091] Furthermore, while the above example uses three thresholds to manage the grading of the pre-reclaim state, this disclosure is not limited thereto. For example, the memory controller 210 may use more or fewer thresholds to manage the grading of the pre-reclaim state.

[0092] Back Figure 2Next, in step S230, the memory controller 210 determines the update order of the valid data bitmap of each virtual block according to the pre-reclaim state of each virtual block.

[0093] In one embodiment, the memory controller 210 prioritizes updating the valid data bitmaps of virtual blocks with larger pre-reclaim states. For example, when the storage device 20 is detected to be in an idle state, the memory controller 210 first updates the valid data bitmaps of virtual blocks with a fourth pre-reclaim state, and then sequentially updates the valid data bitmaps of virtual blocks with a third and second pre-reclaim state. For virtual blocks with a first pre-reclaim state, since their valid data ratio is relatively high, their valid data bitmaps may not be updated temporarily.

[0094] In step S240, the memory controller 210 selects a target virtual block from the plurality of virtual blocks according to the update order of the valid data bitmap of each virtual block, so as to update the target valid data bitmap of the target virtual block using a logical-to-physical index list corresponding to the target virtual block and a logical-to-physical mapping table corresponding to the logical-to-physical index list.

[0095] In one embodiment, specifically, the memory controller 210 first finds all logical-to-physical mapping tables associated with the target virtual block through the logical-to-physical index list of the target virtual block. Then, the memory controller 210 checks whether the physical address of each data region in the target virtual block still exists in these mapping tables. If the physical address of a data region still exists in the mapping table, the bit corresponding to that data region in the target valid data bitmap is set to a first value (e.g., 1); if the physical address of a data region does not exist in any mapping table, the corresponding bit is set to a second value (e.g., 0). After the update is completed, the memory controller 210 stores the target valid data bitmap in the rewritable non-volatile memory module 220.

[0096] In one embodiment, when predetermined conditions are met (e.g., when the storage device 20 is idle), the memory controller 210 can pre-update the valid data bitmap of each virtual block, providing a fast basis for judging the validity of data for subsequent garbage collection operations, thereby improving the efficiency of garbage collection.

[0097] Figure 3 This is a schematic diagram illustrating the logical-to-physical index list update of written data according to an embodiment of the present invention.

[0098] Reference Figure 3 In one embodiment, when write data TD is written to virtual block VB1, memory controller 210 updates logic to the physical index list.

[0099] In detail, as shown by arrow A31, when virtual block VB1 of storage device 20 receives write data, the data is assigned a physical address "PBA1" and stored in virtual block VB1. Simultaneously, memory controller 210 needs to establish a mapping relationship between the logical address "LBA1" and the physical address "PBA1" of this data in the logical-to-physical mapping table L2P1. Specifically, memory controller 210 creates a new entry in the logical-to-physical mapping table L2P1, which includes a logical address field and a physical address field, recording "LBA1" and "PBA1" respectively.

[0100] Next, as indicated by arrow A32, the memory controller 210 also needs to update the logical-to-physical index list IDX1. This logical-to-physical index list IDX1 records the identification codes of one or more logical-to-physical mapping tables associated with the virtual block. In this embodiment, the memory controller 210 records the identification code "L2P1" of the logical-to-physical mapping table L2P1 in the index list IDX1, indicating that the physical address information of the valid data stored in the virtual block VB1 can be found in the mapping table L2P1. This also indicates that the valid data in the virtual block VB1 is associated with the logical-to-physical mapping table L2P1 recorded in the logical-to-physical index list IDX1.

[0101] In one embodiment, the memory controller 210 employs a hierarchical indexing structure when building the logical-to-physical index list. The first layer is a virtual block identifier used to quickly locate the target virtual block; the second layer is a list of identifiers for all L2P mapping tables associated with that virtual block. This hierarchical structure enables the memory controller 210 to quickly find all mapping information associated with a specific virtual block.

[0102] The memory controller 210 updates the L2P index list through the following steps: When new data is written, the memory controller 210 first checks whether the target virtual block of the data already has a corresponding entry in the index list. If not, a new index entry is created; if it already exists, the memory controller 210 checks whether the L2P mapping table corresponding to the new data is already in the mapping table list of that virtual block. For new mapping tables not in the list, the memory controller 210 adds its identifier to the list.

[0103] When the data mapping relationship of the same virtual block is scattered across multiple logical-to-physical mapping tables, the memory controller 210 records the identification codes of all relevant mapping tables in the index list corresponding to the virtual block. This design enables the memory controller 210 to quickly locate and load all the mapping tables that need to be queried (loaded into the cache memory 214) during garbage collection, improving the efficiency of data validity judgment.

[0104] By maintaining this index list mechanism, the memory controller 210 can quickly determine which logical-to-physical mapping tables need to be checked during subsequent garbage collection, thereby improving the efficiency of updating the valid data bitmap. When the memory controller 210 needs to update the valid data bitmap of a virtual block, it only needs to look up the index list corresponding to that virtual block to obtain the identification codes of all mapping tables that need to be checked, avoiding the overhead of traversing all mapping tables, thus accelerating the speed of updating the valid data bitmap.

[0105] Figure 4 This is a schematic diagram of an updated valid data bitmap according to an embodiment of the present invention.

[0106] Reference Figure 4 In one embodiment, the memory controller 210 establishes and maintains a valid data bitmap BM1, which includes multiple bits. Each bit corresponds to a data region of a preset size (e.g., PG1, PG2, PG3) in the virtual block VB1, and is used to indicate whether the data in that data region is valid data. Specifically, when the data stored in a certain data region is still valid (valid data), the memory controller 210 sets the bit corresponding to that region to a first value (e.g., "1"); when the data stored in a certain data region is invalid (not valid data), the memory controller 210 sets the bit corresponding to that region to a second value (e.g., "0").

[0107] In one embodiment, when the storage device 20 is idle (e.g., when no host commands need to be processed), the memory controller 210 performs a valid data bitmap update operation for the target virtual block VB1. First, the memory controller 210 accesses the logical-to-physical index list IDX1 corresponding to the target virtual block VB1, which records the identifiers of all logical-to-physical mapping tables associated with the target virtual block VB1, including "L2P1" and "L2P2".

[0108] The memory controller 210 accesses the logical-to-physical index list IDX1, which records the identifiers of the logical-to-physical mapping tables associated with the virtual block VB1, including "L2P1" and "L2P2". Based on this, the memory controller 210 determines that mapping tables L2P1 and L2P2 need to be loaded and checked to verify the validity of the data in the virtual block VB1.

[0109] After loading the mapping tables L2P1 and L2P2 into the cache memory 214, the memory controller 210 checks whether the physical address of each storage region of the virtual block exists in the physical address recorded in the mapping tables L2P1 and L2P2.

[0110] The memory controller 210 loads the relevant logical data into physical mapping tables L2P1 and L2P2 based on the identifiers in the index list IDX1. As shown by arrow A41, the memory controller 210 checks that the first physical address "PBA11" of the first data region PG1 exists in mapping table L2P1 and is associated with the logical address "LBA11". Therefore, the memory controller 210 determines that the first physical address "PBA11" of the first data region PG1 stores valid data. Next, as shown by arrow A42, the memory controller 210 sets the first bit in the valid data bitmap BM1 corresponding to the first data region to "1" (also called the first value).

[0111] As shown by arrow A43, the memory controller 210 detects that the second physical address "PBA12" of the second data area PG2 does not exist in any logical-to-physical mapping table (marked with "×" in the figure). This indicates that the data stored at this physical address has expired (e.g., the physical address corresponds to invalid data), so the memory controller 210 sets the second bit in the valid data bitmap BM1 corresponding to the second data area to "0" (also called the second value).

[0112] For example, as shown by arrows A44 and A45, for the physical address "PBA13" of the third data region PG3, the memory controller 210 finds its corresponding valid mapping in the mapping table L2P2, where the physical address is associated with the logical address "LBA22". This indicates that the data is still valid, so the memory controller 210 sets the bit in the valid data bitmap BM1 corresponding to the third data region to "1".

[0113] Similarly, the memory controller 210 can update the valid data bitmap BM1 of the corresponding virtual block VB1. In this way, the memory controller 210 completes the update of the valid data bitmap BM1 of the virtual block VB1. The updated bitmap accurately reflects the validity status of each data area in the virtual block VB1, providing a reliable reference for subsequent garbage collection operations.

[0114] After completing the validity checks of all data areas, the memory controller 210 stores the updated target valid data bitmap BM1 into the rewritable non-volatile memory module 220 for use in subsequent garbage collection operations. In this way, the storage device 20 can pre-update the valid data bitmap during idle time, thereby reducing the overhead of garbage collection operations.

[0115] In one embodiment, in practical implementation, the memory controller 210 can employ a batch processing method, simultaneously checking the validity of multiple physical addresses and updating multiple bits in the valid data bitmap at once, thereby improving update efficiency. Furthermore, the memory controller 210 can also maintain a checksum during the update process to verify the integrity of the updated valid data bitmap.

[0116] Figure 6 This is a schematic diagram of a virtual block pre-reclaim status table according to an embodiment of the present invention.

[0117] Reference Figure 6 In one embodiment, the memory controller 210 maintains a virtual block pre-reclaim status table TB61 to record the status information of multiple virtual blocks and guide garbage collection operations.

[0118] The virtual block pre-reclaim status table TB61 contains several fields: a virtual block number / identifier field, used to uniquely identify each virtual block; a valid count field, recording the amount of valid data in each virtual block; a pre-reclaim status field, indicating the pre-reclaim status value of the virtual block; and a "whether to update" field, used to mark whether the valid data bitmap of the virtual block needs to be updated. In this embodiment, a pre-reclaim status of 1 is determined to be because the total amount of valid data exceeds a certain value, and therefore, updating the corresponding valid data bitmap is not required, thereby reducing resource overhead.

[0119] In this embodiment, the memory controller 210 presets three thresholds: a first threshold C1 (45000), a second threshold C2 (35000), and a third threshold C3 (20000). Based on the comparison results of the valid count value with these thresholds, the memory controller 210 assigns a corresponding pre-reclaim state to each virtual block. For example, Figure 6 The valid count of the virtual block numbered "0" is 65536, which is greater than C1, so its pre-reclaim status is set to "1"; while the valid count of the virtual block numbered "1" is 16000, which is less than C3, so its pre-reclaim status is set to "4", and so on.

[0120] The memory controller 210 determines whether the valid data bitmap of the virtual block needs to be updated based on the pre-reclaim status value. Specifically, when the pre-reclaim status value is "1", it is marked as "No" because the proportion of valid data is relatively high, indicating that no update is needed at this time; when the pre-reclaim status value is greater than "1", it is marked as "Yes", indicating that the valid data bitmap needs to be updated when the storage device 20 is idle.

[0121] When foreground garbage collection is required during a host write operation, the memory controller 210 preferentially selects the virtual block with the largest pre-collection state value (i.e., a state value of "4") as the garbage collection target. For example... Figure 6As shown, virtual blocks "1" and "5" have a pre-collection state of "4", with virtual block "1" having a lower effective count (16000), thus being prioritized. If these virtual blocks have been processed, the memory controller 210 will then select the virtual blocks with the second-largest pre-collection state value (i.e., a state value of "3"), such as virtual blocks "6" and "7" in the figure, and so on. In other words, the memory controller 210 can determine the garbage collection order of each virtual block based on its pre-collection state.

[0122] by Figure 6 For example, when a foreground garbage collection needs to be performed, the memory controller 210 first selects virtual block "1" (valid count 16000, pre-collection state "4") as the garbage collection virtual block; then it selects virtual block "5" (valid count 15000, pre-collection state "4"); then it selects virtual blocks "6" and "7" (both with pre-collection states "3"). This selection strategy based on pre-collection state ensures that the garbage collection operation can prioritize processing virtual blocks with a higher proportion of invalid data, thereby improving the efficiency of storage space reclamation.

[0123] Through this pre-reclaim status table mechanism, the memory controller 210 can quickly identify and prioritize the virtual blocks most suitable for reclamation during prospective garbage collection, significantly improving the efficiency of garbage collection.

[0124] Figure 7 This is a flowchart of a memory management method according to another embodiment of the present invention.

[0125] Reference Figure 7 In one embodiment, storage device 20 performs a memory management method incorporating prospective garbage collection.

[0126] In step S710, the memory controller 210 receives a write command sent by the host system 10. After receiving the write command, the memory controller 210 needs to ensure that the storage device 20 has sufficient available space to complete the data write operation.

[0127] In step S720, in response to determining that a foreground garbage collection operation needs to be performed, the memory controller 210 selects a target virtual block based on the pre-collection state of each virtual block and obtains the target valid data bitmap of the corresponding target virtual block. Specifically, the memory controller 210 preferentially selects the virtual block with the largest pre-collection state value as the garbage collection virtual block. If there are multiple virtual blocks with the same pre-collection state value, the processing order is further determined based on the size of the valid count.

[0128] In one embodiment, the memory controller 210 can determine whether a foreground garbage collection operation needs to be performed in a variety of ways.

[0129] In a preferred embodiment, the memory controller 210 determines whether to perform foreground garbage collection by monitoring the available space of the storage device 20. Specifically, the memory controller 210 presets a free space threshold, and triggers a foreground garbage collection operation when it detects that the available space of the storage device 20 is less than the preset threshold. The free space threshold can be set as a percentage of the total capacity of the storage device 20, for example, garbage collection is triggered when the available space is less than 10% of the total capacity.

[0130] In another embodiment, the memory controller 210 determines whether to perform foreground garbage collection based on a comparison between the amount of data requested for writing and the currently available space. When the memory controller 210 receives a write request from the host system 10, it calculates the amount of data to be written and compares it with the currently available space. If the currently available space is insufficient to accommodate the data to be written, a foreground garbage collection operation is initiated.

[0131] In another embodiment, the memory controller 210 determines whether garbage collection needs to be performed by evaluating the state distribution of virtual blocks. Specifically, the memory controller 210 counts the number of virtual blocks in the fourth pre-collection state (maximum state value). When this number exceeds a preset threshold, it indicates that there are a large number of blocks that need to be collected, and at this time, a foreground garbage collection operation is triggered.

[0132] In another embodiment, the memory controller 210 determines whether garbage collection needs to be performed by monitoring the write performance of the storage device 20. When the write speed is detected to be lower than the expected performance threshold, it may indicate that the storage space is severely fragmented, and a foreground garbage collection operation is triggered to reorganize the storage space.

[0133] The memory controller 210 can also adjust the garbage collection strategy according to different triggering conditions. For example, in an emergency, it can prioritize the reclamation of virtual blocks with larger pre-reclaimed status values ​​in order to quickly release storage space.

[0134] Next, the memory controller 210 divides the processing into two branches that are executed in parallel:

[0135] In step S730, the memory controller 210 executes the host write instruction to write the data sent by the host system 10 into the available storage space in the storage device 20.

[0136] Simultaneously, in step S740, the memory controller 210 performs a foreground garbage collection operation. Specifically, the memory controller 210 first acquires the valid data bitmap of the selected garbage collection virtual block. Then, the memory controller 210 scans all bits in the valid data bitmap and identifies multiple first bits with a first value (e.g., "1"), which indicate that valid data is stored in the corresponding data area.

[0137] Based on the identified first bits, the memory controller 210 locates multiple first data regions in the garbage collection virtual block corresponding to these first bits. Subsequently, the memory controller 210 sequentially copies the valid data in these first data regions into pre-allocated data blocks.

[0138] During the data copying process, the memory controller 210 can simultaneously update the corresponding logical-to-physical mapping table, recording the new physical addresses of this valid data in the mapping table.

[0139] After copying the valid data, the memory controller 210 performs an erase operation on the garbage-collected virtual block, restoring it to a usable state. At this time, all storage units in the virtual block are reset to preset values ​​and can be used for subsequent data write operations. The corresponding virtual block mapping table, logical-to-physical index list, and virtual block pre-reclaiming status table are also updated / reset accordingly.

[0140] In this way, the memory controller 210 can efficiently perform garbage collection operations while executing host write instructions, effectively improving the overall performance of the storage device 20. Especially when the storage device 20 is close to being full, this garbage collection method based on pre-reclaimment state can quickly release storage space and ensure the smooth progress of host write operations.

[0141] Finally, this embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is executed in the processor of a host system, the processor executes the process steps of the above-described memory management method and implements the functions of a memory controller. This computer program product can be implemented specifically through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0142] Based on the above, the memory management method and memory controller provided in this disclosure can achieve the following technical effects:

[0143] First, this disclosure employs a virtual block pre-reclaiming state hierarchical mechanism, which divides virtual blocks into different pre-reclaiming states based on valid counts, and pre-updates the valid data bitmap of high-priority virtual blocks when the storage device is idle. This preprocessing mechanism significantly reduces the mapping table lookup overhead during foreseeable garbage collection, thereby improving garbage collection efficiency.

[0144] Secondly, this disclosure designs a multi-layered garbage collection triggering mechanism. By monitoring multiple dimensions of indicators such as available space of the storage device, write load, and block state distribution, it achieves precise control over garbage collection operations. This mechanism can initiate forward garbage collection at appropriate times, ensuring timely release of storage space while avoiding unnecessary garbage collection operations.

[0145] Third, this disclosure establishes a fast indexing relationship between virtual blocks and their associated logical-to-physical mapping tables through a logical-to-physical index list mechanism. This design significantly reduces the overhead of looking up the mapping table when updating valid data bitmaps, thus improving the efficiency of bitmap updates.

[0146] Fourth, when performing prospective garbage collection, this disclosure prioritizes processing virtual blocks with the highest pre-collection state value and quickly identifies and copies valid data based on a valid data bitmap. This method minimizes data migration and improves the speed of garbage collection.

[0147] In summary, the memory management method provided in this disclosure significantly improves the performance of storage devices under high load conditions, and is particularly suitable for applications requiring frequent data writes. By pre-updating the valid data bitmap and combining it with a pre-reclamation state classification mechanism, this solution effectively solves the problem of low efficiency in traditional foreground garbage collection, thereby improving the overall operating efficiency of the storage device.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A memory management method applicable to a storage device equipped with a rewritable non-volatile memory module, characterized in that, The method includes: Obtain the valid counts of each of the multiple virtual blocks, wherein each virtual block includes one or more physical blocks of the rewritable non-volatile memory module; Based on the valid count of each virtual block, the pre-reclaim status of each virtual block is obtained; whereby The valid count of each virtual block is compared with multiple thresholds of different sizes to determine the threshold range in which the valid count of each virtual block falls; and The pre-reclaim status of each virtual block is determined based on the threshold range for each virtual block. If the valid count of a virtual block is greater than the maximum threshold among the plurality of thresholds, the pre-reclaim state of the virtual block is determined to be the minimum pre-reclaim state; If the valid count of a virtual block is less than the minimum threshold among the plurality of thresholds, the pre-reclaim state of the virtual block is determined to be the maximum pre-reclaim state; The update order of the valid data bitmap for each virtual block is determined based on the pre-reclaim status of each virtual block; wherein The first virtual block corresponding to the smallest pre-reclaimed state is determined not to need to update the corresponding first valid data bitmap, and the second virtual block corresponding to the largest pre-reclaimed state is determined to need to prioritize updating the corresponding second valid data bitmap. Based on the update order of the valid data bitmap of each virtual block, a target virtual block is selected from the plurality of virtual blocks to update the target valid data bitmap of the target virtual block using a logical-to-physical index list corresponding to the target virtual block and a logical-to-physical mapping table corresponding to the logical-to-physical index list.

2. The memory management method according to claim 1, characterized in that, Also includes: The garbage collection order of each virtual block is determined based on the pre-collection state of each virtual block.

3. The memory management method according to claim 1, characterized in that, The number of the multiple thresholds is 3, and the pre-recovery states include a first pre-recovery state, a second pre-recovery state, a third pre-recovery state, and a fourth pre-recovery state. Wherein the effective count corresponding to the first pre-recovery state is greater than the first threshold. The effective count corresponding to the second pre-recovery state is greater than the second threshold and less than the first threshold. The effective count corresponding to the third pre-recovery state is greater than the third threshold and less than the second threshold. The effective count corresponding to the fourth pre-recovery state is less than the third threshold, wherein the first threshold is the maximum threshold, the third threshold is the minimum threshold, the first threshold is greater than the second threshold, and the second threshold is greater than the third threshold.

4. The memory management method according to claim 1, characterized in that, The logical-to-physical index list is used to record the identification codes of one or more logical-to-physical mapping tables associated with the corresponding virtual block, wherein the physical address of the valid data stored in the corresponding virtual block is recorded in one of the one or more logical-to-physical mapping tables.

5. The memory management method according to claim 1, characterized in that, The valid data bitmap includes multiple bits, each bit corresponding to a data area of ​​a preset size in the virtual block, used to indicate whether the data in the data area is valid data.

6. The memory management method according to claim 5, characterized in that, The method further includes: The target virtual block is updated when the storage device is idle. The step of updating the target valid data bitmap of the target virtual block includes: The target logic-to-physical mapping table associated with the target virtual block is determined by the logic-to-physical index list of the target virtual block; Check if the physical address of each data region of the target virtual block exists in the one or more target logical-to-physical mapping tables; and The plurality of bits of the target valid data bitmap are updated according to the inspection results of each data region, wherein the updated target valid data bitmap is stored in the rewritable non-volatile memory module.

7. The memory management method according to claim 6, characterized in that, The steps of updating the plurality of bits of the target valid data bitmap include: If the first physical address of the first data region of the target virtual block exists in one of the one or more target logical-to-physical mapping tables, the first bit corresponding to the first data region in the plurality of bits of the target valid data bitmap is set to a first value; and If the second physical address of the second data region of the target virtual block does not exist in any of the one or more target logical-to-physical mapping tables, the second bit of the multiple bits of the target valid data bitmap corresponding to the second data region is set to the second value.

8. The memory management method according to claim 2, characterized in that, The order in which the garbage collection is determined for each virtual block includes: During host write operations, when performing foreground garbage collection, the virtual block with the largest pre-collection state is preferentially selected as the garbage collection virtual block for garbage collection; and Next, the virtual block with the second largest pre-recycling state is selected as the garbage recycling virtual block for garbage recycling.

9. The memory management method according to claim 8, characterized in that, The steps involved in performing waste recycling include: Obtain the valid data bitmap of the selected garbage collection virtual block; Based on a plurality of first bits in the valid data bitmap of the selected virtual block, the first data of each of a plurality of first data regions corresponding to the plurality of first bits in the garbage-collected virtual block is copied to the data block; and Perform an erase operation on the garbage collection virtual block.

10. A memory controller for controlling a storage device configured with a rewritable non-volatile memory module, characterized in that, The memory controller includes: A memory interface control circuit is used to electrically connect to the rewritable non-volatile memory module; A data management circuit is electrically connected to the connection interface circuit of the storage device for receiving data and instructions from the host system via the connection interface circuit. Buffer memory, used to cache data; and A processor electrically connected to the memory interface control circuit, the data management circuit, and the buffer memory, wherein the processor is configured to: Obtain the valid counts of each of the multiple virtual blocks, wherein each of the virtual blocks includes one or more physical blocks of the rewritable non-volatile memory module; Based on the valid count of each virtual block, the pre-reclaim status of each virtual block is obtained; whereby The valid count of each virtual block is compared with multiple thresholds of different sizes to determine the threshold range in which the valid count of each virtual block falls; and The pre-reclaim status of each virtual block is determined based on the threshold range for each virtual block. If the valid count of a virtual block is greater than the maximum threshold among the plurality of thresholds, the pre-reclaim state of the virtual block is determined to be the minimum pre-reclaim state; If the valid count of a virtual block is less than the minimum threshold among the plurality of thresholds, the pre-reclaim state of the virtual block is determined to be the maximum pre-reclaim state; The update order of the valid data bitmap for each virtual block is determined based on the pre-reclaim status of each virtual block; wherein The first virtual block corresponding to the smallest pre-reclaimed state is determined not to need to update the corresponding first valid data bitmap, and the second virtual block corresponding to the largest pre-reclaimed state is determined to need to prioritize updating the corresponding second valid data bitmap. Based on the update order of the valid data bitmap of each virtual block, a target virtual block is selected from the plurality of virtual blocks to update the target valid data bitmap of the target virtual block using a logical-to-physical index list corresponding to the target virtual block and a logical-to-physical mapping table corresponding to the logical-to-physical index list.

11. The memory controller according to claim 10, characterized in that, The processor is also configured to: The garbage collection order of each virtual block is determined based on the pre-collection state of each virtual block.

12. The memory controller according to claim 10, characterized in that, The number of the multiple thresholds is 3, and the pre-recovery states include a first pre-recovery state, a second pre-recovery state, a third pre-recovery state, and a fourth pre-recovery state. Wherein the effective count corresponding to the first pre-recovery state is greater than the first threshold. The effective count corresponding to the second pre-recovery state is greater than the second threshold and less than the first threshold. The effective count corresponding to the third pre-recovery state is greater than the third threshold and less than the second threshold. The effective count corresponding to the fourth pre-recovery state is less than the third threshold, wherein the first threshold is the maximum threshold, the third threshold is the minimum threshold, the first threshold is greater than the second threshold, and the second threshold is greater than the third threshold.

13. The memory controller according to claim 10, characterized in that, The logical-to-physical index list is used to record the identification codes of one or more logical-to-physical mapping tables associated with the corresponding virtual block, wherein the physical address of the valid data stored in the corresponding virtual block is recorded in one of the one or more logical-to-physical mapping tables.

14. The memory controller according to claim 10, characterized in that, The valid data bitmap includes multiple bits, each bit corresponding to a data area of ​​a preset size in the virtual block, used to indicate whether the data in the data area is valid data.

15. The memory controller according to claim 14, characterized in that, The processor is also configured to The target virtual block is updated when the storage device is idle. The step of updating the target valid data bitmap of the target virtual block includes: The target logic-to-physical mapping table associated with the target virtual block is determined by the logic-to-physical index list of the target virtual block; Check if the physical address of each data region of the target virtual block exists in the one or more target logical-to-physical mapping tables; and The plurality of bits of the target valid data bitmap are updated according to the inspection results of each data region, wherein the updated target valid data bitmap is stored in the rewritable non-volatile memory module.

16. The memory controller according to claim 15, characterized in that, When updating the plurality of bits of the target valid data bitmap, the processor is configured to: If the first physical address of the first data region of the target virtual block exists in one of the one or more target logical-to-physical mapping tables, the first bit corresponding to the first data region in the plurality of bits of the target valid data bitmap is set to a first value; and If the second physical address of the second data region of the target virtual block does not exist in any of the one or more target logical-to-physical mapping tables, the second bit of the multiple bits of the target valid data bitmap corresponding to the second data region is set to the second value.

17. The memory controller according to claim 11, characterized in that, In determining the garbage collection order for each virtual block, the processor is configured to: During host write operations, when performing foreground garbage collection, the virtual block with the largest pre-collection state is preferentially selected as the garbage collection virtual block for garbage collection; and Next, the virtual block with the second largest pre-recycling state is selected as the garbage recycling virtual block for garbage recycling.

18. The memory controller according to claim 17, characterized in that, When performing garbage collection, the processor is configured to: Obtain the valid data bitmap of the selected garbage collection virtual block; Based on the multiple first bits in the valid data bitmap of the selected virtual block, the first data of each of the multiple first data regions corresponding to the multiple first bits in the garbage-collected virtual block is copied to the data block. as well as Perform an erase operation on the garbage collection virtual block.

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