Decoding error correction method, device, equipment and medium for instruction pipeline

Abstract

The present application discloses a decoding error correction method, device, equipment and medium for an instruction pipeline, which relates to the field of computer technology and is applied to a general computing graphics processing unit, including: obtaining the current decoded instruction of the current instruction in the instruction pipeline, generating a to-be-judged check code of the current decoded instruction; obtaining a reference check code corresponding to the identification information of the current instruction from a check table; if the reference check code and the to-be-judged check code are not the same, determining that the current decoded instruction meets a preset error correction condition; obtaining the next decoded instruction of the current instruction, generating a verification check code of the next decoded instruction; performing a majority vote on the reference check code, the to-be-judged check code and the verification check code to obtain a target check code; determining the decoded instruction corresponding to the target check code as the target decoded instruction of the current instruction. Through the above scheme, error correction of decoded instructions in the instruction pipeline is achieved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a decoding error correction method, device, equipment and medium for an instruction pipeline. Background Art

[0002] GPGPU (General-Purpose computing on Graphics Processing Units) is a technology that extends the computing power of graphics processing units (GPUs) to general computing tasks. Through this technology, GPGPU is not only used for graphics rendering, but can also efficiently perform various general computing tasks, including scientific computing, data analysis, deep learning, etc.

[0003] GPGPU is manufactured with energy-saving, small-sized, fast-speed, and lower-voltage transistors, but the reduction in size and aggressive voltage scaling increase the device's sensitivity to intrinsic and extrinsic noise, making it prone to transient failures, leading to an increasing SER (soft error rate). The instruction decoding unit is the central unit that generates control signals to execute instructions. Once an error occurs in the decoding stage, the subsequent execution and write-back stages will be meaningless, resulting in a waste of performance and power consumption. In addition, if the decoding error is not corrected, the calculation results or memory access results completed by the erroneous decoding will be written into the register file or other storage structure in the write-back stage. Once read by subsequent instructions for calculation, it will cause chain calculation errors, leading to the failure of the calculation task, which seriously affects the stability and accuracy of the calculation system.

[0004] From the above, it can be seen that how to correct errors of decoded instructions in the instruction pipeline is a problem to be solved in this field. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a decoding error correction method, device, equipment and medium for an instruction pipeline, which can correct the errors of the decoded instructions in the instruction pipeline. The specific scheme is as follows:

[0006] In a first aspect, the present application discloses a decoding error correction method for an instruction pipeline, which is applied to a general-purpose computing graphics processing unit, comprising:

[0007] Obtaining a current decoded instruction of a current instruction in the instruction pipeline, and generating a check code to be judged of the current decoded instruction;

[0008] Acquire a reference check code corresponding to the identification information of the current instruction from a check table;

[0009] If the reference check code and the to-be-judged check code are not the same, it is determined that the currently decoded instruction meets a preset error correction condition;

[0010] Obtaining the next decoded instruction of the current instruction, and generating a verification check code of the next decoded instruction;

[0011] Performing majority voting on the reference check code, the check code to be judged, and the verification check code to obtain a target check code;

[0012] A decoded instruction corresponding to the target check code is determined as a target decoded instruction of the current instruction.

[0013] Optionally, the acquiring, from a check table, a reference check code corresponding to the identification information of the current instruction includes:

[0014] Determine whether there is target identification information matching the identification information of the current instruction in the verification table;

[0015] If the target identification information exists in the verification table, the verification code corresponding to the target identification information is determined as a reference verification code corresponding to the identification information of the current instruction.

[0016] Optionally, the decoding error correction method of the instruction pipeline further includes:

[0017] If the target identification information does not exist in the verification table, the verification code to be judged of the current decoded instruction is determined as the benchmark verification code of the current instruction, the identification information of the current instruction and the benchmark verification code of the current instruction are saved in the verification table, and the new current decoded instruction of the current instruction is obtained, and then the step of generating the verification code to be judged of the current decoded instruction is jumped again.

[0018] Optionally, the check table is used to store a mapping relationship between identification information of each instruction and a reference check code of each instruction, wherein the identification information of the instruction is a program counter.

[0019] Optionally, before obtaining the next decoded instruction of the current instruction, the method further includes:

[0020] Controlling the instruction pipeline to stop processing the current instruction;

[0021] Correspondingly, after determining the decoded instruction corresponding to the target check code as the target decoded instruction of the current instruction, the method further includes:

[0022] The instruction pipeline is controlled to execute a processing flow for the current instruction.

[0023] Optionally, the performing majority voting on the reference check code, the check code to be judged, and the verification check code to obtain a target check code includes:

[0024] If the verification determination check code is the same as the reference check code, determining that the reference check code is the target check code;

[0025] If the verification determination check code is the same as the check code to be judged, the check code to be judged is determined to be the target check code.

[0026] Optionally, after determining that the check code to be judged is a target check code, the method further includes:

[0027] The target check code is used to overwrite the reference check code corresponding to the identification information of the current instruction in the check table, so as to complete the update of the check table.

[0028] In a second aspect, the present application discloses a decoding error correction device for an instruction pipeline, which is applied to a general-purpose computing graphics processing unit, comprising:

[0029] A first check code acquisition module is used to acquire a current decoded instruction of a current instruction in the instruction pipeline, and generate a check code to be judged of the current decoded instruction;

[0030] A second verification code acquisition module, used to obtain a reference verification code corresponding to the identification information of the current instruction from a verification table;

[0031] An error correction condition judgment module, used for judging whether the currently decoded instruction satisfies a preset error correction condition if the reference check code and the check code to be judged are different;

[0032] A third check code acquisition module, used to acquire the next decoded instruction of the current instruction and generate a verification check code for the next decoded instruction;

[0033] A voting and decision module is used to perform majority voting on the reference check code, the check code to be judged and the verification check code to obtain a target check code;

[0034] The decoding instruction error correction module is used to determine the decoded instruction corresponding to the target check code as the target decoded instruction of the current instruction.

[0035] In a third aspect, the present application discloses an electronic device, comprising:

[0036] Memory, used to store computer programs;

[0037] The processor is used to execute the computer program to implement the steps of the decoding and error correction method of the instruction pipeline disclosed above.

[0038] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the decoding and error correction method of the instruction pipeline disclosed above are implemented.

[0039] The beneficial effects of the present application are as follows: the present application is applied to a general computing graphics processing unit, including: obtaining a current decoded instruction of a current instruction in an instruction pipeline, and generating a to-be-judged check code of the current decoded instruction; obtaining a reference check code corresponding to the identification information of the current instruction from a check table; if the reference check code and the to-be-judged check code are not the same, determining that the current decoded instruction meets a preset error correction condition; obtaining a next decoded instruction of the current instruction, and generating a verification judgment check code of the next decoded instruction; performing a majority vote on the reference check code, the to-be-judged check code and the verification judgment check code to obtain a target check code; determining the decoded instruction corresponding to the target check code as the target decoded instruction of the current instruction. It can be seen that the present application utilizes the characteristic of GPGPU that instructions are repeated in time when scheduling different thread bundles, and realizes decoding error monitoring of the instruction pipeline through a check table and a check code. That is, the check table stores the identification information and check code of the instruction, and error monitoring is realized by table lookup verification of repeated instructions. That is, if the reference check code is different from the check code to be judged, then the current decoded instruction meets the preset error correction condition. Further, after the decoding error is detected, that is, when the current decoded instruction meets the preset error correction condition, the decoding error is corrected by multiple re-decoding and voting of multiple decoding results. That is, the next decoded instruction of the current instruction is obtained, and a verification judgment check code of the next decoded instruction is generated. The reference check code, the check code to be judged, and the verification judgment check code are voted by majority to obtain the target check code. Error monitoring and correction can be realized at a lower computing cost, which not only reduces the soft error rate, but also avoids operation errors and system interruptions, and improves operation accuracy and efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0041] Figure 1 A flowchart of a decoding error correction method for an instruction pipeline disclosed in this application;

[0042] Figure 2A specific general-purpose computing graphics processing unit architecture diagram disclosed in this application;

[0043] Figure 3 A schematic diagram of a specific error monitoring and error correction mechanism disclosed in this application;

[0044] Figure 4 A schematic diagram of a specific calibration table structure disclosed in this application;

[0045] Figure 5 A specific majority voting decision unit structure diagram disclosed in this application;

[0046] Figure 6 A specific ruling table diagram disclosed in this application;

[0047] Figure 7 A specific error monitoring and error correction implementation flow chart disclosed in this application;

[0048] Figure 8 A schematic diagram of the structure of a decoding and error correction device for an instruction pipeline disclosed in the present application;

[0049] Fig. 9 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0051] GPGPU is a technology that extends the computing power of graphics processing units (GPUs) to general computing tasks. Through this technology, GPGPU is not only used for graphics rendering, but can also efficiently perform various general computing tasks, including scientific computing, data analysis, deep learning, etc.

[0052] GPGPU is manufactured with energy-saving, small-sized, fast-speed, and lower-voltage transistors, but the reduction in size and aggressive voltage scaling increase the device's sensitivity to intrinsic and extrinsic noise, making it prone to transient failures, leading to a continuous increase in SER. The instruction decoding unit is the central unit that generates control signals to execute instructions. Once an error occurs in the decoding stage, the subsequent execution and write-back stages will be meaningless, resulting in a waste of performance and power consumption. In addition, if the decoding error is not corrected, the calculation results or memory access results completed by the erroneous decoding will be written into the register file or other storage structure in the write-back stage. Once read by subsequent instructions for calculation, it will cause chain calculation errors, leading to the failure of the calculation task, which seriously affects the stability and accuracy of the calculation system.

[0053] To this end, the present application correspondingly provides a decoding error correction scheme for an instruction pipeline, which corrects the errors of the decoded instructions in the instruction pipeline.

[0054] See also Figure 1 As shown, the embodiment of the present application discloses a decoding error correction method of an instruction pipeline, which is applied to a general computing graphics processing unit, including:

[0055] Step S11: obtaining the current decoded instruction of the current instruction in the instruction pipeline, and generating a check code to be judged of the current decoded instruction.

[0056] For example Figure 2 A specific general-purpose computing graphics processing unit architecture diagram is shown, Figure 2 It mainly includes two parts: Host (main processor) and GPGPU; the Host is composed of CPU (Central Processing Unit), memory and compiler. The CPU is used to complete the task establishment, allocation, scheduling and release of the main processor. The program written by the developer on the CPU is translated into hardware instructions that can be parsed by GPGPU through the compiler.

[0057] As a coprocessor, GPGPU handles computationally intensive tasks that the CPU is not good at. It is generally composed of PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) control, thread block scheduling, global memory, L2 Cache, constant parameter memory and multiple SMs (Streaming Multiprocessors).

[0058] The PCIE control module instantiates the PCIE interface, controls the communication between the CPU and GPGPU, and establishes a connection between the GPGPU memory and the HostMemory to realize the data transmission between the Host memory and the GPGPU memory; the GPGPU configuration module initializes the GPGPU and configures the control parameters of the GPGPU.

[0059] L2 Cache is a high-speed cache that pre-fetches data in the global memory by merging memory accesses to reduce pipeline stalls caused by data memory accesses and improve computing efficiency; the thread block scheduling module implements the scheduling and allocation of thread blocks and allocates thread blocks to each SM.

[0060] SM is the computing unit of GPGPU, which is composed of instruction pipeline, thread warp scheduling, register file, L1 Cache, shared memory and error monitoring and correction. Among them, thread warp scheduling realizes the scheduling of thread warps and the control of branch jumps; register file is used to cache data and intermediate calculation results during the operation process; shared memory is used for data exchange between thread warps and threads; L1 Cache pre-fetches data and instructions from L2 Cache to further reduce the memory access time of the pipeline; instruction pipeline is the key to SM to realize computing functions. The instruction pipeline includes instruction fetch, decoding, emission, SP allocation and execution, write-back and other processes. In the execution stage of the pipeline, several threads in a thread warp will be allocated to each SP (Streaming Processor) for execution.

[0061] SP is the smallest computing unit of GPGPU, which completes operations such as ALU (arithmetic and logic unit), SFU (Special Function Units), and FPU (floating point unit). The number of SPs determines the parallelism of thread execution in a warp. Generally speaking, when the number of SPs is the same as the number of threads in a warp, the parallelism is highest, and all threads in the warp can be fully parallel during the execution phase.

[0062] It should be noted that, in this embodiment, the GPGPU also includes an error monitoring and correction circuit, that is, an error monitoring and correction mechanism is introduced to realize the monitoring and correction of decoding errors in the GPGPU instruction pipeline, for example Figure 3 A specific error monitoring and correction mechanism schematic diagram is shown, the error monitoring and correction circuit includes a check table, a comparison unit, a check code generation unit, a control unit and a majority voting decision unit, and the error monitoring and correction circuit is parallel to the instruction pipeline.

[0063] The instruction pipeline completes instruction fetching, that is, the instruction pipeline obtains the current instruction, and then the instruction pipeline decodes the current instruction to obtain the current decoded instruction of the current instruction. Further, the check code generation unit of the error monitoring and error correction circuit obtains the current decoded instruction of the current instruction in the instruction pipeline, and generates a check code to be judged for the current decoded instruction according to the check code generation rule; wherein the check code generation rule can specifically be an instruction compression rule, a CRC (Cyclic Redundancy Check, i.e., cyclic redundancy check code) generation rule, a hash function and other processing rules, or a user-defined rule, that is, the check code generation unit can perform instruction compression on the current decoded instruction to generate a check code to be judged for the current decoded instruction, or the check code generation unit can generate a corresponding cyclic redundancy check code based on the current decoded instruction, and determine the cyclic redundancy check code as the check code to be judged for the current decoded instruction, or the check code generation unit can use a hash function to process the current decoded instruction to generate a check code to be judged for the current decoded instruction.

[0064] Step S12: Obtaining a reference check code corresponding to the identification information of the current instruction from a check table.

[0065] The comparison unit in the error monitoring and correction circuit obtains a reference check code corresponding to the identification information of the current instruction from the check table.

[0066] In this embodiment, the step of obtaining the reference check code corresponding to the identification information of the current instruction from the check table includes: determining whether there is target identification information matching the identification information of the current instruction in the check table; if the target identification information exists in the check table, determining the check code corresponding to the target identification information as the reference check code corresponding to the identification information of the current instruction. It is understandable that the check table may contain target identification information matching the identification information of the current instruction, or may not contain target identification information matching the identification information of the current instruction. If the target identification information exists in the check table, the check code corresponding to the target identification information may be directly determined as the reference check code corresponding to the identification information of the current instruction.

[0067] In this embodiment, it also includes: if the target identification information does not exist in the check table, the to-be-judged check code of the current decoded instruction is determined as the benchmark check code of the current instruction, the identification information of the current instruction and the benchmark check code of the current instruction are saved in the check table, and a new current decoded instruction of the current instruction is obtained, and then the step of generating the to-be-judged check code of the current decoded instruction is re-judged. It should be noted that if the target identification information does not exist in the check table, it means that the corresponding check code needs to be stored in the check table first, that is, the identification information of the current instruction and the benchmark check code of the current instruction are saved in the check table, and a new current decoded instruction of the current instruction is generated by the decoding unit in the instruction pipeline, and the check code generation unit obtains the new current decoded instruction of the current instruction, and then the step of generating the to-be-judged check code of the current decoded instruction is re-judged, so that the benchmark check code of the current instruction is saved in the check table.

[0068] In this embodiment, the check table is used to store the mapping relationship between the identification information of each instruction and the benchmark check code of each instruction, wherein the identification information of the instruction is the program counter. The check table is used to store the check code generated by the check code generation unit after the decoded instruction and the identification information corresponding to the instruction, wherein the identification information can specifically be PC (Program Counter), that is, the mapping relationship between the identification information of each instruction and the benchmark check code of each instruction, for example Figure 4 The schematic diagram of a specific check table structure shown in the figure is composed of several entries, each of which is composed of identification information and a check code. When looking up the table, the check code of the corresponding instruction can be indexed according to the identification information. The number of entries in the check table is customized by the user. The more entries, the more instruction check codes can be stored, the more check instructions can be maintained, and the higher the check efficiency. However, at the same time, the more entries, the longer the check table lookup time. The user needs to design the optimal number to balance the check efficiency and the lookup time according to the needs.

[0069] Furthermore, the identification information of the current instruction and the benchmark check code of the current instruction are saved in the check table, including: determining the target storage partition corresponding to the type of the current instruction from the check table, and saving the identification information of the current instruction and the benchmark check code of the current instruction to the target storage partition in the check table; correspondingly, obtaining the benchmark check code corresponding to the identification information of the current instruction from the check table, including: determining the target storage partition corresponding to the type of the current instruction from the check table, and obtaining the benchmark check code corresponding to the identification information of the current instruction from the target storage partition; that is, when the identification information and the check code are stored in the check table, each storage partition can be established in advance according to the type of instruction, and the instruction can be saved in the corresponding storage partition according to the type of instruction. In this way, when performing a subsequent identification search, the identification search can be directly performed in the corresponding target storage partition, thereby significantly improving the search efficiency.

[0070] Step S13: If the reference check code and the to-be-judged check code are not the same, it is determined that the currently decoded instruction meets a preset error correction condition.

[0071] The comparison unit compares the check code to be judged generated by the check code generation unit with the reference check code of the same PC in the check table, and sends the comparison result to the control unit. It can be understood that after completing the instruction reading, the instruction fetch unit sends the identification information of the current instruction to the comparison unit, and the comparison unit looks up the table in the check table according to the PC and reads the corresponding reference check code. After the check code generation unit generates the check code, the generated check code to be judged is compared with the reference check code in the check table, and the comparison result is sent to the control unit. When the comparison results are inconsistent, the control unit will determine that the current decoded instruction meets the preset error correction condition.

[0072] Step S14: Obtain the next decoded instruction of the current instruction, and generate a verification check code for the next decoded instruction.

[0073] When the current decoded instruction meets the preset error correction condition, the decoding unit of the instruction pipeline generates the next decoded instruction of the current instruction, and the check code generation unit of the error monitoring and error correction circuit can obtain the next decoded instruction of the current instruction, and the check code generation unit generates the verification judgment check code of the next decoded instruction. Further, the decoding unit is responsible for generating decoded instructions corresponding to each instruction. If the decoding unit needs to generate multiple decoded instructions at the same time, these instructions can be prioritized first, that is, the decoding unit can generate decoded instructions of each current instruction to be generated in sequence according to the priority of each current instruction to be generated, ensuring that error detection and error correction of key instructions are prioritized.

[0074] In this embodiment, before obtaining the next decoded instruction of the current instruction, the method further includes: controlling the instruction pipeline to stop processing the current instruction. The control unit of the error monitoring and error correction circuit coordinates the scheduling unit of the instruction pipeline to complete the pause of the instruction pipeline, that is, controlling the instruction pipeline to stop processing the current instruction.

[0075] Step S15: Perform majority voting on the reference check code, the check code to be judged and the verification check code to obtain a target check code.

[0076] When the reference check code and the check code to be judged are different, the control unit will perform a second check code comparison after re-decoding the instruction pipeline and generating the verification judgment check code.

[0077] In this embodiment, the majority voting is performed on the reference check code, the check code to be judged and the verification check code to obtain the target check code, including: if the verification check code is the same as the reference check code, then the reference check code is judged to be the target check code; if the verification check code is the same as the check code to be judged, then the check code to be judged is judged to be the target check code.

[0078] The majority voting decision unit in the error monitoring and correction circuit is used in the error correction stage. In the error correction stage, the majority voting decision unit will perform a majority vote on the check code after three decodings. Because the probability of decoding errors is very small, the probability of decoding errors three times is almost negligible. Therefore, it is only necessary to take the majority value of the three checks to achieve error correction.

[0079] For example Figure 5 A specific majority voting decision unit structure diagram shown and Figure 6 A specific decision table diagram is shown, in which the majority voting decision unit is composed of two comparators and a arbiter. The comparator compares the third check code with the first and second check codes respectively, that is, the comparator compares the verification check code with the reference check code and the check code to be judged respectively, and outputs the comparison result to the arbiter. After the arbiter completes the decision, it writes the check code and PC of the winning result into the check table. Figure 6 The dotted part of the decision table is an impossible result, because when entering the decision process, the reference check code must be different from the check code to be judged, so rs0 (that is, the comparison result of the reference check code and the check code to be judged) is 0, and the situation where the three check codes are different and the three check codes are the same is also impossible. Therefore, the decision table actually has only two situations (that is Figure 6The red part in the middle) appears, that is, the verification determination check code is the same as the reference check code or the verification determination check code is the same as the check code to be judged, which greatly simplifies the decision circuit and reduces the area and power consumption. It can be understood that if the verification determination check code is the same as the reference check code, the reference check code is determined to be the target check code. On the contrary, if the verification determination check code is the same as the check code to be judged, the check code to be judged is determined to be the target check code.

[0080] In this embodiment, after determining that the check code to be judged is the target check code, it also includes: using the target check code to overwrite the reference check code corresponding to the identification information of the current instruction in the check table to complete the update of the check table. It should be noted that if the check code to be judged is determined to be the target check code, it means that the reference check code stored in the check table is inaccurate, so it is necessary to overwrite the reference check code corresponding to the identification information of the current instruction in the check table with the target check code to complete the update of the check table, that is, replace the reference check code with the check code to be judged, so that the check code to be judged becomes the new reference check code, thereby ensuring that when the new reference check code is used as the reference to monitor whether there is an error in the subsequent decoding, the result obtained is accurate.

[0081] Step S16: Determine the decoded instruction corresponding to the target check code as the target decoded instruction of the current instruction.

[0082] It can be understood that the decoded instruction corresponding to the target check code finally determined by the majority voting decision unit is the correct decoded instruction, that is, the target decoded instruction; it can be understood that when the check code to be judged is the target check code, the current decoded instruction is directly determined as the target decoded instruction, and when the benchmark check code is the target check code, two methods can be used to obtain the target decoded instruction. The first method is that if the benchmark check code is the target check code, it means that the verification check code is the same as the benchmark check code, and the decoded instruction corresponding to the verification check code can be determined as the target decoded instruction, that is, the next decoded instruction is determined as the target decoded instruction. The second method is that the decoded instruction corresponding to the benchmark check code can be pre-stored, so that the decoded instruction corresponding to the benchmark check code can be determined as the target decoded instruction of the current instruction.

[0083] In this embodiment, after determining the decoded instruction corresponding to the target check code as the target decoded instruction of the current instruction, the method further includes: controlling the instruction pipeline to execute the processing flow of the current instruction. The control unit of the error monitoring and error correction circuit coordinates the scheduling unit of the instruction pipeline to complete the recovery of the instruction pipeline, that is, controlling the instruction pipeline to execute the processing flow of the current instruction.

[0084] The control unit coordinates the instruction pipeline scheduling unit to complete the suspension and resumption of the pipeline. The pipeline scheduling unit receives the signal from the error monitoring and error correction circuit control unit, suspends the pipeline when decoding errors and error corrections occur, and resumes the pipeline operation after the error correction is completed.

[0085] The beneficial effects of the present application are as follows: the present application is applied to a general computing graphics processing unit, including: obtaining a current decoded instruction of a current instruction in an instruction pipeline, and generating a to-be-judged check code of the current decoded instruction; obtaining a reference check code corresponding to the identification information of the current instruction from a check table; if the reference check code and the to-be-judged check code are not the same, determining that the current decoded instruction meets a preset error correction condition; obtaining a next decoded instruction of the current instruction, and generating a verification judgment check code of the next decoded instruction; performing a majority vote on the reference check code, the to-be-judged check code and the verification judgment check code to obtain a target check code; determining the decoded instruction corresponding to the target check code as the target decoded instruction of the current instruction. It can be seen that the present application utilizes the characteristic of GPGPU that instructions are repeated in time when scheduling different thread bundles, and realizes decoding error monitoring of the instruction pipeline through a check table and a check code. That is, the check table stores the identification information and check code of the instruction, and error monitoring is realized by table lookup verification of repeated instructions. That is, if the reference check code is different from the check code to be judged, then the current decoded instruction meets the preset error correction condition. Further, after the decoding error is detected, that is, when the current decoded instruction meets the preset error correction condition, the decoding error is corrected by multiple re-decoding and voting of multiple decoding results. That is, the next decoded instruction of the current instruction is obtained, and a verification judgment check code of the next decoded instruction is generated. The reference check code, the check code to be judged, and the verification judgment check code are voted by majority to obtain the target check code. Error monitoring and correction can be realized at a lower computing cost, which not only reduces the soft error rate, but also avoids operation errors and system interruptions, and improves operation accuracy and efficiency.

[0086] Below Figure 7 The present application is described accordingly by taking a specific error monitoring and error correction implementation flowchart shown in FIG. 1 as an example. After completing the instruction fetch, the instruction fetch unit of the instruction pipeline sends the current instruction to the decoding unit, and sends the PC of the current instruction to the comparison unit of the error monitoring and error correction circuit. After the decoding unit generates the current decoded instruction of the current instruction, it sends the current decoded instruction to the buffer (cache) and the check code generation unit of the error monitoring and error correction circuit to perform the following error monitoring and error correction process:

[0087] 1) The check code generation unit obtains the current decoded instruction of the current instruction in the instruction pipeline, generates the check code to be judged of the current decoded instruction, and sends the check code to be judged to the comparison unit;

[0088] 2) The comparison unit obtains the reference check code corresponding to the PC of the current instruction from the check table, and compares the check code to be judged with the reference check code, that is, compares the check code generated by the check code generation unit with the check code in the check table;

[0089] 3) If the results match, that is, if the reference check code and the check code to be judged are the same, it means that the current decoding information is correct, and the instruction pipeline continues to enter the execution stage and start executing instructions;

[0090] 4) If the comparison unit does not find the check code corresponding to the current PC value in the check table, it means that the current instruction is executed for the first time. At this time, the control unit coordinates the pipeline scheduling unit to pause the instruction pipeline and execute step 10);

[0091] 5) If the reference check code and the check code to be judged are not the same, it is determined that the current decoded instruction meets the preset error correction condition. In other words, if the results do not match, it means that there may be errors in the current decoding information, and the error correction stage is entered. At this time, the control unit coordinates the pipeline scheduling unit to pause the instruction pipeline and executes steps 6) to 9) for error correction;

[0092] 6) The control unit sends the check code in the check table and the check code generated this time together with the PC value to the majority voting decision unit, that is, the reference check code, the check code to be judged and the identification information of the current instruction are sent to the majority voting decision unit;

[0093] 7) The control unit controls the decoding unit of the instruction pipeline to re-decode the current instruction, and the check code generation unit regenerates the check code, and the check code generated this time is also sent to the majority voting decision unit, that is, the check code generation unit obtains the next decoded instruction of the current instruction, and generates the verification and judgment check code of the next decoded instruction, and sends the reference check code, the check code to be judged and the verification and judgment check code to the majority voting decision unit;

[0094] 8) The majority voting unit performs majority voting on the three groups of check codes sent in, takes the result as the correct check code, and writes it together with the PC into the check table to overwrite the original entry, that is, the majority voting unit performs majority voting on the reference check code, the check code to be judged, and the verification check code to obtain the target check code, and uses the target check code to overwrite the reference check code corresponding to the identification information of the current instruction in the check table to complete the update of the check table;

[0095] 9) After the majority voting decision unit completes the decision and the check code is written, the control unit sends the correct decoded instruction to the instruction pipeline, restores the pipeline, and starts to execute the instruction, that is, after determining the decoded instruction corresponding to the target check code as the target decoded instruction of the current instruction, the control unit controls the instruction pipeline to execute the processing flow of the current instruction;

[0096] 10) If the target identification information does not exist in the check table, the to-be-judged check code of the current decoded instruction is determined as the reference check code of the current instruction, the identification information of the current instruction and the reference check code of the current instruction are saved in the check table, and the new current decoded instruction of the current instruction is obtained, and then the process jumps to the step of generating the to-be-judged check code of the current decoded instruction again; the specific steps are as follows:

[0097] 10.1) The control unit writes the generated verification code to be judged together with the PC into the verification table;

[0098] 10.2) The control unit controls the pipeline decoding unit to re-decode the current instruction to obtain a new current decoded instruction, and the check code generation unit regenerates a new check code and sends it to the comparison unit;

[0099] 10.3) The comparison unit searches the checksum table according to the PC of the current instruction, and compares the new checksum generated by the checksum generation unit with the checksum in the checksum table;

[0100] 10.4) If the results match, it means that the new current decoded instruction is correct, and the instruction pipeline continues to enter the execution stage and start executing the instruction;

[0101] 10.5) If the result does not match, it means that the new current decoded instruction may have an error and enters the error correction stage. At this time, the control unit coordinates the pipeline scheduling unit to pause the instruction pipeline and executes steps 6)~9) for error correction.

[0102] See also Figure 8 As shown, the embodiment of the present application discloses a decoding error correction device for an instruction pipeline, which is applied to a general computing graphics processing unit, including:

[0103] The first check code acquisition module 11 is used to acquire the current decoded instruction of the current instruction in the instruction pipeline and generate a check code to be judged of the current decoded instruction.

[0104] The second verification code acquisition module 12 is used to acquire a reference verification code corresponding to the identification information of the current instruction from the verification table.

[0105] The error correction condition judgment module 13 is used to judge whether the currently decoded instruction meets the preset error correction condition if the reference check code and the check code to be judged are different.

[0106] The third check code acquisition module 14 is used to acquire the next decoded instruction of the current instruction and generate a verification check code for the next decoded instruction.

[0107] The voting and decision module 15 is used to perform majority voting on the reference check code, the check code to be judged and the verification and judgment check code to obtain a target check code.

[0108] The decoding instruction error correction module 16 is used to determine the decoded instruction corresponding to the target check code as the target decoded instruction of the current instruction.

[0109] The beneficial effects of the present application are as follows: the present application is applied to a general computing graphics processing unit, including: obtaining a current decoded instruction of a current instruction in an instruction pipeline, and generating a to-be-judged check code of the current decoded instruction; obtaining a reference check code corresponding to the identification information of the current instruction from a check table; if the reference check code and the to-be-judged check code are not the same, determining that the current decoded instruction meets a preset error correction condition; obtaining a next decoded instruction of the current instruction, and generating a verification judgment check code of the next decoded instruction; performing a majority vote on the reference check code, the to-be-judged check code and the verification judgment check code to obtain a target check code; determining the decoded instruction corresponding to the target check code as the target decoded instruction of the current instruction. It can be seen that the present application utilizes the characteristic of GPGPU that instructions are repeated in time when scheduling different thread bundles, and realizes decoding error monitoring of the instruction pipeline through a check table and a check code. That is, the check table stores the identification information and check code of the instruction, and error monitoring is realized by table lookup verification of repeated instructions. That is, if the reference check code is different from the check code to be judged, then the current decoded instruction meets the preset error correction condition. Further, after the decoding error is detected, that is, when the current decoded instruction meets the preset error correction condition, the decoding error is corrected by multiple re-decoding and voting of multiple decoding results. That is, the next decoded instruction of the current instruction is obtained, and a verification judgment check code of the next decoded instruction is generated. The reference check code, the check code to be judged, and the verification judgment check code are voted by majority to obtain the target check code. Error monitoring and correction can be realized at a lower computing cost, which not only reduces the soft error rate, but also avoids operation errors and system interruptions, and improves operation accuracy and efficiency.

[0110] Furthermore, an embodiment of the present application also provides an electronic device. Fig. 9 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0111] Fig. 9A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the decoding and error correction method of the instruction pipeline executed by the electronic device disclosed in any of the aforementioned embodiments.

[0112] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0113] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0114] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222 and data 223, etc. The storage method can be temporary storage or permanent storage.

[0115] Among them, the operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device to realize the operation and processing of the massive data 223 in the memory 22 by the processor 21, which can be Windows, Unix, Linux, etc. In addition to including a computer program that can be used to complete the decoding and error correction method of the instruction pipeline executed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks. In addition to data transmitted from an external device received by the electronic device, the data 223 can also include data collected by its own input and output interface 25.

[0116] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the decoding error correction method of the instruction pipeline disclosed above is implemented. The specific steps of the method can refer to the corresponding contents disclosed in the above embodiments, and will not be repeated here.

[0117] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0118] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application. The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly with hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable EPROM (Erasable Programmable Read Only Memory), electrically erasable programmable EEPROM (Electrically Erasable Programmable read only memory), register, hard disk, removable disk, CD-ROM (Compact Disc Read-Only Memory), or any other form of storage medium known in the technical field.

[0119] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0120] The above is a detailed introduction to the decoding and error correction method, device, equipment and medium of the instruction pipeline provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A decoding error correction method for an instruction pipeline, characterized in that: Applications in general-purpose computing graphics processing units, including: Obtaining a current decoded instruction of a current instruction in the instruction pipeline, and generating a check code to be judged of the current decoded instruction; Acquire a reference check code corresponding to the identification information of the current instruction from a check table; If the reference check code and the to-be-judged check code are not the same, it is determined that the currently decoded instruction meets a preset error correction condition; Obtaining a next decoded instruction of the current instruction, and generating a verification check code of the next decoded instruction; Performing majority voting on the reference check code, the check code to be judged, and the verification check code to obtain a target check code; A decoded instruction corresponding to the target check code is determined as a target decoded instruction of the current instruction.

2. The decoding error correction method of the instruction pipeline according to claim 1, characterized in that: The obtaining, from the check table, a reference check code corresponding to the identification information of the current instruction includes: Determine whether there is target identification information matching the identification information of the current instruction in the verification table; If the target identification information exists in the verification table, the verification code corresponding to the target identification information is determined as a reference verification code corresponding to the identification information of the current instruction.

3. The decoding error correction method of the instruction pipeline according to claim 2, characterized in that: Also includes: If the target identification information does not exist in the verification table, the verification code to be judged of the current decoded instruction is determined as the benchmark verification code of the current instruction, the identification information of the current instruction and the benchmark verification code of the current instruction are saved in the verification table, and the new current decoded instruction of the current instruction is obtained, and then the step of generating the verification code to be judged of the current decoded instruction is jumped again.

4. The decoding error correction method of the instruction pipeline according to claim 2, characterized in that: The check table is used to store the mapping relationship between the identification information of each instruction and the reference check code of each instruction, wherein the identification information of the instruction is a program counter.

5. The decoding error correction method of the instruction pipeline according to claim 1, characterized in that: Before obtaining the next decoded instruction of the current instruction, the method further includes: Controlling the instruction pipeline to stop processing the current instruction; Correspondingly, after determining the decoded instruction corresponding to the target check code as the target decoded instruction of the current instruction, the method further includes: The instruction pipeline is controlled to execute a processing flow for the current instruction.

6. The decoding error correction method of the instruction pipeline according to any one of claims 1 to 5, characterized in that: The step of performing majority voting on the reference check code, the check code to be judged, and the verification check code to obtain a target check code includes: If the verification determination check code is the same as the reference check code, determining that the reference check code is the target check code; If the verification determination check code is the same as the check code to be judged, the check code to be judged is determined to be the target check code.

7. The decoding error correction method of the instruction pipeline according to claim 6, characterized in that: After determining that the check code to be judged is a target check code, the method further includes: The target check code is used to overwrite the reference check code corresponding to the identification information of the current instruction in the check table, so as to complete the update of the check table.

8. A decoding error correction device for an instruction pipeline, characterized in that: Applications in general-purpose computing graphics processing units, including: A first check code acquisition module is used to acquire a current decoded instruction of a current instruction in the instruction pipeline, and generate a check code to be judged of the current decoded instruction; A second verification code acquisition module, used to obtain a reference verification code corresponding to the identification information of the current instruction from a verification table; An error correction condition judgment module, used for judging whether the currently decoded instruction satisfies a preset error correction condition if the reference check code and the check code to be judged are different; A third check code acquisition module, used to acquire the next decoded instruction of the current instruction and generate a verification check code for the next decoded instruction; A voting and decision module is used to perform majority voting on the reference check code, the check code to be judged and the verification check code to obtain a target check code; The decoding instruction error correction module is used to determine the decoded instruction corresponding to the target check code as the target decoded instruction of the current instruction.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the instruction pipeline decoding and error correction method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the decoding and error correction method of the instruction pipeline as described in any one of claims 1 to 7 are implemented.

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