Processor based on RISC-V architecture, data processing system and method

Abstract

The invention provides a processor based on an RISC-V architecture and a data processing system and method. The processor comprises an instruction obtaining unit, an instruction decoding unit, a register file, a distribution unit, an execution unit, an expansion processing unit and a data access interface. Decoding the program instruction to obtain an instruction type and an application field type; identifying an application field type, distributing the program instruction to an execution unit and an expansion processing unit according to a preset distribution rule under the condition that the application field type accords with a preset field type, and identifying an instruction type under the condition that the application field type does not accord with the preset field type; when the instruction type of the program instruction is an RISC-V instruction set instruction, the RISC-V instruction set instruction is distributed to the execution unit, and when the instruction type of the program instruction is an extension instruction, the extension instruction is distributed to the extension processing unit; the instruction can be quickly processed for different application fields, and the instruction processing efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the semiconductor field, and in particular to a processor, a data processing system, and a method based on a RISC-V architecture. Background Art

[0002] In processors based on the RISC-V architecture, the distribution unit distributes RISC-V instruction set instructions and extended instructions to different processing units for data processing according to the instruction type. Fixed instructions are often required for different application fields, and these fixed instructions still need to be decoded and analyzed one by one before being distributed, resulting in reduced instruction processing efficiency. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The purpose of this application is to solve one of the technical problems existing in the related art to at least a certain extent. The embodiments of this application provide a processor, a data processing system and a method based on the RISC-V architecture, which can improve the instruction processing efficiency for a variety of different application fields.

[0005] An embodiment of the first aspect of the present application, a processor based on RISC-V architecture, includes: An instruction fetch unit, for reading program instructions; An instruction decoding unit, used for decoding the program instruction to obtain an instruction type and an application field type; Register file, including several registers defined by the instruction architecture, used for data interaction during the execution of program instructions; a distribution unit, configured to identify an application domain type, distribute the program instruction to an execution unit and an extended processing unit according to a preset distribution rule when the application domain type conforms to a preset domain type, identify an instruction type when the application domain type does not conform to the preset domain type, distribute the RISC-V instruction set instruction to the execution unit when the instruction type of the program instruction is a RISC-V instruction set instruction, and distribute the extended instruction to the extended processing unit when the instruction type of the program instruction is an extended instruction; An execution unit, configured to execute the RISC-V instruction set instruction and return a first execution result; An extended processing unit, used for executing the extended instruction and returning a second execution result; A data access interface is used to perform read and write operations on the first execution result and the second execution result.

[0006] According to some embodiments of the first aspect of the present application, the expansion processing unit includes: An extended interface, which is an interface for data interaction with the distribution unit, and is used to distribute the extended instruction to one of the control and status register, the register data temporary storage unit, and the extended instruction distribution and recycling unit for read and write operations according to the operation type of the extended instruction; Control and status registers, used to store control parameters and status parameters of the processor system; A register data temporary storage unit, used to store register data of extended instructions, store instruction execution result data of the register operation execution unit, store data operation execution unit and store advanced function execution unit; An extended instruction distribution and recycling unit, used for distributing the extended instruction to one of the register operation execution unit, the storage data operation execution unit and the storage advanced function execution unit for execution according to the operation type of the extended instruction; A register operation execution unit, configured to, after receiving the extended instruction, obtain source data from the register data temporary storage unit, read auxiliary information from the control and status register, perform corresponding operations on the register data according to the operation type of the extended instruction, and obtain instruction execution result data; A storage data operation execution unit, configured to read data from the storage space starting from the source address of the storage space through the data reading unit after receiving the extended instruction, and perform corresponding data function operations according to the operation type of the extended instruction to obtain instruction execution result data; A storage high-level function execution unit is used to read data from the storage space starting from the source address of the storage space and the comparison data source address through the data reading unit after receiving the extended instruction, and perform corresponding functional operations according to the operation type of the extended instruction to obtain instruction execution result data; A data reading unit, used for generating an address and a data length, and reading data of a specified data length from a storage space via a data access interface of an expansion unit; A data writing unit is used to generate an address and a data length, and write data of a specified data length into the storage space via the expansion unit data access interface; The expansion unit data access interface is used to convert data read and write requests into data access requests that comply with the bus protocol.

[0007] An embodiment of the second aspect of the present application is a data processing system based on the RISC-V architecture, comprising: A processor based on the RISC-V architecture as described in the embodiment of the first aspect of the present application, configured to determine the type of a program instruction read, and execute the program instruction according to the determination result, and perform read and write operations on stored data; A first storage module, used for storing program instructions and program data; The second storage module is used to store the preset data, intermediate processing data and result data of each module; A cache module, used to cache read and write data of the processor based on the RISC-V architecture; A first control module, used for controlling an external device; A storage accessor is used to perform data transfer operations under the control of the processor based on the RISC-V architecture.

[0008] According to some embodiments of the second aspect of the present application, the first storage module includes: A low-latency instruction memory, which is a static random access memory for storing program instructions and is accessed by the processor based on the RISC-V architecture; The low-latency data memory is a static random access memory used to store program data and is accessed by the processor based on the RISC-V architecture.

[0009] According to some embodiments of the second aspect of the present application, the second storage module includes: System memory, used to store intermediate processing data of each module; A read-only memory, used for storing preset data; Non-volatile memory, used to store result data.

[0010] According to some embodiments of the second aspect of the present application, the cache module includes: An instruction cache, used to cache data read by the RISC-V architecture-based processor from the system memory or the read-only memory; A data cache is used to cache data read and written by the processor based on the RISC-V architecture to the system memory.

[0011] An embodiment of the third aspect of the present application is a data processing method, which is applied to a processor based on the RISC-V architecture as described in the embodiment of the first aspect of the present application, and the method includes: Reading program instructions through an instruction fetch unit; Decoding the program instruction by an instruction decoding unit to obtain a decoding result, and storing the decoding result in a register file, wherein the decoding result includes an instruction type and an application field type; Reading the decoding result from the register stack through a distribution unit, identifying the application domain type, distributing the program instruction to the execution unit and the extended processing unit according to a preset distribution rule when the application domain type conforms to the preset domain type, identifying the instruction type when the application domain type does not conform to the preset domain type, distributing the RISC-V instruction set instruction to the execution unit when the instruction type of the program instruction is a RISC-V instruction set instruction, and distributing the extended instruction to the extended processing unit when the instruction type of the program instruction is an extended instruction; Execute the RISC-V instruction set instruction through the execution unit, and return a first execution result; Executing the extended instruction through the extended processing unit and returning a second execution result; The first execution result and the second execution result are read and written through a data access interface.

[0012] According to certain embodiments of the third aspect of the present application, when the application domain type conforms to a preset domain type, distributing the program instructions to the execution unit and the extended processing unit according to a preset distribution rule includes: Determining a preset distribution rule corresponding to the application field type from a rule table stored in a system memory; Distributing a first program instruction in the program instructions to the execution unit, wherein the identification code of the first program instruction corresponds to the identification code of the first identification code set in the preset distribution rule; A second program instruction in the program instructions is distributed to the extended processing unit, wherein the identification code of the second program instruction corresponds to the identification code of the second identification code set in the preset distribution rule.

[0013] According to some embodiments of the third aspect of the present application, executing the extended instruction by an extended processing unit includes: receiving, via an extended interface, an extended instruction distributed by the distribution unit, and determining an instruction type of the extended instruction; When the type of the extended instruction is control and status register access, the control parameters and status parameters of the processor system are read or written to the control and status register through the extended interface, and a response message indicating that the instruction is completed is returned; When the type of the extended instruction is execution type, the operation type and the immediate value in the extended instruction are sent to the extended instruction distribution and recovery unit through the extended interface, and the source register data and the destination register identification number in the extended instruction are written into the register data temporary storage unit; Determining the operation type of the extended instruction by the extended instruction distribution and recovery unit; When the operation type of the extended instruction is a register operation extended instruction, the source data is obtained from the register data temporary storage unit through the register operation execution unit, the auxiliary information is read from the control and status register, and the corresponding operation is performed on the register data according to the operation type of the extended instruction to obtain instruction execution result data, the instruction execution result data is written into the destination register of the register data temporary storage unit, and the response information of instruction completion is returned to the extended instruction distribution and recovery unit; When the operation type of the extended instruction is a storage data operation extended instruction, the storage data operation execution unit uses the data reading unit to read data from the storage space starting from the source address of the storage space, and performs corresponding data function operations according to the operation type of the extended instruction to obtain instruction execution result data, write the instruction execution result data into the destination register of the register data temporary storage unit, and return instruction completion response information to the extended instruction distribution and recovery unit; When the operation type of the extended instruction is to store an advanced function extended instruction, the advanced function execution unit uses the data reading unit to read data from the storage space starting from the source address of the storage space and the comparison data source address, and performs corresponding functional operations according to the operation type of the extended instruction to obtain instruction execution result data, write the instruction execution result data into the destination register of the register data temporary storage unit, and return instruction completion response information to the extended instruction distribution and recovery unit.

[0014] An embodiment of the fourth aspect of the present application is a data processing method, which is applied to the data processing system based on the RISC-V architecture as described in the embodiment of the second aspect of the present application, and the method includes: When the data processing system is powered on and reset, the startup program instruction is read by a processor based on the RISC-V architecture, and the startup program instruction is executed; Using the first control module, the processor based on the RISC-V architecture reads the running program instructions from the external memory; By means of the processor based on the RISC-V architecture, according to the running program instruction, jumping from executing the startup program to executing the running program, and reading the program instruction from the first storage module; The type of the program instruction is determined by the processor based on the RISC-V architecture, and the program instruction is executed according to the determination result, and the stored data is read and written to obtain the processing result and return the processing result, and then the next program instruction is executed.

[0015] The above scheme has at least the following beneficial effects: obtaining the instruction type and the application field type by decoding the program instruction; identifying the application field type, distributing the program instruction to the execution unit and the extended processing unit according to the preset distribution rule when the application field type conforms to the preset field type, identifying the instruction type when the application field type does not conform to the preset field type, distributing the RISC-V instruction set instruction to the execution unit when the instruction type of the program instruction is a RISC-V instruction set instruction, and distributing the extended instruction to the extended processing unit when the instruction type of the program instruction is an extended instruction; being able to quickly process instructions for different application fields, thereby improving the instruction processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0017] Figure 1 This is a block diagram of a data processing system based on the RISC-V architecture; Figure 2 This is a block diagram of a processor based on the RISC-V architecture; Figure 3 is a structural diagram of an extended processing unit; Figure 4 is a step diagram of a data processing method applied to a data processing system based on a RISC-V architecture; Figure 5 is a step diagram of a data processing method applied to a processor based on the RISC-V architecture; Figure 6 is a diagram of steps for a distribution unit to distribute program instructions to execution units and extended processing units; Figure 7 It is a step diagram of the extended processing unit executing the extended instruction. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims or the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0020] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0021] An embodiment of the present application provides a processor based on the RISC-V architecture.

[0022] Reference Figure 2 ,The processor includes an instruction fetch unit, an instruction decoding unit, a register file, a distribution unit, an execution unit, an extended processing unit and a data access interface.

[0023] Among them, the instruction acquisition unit is used to read the program instructions; the instruction decoding unit is used to decode the program instructions to obtain the instruction type and the application field type; the register stack includes a number of registers defined by the instruction architecture, which are used for data interaction during the execution of the program instructions; the distribution unit is used to identify the application field type, and distribute the program instructions to the execution unit and the extended processing unit according to the preset distribution rules when the application field type conforms to the preset field type, and identify the instruction type when the application field type does not conform to the preset field type, and distribute the RISC-V instruction set instructions to the execution unit when the instruction type of the program instruction is a RISC-V instruction set instruction, and distribute the extended instruction to the extended processing unit when the instruction type of the program instruction is an extended instruction; the execution unit is used to execute the RISC-V instruction set instruction and return a first execution result; the extended processing unit is used to execute the extended instruction and return a second execution result; the data access interface is used to read and write the first execution result and the second execution result.

[0024] In this embodiment, instructions can be quickly processed for different application fields, thereby improving instruction processing efficiency.

[0025] The extended processing unit uses the processor's data access interface to read or write data in the system memory via the data cache, or directly access the low-latency data memory. The external associated modules read by the instruction acquisition unit include low-latency instruction memory, instruction cache, system memory, etc., and the above modules are used to store instructions. The register stack is an internal module of the processor, which contains a certain number of registers defined by the instruction architecture, such as 32 registers, which are used for data interaction during instruction execution. The distribution unit is an internal module of the processor, which is responsible for sending instructions and data to the executor, such as the execution unit or the extended processing unit, according to the instruction function. The external associated modules read by the data access interface include low-latency data memory, data cache, system memory, etc., and the above modules are used to store data. The extended processing unit is an internal module of the processor and processes customized data storage instructions.

[0026] Reference Figure 3 The extended processing unit includes an extended interface, a control and status register, a register data temporary storage unit, an extended instruction distribution and recovery unit, a register operation execution unit, a storage data operation execution unit, a storage advanced function execution unit, a data reading unit, a data writing unit and an extended unit data access interface.

[0027] Among them, the extended interface is an interface for data interaction with the distribution unit, and is used to distribute the extended instruction to one of the control and status register, the register data temporary storage unit, and the extended instruction distribution and recovery unit for read and write operations according to the operation type of the extended instruction. The control and status register is used to store the control parameters and status parameters of the processor system. The register data temporary storage unit is used to store the register data of the extended instruction, and store the instruction execution result data of the register operation execution unit, the storage data operation execution unit, and the storage advanced function execution unit. The extended instruction distribution and recovery unit is used to distribute to one of the register operation execution unit, the storage data operation execution unit, and the storage advanced function execution unit for execution according to the operation type of the extended instruction. The register operation execution unit is used to obtain source data from the register data temporary storage unit after receiving the extended instruction, read auxiliary information from the control and status register, and perform corresponding operations on the register data according to the operation type of the extended instruction to obtain instruction execution result data. The storage data operation execution unit is used to read data from the storage space starting from the source address of the storage space through the data reading unit after receiving the extended instruction, and perform corresponding data function operations according to the operation type of the extended instruction to obtain instruction execution result data. The storage high-level function execution unit is used to read data from the storage space starting from the source address of the storage space and the comparison data source address through the data reading unit after receiving the extended instruction, and perform the corresponding functional operation according to the operation type of the extended instruction to obtain the instruction execution result data. The data reading unit is used to generate the address and data length, and read the data of the specified data length from the storage space through the extended unit data access interface. The data writing unit is used to generate the address and data length, and write the data of the specified data length to the storage space through the extended unit data access interface. The extended unit data access interface is used to convert the data read and write request into the data access request that conforms to the bus protocol.

[0028] Furthermore, the extended interface is an interface for interacting with the distribution unit in the processor, transmitting instructions and data to be processed, and for accessing the control and status register, the register data temporary storage unit or the extended instruction distribution and recovery unit, and obtaining the returned processed data and results from these three modules. The control and status register is a register module of the extended processing unit, including configurable information. The program controls the functions of the extended processing unit by setting the register through instructions. It also includes the storage of status information. The program can obtain the status of the extended processing unit by reading the register through instructions. The extended instruction distribution and recovery unit distributes the instruction to the appropriate execution object according to the instruction type, receives the data and results returned by the execution object, and then returns it to the processor via the extended interface. The register data temporary storage unit is a register used internally by the extension, storing the data transmitted by the processor and the data after the extended processing unit completes the processing. The register operation execution unit obtains source data from the register data temporary storage unit, reads other auxiliary information from the control and status register, such as the starting bit of the partial bit and the number of bits of the partial bit, and performs corresponding operations on the register data according to the operation type, such as partial bit comparison, partial bit addition and subtraction, count 1 operation, count 0 operation, etc. After completion, the result data is written to the destination register of the register data temporary storage unit, and a completion response is issued to the extended instruction distribution and recovery unit. The storage data operation execution unit starts from the source address of the storage space, reads data from the storage space through the data reading unit, and performs corresponding data function operations, such as copying the storage space, resetting the storage space, counting the storage space setting value, searching the first setting value position of the storage space, etc. If there is a destination address, the processed data is written to the storage space starting from the destination address of the storage space through the data writing unit, and the execution is repeated until all data processing within the data length range is completed. If there is a destination register identifier, the obtained processing information is returned to the destination register of the register data temporary storage unit, and a completion response is issued to the extended instruction distribution and recovery unit. The storage advanced function execution unit obtains the source address, data length, destination address or destination register identifier from the register data temporary storage unit, and reads other auxiliary information from the control and status register, such as comparison source address and search conditions. The data reading unit is used to generate the address and data length, and reads data of the specified data length from the storage space (including the address space of system memory, low-latency data storage, non-volatile memory and flash memory, etc.) through the data access interface of the expansion unit. The data writing unit is used to generate the address and data length, and write data of the specified data length to the storage space (including the address space of system memory, low-latency data storage, non-volatile memory and flash memory, etc.) through the data access interface of the expansion unit.

[0029] An embodiment of the present application provides a data processing system based on the RISC-V architecture.

[0030] Reference Figure 1 The data processing system includes a processor based on the RISC-V architecture, a first storage module, a second storage module, a cache module, a first control module and a storage accessor.

[0031] Among them, the processor based on the RISC-V architecture is used to judge the type of program instructions read, execute the program instructions according to the judgment result, and perform read and write operations on the stored data; the first storage module is used to store program instructions and program data; the second storage module is used to store preset data, intermediate processing data and result data of each module; the cache module is used to cache the read and write data of the processor based on the RISC-V architecture; the first control module is used to control external devices; the storage accessor is used to perform data transmission operations under the control of the processor based on the RISC-V architecture.

[0032] In the data processing system, a bus is set up, and each module is connected to the bus. The bus is the channel for data and control transmission inside the chip. Each module communicates in accordance with a consistent bus protocol. A reset control module and a clock control module are set up. The reset signal of each module is controlled by the reset control module; the clock signal of each module is controlled by the clock module, such as frequency division, clock shutdown, etc.

[0033] The memory access device is a direct memory access device (DMA). The processor controls the direct memory access device to perform data transfer operations, read data from one address, and write the data to another address.

[0034] The first storage module includes a low-latency instruction memory and a low-latency data memory. The low-latency instruction memory is a static random access memory for storing program instructions and is directly accessed by the processor with short latency; the low-latency data memory is a static random access memory for storing program data and is directly accessed by the processor with short latency.

[0035] The second storage module includes system memory, read-only memory and non-volatile memory. The system memory is used to store the data of each module and the intermediate results of operation; the read-only memory is used to store the preset program. When powered on, the processor reads the preset program from the read-only memory and executes it; the non-volatile memory is used to store some important information in the system.

[0036] Furthermore, the system memory is a static random access memory inside the chip that is provided to each module in the system, or a dynamic random access memory outside the chip with the same purpose or other forms of memory outside the chip, which is used to store data and intermediate results of operation. Read-only memory is a memory that is written with specific data when the chip is manufactured. During the operation of the chip, data can only be read from the read-only memory and cannot be written again. The data remains unchanged when the system is powered off. It is generally used to store the program when the chip is powered on, and the processor reads the program instructions from it and executes them. The data of non-volatile memory remains unchanged when the system is powered off, but the storage capacity is relatively small. It is used to store a small amount of important information in the system.

[0037] The cache module includes instruction cache and data cache. The instruction cache is used to cache some instructions read by the processor from the system memory or read-only memory; the data cache is used to cache some data read and written by the processor from the system memory.

[0038] The instructions read by the processor from the system memory or read-only memory are partially cached in the instruction cache; the data read and written by the processor from the system memory are partially cached in the data cache. The instruction cache and data cache can be a one-level, two-level, or multi-level structure.

[0039] The first control module includes a main control interface controller and a flash memory interface controller. The main control interface controller is used to control the interface of the external main control and process the interface protocol; the flash memory interface controller is used to control the external flash memory. The flash memory interface controller controls the external NAND Flash memory chip, which is a large-capacity data storage chip.

[0040] An embodiment of the present application provides a data processing method, which is applied to a data processing system based on a RISC-V architecture.

[0041] Reference Figure 4 , the data processing method includes but is not limited to the following steps: When the data processing system is powered on and reset, the boot program instructions are read and executed by the processor based on the RISC-V architecture; Using a first control module, a processor based on a RISC-V architecture reads program instructions from an external memory; By using a processor based on the RISC-V architecture, jumping from executing the startup program to executing the running program according to the running program instruction, and reading the program instruction from the first storage module; The type of program instruction is judged by a processor based on the RISC-V architecture, and the program instruction is executed according to the judgment result, and the stored data is read and written to obtain and return the processing result, and then the next program instruction is executed.

[0042] Specifically, after the system is powered on, the processor based on the RISC-V architecture reads the startup program instructions from the read-only memory or other non-volatile memory and executes the instructions; the processor based on the RISC-V architecture initializes the flash memory interface controller; the processor based on the RISC-V architecture sends a command to the flash memory interface controller to read the running program instructions from the flash memory, or other non-volatile memory to read the running program instructions, and sets the location for storing the running program; generally, the running program instructions are transmitted through the bus and written to the system memory or other low-latency instruction memory; the processor based on the RISC-V architecture jumps from the startup program to the execution of the running program, and reads the instructions from the system memory or other low-latency instruction memory. The instructions are divided into RISC-V instruction set instructions and data storage extension instructions, data storage extension instructions include register operation extension instructions, storage data operation extension instructions and storage advanced function extension instructions; during the execution of instruction set instructions, it is sometimes necessary to read or write data from the system memory through the data cache, or directly write or read data from the low-latency data memory; during the execution of extended instructions, the extended processing unit needs to read or write data from the system memory through the extended unit data access interface; after the instruction execution is completed, the processing result is returned to the processor based on the RISC-V architecture, and the processor based on the RISC-V architecture continues to process the next one or more instructions; during the operation of the processor based on the RISC-V architecture, if the processor based on the RISC-V architecture loses power, the running program is terminated.

[0043] It can be understood that in the data processing method applied to the data processing system based on the RISC-V architecture, when the processor based on the RISC-V architecture reads the program instructions from the first memory, the processor based on the RISC-V architecture processes according to the following data processing method.

[0044] An embodiment of the present application provides a data processing method, which is applied to a processor based on a RISC-V architecture.

[0045] Reference Figure 5 , the data processing method includes but is not limited to the following steps: Reading program instructions through an instruction fetch unit; The program instruction is decoded by the instruction decoding unit to obtain a decoding result, and the decoding result is stored in a register file. The decoding result includes the instruction type and the application field type; Reading the decoding result from the register stack through the distribution unit, identifying the application domain type, distributing the program instruction to the execution unit and the extended processing unit according to the preset distribution rule when the application domain type conforms to the preset domain type, identifying the instruction type when the application domain type does not conform to the preset domain type, distributing the RISC-V instruction set instruction to the execution unit when the instruction type of the program instruction is a RISC-V instruction set instruction, and distributing the extended instruction to the extended processing unit when the instruction type of the program instruction is an extended instruction; Execute the RISC-V instruction set instruction through the execution unit, and return a first execution result; Executing the extended instruction through the extended processing unit and returning a second execution result; The first execution result and the second execution result are read and written through the data access interface.

[0046] Specifically, the instruction acquisition unit calculates the position of the next instruction, reads the instruction of the system memory via the instruction cache, or directly reads the instruction of the low-latency data memory. After the instruction enters the processor, it passes through the instruction decoding unit to parse and obtain the instruction type, application field type, operation type, register identification number used by the instruction, immediate number, etc. The corresponding register data is read from the register stack. The distribution unit reads the decoding result from the register stack, identifies the application field type, and distributes the program instruction to the execution unit and the extended processing unit according to the preset distribution rule when the application field type meets the preset field type. When the application field type does not meet the preset field type, the instruction type is identified, and when the instruction type of the program instruction is a RISC-V instruction set instruction, the RISC-V instruction set instruction is distributed to the execution unit, and when the instruction type of the program instruction is an extended instruction, the extended instruction is distributed to the extended processing unit. The execution unit processes the RISC-V basic instruction, and after completion, writes the first execution result back to the register stack, or loads data from the system memory or the low-latency data memory through the data access interface and then writes it back to the register stack, or writes data into the system memory or the low-latency data memory through the data access interface. It can be understood that the first execution result is the execution result of the execution unit processing the RISC-V basic instruction. The extended processing unit performs the operation of the extended instruction. After the processing is completed, it returns the response information of the instruction completion through the extended interface, writes the second execution result back to the register file through the extended interface, or loads data from the system memory or low-latency data memory through the data access interface and then writes it back to the register file through the extended interface, or writes the data to the system memory or low-latency data memory through the extended unit data access interface. It can be understood that the second execution result is the execution result of the extended processing unit executing the extended instruction.

[0047] Reference Figure 6, further, when the application domain type conforms to the preset domain type, the distribution unit distributes the program instructions to the execution unit and the extended processing unit according to the preset distribution rule, including but not limited to the following steps: Determining a preset distribution rule corresponding to the application field type from a rule table stored in a system memory; Distributing a first program instruction among the program instructions to an execution unit; Second program instructions among the program instructions are distributed to the extended processing unit.

[0048] The identification code of the first program instruction corresponds to the identification code of the first identification code set in the preset distribution rule, and the identification code of the second program instruction corresponds to the identification code of the second identification code set in the preset distribution rule.

[0049] Specifically, a plurality of preset distribution rules corresponding to application field types are stored in the rule table pre-stored in the system memory, for example, distribution rules for the encryption field, distribution rules for the graphics processing field, etc. are set.

[0050] Each distribution rule stores multiple identification codes. For example, the distribution rule for the encryption field stores two identification code sets, namely the first identification code set and the second identification code set. The first identification code set is a set of identification codes for the RISC-V basic instructions required for the encryption field, and the second identification code set is a set of identification codes for the extended instructions required for the encryption field.

[0051] The program instructions are also provided with the same identification code. The instructions whose identification codes in the program instructions correspond to the identification codes of the first identification code set in the preset distribution rules are RISC-V basic instructions for specific fields. The instructions whose identification codes in the program instructions correspond to the identification codes of the second identification code set in the preset distribution rules are extended instructions for specific fields.

[0052] The distribution unit only needs to directly distribute the first program instruction in the program instructions to the execution unit and distribute the second program instruction in the program instructions to the extended processing unit according to the distribution rule without additionally identifying the instruction type, thereby improving the distribution efficiency of the instructions.

[0053] Reference Figure 7 Further, when the extended processing unit executes the extended instruction, the following steps are included but not limited to: receiving the extended instruction distributed by the distribution unit through the extended interface, and determining the instruction type of the extended instruction; When the type of the extended instruction is control and status register access, the control parameters and status parameters of the processor system are read or written to the control and status register through the extended interface, and the response information of the completion of the instruction is returned; When the type of the extended instruction is execution type, the operation type and the immediate value in the extended instruction are sent to the extended instruction distribution and recovery unit through the extended interface, and the source register data and the destination register identification number in the extended instruction are written into the register data temporary storage unit; Determine the operation type of the extended instruction by the extended instruction distribution and recycling unit; When the operation type of the extended instruction is a register operation extended instruction, the source data is obtained from the register data temporary storage unit through the register operation execution unit, the auxiliary information is read from the control and status register, and the corresponding operation is performed on the register data according to the operation type of the extended instruction to obtain the instruction execution result data, the instruction execution result data is written into the destination register of the register data temporary storage unit, and the response information of the instruction completion is returned to the extended instruction distribution and recovery unit; When the operation type of the extended instruction is a storage data operation extended instruction, the storage data operation execution unit uses the data reading unit to read data from the storage space starting from the source address of the storage space, and performs corresponding data function operations according to the operation type of the extended instruction to obtain instruction execution result data, write the instruction execution result data into the destination register of the register data temporary storage unit, and return the response information of the instruction completion to the extended instruction distribution and recovery unit; When the operation type of the extended instruction is to store an advanced function extended instruction, the advanced function execution unit uses the data reading unit to read data from the storage space starting from the source address of the storage space and the comparison data source address, and performs corresponding functional operations according to the operation type of the extended instruction to obtain the instruction execution result data, write the instruction execution result data into the destination register of the register data temporary storage unit, and return the response information of the instruction completion to the extended instruction distribution and recovery unit.

[0054] Specifically, the extended interface receives data storage extended instruction information, the extended interface determines the operation type of the instruction information, and accesses the extended instruction distribution and recovery unit, the register data temporary storage unit and the control and status register respectively. If the operation type of the instruction is execution type, the extended interface sends the operation type and immediate value in the instruction information to the extended instruction distribution and recovery unit, and writes the source register data and destination register identification number in the instruction information into the register data temporary storage unit. The register temporary storage unit has a certain temporary storage depth and can temporarily store the register data of several extended instructions. If the operation type of the instruction is control and status register access, the extended interface will read or write the control and status register and return the response information of the instruction completion. The extended instruction distribution and recovery unit determines the operation type of the instruction, and distributes the operation type and immediate value of the instruction to the register operation execution unit, the storage data operation execution unit or the storage advanced function execution unit respectively. The register operation execution unit obtains the source data from the register data temporary storage unit, reads other auxiliary information from the control and status register, such as the starting bit of the partial bit and the number of the partial bit, and performs corresponding operations on the register data according to the operation type, such as partial bit comparison, partial bit addition and subtraction, count 1 operation, count 0 operation, etc. After completion, the result data is written to the destination register of the register data temporary storage unit, and a completion response is sent to the extended instruction distribution and recovery unit. The storage data operation execution unit obtains the source address, data length, destination address or destination register identifier from the register data temporary storage unit according to the operation type, and reads other auxiliary information from the control and status register, such as the copy style and the value of the set value. The storage data operation execution unit starts from the source address of the storage space, reads data from the storage space through the data reading unit, and performs corresponding data function operations, such as copying the storage space, resetting the storage space, counting the storage space setting value, searching the first setting value position of the storage space, etc. If there is a destination address, the data writing unit starts from the destination address of the storage space and writes the processed data to the storage space, and executes repeatedly until all data processing within the data length range is completed. If there is a destination register identifier, the obtained processing information is returned to the destination register of the register data temporary storage unit, and a completion response is issued to the extended instruction distribution and recovery unit. The storage advanced function execution unit obtains the source address, data length, destination address or destination register identifier from the register data temporary storage unit, and reads other auxiliary information from the control and status register, such as comparing the source address and search conditions.The storage high-level function execution unit starts from the source address of the storage space and the comparison data source address, reads data of the specified data length from the storage space through the data reading unit, and performs corresponding high-level function operations, such as data comparison between two storage spaces, data addition and subtraction between two storage spaces, storage space conditional search, etc. If there is a destination address, the data writing unit starts from the destination address of the storage space and writes the processed data to the storage space, and executes repeatedly until all data processing within the data length range is completed. If there is a destination register identifier, the obtained processing information is returned to the destination register of the register data temporary storage unit, and a completion response is issued to the extended instruction distribution and recovery unit.

[0055] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the embodiments. Technical personnel familiar with the field can make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A processor based on RISC-V architecture, characterized in that: include: An instruction fetch unit, for reading program instructions; An instruction decoding unit, used for decoding the program instruction to obtain an instruction type and an application field type; Register file, including several registers defined by the instruction architecture, used for data interaction during the execution of program instructions; a distribution unit, configured to identify an application domain type, distribute the program instruction to an execution unit and an extended processing unit according to a preset distribution rule when the application domain type conforms to a preset domain type, identify an instruction type when the application domain type does not conform to the preset domain type, distribute the RISC-V instruction set instruction to the execution unit when the instruction type of the program instruction is a RISC-V instruction set instruction, and distribute the extended instruction to the extended processing unit when the instruction type of the program instruction is an extended instruction; An execution unit, configured to execute the RISC-V instruction set instruction and return a first execution result; An extended processing unit, used for executing the extended instruction and returning a second execution result; A data access interface is used to perform read and write operations on the first execution result and the second execution result.

2. The processor based on RISC-V architecture according to claim 1, characterized in that: The expansion processing unit comprises: An extended interface, which is an interface for data interaction with the distribution unit, and is used to distribute the extended instruction to one of the control and status register, the register data temporary storage unit, and the extended instruction distribution and recycling unit for read and write operations according to the operation type of the extended instruction; Control and status registers, used to store control parameters and status parameters of the processor system; A register data temporary storage unit, used to store register data of extended instructions, store instruction execution result data of the register operation execution unit, store data operation execution unit and store advanced function execution unit; An extended instruction distribution and recycling unit, used for distributing the extended instruction to one of the register operation execution unit, the storage data operation execution unit and the storage advanced function execution unit for execution according to the operation type of the extended instruction; A register operation execution unit, configured to, after receiving the extended instruction, obtain source data from the register data temporary storage unit, read auxiliary information from the control and status register, perform corresponding operations on the register data according to the operation type of the extended instruction, and obtain instruction execution result data; A storage data operation execution unit, configured to read data from the storage space starting from the source address of the storage space through the data reading unit after receiving the extended instruction, and perform corresponding data function operations according to the operation type of the extended instruction to obtain instruction execution result data; A storage high-level function execution unit is used to read data from the storage space starting from the source address of the storage space and the comparison data source address through the data reading unit after receiving the extended instruction, and perform corresponding functional operations according to the operation type of the extended instruction to obtain instruction execution result data; A data reading unit, used to generate an address and a data length, and read data of a specified data length from a storage space via a data access interface of the expansion unit; A data writing unit is used to generate an address and a data length, and write data of a specified data length into the storage space via the expansion unit data access interface; The expansion unit data access interface is used to convert data read and write requests into data access requests that comply with the bus protocol.

3. A data processing system based on RISC-V architecture, characterized in that: include: The RISC-V architecture-based processor according to claim 1 or 2, configured to determine the type of a program instruction read, and execute the program instruction according to the determination result, and perform read and write operations on stored data; A first storage module, used for storing program instructions and program data; The second storage module is used to store the preset data, intermediate processing data and result data of each module; A cache module, used to cache read and write data of the processor based on the RISC-V architecture; A first control module, used for controlling an external device; A storage accessor is used to perform data transfer operations under the control of the processor based on the RISC-V architecture.

4. The data processing system based on RISC-V architecture according to claim 3, characterized in that: The first storage module comprises: A low-latency instruction memory, which is a static random access memory for storing program instructions and is accessed by the processor based on the RISC-V architecture; The low-latency data memory is a static random access memory used to store program data and is accessed by the processor based on the RISC-V architecture.

5. The data processing system based on RISC-V architecture according to claim 3, characterized in that: The second storage module comprises: System memory, used to store intermediate processing data of each module; A read-only memory, used for storing preset data; Non-volatile memory, used to store result data.

6. The data processing system based on RISC-V architecture according to claim 5, characterized in that: The cache module comprises: An instruction cache, used to cache data read by the RISC-V architecture-based processor from the system memory or the read-only memory; A data cache is used to cache data read and written by the processor based on the RISC-V architecture to the system memory.

7. A data processing method, characterized in that: Applied to the RISC-V architecture-based processor as claimed in claim 1 or 2, the method comprising: Reading program instructions through an instruction fetch unit; Decoding the program instruction by an instruction decoding unit to obtain a decoding result, and storing the decoding result in a register file, wherein the decoding result includes an instruction type and an application field type; Reading the decoding result from the register stack through a distribution unit, identifying the application domain type, distributing the program instruction to the execution unit and the extended processing unit according to a preset distribution rule when the application domain type conforms to the preset domain type, identifying the instruction type when the application domain type does not conform to the preset domain type, distributing the RISC-V instruction set instruction to the execution unit when the instruction type of the program instruction is a RISC-V instruction set instruction, and distributing the extended instruction to the extended processing unit when the instruction type of the program instruction is an extended instruction; Execute the RISC-V instruction set instruction through the execution unit, and return a first execution result; Executing the extended instruction through the extended processing unit and returning a second execution result; The first execution result and the second execution result are read and written through a data access interface.

8. The data processing method according to claim 7, characterized in that: The method of distributing the program instructions to the execution unit and the extended processing unit according to a preset distribution rule when the application domain type conforms to the preset domain type includes: Determining a preset distribution rule corresponding to the application field type from a rule table stored in a system memory; Distributing a first program instruction in the program instructions to the execution unit, wherein the identification code of the first program instruction corresponds to the identification code of the first identification code set in the preset distribution rule; A second program instruction in the program instructions is distributed to the extended processing unit, wherein the identification code of the second program instruction corresponds to the identification code of the second identification code set in the preset distribution rule.

9. The data processing method according to claim 7, characterized in that: The step of executing the extended instruction by an extended processing unit includes: receiving, via an extended interface, an extended instruction distributed by the distribution unit, and determining an instruction type of the extended instruction; When the type of the extended instruction is control and status register access, the control parameters and status parameters of the processor system are read or written to the control and status register through the extended interface, and a response message indicating that the instruction is completed is returned; When the type of the extended instruction is execution type, the operation type and the immediate value in the extended instruction are sent to the extended instruction distribution and recovery unit through the extended interface, and the source register data and the destination register identification number in the extended instruction are written into the register data temporary storage unit; Determining the operation type of the extended instruction by the extended instruction distribution and recovery unit; When the operation type of the extended instruction is a register operation extended instruction, the source data is obtained from the register data temporary storage unit through the register operation execution unit, the auxiliary information is read from the control and status register, and the corresponding operation is performed on the register data according to the operation type of the extended instruction to obtain instruction execution result data, the instruction execution result data is written into the destination register of the register data temporary storage unit, and the response information of instruction completion is returned to the extended instruction distribution and recovery unit; When the operation type of the extended instruction is a storage data operation extended instruction, the storage data operation execution unit uses the data reading unit to read data from the storage space starting from the source address of the storage space, and performs corresponding data function operations according to the operation type of the extended instruction to obtain instruction execution result data, write the instruction execution result data into the destination register of the register data temporary storage unit, and return instruction completion response information to the extended instruction distribution and recovery unit; When the operation type of the extended instruction is to store an advanced function extended instruction, the advanced function execution unit uses the data reading unit to read data from the storage space starting from the source address of the storage space and the comparison data source address, and performs corresponding functional operations according to the operation type of the extended instruction to obtain instruction execution result data, write the instruction execution result data into the destination register of the register data temporary storage unit, and return instruction completion response information to the extended instruction distribution and recovery unit.

10. A data processing method, characterized in that: Applied to the RISC-V architecture-based data processing system according to any one of claims 3 to 7, the method comprising: When the data processing system is powered on and reset, the startup program instruction is read by a processor based on the RISC-V architecture, and the startup program instruction is executed; Using the first control module, the processor based on the RISC-V architecture reads the running program instructions from the external memory; By means of the processor based on the RISC-V architecture, according to the running program instruction, jumping from executing the startup program to executing the running program, and reading the program instruction from the first storage module; The type of the program instruction is determined by the processor based on the RISC-V architecture, and the program instruction is executed according to the determination result, and the stored data is read and written to obtain the processing result and return the processing result, and then the next program instruction is executed.

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