Method and system for end-to-end simulation of hardware offload operations

Abstract

Embodiments of the present disclosure relate to methods and systems for end-to-end simulation of hardware offload operations. Systems and methods for providing a platform for emulating hardware offloading, when executed on a host system, include: a guest system running on the host system, the guest system configured to receive data processing commands; a virtual device interface to communicate between the guest system and the accelerator emulator; and a hardware accelerator emulated by the accelerator emulator for executing data processing commands received through the virtual device interface, where the hardware accelerator includes an offload hardware component and a controller component.

Description

Technical Field

[0001] Embodiments described herein generally relate to hardware offload systems. More specifically, embodiments described herein relate to methods and systems for end-to-end simulation and evaluation of offload operations performed by a hardware accelerator having a controller emulation and an offload hardware emulation that emulates the interactions between hardware components and software components of the emulated hardware accelerator. Background Art

[0002] Hardware offloading involves delegating computational tasks from the central processing unit (CPU) to a hardware accelerator, which is a dedicated hardware component that includes components that can accelerate data processing and analysis, improve performance, and reduce power consumption. Accelerators can be specifically designed for certain data processing functions. Hardware prototyping and / or proof-of-concept designs for accelerators can involve significant time and financial investment. Summary of the invention

[0003] Embodiments described herein generally relate to hardware offload systems. More specifically, embodiments described herein relate to methods and systems for end-to-end simulation and evaluation of offload operations performed by a hardware accelerator having a controller emulation and an offload hardware emulation that emulates the interactions between hardware components and software components of the emulated hardware accelerator.

[0004] In big data applications or machine learning applications, hardware offload can be used to accelerate the data processing operations that support these applications. Systems that cope with data processing operations and support application functions can be created for these applications.

[0005] End-to-end simulation of a hardware / software co-design system can be provided to evaluate a system that uses one or more hardware accelerators to perform offload operations. It should be understood that a co-design system with a hardware accelerator for offload operations is complex, and based on the performance characteristics of each component, the performance of the system as a whole is unpredictable. By performing end-to-end simulation of the offload system, the performance and compatibility of the hardware components and software components in the system can be predicted and evaluated. Problems or bottlenecks in software design and / or hardware design, their integration, and system architecture can be identified by monitoring the simulation and monitoring the performance statistics obtained from the simulation. Evaluation and performance optimization can be performed through simulation, thereby avoiding and / or reducing the need for physical prototypes.

[0006] In one embodiment, when executed on a host system, a platform for simulating hardware offloading includes: a guest system running on the host system, the guest system being configured to receive data processing commands; a virtual device interface communicating between the guest system and an accelerator emulator; and a hardware accelerator emulated by the accelerator emulator to execute the data processing commands received through the virtual device interface, wherein the hardware accelerator includes an offload hardware component and a controller component.

[0007] In one embodiment, the controller component emulates parsing data processing commands from the guest system.

[0008] In one embodiment, the offload hardware component emulates execution of the data processing commands in a hardware accelerator.

[0009] In one embodiment, the hardware accelerator is emulated in the Quick Emulator (QEMU) as a virtual device that communicates with the guest system.

[0010] In one embodiment, the host system includes an emulated storage device for emulating storage of data processed by the hardware accelerator.

[0011] In one embodiment, the guest system further includes an emulator library included in the guest system, the emulator library providing an application programming interface (API) to offload data operations to a hardware accelerator emulated by the accelerator emulator according to a data processing command.

[0012] In one embodiment, the hardware accelerator is emulated by the accelerator emulator as a non-volatile memory express (NVMe) device, and the emulator library includes an NVMe driver for controlling the NVMe device.

[0013] In one embodiment, the platform includes a profiler that obtains performance statistics from the guest system.

[0014] In one embodiment, the profiler runs with a provided user application or emulator library to collect performance statistics.

[0015] In one embodiment, the profiler or emulator library includes a profiler library that provides the profiler with an API for hooks or callbacks for performance statistics.

[0016] In one embodiment, a method for simulating a hardware accelerator is disclosed. The method includes: running a guest system on a host system that provides a simulation platform; the guest system receiving a data processing command; an accelerator emulator emulating a hardware accelerator; the hardware accelerator receiving the data processing command through a virtual device interface; and a controller component of the hardware accelerator controlling an offload hardware component of the hardware accelerator to simulate the hardware accelerator executing the data processing command.

[0017] In one embodiment, the accelerator emulator emulates a hardware accelerator in a quick emulator (QEMU) as a virtual device that communicates with a guest system.

[0018] In one embodiment, the method includes: storing, in an emulation storage device, data processed by a hardware accelerator emulated by an accelerator emulator.

[0019] In one embodiment, the method includes: an accelerator emulator implements a hardware accelerator as a non-volatile memory express (NVMe) device; and an emulator library in a guest system provides an NVMe driver for controlling the NVMe device to execute data processing commands.

[0020] In one embodiment, the method includes obtaining, by a profiler, performance statistics from a guest system.

[0021] In one embodiment, a non-transitory computer-readable medium having computer-executable instructions stored thereon, the computer-executable instructions, when executed, causing one or more processors to perform operations for emulating a hardware accelerator, the operations comprising: running a guest system in a host system providing an emulation platform; receiving data processing commands from the guest system; emulating the hardware accelerator using an accelerator emulator; receiving the data processing commands into the hardware accelerator through a virtual device interface; and controlling an offload hardware component of the hardware accelerator using a controller component of the hardware accelerator to emulate execution of the data processing commands by the hardware accelerator.

[0022] In one embodiment, the non-transitory computer readable medium includes: emulating a hardware accelerator as a virtual device in a quick emulator (QEMU) that communicates with a guest system using an accelerator emulator.

[0023] In one embodiment, the non-transitory computer readable medium includes storing data processed by the hardware accelerator in an emulated storage device emulated by the accelerator emulator.

[0024] In one embodiment, the non-transitory computer-readable medium includes: implementing a hardware accelerator as a non-volatile memory express (NVMe) device using an accelerator emulator, and providing an NVMe driver in an emulator library of a guest system for controlling the NVMe device to execute data processing commands.

[0025] In one embodiment, the non-transitory computer readable medium includes utilizing a profiler to obtain performance statistics from a guest system. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings illustrate various embodiments of systems, methods, and embodiments of various other aspects of the present disclosure. It will be appreciated by any person of ordinary skill in the art that the element boundaries (e.g., boxes, multiple groups of boxes, or other shapes) shown in the figures represent an example of boundaries. In some examples, an element may be designed as multiple elements, or multiple elements may be designed as one element. In some examples, an element shown as an internal component of an element may be implemented as an external component in another element, and vice versa. A non-restrictive, non-exhaustive description is described with reference to the following figures. The components in the figures are not necessarily drawn to scale, but emphasize the explanation principle. In the following specific embodiments, the embodiments are described only as explanations, because various changes and modifications may become apparent to those skilled in the art according to the following specific embodiments.

[0027] Figure 1 is a schematic diagram of a host system arranged to emulate end-to-end (E2E) hardware offload in accordance with at least some embodiments described herein.

[0028] Figure 2 is a schematic diagram of the architecture of an E2E emulator arranged in accordance with at least some embodiments described herein.

[0029] Figure 3 is a flow chart illustrating a profiling operation in accordance with at least some embodiments described herein.

[0030] Figure 4 is a schematic diagram of the architecture of an E2E hardware offload emulator arranged in accordance with at least some embodiments described herein.

[0031] Figure 5 is a flow chart illustrating an E2E simulation method according to at least some embodiments described herein.

[0032] Like reference numerals refer to like parts throughout. DETAILED DESCRIPTION

[0033] Embodiments described herein generally relate to hardware offload systems. More specifically, embodiments described herein relate to methods and systems for end-to-end simulation and evaluation of offload operations performed by a hardware accelerator having a controller emulation and an offload hardware emulation that emulates the interactions between hardware components and software components of the emulated hardware accelerator.

[0034] In the following detailed description, specific embodiments of the present disclosure are described herein with reference to the accompanying drawings, which form a part of the description. In this specification and the accompanying drawings, similar reference numerals represent elements that can perform the same, similar or equivalent functions, unless the context otherwise dictates. In addition, unless otherwise specified, the description of each consecutive figure may refer to features from one or more previous figures to provide a clearer context and more substantial explanation of the current example embodiment. Nevertheless, the example embodiments described in the specific embodiments, the accompanying drawings, and the claims are not intended to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein. It will be readily understood that, as generally described herein and shown in the accompanying drawings, the various aspects of the present disclosure may be arranged, replaced, combined, separated, and designed in a variety of different configurations, all of which are explicitly contemplated herein.

[0035] It should be understood that the disclosed embodiments are merely examples of the present disclosure, which may be embodied in various forms. Well-known functions or structures are not described in detail to avoid unnecessary details that obscure the present disclosure. Therefore, the specific structural and functional details disclosed herein should not be interpreted as limiting, but merely as a basis for the claims, and as a representative basis for teaching those skilled in the art to variously adopt the present disclosure with almost any appropriate detailed structure.

[0036] In addition, the present disclosure may be described herein in terms of functional block components and various processing steps. It should be understood that these functional blocks may be implemented by any number of hardware components and / or software components configured to perform the specified functions.

[0037] The scope of the present disclosure should be determined by the appended claims and their legal equivalents, rather than by the examples given herein. For example, the steps recited in any method claim may be performed in any order and are not limited to the order presented in the claim. In addition, no element is essential to the practice of the present disclosure unless specifically described as "critical" or "essential" herein.

[0038] As mentioned herein, "network" or "computer network system" is a technical term and may refer to interconnected computing devices that can exchange data and share resources with each other. It should be understood that networked devices can use a system of rules (e.g., communication protocols, etc.) to transmit information through wired or wireless technologies.

[0039] As referred to herein, "NVMe protocol or interface" may refer to a non-volatile fast memory protocol that provides a fast interface between a computer processing unit and a storage device, such as a solid-state device (SSD). The NVMe protocol or interface may use a high-speed Peripheral Component Interconnect Express (PCIe) bus that provides a more streamlined interface for accessing an SSD.

[0040] In some computer network systems (such as cloud-based storage environments), for example, in a data center or server system, a hardware offload operation can be provided so that a host device having a controller (such as a central processing unit (CPU)) can offload certain functions or operations from the host device to a controller (or CPU) on a server connected to (multiple) storage devices. For example, in some embodiments, a processor-enabled server (e.g., having hardware operations, software operations, and / or firmware operations) may include various hardware offload engines, such as data flow accelerators and in-memory analysis accelerators. In an example embodiment, the host device may be designed, programmed, or otherwise configured to provide (e.g., transmit / send) an offload command to the server for performing hardware offload operations / functions to the hardware offload engine on the processor-enabled server (and / or the processor-enabled server may be designed, programmed, or otherwise configured to obtain an offload command). The E2E simulation platform disclosed herein may be configured to simulate and / or evaluate such a computer network system.

[0041] Figure 1 is a schematic diagram of a host system 100 arranged to emulate E2E hardware offload in accordance with at least some embodiments described herein.

[0042] The host system 100 provides an E2E hardware offload simulation platform. In one embodiment, the host system 100 provides an E2E simulation platform for E2E simulation of one or more hardware accelerators. The simulation of the hardware accelerator includes hardware components and / or software components for simulating the execution of one or more offload operations. In one embodiment, the host system 100 can be a computer, a computer network, a cloud computing center, etc. The host system 100 executes a non-transitory computer-readable medium to provide an E2E simulation platform configured to simulate a hardware accelerator.

[0043] like Figure 1As shown, when executed by the host system 100, the E2E emulation platform includes a guest system 110, an emulator interface 160, an accelerator emulator 170, and an SSD emulator 190. In one embodiment, the guest system 110, the emulator interface 160, the accelerator emulator 170, and the SSD emulator 190 operate in a QEMU process running on the host system 100.

[0044] The guest system 110 is a system that communicates with the host system 100. The guest system 110 provides the performance and functionality of a guest device that requests one or more hardware offload operations. For example, the guest system 100 may include a software package or module for requesting data processing to be offloaded from the CPU of the guest system 100 to a hardware accelerator (such as a graphics processing unit (GPU), a field-programmable gate array (FPGA), or an application-specific integrated circuit (ASIC). In one embodiment, the guest system 110 is a virtual system, such as a virtual machine that communicates with the host system 100 and / or is generated by the host system 100. The guest system 110 may include a virtual processor, a virtual random-access memory (RAM), a virtual storage device, a driver, etc., for virtually executing an operating system, an application, etc., and communicating with another physical device such as device 155 or a virtual device (e.g., a hardware accelerator).

[0045] The user application 115 may be loaded into and / or executed by the guest system 110. The user application 115 typically performs application function(s). The user application 115 issues one or more data processing commands to request one or more data processing operations to support the application function(s) of the user application 115. The application function(s) may include filtering, decompression, decoding, machine learning, etc. The guest system 110 executes the processing commands through its processor and / or by offloading to a hardware accelerator.

[0046] The emulator library 120 is connected between the user application 115 and the hardware or emulated hardware for offloading operations. The emulator library 120 includes one or more application programming interfaces (APIs) or unified APIs to connect, transmit, transcribe and / or compile processing commands from the user application 115 into readable commands for physical devices or virtual devices such as device 155. In one embodiment, the emulator library 120 includes an NVMe driver for controlling an actual / physical NVMe device or an emulated or virtual NVMe device. In one embodiment, the emulator library 120 includes a platform API, a runtime API, a memory API, and a storage device API to provide a unified API for hardware offloading operations.

[0047] The profiler 125 obtains performance data of components in the host system 100 (e.g., the guest system 110). For example, the profiler 125 can obtain performance data of hardware components and / or software components of the host system 100. In one embodiment, the profiler 125 may include (multiple) software modules executed in the guest system 110, which are configured to receive, monitor, analyze and / or visualize performance data. In one embodiment, the profiler 125 communicates with the guest system 110 and / or runs on the guest system 100 to obtain operational performance data of the guest system 110. The profiler 125 obtains data when the guest system 110 is running a user application 115. In one embodiment, the profiler 125 communicates with the user application 115 and / or the emulator library 120 to obtain performance data. The profiler may include a profiler library that provides one or more APIs for profiler hooks and / or callbacks. The profiler library is shared or integrated with the user application 115 and / or the emulator library 120 to provide hook and callback functions for the profiler 125. Performance statistics may include runtime data (eg, clock speed, runtime, latency, error counts, etc.).

[0048] It should be understood that the E2E simulation can be performed to simulate the hardware accelerator for the specific data processing request of the user application 115, thereby simulating the E2E performance of the hardware components and software components performing the offload operation. By monitoring the performance at various components in the host system 100 during the offload operation, any hardware and software performance bottlenecks can be identified in the E2E simulation to diagnose, improve, optimize, etc. the hardware architecture and / or software architecture.

[0049] The device 155 communicates with the user application 115 through the emulator library 120 to execute one or more data processing commands from the user application 115 connected to the emulator library 120. In one embodiment, the device 155 is implemented as an NVMe device that communicates with, for example, the emulator library 120 using the NVMe protocol. In one embodiment, the device 155 is a virtual device that provides the QEMU emulator 150 for emulating a hardware accelerator within the QEMU emulator 150. It should be understood that the QEMU emulator 150 can emulate one or more components that operate in the host system 100 and / or interact with the guest system 110. For example, the QEMU emulator 150 can emulate the host system 100 and provide an emulator interface 160, an accelerator emulator 170, and / or an SSD emulation 190.

[0050] The emulator interface 160 facilitates communication between the emulated device 155 and the accelerator emulator 170. In one embodiment, the emulator interface 160 is a QEMU virtual device interface configured to connect between the virtual device 155 using the NVMe protocol and the accelerator emulator 170 emulated in the QEMU emulator 150. The emulator interface 160 may include one or more APIs, unified APIs, one or more shared libraries, one or more drivers, etc., for an interface between the accelerator emulator 170 and a device (e.g., device 155).

[0051] The accelerator emulator 170 creates an emulated hardware accelerator to perform data processing functions offloaded from the CPU. The CPU may be a virtual processor of the guest system 110. In one embodiment, the accelerator emulator 170 is provided by the QEMU emulator as an emulated device. The accelerator emulator 170 uses QEME to emulate the hardware components and software components of the hardware accelerator. The software component of the emulated accelerator may be a controller emulation 175. The controller emulation 175 may include instructions for processing data according to the data processing function. The instructions may include, for example, parsing the offload command, sending low-level instructions to the offload hardware emulation 180 to implement the execution of (multiple) offload commands, etc. In one embodiment, the controller emulation 175 is configured to process instructions to submit and / or complete the offload function according to the offload command. The hardware component of the emulated accelerator may be an offload hardware emulation 180. For example, the offload hardware emulation 180 may emulate the custom data processing algorithm / function and / or circuit design of the hardware accelerator for performing one or more data processing functions according to the offload command. In one embodiment, the accelerator emulator 170 is emulated in the host system 100 by the QEMU emulator 150.

[0052] SSD emulation 190 emulates hardware reception and storage of data. SSD emulation 190 may emulate the functionality and performance of a physical SSD that receives data from another operation.

[0053] In one embodiment, QEMU emulator 150 is included on host system 100 and / or executed on host system 100. For example, QEMU emulator can be run in the operating system of host system 100. QEMU emulator is a system for emulating one or more pieces of custom or standard hardware. In one embodiment, host system 100 includes QEMU emulator 150 to provide one or more virtual / emulated hardware components in host system 100. QEMU emulator 150 emulates virtual devices to interact with physical devices or other virtual devices included in or connected to host system 100. In one embodiment, device 155, emulator interface 160, accelerator emulator 170 and SSD emulator 190 are emulated in QEMU emulator 150.

[0054] Figure 2 is a schematic diagram of an architecture of an E2E simulator arranged according to at least some embodiments described herein. In one embodiment, the E2E simulator may run as described above with reference to Figure 1 The host system 100. Figure 2 As shown, emulator library 120 interfaces between user application 115 and one or more devices 155A-155F. Emulator library 120 may be configured to deliver commands from user application 115 to emulated devices and / or physical devices (eg, devices 155A-155F).

[0055] The user application 115 may include an execution engine for transmitting data processing commands for data processing functions (e.g., screening, decoding, decompression, etc.). The execution engine may be a unified execution engine provided for data processing and encapsulation of a data management system. In one embodiment, the user application 115 may be configured for the simulator library 120 and communicate directly with the simulator library 120 for transmitting and / or transcribing data processing commands.

[0056] In one embodiment, the user application 115 communicates with the simulator library 120 through an intermediate layer and / or an API. For example, the user application 115 may transcribe a data processing command through the user API 116 for transmitting the command to the plane switching layer 117. The plane switching layer 117 may be a software module that converts a command from the user application 115 into another version compatible with the simulator library 120. The plane switching layer 117 then provides the transcribed command to the simulator library 120. In one embodiment, the user application 115 issues a data processing command using a query engine.

[0057] The emulator library 120 receives commands from the user application 115 or through the plane switching layer 117 for transmission to a device, such as device 155 ( Figure 1 155A-155F. The library 120 may include an API and / or a driver for controlling the device to perform the offload operation. In one embodiment, a device driver 121 is provided to communicate with one or more physical devices or virtual devices. The physical device or virtual device may be an accelerator for big data or machine learning operations or functions (e.g., decompression, filtering, decoding, etc.).

[0058] Physical devices or virtual devices can be implemented using the PCIe / NVMe+ protocol (e.g., devices 155A-155D) by being controlled through a C / C++ interface or the like.

[0059] In one embodiment, the simulator library 120 is configured to connect to a real accelerator (e.g., a physical device or real device 155A or 155B) and provide (multiple) commands to the real accelerator (e.g., a physical device or real device 155A or 155B). In such an embodiment, simulation can be performed to evaluate the compatibility of the user application 115 and / or the simulator library 120, and / or with the real accelerator (e.g., a real accelerator or a physical accelerator).

[0060] In one embodiment, the simulator library 120 is configured to connect to and / or provide (multiple) commands to a simulator accelerator (e.g., device 155C or 155D) controllable by a PCIe / NVMe+ protocol. In such an embodiment, the simulator accelerator may be a prototype or design concept for performance evaluation.

[0061] In one embodiment, the emulated device (e.g., device 155E or 155F) can be a C / C++ interface device, for example, a C / C++ interface device for early integration and testing. The C / C++ interface device can be a virtual device implemented and connected in C or C++ language. In such an embodiment, the device driver can be omitted.

[0062] Figure 3 3 is a flow chart illustrating a profiling operation 300 according to at least some embodiments described herein. Figure 1 The profiler 125 of the host system 100 may perform the profiling operation 300 to obtain performance data of components in a host system (e.g., the host system 100), a guest system (e.g., the guest system 110), an emulated hardware accelerator, etc. In one embodiment, the profiling operation 300 may be configured to obtain performance data of components in the host system 100 ( Figure 1 ), visitor system 110 ( Figure 1 As shown), performance data of components in user application 115, emulator library 120, etc.

[0063] At 310, the profiler performs instrumentation to obtain performance statistics. In one embodiment, when instrumented, the profiler includes a process that operates with the user application 115, and the process records and collects performance statistics during the runtime of the process and / or the user application 115. In another embodiment, the profiler shares a profiler library with the user application 115 and / or the simulator library 120. The profiler library is integrated with the user application 115 and / or the simulator library 120 to provide profiler hooks and callbacks for the profiler requesting and / or receiving performance statistics. The performance statistics may include runtime data (e.g., clock speed, runtime, latency, error count, etc.). Then, method 300 proceeds to 350.

[0064] At 350 , the profiler collects performance statistics, for example, by organizing the data in memory of the guest system and / or the host system. Method 300 then proceeds to 380 .

[0065] At 380, the profiler aggregates and analyzes the collected data, and visualizes the collected data. The collected data can be visualized on a user interface for a user to view the collected data and evaluate the performance of the simulated hardware accelerator, the user application 115, the simulator library 120, etc., and / or identify design bottlenecks of the hardware components and / or software components of the simulated hardware accelerator. In one embodiment, the collected data can be transmitted (e.g., via an API) to another module or application for processing and visualization.

[0066] Figure 4 1 is a schematic diagram of an architecture of a hardware offload emulator arranged according to at least some embodiments described herein. In one embodiment, the hardware offload emulator can be configured to emulate control software and / or hardware components of a hardware accelerator. In one embodiment, the hardware accelerator is emulated in a QEMU emulator 150. The QEMU emulated hardware accelerator can be implemented as an NVMe device controlled by a driver 121 using the NVMe protocol. In one embodiment, a user application 115, an E2E emulation library 120, and a driver 121 are provided in a guest system 110.

[0067] The driver 121 transmits and / or transcribes data processing commands from the user application 115 in the guest system 110 to the QEMU emulator 150. In the QEMU emulator 150, the controller emulation 175 receives and parses commands from the guest system 110, and instructs the unloaded function to perform data processing on the QEMU emulation hardware accelerator (e.g., controller emulation 175, accelerator emulation 180, etc.). In one embodiment, the unloaded function may include decompression 182, decoding 184, screening 186, etc. The unloaded functions may be configured for different workloads or specific data processing to support different user applications, such as data analysis, machine learning training, video processing, etc. In one embodiment, the QEMU emulator 150 is implemented as a multi-threaded program, wherein each unloaded function is provided with one or more processor threads. One or more cores of a processor or virtual processor may be allocated to execute (multiple) unloaded functions. By increasing the number of cores of a processor or virtual processor, more unloaded functions may be executed in parallel. It should be understood that the QEMU emulator 150 may provide a thread pool to combine (multiple) computing resources provided by (e.g., a multi-threaded CPU) and / or to simulate multiple components in parallel. The kernel function of the operating system (e.g., a Linux system running QEMU) may provide thread pools to the QEMU emulator 150 and / or the accelerator emulator (e.g., Figure 1 An accelerator simulator 170; or Figure 4 182, 184 and / or 186; etc.) to allocate different numbers of CPU cores for simulating the execution of (multiple) offloaded functions. A thread pool can be provided to simulate the execution of multiple identical or different simulated hardware accelerators 182, 184 and / or 186 in parallel for simulating an offload system using multiple accelerators. The simulation and / or accelerator simulator 170 ( Figure 1 The computing capacity of the accelerator emulator 170 (as shown) can be adjusted by adjusting the computing resources (e.g., emulated cores, real cores, etc.) allocated to the simulation of the accelerator(s) and / or the accelerator emulator 170 through thread pool and kernel functions. By adjusting the computing capacity, the performance of the simulation offload system can be evaluated and bottlenecks can be identified.

[0068] Figure 5 5 is a flow chart illustrating a method 500 for emulating a hardware accelerator according to at least some embodiments described herein. In one embodiment, the method may be performed by a host system (e.g., Figure 1The method 500 may be performed by a host system 100) to provide an E2E simulation platform for simulating hardware components and software components of a hardware accelerator. The simulation may be used to identify compatibility and / or performance issues of the simulated hardware accelerator. In one embodiment, a non-transitory computer-readable medium may be configured to instruct a processor to execute method 500. It should be understood that one or more software programs, when executed by one or more processors, may cause one or more processors to execute the method(s) described in any of the embodiments described herein. In addition, it should be understood that, according to the embodiments described herein, a computer-readable non-volatile medium may be provided. The computer-readable medium stores a computer program for executing the method(s) described in any of the embodiments described herein when executed by a processor.

[0069] Method 500 starts at 510. At 510, method 500 includes running a guest system on a host system providing an emulation platform. The guest system may be a virtual system created by the host system. Then, method 500 proceeds to 520.

[0070] At 520, the method 500 includes initiating a data processing command by a user application in the guest system. The method 500 initiates the data processing command, for example, by a user application activated by the guest system and / or loaded into the guest system, for example, to support one or more functions of the user application. Then, the method 500 proceeds to 530.

[0071] At 530, method 500 includes an accelerator emulator emulating a hardware accelerator, for example, a real hardware accelerator. Method 500 emulates a hardware accelerator that receives data processing commands from, for example, a user application through a virtual device interface. In one embodiment, the hardware emulator is implemented by the hardware accelerator as a non-volatile fast memory (NVMe) virtual device. The hardware emulator can be a QEMU emulator. In one embodiment, the accelerator emulator implements the hardware accelerator as an NVMe virtual device. Method 500 can provide an emulator library for providing an NVMe driver in a guest system for controlling the NVMe virtual device to execute data processing commands. Then, method 500 proceeds to 540.

[0072] At 540, method 500 includes simulating the hardware accelerator using an accelerator emulator. Method 500 may use the accelerator emulator to emulate a controller component (e.g., Figure 1 controller simulator 175) and hardware components (e.g., Figure 1 The method 500 uses a controller component of the hardware accelerator to control the hardware component and simulates the execution of the data processing command by the hardware accelerator. Then, the method 500 proceeds to 550.

[0073] At 550 , method 500 includes emulating a storage device to store data processed by a hardware accelerator emulated by an accelerator emulator.

[0074] It should be understood that reference Figure 5 The processes described in the flowcharts and / or the processes described in other figures can be implemented as computer software programs or implemented in hardware. The computer program product may include a computer program stored in a computer-readable non-volatile medium. The computer program includes program code for executing the methods shown in the flowcharts and / or GUIs.

[0075] It should be understood that the disclosed and other solutions, examples, embodiments, modules and functional operations described in this document can be implemented in digital electronic circuits, or in computer software, firmware or hardware (including the structures disclosed in this document and their structural equivalents), or in a combination of one or more of them. The disclosed and other embodiments can be implemented as one or more computer program products, that is, one or more modules of computer program instructions encoded on a computer-readable medium, for execution by a data processing device or controlling the operation of the data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a material combination that implements a machine-readable propagation signal, or a combination of one or more of them. The term "data processing device" covers all devices, equipment and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. In addition to hardware, the device may also include code that creates an execution environment for the computer program in question, for example, code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0076] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, and it may be deployed in any form, including as a stand-alone program, or as a module, component, subroutine, or other unit suitable for a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored as part of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, subroutines, or code portions). A computer program may be deployed to execute on one computer, or on multiple computers located at one location or distributed at multiple locations and interconnected by a communications network.

[0077] The processes and logic flows described in this document may be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows may also be performed by special purpose logic circuits, and the apparatus may also be implemented as special purpose logic circuits, such as field programmable gate arrays, application specific integrated circuits, etc.

[0078] For example, processors suitable for executing computer programs include general-purpose microprocessors and special-purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, the computer will also include or be operatively coupled to one or more large-capacity storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks) for storing data to receive data from it, or to transfer data to it, or both. However, the computer is not required to have such a device. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example: semiconductor memory devices, such as erasable programmable read-only memory, electrically erasable programmable read-only memory, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and compact disk read-only memory and digital video disk read-only memory disks. The processor and memory may be supplemented or incorporated by dedicated logic circuits.

[0079] It should be understood that various details have been used to illustrate and describe different features, variations, and multiple different embodiments. In this application, the content sometimes described according to specific embodiments is only for illustrative purposes, rather than for limiting or suggesting that the content envisioned is only a specific embodiment or multiple specific embodiments. It should be understood that the present disclosure is not limited to any single specific embodiment or the variants listed. Many modifications, variations, and other embodiments will occur to those skilled in the art, and these modifications, variations, and other embodiments are intended to represent the present disclosure and are actually covered by the present disclosure. In fact, the scope of the present disclosure should be determined by the appropriate legal interpretation and understanding (including equivalents) of the present disclosure, as understood by those skilled in the art by the complete disclosure presented at the time of submission.

[0080] aspect:

[0081] Aspect 1: A platform for emulating hardware offload, which when executed on a host system includes: a guest system, running on the host system, the guest system being configured to receive data processing commands; a virtual device interface, communicating between the guest system and an accelerator emulator; and a hardware accelerator, emulated by the accelerator emulator, for executing the data processing commands received through the virtual device interface, wherein the hardware accelerator includes an offload hardware component and a controller component.

[0082] Aspect 2: The platform according to aspect 1, wherein the controller component in the accelerator emulator emulates parsing of data processing commands from the guest system.

[0083] Aspect 3: The platform according to aspect 1 or 2, wherein the offload hardware component in the accelerator emulator emulates the execution of the data processing command in the hardware accelerator.

[0084] Aspect 4: The platform of any one of aspects 1-3, wherein the hardware accelerator is emulated in the quick emulator (QEMU) as a virtual device that communicates with the guest system.

[0085] Aspect 5: The platform according to any one of aspects 1-4, wherein the host system includes an emulated storage device for emulating storage of data processed by the hardware accelerator.

[0086] Aspect 6: A platform according to any one of Aspects 1-5, wherein the guest system further comprises an emulator library included in the guest system, the emulator library providing an application programming interface (API) to offload data operations to a hardware accelerator emulated by the accelerator emulator according to a data processing command.

[0087] Aspect 7: A platform according to any one of Aspects 1-6, wherein the hardware accelerator is emulated by the accelerator emulator as a non-volatile memory express (NVMe) device, and the emulator library includes an NVMe driver for controlling the NVMe device.

[0088] Aspect 8: The platform according to any one of aspects 1-7 further comprises a profiler for obtaining performance statistics from the guest system.

[0089] Aspect 9: The platform according to Aspect 8, wherein the profiler runs with a provided user application or emulator library to collect performance statistics.

[0090] Aspect 10: The platform according to Aspect 8 or 9, wherein the profiler or emulator library comprises a profiler library, the profiler library providing the profiler with an API for hooking or callback of performance statistics.

[0091] Aspect 11: A method for simulating a hardware accelerator, the method comprising: running a guest system on a host system that provides a simulation platform; the guest system receiving a data processing command; an accelerator emulator simulating a hardware accelerator; the hardware accelerator receiving the data processing command through a virtual device interface; and a controller component of the hardware accelerator controlling an offload hardware component of the hardware accelerator to simulate execution of the data processing command by the hardware accelerator.

[0092] Aspect 12: The method according to aspect 11, wherein the accelerator emulator emulates the hardware accelerator as a virtual device communicating with the guest system in a quick emulator (QEMU).

[0093] Aspect 13: The method according to Aspect 11 or 12, further comprising: the emulation storage device stores data processed by the hardware accelerator emulated by the accelerator emulator.

[0094] Aspect 14: The method according to any one of Aspects 11-13 further includes: the accelerator emulator implements the hardware accelerator as a non-volatile memory express (NVMe) device; and the emulator library in the guest system provides an NVMe driver for controlling the NVMe device to execute data processing commands.

[0095] Aspect 15: The method according to any one of Aspects 11-14, further comprising: the profiler obtaining performance statistics from the guest system.

[0096] Aspect 16: A non-transitory computer-readable medium having computer-executable instructions stored thereon, which when executed cause one or more processors to perform operations for emulating a hardware accelerator, the operations comprising: running a guest system in a host system that provides an emulation platform; receiving data processing commands from the guest system; emulating a hardware accelerator using an accelerator emulator; receiving the data processing commands into the hardware accelerator through a virtual device interface; and controlling an offload hardware component of the hardware accelerator using a controller component of the hardware accelerator to simulate execution of the data processing commands by the hardware accelerator.

[0097] Aspect 17: The non-transitory computer-readable medium according to Aspect 16, further comprising: using an accelerator emulator to emulate a hardware accelerator in a quick emulator (QEMU) as a virtual device that communicates with a guest system.

[0098] Aspect 18: The non-transitory computer-readable medium according to Aspect 16 or 17, further comprising: storing data processed by the hardware accelerator in an emulated storage device emulated by the accelerator emulator.

[0099] Aspect 19: The non-transitory computer-readable medium according to any one of Aspects 16-18 further includes: implementing the hardware accelerator as a non-volatile memory express (NVMe) device using an accelerator emulator, and providing an NVMe driver in the emulator library of the guest system for controlling the NVMe device to execute data processing commands.

[0100] Aspect 20: The non-transitory computer-readable medium according to any one of Aspects 16-19, further comprising: obtaining performance statistics from the guest system using a profiler.

[0101] Aspect 21: A platform for evaluating simulated hardware offload, which, when executed on a host system, includes: a guest system, running on the host system, the guest system being configured to receive data processing commands; a virtual device interface, communicating between the guest system and an accelerator emulator; a hardware accelerator, emulated by the accelerator emulator, for executing data processing commands received through the virtual device interface, wherein the hardware accelerator includes an offload hardware component and a controller component; and a profiler, included in the guest system, for obtaining performance statistics from the guest system.

[0102] Aspect 22: The platform according to Aspect 21, wherein the controller emulator in the accelerator emulator emulates parsing of data processing commands from the guest system.

[0103] Aspect 23: The platform according to Aspect 21 or 22, wherein the offload hardware emulation in the accelerator emulator emulates the execution of the data processing commands in the hardware accelerator.

[0104] Aspect 24: The platform of any one of Aspects 21-23, wherein the hardware accelerator is emulated in the quick emulator (QEMU) as a virtual device that communicates with the guest system.

[0105] Aspect 25: The platform according to any one of Aspects 21-24, wherein the host system includes an emulated storage device for emulating and storing data processed by the hardware accelerator emulated by the accelerator emulator.

[0106] Aspect 26: A platform according to any one of Aspects 21-25, wherein the guest system further comprises an emulator library included in the guest system, the emulator library providing an application programming interface (API) to offload data operations according to the data processing commands to a hardware accelerator emulated by the accelerator emulator.

[0107] Aspect 27: A platform according to any one of Aspects 21-26, wherein the hardware accelerator is emulated by the accelerator emulator as a non-volatile memory express (NVMe) virtual device, and the emulator library includes an NVMe driver for controlling the NVMe virtual device.

[0108] Aspect 28: A platform according to any one of Aspects 21-27, wherein the profiler runs with a provided user application or emulator library to collect performance statistics.

[0109] Aspect 29: A platform according to any one of Aspects 21-28, wherein the profiler or emulator library comprises a profiler library, the profiler library providing an API for hooks or callbacks for performance statistics to the profiler.

[0110] Aspect 30: The platform of any of Aspects 21-29, wherein the profiler visualizes performance statistics obtained from the guest system.

[0111] Aspect 31: A method for evaluating an emulated hardware accelerator, the method comprising: a guest system running on a host system providing an emulation platform; the guest system receiving a data processing command; an accelerator emulator emulating a hardware accelerator; the hardware accelerator receiving the data processing command through a virtual device interface; a controller of the hardware accelerator emulating an offloaded hardware emulation controlling the hardware accelerator to emulate the execution of the data processing command by the hardware accelerator; and a profiler obtaining performance statistics from the guest system.

[0112] Aspect 32: The method according to aspect 31, wherein the accelerator emulator emulates the hardware accelerator as a virtual device communicating with the guest system in a quick emulator (QEMU).

[0113] Aspect 33: The method according to Aspect 31 or 32 further includes: the emulation storage device stores data processed by the hardware accelerator emulated by the accelerator emulator.

[0114] Aspect 34: The method according to any one of Aspects 31-33 further includes: the accelerator emulator implements the hardware accelerator as a non-volatile memory express (NVMe) device; and the emulator library in the guest system provides an NVMe driver for controlling the NVMe virtual device to execute data processing commands.

[0115] Aspect 35: The method according to any one of Aspects 31-34, wherein the profiler runs with a provided user application or emulator library to collect performance statistics.

[0116] Aspect 36: The method according to any one of Aspects 31-35, wherein the profiler or simulator library comprises a profiler library, the profiler library providing the profiler with an API for hooking or callback of performance statistics data.

[0117] Aspect 37: A non-temporary computer-readable medium having computer-executable instructions stored thereon, which when executed cause one or more processors to perform operations for emulating a hardware accelerator, including: running a guest system in a host system that provides an emulation platform; providing data processing commands from the guest system; emulating a hardware accelerator using an accelerator emulator; receiving data processing commands to the hardware accelerator through a virtual device interface; controlling an offload hardware component of the hardware accelerator using a controller component to simulate execution of the data processing commands by the hardware accelerator; and obtaining performance statistics from the guest system using a profiler.

[0118] Aspect 38: The non-transitory computer-readable medium according to Aspect 37, further comprising: emulating the hardware accelerator in a quick emulator (QEMU) as a virtual device that communicates with a guest system.

[0119] Aspect 39: The non-transitory computer-readable medium according to Aspect 37 or 38, further comprising: storing data processed by the hardware accelerator simulated by the accelerator simulator in the simulation storage device.

[0120] Aspect 40: The non-transitory computer-readable medium according to any one of Aspects 37-39 further includes: implementing the hardware accelerator as a non-volatile memory express (NVMe) device, and providing an NVMe driver for controlling the NVMe device to execute data processing commands.

[0121] Aspect 41: The non-transitory computer-readable medium according to any one of Aspects 37-40, further comprising: running a profiler together with a provided user application or emulator library to collect performance statistics.

[0122] Aspect 42: The non-transitory computer-readable medium according to any one of Aspects 37-41, further comprising: including a profiler library in a profiler or emulator library, the profiler library providing an API for hooking or callback of performance statistics to the profiler.

[0123] Aspect 43: The platform of any one of Aspects 1-8, wherein the accelerator emulator is configured to emulate a hardware accelerator on a thread pool provided by one or more CPU cores.

[0124] Aspect 44: The platform of Aspect 43, wherein the accelerator emulator is configured to emulate a plurality of hardware accelerators operating in parallel on a thread pool.

[0125] The terms used in this specification are intended to describe specific embodiments and are not restrictive. The terms "a", "an" and "the" also include plural forms unless otherwise expressly indicated. When used in this specification, the terms "include" and / or "comprise" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements and / or components.

[0126] With respect to the foregoing description, it should be understood that changes may be made in detail, especially in the construction materials adopted and the shapes, sizes and arrangements of the parts, without departing from the scope of the present disclosure. This specification and the described embodiments are exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A platform for emulating hardware offloading, the platform comprising, when executed on a host system: a guest system, running on the host system, the guest system being configured to receive a data processing command; a virtual device interface for communicating between the guest system and the accelerator emulator; as well as A hardware accelerator is emulated by the accelerator emulator to execute the data processing command received through the virtual device interface, wherein the hardware accelerator includes an offload hardware component and a controller component.

2. The platform according to claim 1, wherein The controller component emulates and interprets data processing commands from the guest system.

3. The platform according to claim 1, wherein The offload hardware component emulates execution of the data processing command in the hardware accelerator.

4. The platform according to claim 1, wherein The hardware accelerator is emulated in the fast emulator QEMU as a virtual device that communicates with the guest system.

5. The platform according to claim 1, wherein The host system includes an emulated storage device, and the emulated storage device is used for emulating and storing data processed by the hardware accelerator.

6. The platform according to claim 1, wherein The guest system further includes an emulator library included in the guest system, the emulator library providing an application programming interface (API) to offload data operations to the hardware accelerator emulated by the accelerator emulator according to the data processing command.

7. The platform according to claim 1, wherein The hardware accelerator is simulated by the accelerator emulator as a non-volatile fast memory NVMe device, and The emulator library includes an NVMe driver for controlling the NVMe device.

8. The platform of claim 1, further comprising a profiler that obtains performance statistics from the guest system.

9. The platform of claim 8, wherein the profiler or emulator library comprises a profiler library that provides an API for hooks or callbacks of performance statistics to the profiler.

10. A method for simulating a hardware accelerator, the method comprising: Running the guest system on a host system that provides an emulation platform; The guest system receives a data processing command; An accelerator emulator emulates the hardware accelerator; The hardware accelerator receives the data processing command through a virtual device interface; as well as The controller component of the hardware accelerator controls the offload hardware component of the hardware accelerator to simulate execution of the data processing command by the hardware accelerator. 11 . The method according to claim 10 , wherein the accelerator emulator emulates a hardware accelerator as a virtual device communicating with the guest system in a fast emulator QEMU.

12. The method according to claim 10, further comprising: A profiler obtains performance statistics from the guest system.

13. A non-transitory computer-readable medium having computer-executable instructions stored thereon, the computer-executable instructions, when executed, causing one or more processors to perform operations for emulating a hardware accelerator, comprising: Running a guest system in a host system that provides an emulation platform; receiving a data processing command from the guest system; Use the accelerator simulator to simulate the hardware accelerator; receiving the data processing command into the hardware accelerator through a virtual device interface; as well as The controller component of the hardware accelerator is used to control the offload hardware component of the hardware accelerator to simulate the execution of the data processing command by the hardware accelerator.

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