Method and device for managing accelerator, equipment and storage medium

Abstract

The embodiment of the invention provides a method and device for managing an accelerator, equipment and a storage medium. A method for managing accelerators includes obtaining interface information associated with a set of accelerators in a computing device, the interface information indicating at least respective identification information and respective mapping information of the set of accelerators, where the mapping information of one accelerator indicates hardware resources in the computing device for the accelerator; initializing, using a driver of the computing device, a set of accelerators according to the interface information; and executing the task with at least a portion of the initialized set of accelerators. In this way, the configuration flexibility and utilization rate of the accelerator can be improved.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to the field of computers, and more particularly to methods, devices, apparatuses, and computer-readable storage media for managing accelerators. Background Art

[0002] With the rapid development of big data and artificial intelligence applications, the demand for computing power has also increased significantly. For example, processors need to be extremely efficient when handling complex data analysis, machine learning, and deep learning tasks, so it is expected that processors can be configured in a more efficient way. Summary of the invention

[0003] In a first aspect of the present disclosure, a method for managing an accelerator is provided. The method comprises: obtaining interface information associated with a group of accelerators in a computing device, the interface information at least indicating corresponding identification information and corresponding mapping information of the group of accelerators, wherein the mapping information of one accelerator indicates hardware resources for the accelerator in the computing device; using a driver of the computing device to initialize the group of accelerators according to the interface information; and using at least a portion of the initialized group of accelerators to perform a task.

[0004] In a second aspect of the present disclosure, a device for managing accelerators is provided. The device includes: an interface information acquisition module configured to acquire interface information associated with a group of accelerators in a computing device, the interface information at least indicating corresponding identification information and corresponding mapping information of a group of accelerators, wherein the mapping information of one accelerator indicates hardware resources for the accelerator in the computing device; an accelerator initialization module configured to use a driver of the computing device to initialize the group of accelerators according to the interface information; and a task execution module configured to use at least a portion of the initialized group of accelerators to execute a task.

[0005] In a third aspect of the present disclosure, an electronic device is provided. The device includes at least one processing unit; and at least one memory, the at least one memory is coupled to the at least one processing unit and stores instructions for execution by the at least one processing unit. When the instructions are executed by the at least one processing unit, the device executes the method of the first aspect.

[0006] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and the computer program can be executed by a processor to implement the method of the first aspect.

[0007] It should be understood that the contents described in this content section are not intended to limit the key features or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0009] Figure 1 A schematic diagram showing an example environment in which embodiments of the present disclosure can be implemented;

[0010] Figure 2 A schematic diagram showing an example architecture of a processing unit including an accelerator according to some embodiments of the present disclosure;

[0011] Figure 3 A schematic diagram showing an example mapping relationship between an accelerator and other hardware resources according to some embodiments of the present disclosure;

[0012] Figure 4 A schematic diagram showing an example of interface information according to some embodiments of the present disclosure;

[0013] Figure 5 A schematic diagram showing an example for managing an accelerator according to some embodiments of the present disclosure;

[0014] Figure 6 A flowchart of a method for managing an accelerator according to some embodiments of the present disclosure is shown;

[0015] Figure 7 A block diagram showing an apparatus for managing an accelerator according to some embodiments of the present disclosure; and

[0016] Figure 8 A block diagram of a device capable of implementing various embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0017] It is understandable that before using the technical solutions disclosed in the embodiments of the present disclosure, the types, scope of use, usage scenarios, etc. of the personal information involved in the present disclosure should be informed to the user and the user's authorization should be obtained in an appropriate manner in accordance with relevant laws and regulations.

[0018] For example, in response to receiving an active request from a user, a prompt message is sent to the user to clearly prompt the user that the operation requested to be performed will require obtaining and using the user's personal information. Thus, the user can autonomously choose whether to provide personal information to software or hardware such as an electronic device, application, server, or storage medium that performs the operation of the technical solution of the present disclosure according to the prompt message.

[0019] As an optional but non-limiting implementation, in response to receiving an active request from the user, the prompt information may be sent to the user in the form of a pop-up window, in which the prompt information may be presented in text form. In addition, the pop-up window may also carry a selection control for the user to select "agree" or "disagree" to provide personal information to the electronic device.

[0020] It is understandable that the above notification and the process of obtaining user authorization are merely illustrative and do not constitute a limitation on the implementation of the present disclosure. Other methods that meet the relevant laws and regulations may also be applied to the implementation of the present disclosure.

[0021] It is understandable that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and relevant provisions.

[0022] The term "in response to" as used herein refers to a state in which a corresponding event occurs or a condition is satisfied. It will be understood that the timing of executing a subsequent action executed in response to the event or condition is not necessarily strongly related to the time when the event occurs or the condition is satisfied. For example, in some cases, the subsequent action may be executed immediately when the event occurs or the condition is satisfied; while in other cases, the subsequent action may be executed some time after the event occurs or the condition is satisfied.

[0023] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0024] It should be noted that the titles of any sections / subsections provided herein are not restrictive. Various embodiments are described throughout this article, and any type of embodiment may be included under any section / subsection. In addition, the embodiments described in any section / subsection may be combined in any manner with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0025] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may be included below. The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may be included below.

[0026] As briefly mentioned above, due to the increasing demand for computing power, traditional general-purpose processors may not be efficient enough when handling complex data analysis, machine learning, and deep learning tasks. Considering that general-purpose processors may consume more energy when handling specific tasks, the introduction of specialized accelerators can provide higher energy efficiency and lower power consumption. This is crucial for extending battery life, reducing heat generation, and improving device performance. For example, a graphics processing unit (GPU) can work more efficiently than a central processing unit (CPU) in graphics rendering. For another example, a tensor processing unit (TPU) designed for deep learning tasks can significantly increase the speed of machine learning model training and reasoning.

[0027] In addition, some accelerators supported by application platforms usually have programmable features, allowing developers to customize and optimize them as needed. Therefore, accelerators become an important solution to meet application needs.

[0028] Some accelerator devices, such as those for the Peripheral Component Interconnect Express (PPCIe) bus standard, can be configured on an X86 application platform. However, there is no universal solution for configuring accelerator devices for non-PCIe bus standards on some application platforms, such as platforms based on advanced reduced instruction sets.

[0029] In order to at least partially solve the above problems, an embodiment of the present disclosure proposes a solution for managing accelerators. According to various embodiments of the present disclosure, interface information associated with a group of accelerators in a computing device is obtained. The interface information at least indicates the corresponding identification information and corresponding mapping information of these accelerators. The mapping information of each accelerator indicates the hardware resources used for the accelerator in the computing device, such as an address translation unit, an interrupt service unit, etc. The driver of the computing device then initializes the group of accelerators according to the interface information, for example, enumerates these accelerators. Further, in subsequent business processing, at least a part of this group of initialized accelerators is used to perform tasks according to actual needs. According to an embodiment of the present disclosure, the accelerator is used as a platform device, and PCIe enumeration is not required, but the enumeration of the accelerator is completed by the driver. As a result, the configuration flexibility and utilization rate of the accelerator can be improved.

[0030] Example embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0031] Figure 1 A schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented is shown. In the environment 100, a computing device 110 includes hardware for performing computing-related tasks. Such a computing device 110 is, for example, a personal computer, a server, a mobile device, and the like.

[0032] The computing device 110 includes one or more accelerators 130, such as accelerator 130-1, accelerator 130-2, ... accelerator 130-N, etc. These accelerators may be individually or collectively referred to as accelerators 130. Such accelerators 130 may be utilized to increase the execution speed of a particular type of task (such as graphics processing, machine learning, etc.) or a particular type of data.

[0033] The operating system 120 may be software running on the computing device 110 for allocating resources to applications running on the computing device 110. Furthermore, the operating system 120 may utilize the computing device 110 to perform tasks, and may also utilize the accelerator 130 to accelerate specific types of tasks or specific types of data.

[0034] It should be understood that the structure and functionality of the environment 100 are described for exemplary purposes only and do not imply any limitation on the scope of the present disclosure. Figure 2 and Figure 3 Describes the architecture used to manage accelerators from a hardware perspective.

[0035] Figure 2A schematic diagram of an example architecture 200 of a processing unit including an accelerator according to some embodiments of the present disclosure is shown. The architecture 200 may include multiple processing units, such as processing unit 210-1, processing unit 210-2, ... processing unit 210-X, etc. These processing units may be referred to as processing units 210 individually or collectively.

[0036] Each processing unit 210 may include multiple processing cores, such as processing core 220-1, processing core 220-2, ... processing core 220-Y, etc. These processing cores may be individually or collectively referred to as processing cores 220. As a basic component of processing unit 210, processing core 220 may execute various instructions and coordinate system resources in a coordinated or independent manner. Processing core 220 may run multiple threads or processes simultaneously and share certain resources such as cache, registers, etc.

[0037] Each processing unit 210 may further include a system memory management unit (SMMU) 230. The SMMU 230 may be used for address translation between an interface device and a bus, memory attribute translation, permission checking, and the like.

[0038] Each processing unit 210 may also include an accelerator 130. In some embodiments, such as Figure 2 As shown, the accelerator 130 may include multiple acceleration units, such as acceleration unit 250-1, acceleration unit 250-2, ..., acceleration unit 250-Z, etc. These acceleration units may be individually or collectively referred to as acceleration units 250. The accelerator 130 including multiple acceleration units 250 is also referred to as a first accelerator.

[0039] In some embodiments, an accelerator 130 can be regarded as an independent platform device, as a parent device of multiple acceleration units 250 attached to it. Therefore, unified acceleration unit resource management, device overall error handling and recovery and other operational support can be provided for the accelerator.

[0040] In some embodiments, depending on the device configuration settings in the basic input / output system (BIOS) and the support of the dynamic advanced configuration and power interface (ACPI), one acceleration unit 250 can be regarded as an independent platform device, or a combination of multiple acceleration units 250 can be regarded as a platform device. Thus, one or more acceleration units 250 can be used as a sub-device attached to an accelerator 130.

[0041] It should be understood that although each processing unit 210 is shown as including the same number of processing cores and acceleration units, these processing units 210 may respectively include any appropriate number of processing cores and acceleration units, or may only include an appropriate number of processing cores and one accelerator, and the present disclosure is not limited to this.

[0042] Figure 3 A schematic diagram of an example mapping relationship 300 between an accelerator and other hardware resources according to some embodiments of the present disclosure is shown. The mapping relationship 300 generally involves the accelerator 130, the SMMU 230, and the interrupt controller 320. For the accelerator 130, the SMMU 230 and the interrupt controller 320 can be regarded as hardware resources available to the accelerator 130 in the computing device 110.

[0043] The accelerator 130 is mounted to the bus 310 through the SMMU 230. The SMMU 310 is used to achieve security isolation between the accelerators 130 or between the multiple acceleration units 250 included in each accelerator 130. For example, the SMMU 310 can assign a stream ID (Stream ID, SID) to each attached or mounted accelerator 130. Thus, the SID can be used to identify different accelerators 130, thereby achieving security isolation between accelerators. For another example, the SMMU 310 can also assign a substream ID (SubStream ID, SSID) to each attached or mounted acceleration unit 250. Thus, the SSID can be used to identify different acceleration units 250, thereby achieving isolation of process address space.

[0044] The SMMU 230 can convert the stream identifier into a device identifier (device ID) recognizable by the interrupt controller 320, and communicate with the interrupt controller 320 through the bus 310. The interrupt controller 320 is used to manage and distribute interrupt signals generated by hardware devices. For example, the accelerator 130 or the acceleration unit 250 triggers an interrupt signal, and such an interrupt signal is sent to the interrupt controller 320 via the SMMU 230. The interrupt controller 320 provides an interrupt translation service (ITS) so that the operating system 120 determines which accelerator 130 or which acceleration unit 250 the interrupt signal is triggered by, and then executes the corresponding interrupt handler.

[0045] The above describes an example architecture for managing accelerators from a hardware level. The example architecture 200 and the example mapping relationship 300 can be implemented in the environment 100. Figure 1 , the operating system 120 may obtain interface information associated with a set of accelerators 130 in the computing device 110. Such interface information may include corresponding identification information of the set of accelerators 130, and may also include corresponding mapping information. The mapping information of each accelerator 130 may indicate hardware resources for the accelerator in the computing device 110, such as indicating the SMMU and ITS for the accelerator.

[0046] In some embodiments, the interface information may be reported by the firmware to the operating system 120. For example, during a power-on self-test (POST) phase, the firmware may report the interface information used by the accelerator 130 to the operating system 120.

[0047] In some embodiments, the interface information may include description tables and mapping tables to help the operating system 120 identify the accelerator and determine hardware resources for the accelerator. Figure 4 A schematic diagram of an example 400 of interface information according to some embodiments of the present disclosure is shown. The example 400 may include at least one of a mapping table 410, a description table 420 (also referred to as a first description table), or a description table 430 (also referred to as a second description table).

[0048] In some embodiments, mapping table 410 indicates hardware resources for each accelerator in computing device 110, such as SMMU, interrupt translation services provided by an interrupt controller, etc. Exemplarily, mapping table 410 includes ITS node 412, SMMU node 414, and component node 416. In mapping table 410, component node 416 indicates accelerator 130 (e.g., Figure 4 The mapping relationship between the accelerator 1, accelerator 2, accelerator 3, etc. shown in the figure and the SMMU and ITS is shown in the figure. Through such a mapping table 410, it can be ensured that the accelerator 130 can normally initiate interrupts in the operating system 120, such as line interrupts and message signal interrupts (MSI). The SMMU node 414 indicates the SMMU hardware information in the computing device 110, and the ITS node 416 indicates the ITS-related hardware information in the computing device 110. The mapping table 410 can be, for example, an input-output remapping table (IORT).

[0049] In some embodiments, the description table 420 includes a set of corresponding hardware identifiers (HIDs) and corresponding register addresses of the accelerator 130 to ensure that the operating system can normally access the registers of the accelerator 130. Such a description table 420 may include, for example, a differentiated system description table (DSDT). In the Advanced Configuration and Power Interface (ACPI) specification, the DSDT supports matching the defined and described hardware identifiers to the corresponding accelerators.

[0050] A hardware identifier is a unique identification symbol used to mark and distinguish a hardware device, also known as a hardware identifier, which usually includes a set of numbers and letters. Generally speaking, a hardware identifier is assigned to each device by a device manufacturer during the manufacturing process. However, the ACPI specification does not describe an accelerator 130 that is considered a platform device.

[0051] In some embodiments, a set of hardware identifiers of accelerators can be customized to ensure that the operating system 120 can identify and run the accelerators. Exemplarily, the accelerator 130 includes three types of accelerators, such as CDA accelerators, DTE accelerators, and DLA accelerators. For CDA accelerators, their hardware identifiers are, for example, BCDA0000, BCDA0001, BCDA0002, etc. For DTE accelerators, their hardware identifiers are, for example, BDTE0000, BDTE0001, BDTE0002, etc. For DLA accelerators, their hardware identifiers are, for example, DBLA0000, DBLA0001, DBLA002, etc. In this way, it is possible to use the accelerator as a platform device and assign a hardware identifier to it.

[0052] In some embodiments, one or some of the accelerators 130 (also referred to as the first accelerator) may include multiple acceleration units 250, or multiple acceleration units of the first accelerator may need to be exposed to the operating system as platform devices. In such an embodiment, the description table 420 may include a hardware identifier of the first accelerator and a register address corresponding to the first accelerator, and may also include register addresses corresponding to each acceleration unit. Thus, it is possible to use the acceleration unit as a sub-device and assign a register address to it. In this way, flexible configuration of the acceleration unit can be achieved.

[0053] In some embodiments, the description table 430 includes corresponding identifiers of hardware resources for a group of accelerators 130 in the computing device 110 to ensure that the group of accelerators 130 can normally access the interrupt controller. Such a description table 420 includes, for example, an Advanced Programmable Interrupt Controller Description Table (MADT). In the ACPI specification, the MADT contains relevant information about the interrupt controller, such as Figure 4 The ITS index shown in , ITS 0, ITS1, ITS2, etc.

[0054] The interface information associated with a set of accelerators 130 is described above through multiple embodiments. After obtaining such interface information, the operating system 120 can use the driver of the computing device 110 to initialize a set of accelerators 130 according to such interface information. In other words, the driver enumerates the reported accelerators and their acceleration units (if applicable). Exemplarily, the driver first detects the accelerators 130 in the computing device 110, and then enumerates and initializes the available accelerators 130 one by one. Further, the operating system 120 can use the initialized accelerators 130 to perform tasks. Exemplarily, after initializing the accelerators 130, the operating system 120 can select an accelerator with a suitable computing architecture and programming interface from the initialized accelerators 130 to perform calculations. The following reference Figure 5 A specific example is described.

[0055] Figure 5 A schematic diagram of an example 500 for managing an accelerator according to some embodiments of the present disclosure is shown. Specifically, in block 510, the firmware side reports interface information associated with the accelerator, such as Figure 4 IORT, MADT, DSDT, etc. in the ACPI shown. In box 520, the driver side matches the accelerator according to the reported interface information and performs accelerator enumeration. That is, the driver side searches for all available accelerators in the computing device 110 and performs hardware enablement on the found accelerators. In box 530, the user side uses at least a portion of the enumerated accelerators to perform specific tasks, such as parallel computing tasks. Depending on the specific implementation, the user side can use one or more of the enumerated accelerators, or one or more acceleration units.

[0056] In some embodiments, the operating system 120 (e.g., a driver) can also use the driver to set the sharing mode of the acceleration unit. Such a sharing mode indicates whether the acceleration unit can be shared by multiple processes. In this way, the problem of limiting the number of acceleration units can be solved.

[0057] Exemplarily, the operating system 120 can set multiple acceleration units in a group of accelerators to support the sharing mode as required, so that these acceleration units can only be shared and used by multiple processes. Such multiple acceleration units can be acceleration units attached to one accelerator, or they can be acceleration units attached to different accelerators, and the present disclosure does not limit this. For another example, the firmware side can report which one or which acceleration units support the sharing mode in the interface information. Furthermore, the driver side can set the sharing mode according to the report on the firmware side.

[0058] In some embodiments, the accelerator or acceleration unit can be used as a standalone device. In some embodiments, one or more acceleration units can be assigned to a virtual machine for use. Figure 2 For a processing unit 210, the operating system 120 can also allocate the first number of processing cores 220 and the second number of acceleration units 250 therein to a virtual machine, and execute the task through the virtual machine. In this way, the flexibility of using the acceleration unit in different application scenarios can be achieved.

[0059] Exemplarily, the operating system 120 can use the SMMU 230 to assign an SSID to each acceleration unit 250. When performing virtualization deployment, an appropriate number of processing cores 220 and an appropriate number of acceleration units 250 are bound for use, for example, four processing cores 220 and four acceleration units 250 are assigned to one virtual machine. For different application scenarios, the operating system 120 can also dynamically configure the first number and the second number. Additionally or alternatively, the first number of processing cores 220 and the second number of acceleration units 250 can also be used as an independent device in non-virtualization deployment.

[0060] In some embodiments, computing device 110 is based on an advanced RISC architecture and is Figure 2 As shown, the computing device 110 may include multiple processing units 210, which in turn may include a set of accelerators 130. In this way, the requirements for computing power, energy efficiency and power consumption of an advanced reduced instruction set architecture, as well as diverse application scenarios and requirements for programmability can be met.

[0061] In summary, the present disclosure proposes to use the accelerator as a platform device and define its hardware identification. Furthermore, according to the interface information associated with the accelerator obtained, the driver can be used to complete the initialization of the accelerator and use the initialized accelerator to perform tasks. Thus, the accelerator management solution for non-PCIe bus standards can be implemented without PCIe bus enumeration. In this way, the configuration flexibility and utilization rate of the accelerator can be improved.

[0062] Example Process

[0063] Figure 6 1 is a flowchart of a method 600 for managing an accelerator according to some embodiments of the present disclosure. The method 600 may be implemented at the operating system 120. Figure 1 Method 600 is described.

[0064] In block 610, the operating system 120 obtains interface information associated with a set of accelerators in the computing device. The interface information indicates at least corresponding identification information and corresponding mapping information of a set of accelerators, wherein the mapping information of an accelerator indicates hardware resources for the accelerator in the computing device.

[0065] At block 620 , the operating system 120 utilizes a driver of the computing device to initialize a set of accelerators according to the interface information.

[0066] At block 630 , the operating system 120 utilizes at least a portion of the initialized set of accelerators to execute a task.

[0067] In some embodiments, the interface information is reported by firmware to an operating system of the computing device.

[0068] In some embodiments, the interface information includes at least one of the following: a first description table including corresponding hardware identifications and corresponding register addresses of a set of accelerators, a mapping table indicating, for each accelerator in the set of accelerators, at least one hardware resource in the computing device for the accelerator, or a second description table including corresponding identifications of hardware resources in the computing device for the set of accelerators.

[0069] In some embodiments, at least a first accelerator in a group of accelerators includes multiple acceleration units, and the first description table includes at least any of the following: a hardware identification of the first accelerator, a register address corresponding to the first accelerator, or register addresses corresponding to multiple acceleration units respectively.

[0070] In some embodiments, the at least one hardware resource includes at least one of: a system memory management unit, or an interrupt translation service.

[0071] In some embodiments, initializing a group of accelerators includes: using a driver to set corresponding sharing modes of a plurality of acceleration units, wherein the sharing mode of an acceleration unit indicates whether the acceleration unit is shared by a plurality of processes.

[0072] In some embodiments, the computing device is based on an advanced reduced instruction set architecture, and a set of accelerators is included in a processing unit of the computing device.

[0073] In some embodiments, the computing device includes multiple processing cores, a second accelerator in a group of accelerators includes multiple acceleration units, and executing a task includes: assigning a first number of processing cores in the multiple processing cores and a second number of acceleration units in the multiple acceleration units to a virtual machine; and executing the task through the virtual machine.

[0074] Example devices and equipment

[0075] Figure 7 A schematic structural block diagram of an apparatus 700 for managing an accelerator according to some embodiments of the present disclosure is shown. The apparatus 700 may be implemented as or included in the operating system 120. Each module / component in the apparatus 700 may be implemented by hardware, software, firmware, or any combination thereof.

[0076] As shown in the figure, the apparatus 700 includes an interface information acquisition module 710, which is configured to acquire interface information associated with a group of accelerators in a computing device. The interface information at least indicates corresponding identification information and corresponding mapping information of a group of accelerators, wherein the mapping information of one accelerator indicates the hardware resources used for the accelerator in the computing device. The apparatus 700 also includes an accelerator initialization module 720, which is configured to use a driver of the computing device to initialize a group of accelerators according to the interface information. The apparatus 700 also includes a task execution module 730, which is configured to use at least a part of the initialized group of accelerators to execute a task.

[0077] In some embodiments, the interface information is reported by firmware to an operating system of the computing device.

[0078] In some embodiments, the interface information includes at least one of the following: a first description table including corresponding hardware identifications and corresponding register addresses of a set of accelerators, a mapping table indicating, for each accelerator in the set of accelerators, at least one hardware resource in the computing device for the accelerator, or a second description table including corresponding identifications of hardware resources in the computing device for the set of accelerators.

[0079] In some embodiments, at least a first accelerator in a group of accelerators includes multiple acceleration units, and the first description table includes at least any of the following: a hardware identification of the first accelerator, a register address corresponding to the first accelerator, or register addresses corresponding to multiple acceleration units respectively.

[0080] In some embodiments, the at least one hardware resource includes at least one of: a system memory management unit, or an interrupt translation service.

[0081] In some embodiments, the accelerator initialization module 720 is further configured to use a driver to set corresponding sharing modes of multiple acceleration units, wherein the sharing mode of an acceleration unit indicates whether the acceleration unit is shared by multiple processes.

[0082] In some embodiments, the computing device is based on an advanced reduced instruction set architecture, and a set of accelerators is included in a processing unit of the computing device.

[0083] In some embodiments, the computing device includes multiple processing cores, a second accelerator in a group of accelerators includes multiple acceleration units, and the task execution module is also configured to assign a first number of processing cores in the multiple processing cores and a second number of acceleration units in the multiple acceleration units to the virtual machine; and execute the task through the virtual machine.

[0084] Figure 8 A block diagram of an electronic device 800 is shown in which one or more embodiments of the present disclosure may be implemented. It should be understood that Figure 8The electronic device 800 shown is merely exemplary and should not constitute any limitation on the functionality and scope of the embodiments described herein. Figure 8 The electronic device 800 shown can be used to implement Figure 1 operating system 120.

[0085] like Figure 8 As shown, the electronic device 800 is in the form of a general electronic device. The components of the electronic device 800 may include, but are not limited to, one or more processors or processing units 810, a memory 820, a storage device 830, one or more communication units 840, one or more input devices 850, and one or more output devices 860. The processing unit 810 may be an actual or virtual processor and is capable of performing various processes according to a program stored in the memory 820. In a multi-processor system, multiple processing units execute computer executable instructions in parallel to improve the parallel processing capability of the electronic device 800.

[0086] The electronic device 800 typically includes a plurality of computer storage media. Such media may be any accessible media that is accessible to the electronic device 800, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 820 may be a volatile memory (e.g., a register, a cache, a random access memory (RAM)), a non-volatile memory (e.g., a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 830 may be a removable or non-removable medium, and may include a machine-readable medium, such as a flash drive, a disk, or any other medium, which may be capable of being used to store information and / or data (e.g., training data for training) and may be accessed within the electronic device 800.

[0087] The electronic device 800 may further include additional removable / non-removable, volatile / non-volatile storage media. Figure 8 As shown in , a disk drive for reading or writing from a removable, non-volatile disk (e.g., a "floppy disk") and an optical drive for reading or writing from a removable, non-volatile optical disk may be provided. In these cases, each drive may be connected to the bus (not shown) by one or more data media interfaces. The memory 820 may include a computer program product 825 having one or more program modules that are configured to perform various methods or actions of various embodiments of the present disclosure.

[0088] The communication unit 840 implements communication with other electronic devices through a communication medium. Additionally, the functions of the components of the electronic device 800 can be implemented with a single computing cluster or multiple computing machines that can communicate through a communication connection. Therefore, the electronic device 800 can operate in a networked environment using a logical connection with one or more other servers, a network personal computer (PC), or another network node.

[0089] The input device 850 may be one or more input devices, such as a mouse, a keyboard, a tracking ball, etc. The output device 860 may be one or more output devices, such as a display, a speaker, a printer, etc. The electronic device 800 may also communicate with one or more external devices (not shown) through the communication unit 840 as needed, such as a storage device, a display device, etc., communicate with one or more devices that allow a user to interact with the electronic device 800, or communicate with any device that allows the electronic device 800 to communicate with one or more other electronic devices (e.g., a network card, a modem, etc.). Such communication may be performed via an input / output (I / O) interface (not shown).

[0090] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored, wherein the computer-executable instructions are executed by a processor to implement the method described above. According to an exemplary implementation of the present disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, and the computer-executable instructions are executed by a processor to implement the method described above.

[0091] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices, equipment, and computer program products implemented according to the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0092] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0093] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0094] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple implementations of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some implementations as replacements, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and computer instructions.

[0095] The above descriptions of various implementations of the present disclosure are exemplary, non-exhaustive, and not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The selection of terms used herein is intended to best explain the principles of the implementations, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the various implementations disclosed herein.

Claims

1. A method for managing an accelerator, comprising: Acquire interface information associated with a group of accelerators in a computing device, the interface information at least indicating corresponding identification information and corresponding mapping information of the group of accelerators, wherein the mapping information of one accelerator indicates hardware resources for the accelerator in the computing device; Initializing the set of accelerators according to the interface information using a driver of the computing device; as well as A task is performed using at least a portion of the initialized set of accelerators. 2 . The method according to claim 1 , wherein the interface information is reported by firmware to an operating system of the computing device.

3. The method according to claim 1, wherein the interface information comprises at least one of the following: A first description table includes corresponding hardware identifiers and corresponding register addresses of the group of accelerators, a mapping table, for each accelerator in the set of accelerators, indicating at least one hardware resource in the computing device for the accelerator, or The second description table includes corresponding identifiers of hardware resources for the group of accelerators in the computing device.

4. The method of claim 3, wherein at least a first accelerator in the set of accelerators comprises a plurality of acceleration units, and the first description table comprises at least any one of the following: a hardware identifier of the first accelerator, corresponds to the register address of the first accelerator, or The register addresses respectively correspond to the multiple acceleration units.

5. The method according to claim 3, wherein the at least one hardware resource comprises at least one of the following: The system memory management unit, or Interruption of translation service.

6. The method of claim 4, wherein initializing the set of accelerators comprises: The driver is used to set corresponding sharing modes of the plurality of acceleration units, wherein the sharing mode of one acceleration unit indicates whether the acceleration unit is shared by a plurality of processes. 7 . The method according to claim 1 , wherein the computing device is based on an advanced reduced instruction set architecture, and the set of accelerators is included in a processing unit of the computing device.

8. The method of claim 1 , wherein the computing device comprises a plurality of processing cores, a second accelerator in the set of accelerators comprises a plurality of acceleration units, and performing the task comprises: Allocating a first number of processing cores among the plurality of processing cores and a second number of acceleration units among the plurality of acceleration units to a virtual machine; as well as The task is executed by the virtual machine.

9. A device for managing an accelerator, comprising: an interface information acquisition module, configured to acquire interface information associated with a group of accelerators in a computing device, wherein the interface information at least indicates corresponding identification information and corresponding mapping information of the group of accelerators, wherein the mapping information of one accelerator indicates hardware resources for the accelerator in the computing device; an accelerator initialization module, configured to initialize the set of accelerators according to the interface information using a driver of the computing device; as well as The task execution module is configured to execute a task using at least a portion of the initialized set of accelerators.

10. An electronic device, comprising: at least one processing unit; as well as At least one memory, the at least one memory being coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions causing the electronic device to perform the method according to any one of claims 1 to 8 when executed by the at least one processing unit.

11. A computer-readable storage medium having a computer program stored thereon, wherein the computer program can be executed by a processor to implement the method according to any one of claims 1 to 8.

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