Model arrangement method and device, electronic equipment, storage medium and computer program product

Abstract

The invention discloses a model arrangement method and device, electronic equipment, a storage medium and a computer program product, and the method comprises the steps: determining a first task node in a plurality of task nodes of a first model under the condition that the accuracy rate of an output result of the first model deployed on a storage and calculation integrated chip is smaller than a first threshold; progressively increasing the number of the weight parameters of the same first task node, and updating the first model; the first task node represents a task node of which the weight parameter needs to be copied; the input of the same first task node is the same.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence technology, and in particular to a model compilation method, device, electronic device, storage medium and computer program product. Background Art

[0002] In order to break through the storage wall and power consumption wall problems caused by the von Neumann architecture that separates storage and computing, the integrated storage and computing chip architecture has received widespread attention. Currently, before using an integrated storage and computing chip to perform a task, the model is deployed on the integrated storage and computing chip, and the model is arranged with the weights required for each task node to perform the task. Most models consider duplicating different weights to increase parallelism during the weight arrangement process, so that the calculation of task nodes with large computational workloads can be completed within one computing cycle, but there is a problem that the accuracy of the calculation cannot be guaranteed. Summary of the invention

[0003] To solve related technical problems, embodiments of the present application provide a model compilation method, device, electronic device, storage medium and computer program product.

[0004] The technical solution of the embodiment of the present application is implemented as follows:

[0005] The present application provides a model arrangement method, the method comprising:

[0006] When the accuracy of the output result of the first model deployed on the storage-computing integrated chip is less than the first threshold, a first task node is determined among the multiple task nodes of the first model, and the first task node represents the task node for which the weight parameter needs to be copied; the input of the same first task node is the same;

[0007] The number of weight parameters of the same first task node is increased incrementally to update the first model.

[0008] In the above scheme, the method further comprises:

[0009] In the case where the accuracy of the output result of the first model is greater than or equal to the first threshold, determining a second task node and a first value of the second task node among the multiple task nodes of the first model, the second task node represents a task node that needs to copy a weight parameter, and the first value represents the number of copies of the weight parameter of the same second task node; the inputs of the same second task node are different;

[0010] Determine a second model based on the first model, the second task node, and the first value of the second task node;

[0011] Deploy the second model onto the storage and computing integrated chip.

[0012] In the above solution, after deploying the second model on the storage-computing integrated chip, the method further includes:

[0013] When the accuracy of the output result of the second model deployed on the integrated storage and computing chip is less than a second threshold, the first threshold is updated and the first model is restored on the integrated storage and computing chip.

[0014] In the above scheme, the method further includes:

[0015] When the accuracy of the output result of the first model restored on the integrated storage and computing chip is less than the updated first threshold, the step of determining the first task node from the multiple task nodes of the first model is executed.

[0016] In the above scheme, the method further includes:

[0017] When the accuracy of the output result of the first model restored on the integrated computing and storage chip is greater than or equal to the updated first threshold, the step of determining the second task node and the first value of the second task node among the multiple task nodes of the first model is executed.

[0018] In the above solution, the first threshold is determined based on the second threshold and the accuracy evaluation coefficient; and updating the first threshold includes:

[0019] The accuracy evaluation coefficient is corrected based on the second value to obtain a corrected accuracy evaluation coefficient; the second value is determined based on the second threshold and the accuracy of the output result of the second model deployed on the storage-computing integrated chip;

[0020] Based on the corrected accuracy evaluation coefficient and the second threshold, an updated first threshold is determined.

[0021] In the above solution, determining the first task node from the plurality of task nodes of the first model includes:

[0022] determining a first task node from among a plurality of task nodes of the first model based on a third value of each task node of the first model; or,

[0023] Based on the third value and the fourth value of each task node of the first model, a first task node is determined from a plurality of task nodes of the first model; wherein,

[0024] The third numerical value represents the deviation between the actual output result of the task node of the first model and the corresponding benchmark output result, and the fourth numerical value represents the number of storage and computing units corresponding to a weight parameter of the task node in the storage and computing integrated chip.

[0025] In the above solution, updating the first model includes:

[0026] Copying the incremented weight parameter of the first task node to the idle storage and computing unit of the storage and computing integrated chip;

[0027] All output results of the same first task node are averaged and used as input of the next task node adjacent to the same first task node to update the first model.

[0028] In the above solution, the first threshold is determined based on at least the second threshold; and the method further includes:

[0029] When the accuracy of the output result of the first model is less than the first threshold, and the number of storage and computing units corresponding to a weight parameter of each task node of the first model in the storage and computing integrated chip is greater than the number of remaining storage and computing units in the storage and computing integrated chip, output information; wherein,

[0030] The information is used to indicate one or more of the following:

[0031] The accuracy of the output result of the first model cannot meet the requirements;

[0032] Retraining the first model;

[0033] The second threshold is updated.

[0034] The present application also provides a model arrangement device, the device comprising:

[0035] A first determination module is used to determine a first task node among multiple task nodes of the first model deployed on the storage-computing integrated chip when the accuracy of the output result of the first model deployed on the storage-computing integrated chip is less than a first threshold, wherein the first task node represents a task node for which weight parameters need to be copied; and the inputs of the same first task node are the same;

[0036] The first updating module is used to increase the number of weight parameters of the same first task node and update the first model.

[0037] The embodiment of the present application also provides an electronic device, including: a processor and a communication interface; wherein,

[0038] The processor is used to determine a first task node among multiple task nodes of a first model deployed on a storage-computing integrated chip when the accuracy of an output result of the first model is less than a first threshold; to increase the number of copies of weight parameters of the same first task node and update the first model; the first task node represents a task node that needs to copy weight parameters; and the input of the same first task node is the same.

[0039] An embodiment of the present application further provides an electronic device, comprising a processor and a memory for storing a computer program that can be run on the processor, wherein the processor is used to execute the steps of any one of the methods described above when running the computer program.

[0040] An embodiment of the present application further provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0041] An embodiment of the present application further provides a computer program product, including a computer program, which implements the steps of any of the above methods when executed by a processor.

[0042] In the model arrangement method, device, electronic device, storage medium and computer program product provided by the embodiments of the present application, when the accuracy of the output result of the first model deployed on the storage-computing integrated chip is less than the first threshold, a first task node is determined among multiple task nodes of the first model, the first task node represents the task node that needs to copy the weight parameter, the number of copies of the weight parameter of the same first task node is increased, the first model is updated, and the input of the same first task node is the same. The above scheme takes into account the accuracy of the output result of the first model deployed on the storage-computing integrated chip, and when the accuracy does not meet the requirements, the first model is updated by increasing the number of copies of the weight parameter of the same first task node, and the input of the same first task node is the same, so as to ensure that the output result of the same first task node can be averaged to reduce the calculation error in the future, thereby improving the output accuracy of the first task node, improving the accuracy of the output result of the updated first model, and ensuring that the calculation accuracy of the first model is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic diagram of the structure of a storage-computing integrated chip applicable to the embodiment of the present application in the related art;

[0044] Figure 2 This is a schematic diagram of the first weight replication applicable to the embodiment of the present application in the related art;

[0045] Figure 3 A schematic diagram of a second weight replication applicable to the embodiment of the present application in the related art;

[0046] Figure 4 A schematic diagram of a model arrangement method flow in an embodiment of the present application;

[0047] Figure 5 A schematic diagram of a process for determining a benchmark output result of each task node of the first model of an embodiment of the present application;

[0048] Figure 6A schematic diagram of a process for determining the actual output result of each task node of the first model of an embodiment of the present application;

[0049] Figure 7 A schematic diagram of updating the first model for an embodiment of the present application;

[0050] Figure 8 This is a schematic diagram of the overall process of the model arrangement method of the embodiment of the present application;

[0051] Fig. 9 This is a schematic diagram of the process flow of the model preparation stage of the embodiment of the present application;

[0052] Fig.10 This is a flow chart of the model accuracy evaluation phase of the embodiment of the present application;

[0053] Fig.11 This is a flow chart of the model deployment phase of the embodiment of the present application;

[0054] Fig.12 This is a schematic diagram of the process flow of the model accuracy test phase of the embodiment of the present application;

[0055] Fig.13 This is a schematic diagram of the structure of the model arrangement device of the embodiment of the present application;

[0056] Fig.14 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0057] In order to break through the storage wall and power consumption wall caused by the von Neumann architecture that separates storage and computing, the integrated storage and computing chip architecture has received widespread attention. As a new computing technology, the integrated storage and computing chip architecture can perform calculations directly in the memory, greatly improving the computing power and energy efficiency. It is particularly suitable for scenarios such as neural networks that require a large amount of memory access and computing, and can be used as the main computing architecture for artificial intelligence (AI) scenarios.

[0058] At present, there are differences in the device structures of different types of storage and computing chips, but the storage and computing principles of storage and computing chips are basically similar. They all achieve the representation of different resistance states by applying pressure to maintain different states of charge in the storage and computing device, that is, the storage of different weight values, and then realize multiplication and addition operations by inputting voltage and outputting current.

[0059] Specifically, the storage-computing integrated chip is prepared in a crossbar array to realize highly parallel matrix multiplication and addition operations in the memory, which is suitable for the reasoning acceleration of deep neural network models. Figure 1 shown. Figure 1 The weight matrix of the integrated storage and computing chip is Among them, G ij is the conductivity, i = 1, 2, 3, j = 1, 2, 3. Due to Ohm's law I = U / R = UG, the conductivity G = 1 / R is determined, I is the current, U is the voltage, and R is the resistance. ij Represents the weight, that is, the conductance value of the cross array of the RRAM storage and computing chip is adjusted according to the data of the weight matrix B. The process of the storage and computing chip performing calculations is to input voltage to the cross array of the RRAM storage and computing chip according to the data of the input matrix. Based on Ohm's law and Kirchhoff's law, the output current is the output matrix. Specifically, in the case of input matrix A, the multiplication and addition calculation I is realized based on Kirchhoff's law. i =∑G ij V j , output matrix C, that is, A*B=C; where A=[V1 V2 V3], V j is voltage, j = 1, 2, 3; I i is the current, i=1, 2, 3; C=[∑G 1j V j ∑G 2j V j ∑G 3j V j ]. It should be understood that Figure 1 This is only an example of a storage-computing integrated chip, and the number of rows and columns of the crossbar array of the specific storage-computing integrated chip is not limited.

[0060] Since the crossbar array unit in the integrated storage and computing chip is both a computing unit and a storage unit, when there is enough storage space in the crossbar array, the same weight matrix data can be copied to multiple crossbar arrays to exchange storage space for improved computing performance, including the following two situations:

[0061] The first case: parallel weight replication can improve the parallelism of calculation;

[0062] Specifically, the first weight replication diagram is as follows: Figure 2 As shown in the figure, in order to shorten the computing delay and improve the throughput, for task nodes with large computing load, the same weight can be mapped on multiple cross arrays to improve the parallelism of the calculation. Figure 2 In each calculation cycle, different crossbar arrays corresponding to the same weight receive different input data, and these input data perform matrix multiplication and addition operations simultaneously, thereby reducing the number of calculation cycles and calculation latency. The number of times the crossbar array is copied is called "parallel granularity". The higher the parallel granularity, the smaller the calculation latency and the higher the calculation throughput. When the crossbar array storage space is sufficient, the calculation of a task node can be completed within the length of a calculation cycle.

[0063] The second case: redundant weight replication can improve calculation accuracy;

[0064] Specifically, the second weight replication schematic diagram is as follows: Figure 3 As shown; the cross array of the integrated storage and computing chip performs calculations in the form of current convergence. Compared with digital logic, the analog computing nature of the integrated storage and computing chip usually results in errors when adjusting the conductance value of the cross array according to the weight parameters, which is mainly manifested as random fluctuations in parameters between different chips, different devices and different cycles; in order to make the conductance value closer to the true value, the weight parameter is usually written multiple times until the difference between the read data and the true value is smaller than expected; but due to the errors in the data reading process itself, and the resistance of the circuit wires of the integrated storage and computing chip, the calculation results based on the integrated storage and computing chip cannot avoid errors. Studies have shown that a 2% random error will affect the accuracy of the final output; in order to improve the calculation accuracy, the same weights are copied to multiple arrays, and redundancy is used to reduce the impact of random errors. Figure 3 In each calculation cycle, different cross arrays corresponding to the same weight receive the same input data, and different cross arrays corresponding to the same weight perform matrix multiplication and addition operations at the same time, and take the average of the output results, thereby reducing the calculation error.

[0065] It is not difficult to see that the essence of parallel weight replication and redundant weight replication is to copy the same weights to multiple cross arrays when deploying the weight parameter model. The only difference is that when performing inference calculations, different cross arrays corresponding to the same weights receive different input data or the same input data. If different data is input to multiple replication arrays in the same computing cycle, the purpose of improving computing parallelism and shortening computing latency can be achieved; if the same data is input to multiple replication arrays in the same computing cycle, the computing accuracy can be improved. However, whether it is to improve computing parallelism or accuracy, it will increase the storage space resource occupancy rate. When hardware storage space resources are limited, model orchestration is required to optimize computing performance.

[0066] At present, before using a storage-computing integrated chip to perform a task, the model will be deployed on the storage-computing integrated chip, and the model will be arranged with the weights required for each task node to perform the task. The weight replication scheme in the storage-computing integrated chip usually considers the computational amount of each task node and the data dependency between each task node during the model arrangement process, and increases the parallelism through weight replication as much as possible within the scope allowed by space resources to shorten the computational delay and ultimately improve the computational energy efficiency. For example, according to the proportional relationship between the data volume of the input data of each convolutional layer in the neural network, the proportional relationship between the number of copies of the weights of each convolutional layer is established. When the total number of computing cores of all convolutional layers does not exceed the total number of computing cores, the number of computing cores of each convolutional layer is maximized, and the non-dominated sorting genetic algorithm is used to minimize the communication power consumption and maximum bandwidth to obtain the final optimized layout result; or, after using the simulated annealing method to screen out the weight replication candidate strategy that meets the array quantity restriction, the genetic algorithm is used to select the macro unit mapping scheme with the best energy consumption and delay ratio, thereby obtaining the convolutional neural network weight replication candidate strategy, the in-memory computing accelerator hardware parameter combination and the hardware resource allocation scheme.

[0067] However, model arrangement in current storage-computing integrated chips mostly shortens computing latency through weight replication. In application scenarios where computing accuracy and reliability are more sensitive, when the random errors inherent in the storage-computing integrated chip itself seriously affect the accuracy of the calculation results, since limited space resources are all used to increase computing parallelism, weight replication cannot be performed to suppress random errors, resulting in the calculation accuracy being unable to meet application requirements.

[0068] Based on this, in various embodiments of the present application, when the accuracy of the output result of the first model deployed on the storage-computing integrated chip is less than the first threshold, a first task node is determined among multiple task nodes of the first model, the first task node represents the task node that needs to copy the weight parameter, the number of copies of the weight parameter of the same first task node is increased, and the first model is updated, and the input of the same first task node is the same. The above scheme takes into account the accuracy of the output result of the first model deployed on the storage-computing integrated chip, and when the accuracy does not meet the requirements, the first model is updated by increasing the number of copies of the weight parameter of the same first task node, and the input of the same first task node is the same, so as to ensure that the output result of the same first task node can be averaged to reduce the calculation error in the future, thereby improving the output accuracy of the first task node, improving the accuracy of the output result of the updated first model, and ensuring that the calculation accuracy of the first model is high.

[0069] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0070] The embodiment of the present application provides a model arrangement method, which is applied to an electronic device, which may have a display screen or display function, or may be connected to a display screen; the electronic device includes a terminal and / or a device with a display screen or display function. Figure 4 As shown, including:

[0071] Step 401: When the accuracy of the output result of the first model deployed on the storage and computing integrated chip is less than a first threshold, determine a first task node among multiple task nodes of the first model.

[0072] The first task node represents a task node that needs to copy weight parameters; the input of the same first task node is the same.

[0073] Here, the first model is used to perform the set task, including the weights required for multiple task nodes. The set task can be set according to actual needs. The calculation method of the accuracy of the output result of the first model deployed on the storage and computing integrated chip is determined based on the model type of the first model and / or the task type of the set task. For example, if the first model is a classification model, the accuracy of the output result of the first model deployed on the storage and computing integrated chip is obtained by dividing the fifth value by the sixth value, and the fifth value represents the number of output results of the first model deployed on the storage and computing integrated chip that matches the expected result, and the sixth value represents the total number of output results of the first model deployed on the storage and computing integrated chip; if the first model is a regression model, the accuracy of the output result of the first model deployed on the storage and computing integrated chip is the mean square error or root mean square error of the output result of the first model deployed on the storage and computing integrated chip.

[0074] The first threshold can be set according to actual needs, or it can be determined based on the second threshold and the accuracy evaluation coefficient. In the case where the first threshold is determined based on the second threshold and the accuracy evaluation coefficient, the first threshold can be the product of the second threshold and the accuracy evaluation coefficient; the second threshold can be set according to actual needs, or it can be determined based on the model type of the first model and / or the task type of the set task; the accuracy evaluation coefficient can be set to an initial value of 1, or it can be set according to actual needs.

[0075] When the accuracy of the output result of the first model deployed on the storage-computing integrated chip is less than the first threshold, the first task node is determined among the multiple task nodes of the first model. The first task node can be determined among the multiple task nodes of the first model based on the deviation between the actual output result of the task node of the first model and the corresponding benchmark output result; or the first task node can be determined among the multiple task nodes of the first model based on the deviation between the actual output result of the task node of the first model and the corresponding benchmark output result, and the number of storage-computing units corresponding to a weight parameter of the task node in the storage-computing integrated chip. It is worth noting that the actual output result of the task node is obtained when the input of the task node is the benchmark input, and the benchmark input and benchmark output results are obtained based on the test data set when the first model is not deployed on the storage-computing integrated chip.

[0076] For example, a schematic diagram of the determination process of the benchmark output result of each task node of the first model is as follows: Figure 5 shown. Figure 5 It is shown that in a development environment, the first model is tested based on a test data set. The first model has a total of N task nodes. The test data in the test data set is used as the benchmark input of task node 1, the benchmark output result of task node 1 is used as the benchmark input of task node 2, the benchmark output result of task node 2 is used as the benchmark input of task node 3, the benchmark output result of task node 3 is used as the benchmark input of task node 4, ..., the benchmark output result of task node N-1 is used as the benchmark input of task node N, and the benchmark output result of task node N is used as the expected result of the first model.

[0077] A schematic diagram of the process of determining the actual output result of each task node of the first model is shown in FIG. Figure 6 shown. Figure 6 It is shown that when the first model is deployed on the storage-computing integrated chip, in the storage-computing integrated chip operating environment, the first model has a total of N task nodes, the benchmark input of task node 1 is input to task node 1, and the actual output result of task node 1 is obtained, the benchmark input of task node 2 is input to task node 2, and the actual output result of task node 2 is obtained, the benchmark input of task node 3 is input to task node 3, and the actual output result of task node 3 is obtained, ..., the benchmark input of task node N is input to task node N, and the actual output result of task node N is obtained.

[0078] In one embodiment, determining the first task node among the plurality of task nodes of the first model includes:

[0079] determining a first task node from among a plurality of task nodes of the first model based on a third value of each task node of the first model; or,

[0080] Based on the third value and the fourth value of each task node of the first model, a first task node is determined from a plurality of task nodes of the first model; wherein,

[0081] The third value represents the deviation between the actual output result of the task node of the first model and the corresponding benchmark output result, and the fourth value represents the number of storage and computing units corresponding to a weight parameter of the task node in the storage and computing integrated chip. It is worth noting that the third values ​​of all task nodes of the first model need to be normalized.

[0082] Here, based on the third value of each task node of the first model, determining the first task node from the plurality of task nodes of the first model includes:

[0083] Determine the task node of the first model corresponding to the largest third value or the largest seventh value as the first task node; or

[0084] The first task node is determined from among the plurality of task nodes of the first model according to a first setting sequence, wherein the first setting sequence represents the order in which the third value or the seventh value of each task node of the first model is sorted from large to small. The seventh value is the product of the third value and the first correction coefficient, and the first correction coefficient can be set according to actual needs.

[0085] It is worth noting that every time the accuracy of the output result of the first model deployed on the storage and computing integrated chip is less than the first threshold, the first task node is determined once, and the number of first task nodes determined each time is one.

[0086] Determine the first task node from multiple task nodes of the first model according to the first set order. Specifically, determine the task node located at the first position in the first set order, that is, the task node of the first model corresponding to the maximum third value or the maximum seventh value, as the first task node. When the number of storage and computing units corresponding to a weight parameter of the first task node in the storage and computing chip is greater than the number of remaining storage and computing units in the storage and computing chip, determine the task node located at the second position in the first set order as the first task node, until the number of storage and computing units corresponding to a weight parameter of the first task node in the storage and computing chip is less than or equal to the number of remaining storage and computing units in the storage and computing chip, so as to finally determine the first task node determined currently.

[0087] Determining a first task node from among a plurality of task nodes of the first model based on the third value and the fourth value of each task node of the first model includes:

[0088] Determine the task node of the first model corresponding to the largest eighth value or the largest ninth value as the first task node; or

[0089] The first task node is determined from among the plurality of task nodes of the first model according to the second setting sequence, and the second setting sequence represents the order in which the eighth value or the ninth value of each task node of the first model is sorted from large to small. The eighth value is obtained by dividing the third value by the fourth value; the ninth value is the product of the eighth value and the second correction coefficient, and the second correction coefficient can be set according to actual needs.

[0090] Determine the first task node from multiple task nodes of the first model according to the second set order. Specifically, determine the task node located at the first position in the second set order, that is, the task node of the first model corresponding to the maximum eighth value or the maximum ninth value, as the first task node. When the number of storage and computing units corresponding to a weight parameter of the first task node in the storage and computing integrated chip is greater than the number of remaining storage and computing units in the storage and computing integrated chip, determine the task node located at the second position in the second set order as the first task node, until the number of storage and computing units corresponding to a weight parameter of the first task node in the storage and computing integrated chip is less than or equal to the number of remaining storage and computing units in the storage and computing integrated chip, so as to finally determine the first task node determined currently.

[0091] In this embodiment, a method for determining the first task node among multiple task nodes of the first model is clarified, and the first task node is determined in consideration of the deviation between the actual output result of the task node based on the first model and the corresponding benchmark output result, so that the determined first task node is a task node with lower calculation accuracy. Subsequent weight replication of the first task node can improve the calculation accuracy of the corresponding task node, thereby helping to improve the calculation accuracy of the first model, and the first task node can also be determined in combination with a weight parameter of the task node and the number of storage and computing units corresponding to the storage and computing integrated chip, so that the calculation accuracy can be improved while occupying as few storage and computing units in the storage and computing integrated chip as possible, so as to maximize the utilization of the storage and computing units in the storage and computing integrated chip.

[0092] Step 402: Incrementally increase the number of weight parameters of the same first task node and update the first model.

[0093] It should be understood that the first task node determined each time may be the same or different; the weight parameter of each task node of the first model is initially 1.

[0094] Here, the number of weight parameters of the same first task node is increased, and each time the weight parameter is increased by 1. For example, if the first task node determined for the first time is task node 3, the number of weight parameters of task node 3 is 2, and the first task node determined for the second time is still task node 3, the number of weight parameters of task node 3 is 3.

[0095] The first model may be updated by directly updating the first model on the storage-computing integrated chip, or the first model may be updated and then deployed on the storage-computing integrated chip.

[0096] In this embodiment, the accuracy of the output results of the first model deployed on the storage and computing integrated chip is taken into consideration, and when the accuracy does not meet the requirements, the first model is updated by increasing the number of weight parameters of the same first task node, and the input of the same first task node is the same to ensure that the output results of the same first task node can be averaged to reduce the calculation error, thereby improving the output accuracy of the first task node, improving the accuracy of the output results of the updated first model, and ensuring that the calculation accuracy of the first model is high.

[0097] In one embodiment, updating the first model includes:

[0098] Copying the incremented weight parameter of the first task node to the idle storage and computing unit of the storage and computing integrated chip;

[0099] All output results of the same first task node are averaged and used as input of the next task node adjacent to the same first task node to update the first model.

[0100] Specifically, the schematic diagram of the first model is updated, such as Figure 7 shown. Figure 7 The left side is the structure of the initial first model, and the right side is the structure of the updated first model. The structure of the initial first model includes multiple task nodes, including at least task node n-1, task node n, and task node n+1. It is not difficult to see from the structure of the updated first model that the number of weight parameters of task node n is Rn, and task node n includes task node n1, task node n2, ..., task node n+1. Rn , the input data of Rn task nodes n are the same, and the average of all output results of task node n is taken as the input of task node n+1. It should be understood that Figure 7 The first task node shown is task node n, Figure 7 This is only an example and does not constitute a limitation on the first task node.

[0101] In this embodiment, the weight parameters of the incremental first task nodes are copied to the idle storage and computing units of the storage and computing integrated chip, and all output results of the same first task node are averaged, which can improve the accuracy of the output results of the corresponding task nodes. The average of all output results of the same first task node is used as the input of the next task node adjacent to the same first task node, which can improve the calculation accuracy of the updated first model.

[0102] In one embodiment, the first threshold is determined based on at least the second threshold; in actual application, the second threshold is obtained by multiplying the accuracy rate obtained by running the first model in the development environment by the loss coefficient, and the loss coefficient is determined based on the quantization level and / or hardware characteristics; the model arrangement method further includes:

[0103] When the accuracy of the output result of the first model is less than the first threshold, and the number of storage and computing units corresponding to a weight parameter of each task node of the first model in the storage and computing integrated chip is greater than the number of remaining storage and computing units in the storage and computing integrated chip, output information; wherein,

[0104] The information is used to indicate one or more of the following:

[0105] The accuracy of the output result of the first model cannot meet the requirements;

[0106] Retraining the first model;

[0107] The second threshold is updated.

[0108] The accuracy of the output result of the first model is less than the first threshold, and the number of storage and computing units corresponding to a weight parameter of each task node of the first model in the storage and computing integrated chip is greater than the number of remaining storage and computing units in the storage and computing integrated chip, which indicates that the first task node is determined among multiple task nodes of the first model, and the number of weight parameters of the same first task node cannot be increased incrementally to update the first model, that is, the first model cannot be updated. At this time, the output information.

[0109] In this embodiment, when it is clear that the first model cannot be updated, information is output to improve the practicality of the model arrangement method, and it is indicated that the accuracy of the output result of the first model cannot meet the requirements and / or the first model is retrained and / or the second threshold is updated to ensure the calculation accuracy of the first model as much as possible.

[0110] In one embodiment, the model arrangement method further includes:

[0111] In the case where the accuracy of the output result of the first model is greater than or equal to the first threshold, determining a second task node and a first value of the second task node among the multiple task nodes of the first model, the second task node represents a task node that needs to copy a weight parameter, and the first value represents the number of copies of the weight parameter of the same second task node; the inputs of the same second task node are different;

[0112] Determine a second model based on the first model, the second task node, and the first value of the second task node;

[0113] Deploy the second model onto the storage and computing integrated chip.

[0114] Here, the accuracy of the output result of the first model is greater than or equal to the first threshold, which may be that the accuracy of the initial output result of the first model is greater than or equal to the first threshold, or that the accuracy of the output result of the updated first model is greater than or equal to the first threshold.

[0115] The second task node and the first value of the second task node are determined in the multiple task nodes of the first model. It should be understood that the first values ​​of the second task node and the second task node are determined as many as possible within the range allowed by the remaining storage and computing units of the storage and computing integrated chip. There can be multiple second task nodes, and the multiple second task nodes can be the same or different.

[0116] Based on the first model, the second task node and the first value of the second task node, the second model is determined by mapping the weight parameters of each task node to the storage and computing unit of the storage and computing integrated chip based on the second task node and the first value of the second task node to obtain the second model. It should be understood that the weight parameters copied by the first task node to the storage and computing unit of the storage and computing integrated chip can be changed, and the storage and computing unit of the storage and computing integrated chip corresponding to the weight parameters of each task node of the first model can also be changed.

[0117] The second model can be deployed on the storage-computing integrated chip by downloading the weight parameters of the second model to the storage-computing integrated chip. After the download is completed, it is determined whether the difference between the storage-computing unit data read on the storage-computing integrated chip and the data of the second model meets expectations. If it does not meet expectations, it is downloaded again until it meets expectations. It is determined whether the difference between the storage-computing unit data read on the storage-computing integrated chip and the data of the second model meets expectations. For example, if the difference between the storage-computing unit data read on the storage-computing integrated chip and the data of the second model is greater than the third threshold, it does not meet expectations; if the difference between the storage-computing unit data read on the storage-computing integrated chip and the data of the second model is less than or equal to the third threshold, it meets expectations.

[0118] In this embodiment, when the accuracy of the output result of the first model is greater than or equal to the first threshold, the second task node and the first value of the second task node are determined among the multiple task nodes of the first model. The input of the same second task node is different, which can shorten the processing time of the second task node. The second model determined based on the first model, the second task node and the first value of the second task node has a high degree of parallelism to shorten the calculation delay. The second model can improve the model calculation efficiency while ensuring a high calculation accuracy.

[0119] In one embodiment, after deploying the second model on the storage-computing integrated chip, the model orchestration method further includes:

[0120] When the accuracy of the output result of the second model deployed on the integrated storage and computing chip is less than a second threshold, the first threshold is updated and the first model is restored on the integrated storage and computing chip.

[0121] Here, the method for calculating the accuracy of the output results of the second model deployed on the integrated storage and computing chip is the same as the method for calculating the accuracy of the output results of the first model deployed on the integrated storage and computing chip.

[0122] The first threshold can be set according to actual needs, or can be determined based on the second threshold and the accuracy evaluation coefficient. Updating the first threshold can be to reduce the first threshold according to actual needs; or to multiply the first threshold by a third correction coefficient, which can be set according to actual needs; or to correct the accuracy evaluation coefficient and update the first threshold based on the corrected accuracy evaluation coefficient and the second threshold.

[0123] To restore the first model on the storage-computing integrated chip, all copied weight parameters of all second task nodes of the second model can be directly deleted on the storage-computing integrated chip; or the second model on the storage-computing integrated chip can be deleted and the first model can be redeployed on the storage-computing integrated chip.

[0124] In this embodiment, it is determined whether the accuracy of the output result of the second model deployed on the storage and computing integrated chip meets the requirements. If the requirements are not met, that is, the accuracy of the output result of the second model deployed on the storage and computing integrated chip is less than the second threshold, the first threshold is updated and the model is rearranged so that the final second model can ensure high calculation accuracy while ensuring high model calculation efficiency.

[0125] In one embodiment, the first threshold is determined based on the second threshold and the accuracy evaluation coefficient. In practical applications, the first threshold is the product of the second threshold and the accuracy evaluation coefficient. The updating of the first threshold includes:

[0126] The accuracy evaluation coefficient is corrected based on the second value to obtain a corrected accuracy evaluation coefficient; the second value is determined based on the second threshold and the accuracy of the output result of the second model deployed on the storage-computing integrated chip;

[0127] Based on the corrected accuracy evaluation coefficient and the second threshold, an updated first threshold is determined.

[0128] Here, the accuracy evaluation coefficient is corrected based on the second value to obtain the corrected accuracy evaluation coefficient. The product of the second value and the accuracy evaluation coefficient can be used as the corrected accuracy evaluation coefficient; or the product of the second value, the fourth correction coefficient and the accuracy evaluation coefficient can be used as the corrected accuracy evaluation coefficient. The fourth correction coefficient can be set according to actual needs. In practical applications, the product of the second value and the accuracy evaluation coefficient is used as the corrected accuracy evaluation coefficient.

[0129] The second value is determined based on the second threshold and the accuracy of the output result of the second model deployed on the storage-computing integrated chip. Specifically, the second threshold can be divided by the accuracy of the output result of the second model deployed on the storage-computing integrated chip to obtain the second value; or the ratio of the second threshold to the accuracy of the output result of the second model deployed on the storage-computing integrated chip is multiplied by the fifth correction coefficient to obtain the second value. The fifth correction coefficient can be set according to actual needs. In actual applications, the second threshold is divided by the accuracy of the output result of the second model deployed on the storage-computing integrated chip to obtain the second value.

[0130] Based on the corrected accuracy evaluation coefficient and the second threshold, the updated first threshold is determined, and the product of the corrected accuracy evaluation coefficient and the second threshold can be determined as the updated first threshold; or the product of the corrected accuracy evaluation coefficient, the sixth correction coefficient and the second threshold can be determined as the updated first threshold, and the sixth correction coefficient can be set according to actual needs. In practical applications, the product of the corrected accuracy evaluation coefficient and the second threshold is determined as the updated first threshold.

[0131] In this embodiment, the first threshold is determined based on the second threshold and the accuracy evaluation coefficient, and the method for updating the first threshold is clarified. The accuracy evaluation coefficient is corrected based on the accuracy of the output result of the second model deployed on the storage and computing integrated chip, so that the updated first threshold obtained based on the corrected accuracy evaluation coefficient is more reasonable, thereby helping the model arrangement to ensure that the final model can ensure both high calculation accuracy and high calculation efficiency.

[0132] In one embodiment, the model arrangement method further includes:

[0133] When the accuracy of the output result of the first model restored on the integrated storage and computing chip is less than the updated first threshold, the step of determining the first task node from the multiple task nodes of the first model is executed.

[0134] It should be understood that the situation where the accuracy of the output result of the first model restored on the storage and computing integrated chip is less than the updated first threshold can be regarded as the situation where the accuracy of the output result of the first model deployed on the storage and computing integrated chip is less than the first threshold, and the step of determining the first task node among the multiple task nodes of the first model is returned to continue execution, and the subsequent first thresholds are all the updated first thresholds.

[0135] In this embodiment, it is clear that the subsequent processing method when the accuracy of the output result of the first model restored on the storage and computing integrated chip is less than the updated first threshold can ensure that the calculation accuracy of the final first model is high.

[0136] In one embodiment, the model arrangement method further includes:

[0137] When the accuracy of the output result of the first model restored on the integrated computing and storage chip is greater than or equal to the updated first threshold, the step of determining the second task node and the first value of the second task node among the multiple task nodes of the first model is executed.

[0138] It should be understood that the situation where the accuracy of the output result of the first model restored on the storage and computing integrated chip is greater than or equal to the updated first threshold can be regarded as the situation where the accuracy of the output result of the first model is greater than or equal to the first threshold, and the step of returning to determine the second task node and determining the first value of the second task node among the multiple task nodes of the first model continues to be executed, and the subsequent first thresholds are all the updated first thresholds.

[0139] In this embodiment, the subsequent processing method is clearly defined when the accuracy of the output result of the first model restored on the storage and computing integrated chip is greater than or equal to the updated first threshold, which can ensure that the calculation accuracy and efficiency of the final second model are high.

[0140] The present application is described in further detail below in conjunction with application examples.

[0141] The overall flow chart of the model arrangement method of this application is as follows: Figure 8 shown. Figure 8 There are five stages shown in the figure, which are model preparation stage, model accuracy evaluation stage, model deployment stage, model accuracy testing stage and model operation stage. Figures 9 to 12 Shown separately Figure 8 The contents of the model preparation phase, model accuracy evaluation phase, model deployment phase, and model accuracy testing phase are described in detail below.

[0142] Phase 1: Model preparation phase.

[0143] like Fig. 9As shown, the model preparation phase includes:

[0144] Step 1.1: Train the model.

[0145] According to user needs and storage-computing integrated chip resources, the model is trained and adapted in the development environment to obtain the first model. For example, the storage and calculation of the storage-computing integrated chip usually only support integer data, and the weight parameters of the trained model are usually floating-point data, so the model parameters need to be quantized into integers.

[0146] Step 1.2: Test the model.

[0147] The first model is tested based on the test data set provided by the user to obtain the expected results of the first model and the benchmark input and benchmark output results of each task node of the first model. After obtaining the expected results of the first model and the benchmark input and benchmark output results of each task node of the first model, the second stage is executed.

[0148] The second stage: model accuracy evaluation stage.

[0149] like Fig.10 As shown in Figure 1, the model accuracy evaluation stage includes:

[0150] Step 2.1: Determine model pre-deployment.

[0151] Determine that the first model is deployed on the storage-computing integrated chip. Specifically, the first model is deployed on the storage-computing integrated chip in such a way that the weight parameters of the first model are mapped to the storage-computing unit of the storage-computing integrated chip, i.e., the chip array of the storage-computing integrated chip, based on the model structure of the first model and the current usage status of the storage-computing integrated chip, and the weight parameters of the first model are downloaded to the storage-computing integrated chip based on the mapping scheme. After the download is completed, it is determined whether the difference between the storage-computing unit data read on the storage-computing integrated chip and the data of the first model meets expectations. If it does not meet expectations, re-download until it meets expectations. Determine whether the difference between the storage-computing unit data read on the storage-computing integrated chip and the data of the first model meets expectations. For example, if the difference between the storage-computing unit data read on the storage-computing integrated chip and the data of the first model is greater than the fourth threshold, it does not meet expectations; if the difference between the storage-computing unit data read on the storage-computing integrated chip and the data of the first model is less than or equal to the fourth threshold, it meets expectations.

[0152] Step 2.2: Determine the output result of the first model deployed on the storage and computing integrated chip.

[0153] The first model deployed on the storage-computing integrated chip is tested based on the test data set to obtain the output result of the first model deployed on the storage-computing integrated chip.

[0154] Step 2.3: Determine whether the accuracy of the output result of the first model deployed on the storage-computing integrated chip meets the requirements. If the requirements are met, that is, the accuracy of the output result of the first model deployed on the storage-computing integrated chip is greater than or equal to the first threshold, then execute step 3.1; if the requirements are not met, that is, the accuracy of the output result of the first model deployed on the storage-computing integrated chip is less than the first threshold, then execute step 2.4. The first threshold is the product of the second threshold and the accuracy evaluation coefficient.

[0155] Step 2.4: Determine a third value of each task node of the first model.

[0156] Based on the benchmark input of each task node of the first model, the actual output result of each task node of the first model is obtained; the deviation between the actual output result of each task node of the first model and the corresponding benchmark output result is determined as the third value of the corresponding task node of the first model, and the third value can be normalized. It is worth noting that the actual output result of the same task node is the average of all actual output results of the task node.

[0157] Step 2.5: Determine the first task node, update the first model, and return to continue executing step 2.2. The first model at this time is the updated first model.

[0158] The first task node is determined from among the multiple task nodes of the first model according to the second set order; the second set order represents the order in which the eighth values ​​of each task node of the first model are sorted from large to small, the eighth value is obtained by dividing the third value by the fourth value, and the fourth value represents the number of storage and computing units corresponding to a weight parameter of the task node in the storage and computing integrated chip;

[0159] The number of weight parameters of the same first task node is increased incrementally to update the first model.

[0160] When the accuracy of the output result of the first model is less than the first threshold, and the number of storage and computing units corresponding to a weight parameter of each task node of the first model in the storage and computing chip is greater than the number of remaining storage and computing units in the storage and computing chip, output information; the information is used to indicate one or more of the following: the accuracy of the output result of the first model cannot meet the requirements, the first model is retrained, and the second threshold is updated.

[0161] The third stage: model deployment stage.

[0162] like Fig.11 As shown in the figure, the model deployment phase includes:

[0163] Step 3.1: Determine the final first model.

[0164] The accuracy of the final output result of the first model is greater than or equal to the first threshold.

[0165] Step 3.2: Determine the second model.

[0166] The model is arranged based on the final model structure of the first model and the chip array status of the storage-computing integrated chip to determine the second task node and the first value of the second task node; the second model is determined based on the first model, the second task node and the first value of the second task node.

[0167] Step 3.3: Determine that the second model is deployed on the storage and computing integrated chip.

[0168] The way to deploy the second model to the storage-computing integrated chip is to download the weight parameters of the second model to the storage-computing integrated chip. After the download is completed, it is determined whether the difference between the storage-computing unit data read on the storage-computing integrated chip and the data of the second model meets expectations. If it does not meet expectations, re-download until it meets expectations. It is determined whether the difference between the storage-computing unit data read on the storage-computing integrated chip and the data of the second model meets expectations. For example, if the difference between the storage-computing unit data read on the storage-computing integrated chip and the data of the second model is greater than the third threshold, it does not meet expectations; if the difference between the storage-computing unit data read on the storage-computing integrated chip and the data of the second model is less than or equal to the third threshold, it meets expectations. After determining that the second model is deployed on the storage-computing integrated chip, the fourth stage is executed.

[0169] The fourth stage: model accuracy testing stage.

[0170] like Fig.12 As shown in Figure 1, the model accuracy test phase includes:

[0171] Step 4.1: Get the output of the second model.

[0172] The second model deployed on the storage-computing integrated chip is tested based on the test data set to obtain the output result of the second model deployed on the storage-computing integrated chip.

[0173] Step 4.2: Determine whether the accuracy of the output result of the second model deployed on the storage and computing integrated chip meets the requirements. If it meets the requirements, that is, the accuracy of the output result of the second model deployed on the storage and computing integrated chip is greater than or equal to the second threshold, execute the steps of the fifth stage; if it does not meet the requirements, that is, the accuracy of the output result of the second model deployed on the storage and computing integrated chip is less than the second threshold, execute step 4.3.

[0174] Step 4.3: Adjust the accuracy evaluation coefficient and return to continue executing steps 2.1 to 2.5 of the second stage. The first threshold at this time is the updated first threshold.

[0175] The accuracy evaluation coefficient is corrected based on the second value to obtain a corrected accuracy evaluation coefficient; based on the corrected accuracy evaluation coefficient and the second threshold, an updated first threshold is determined; the second value is determined based on the second threshold and the accuracy of the output result of the second model deployed on the storage and computing integrated chip.

[0176] Phase 5: Model operation phase.

[0177] After the model is confirmed, it can enter the model operation phase. In the model operation phase, the model is run, and calculations are performed based on the input data to obtain the output results of the model.

[0178] The model arrangement method provided in the present application gives priority to using the redundancy brought by weight replication to suppress random errors when the accuracy of the output results of the model does not meet the requirements, that is, taking the average of all output results of the same first task node as the input of the next task node adjacent to the same first task node, and comprehensively considering the accuracy, i.e., the third value, and the space occupancy, i.e., the fourth value, when determining the first task node to improve the space utilization efficiency of the storage-computing integrated chip; comprehensively considering the needs of improving the parallelism and accuracy of calculations when determining the second model, and determining as many second task nodes and the first values ​​of the second task nodes as possible under the condition of meeting the chip array storage space limit of the storage-computing integrated chip, thereby ensuring the accuracy of the calculation results and making full use of the idle chip array space to improve parallelism and shorten the calculation delay; and also determining whether the accuracy of the output results of the second model deployed on the storage-computing integrated chip meets the requirements. If the accuracy of the output results of the second model deployed on the storage-computing integrated chip does not meet the requirements, adjusting the accuracy evaluation coefficient to enter the model accuracy evaluation stage again to ensure that the calculation accuracy of the model finally deployed meets the requirements.

[0179] In order to implement a model arrangement method provided in an embodiment of the present application, an embodiment of the present application also provides a model arrangement device, such as Fig.13 As shown, the device comprises:

[0180] A first determination module 1301 is used to determine a first task node among multiple task nodes of the first model when the accuracy of the output result of the first model deployed on the storage-computing integrated chip is less than a first threshold, wherein the first task node represents a task node for which weight parameters need to be copied; and the inputs of the same first task node are the same;

[0181] The first updating module 1302 is used to increase the number of weight parameters of the same first task node and update the first model.

[0182] In one embodiment, the device further comprises:

[0183] A second determination module is used to determine a second task node and a first value of the second task node among multiple task nodes of the first model when the accuracy of the output result of the first model is greater than or equal to the first threshold, the second task node represents a task node that needs to copy the weight parameter, and the first value represents the number of copies of the weight parameter of the same second task node; the input of the same second task node is different;

[0184] A third determination module, configured to determine a second model based on the first model, the second task node, and the first value of the second task node;

[0185] A deployment module is used to deploy the second model onto the storage and computing integrated chip.

[0186] In one embodiment, after deploying the second model on the storage-computing integrated chip, the device further includes:

[0187] The second update module is used to update the first threshold and restore the first model on the storage-computing integrated chip when the accuracy of the output result of the second model deployed on the storage-computing integrated chip is less than the second threshold.

[0188] In one embodiment, the first determination module 1301 is further used to execute the determination of the first task node among multiple task nodes of the first model when the accuracy of the output result of the first model restored on the storage and computing integrated chip is less than the updated first threshold.

[0189] In one embodiment, the second determination module is also used to execute the determination of the second task node and the first value of the second task node among multiple task nodes of the first model when the accuracy of the output result of the first model restored on the storage and computing integrated chip is greater than or equal to the updated first threshold.

[0190] In one embodiment, the first threshold is determined based on the second threshold and an accuracy evaluation coefficient; the second update module is specifically used to correct the accuracy evaluation coefficient based on the second value to obtain a corrected accuracy evaluation coefficient; the second value is determined based on the second threshold and the accuracy of the output result of the second model deployed on the storage and computing integrated chip; based on the corrected accuracy evaluation coefficient and the second threshold, the updated first threshold is determined.

[0191] In one embodiment, the first determining module 1301 is specifically configured to determine a first task node from among a plurality of task nodes of the first model based on a third value of each task node of the first model; or

[0192] Based on the third value and the fourth value of each task node of the first model, a first task node is determined from a plurality of task nodes of the first model; wherein,

[0193] The third numerical value represents the deviation between the actual output result of the task node of the first model and the corresponding benchmark output result, and the fourth numerical value represents the number of storage and computing units corresponding to a weight parameter of the task node in the storage and computing integrated chip.

[0194] In one embodiment, the first updating module 1302 is specifically used to copy the weight parameter of the incremented first task node to the idle storage and computing unit of the storage and computing integrated chip;

[0195] All output results of the same first task node are averaged and used as input of the next task node adjacent to the same first task node to update the first model.

[0196] In one embodiment, the first threshold is determined based on at least the second threshold; and the apparatus further comprises:

[0197] An output module, configured to output information when the accuracy of the output result of the first model is less than the first threshold and the number of storage and computing units corresponding to a weight parameter of each task node of the first model in the storage and computing integrated chip is greater than the number of remaining storage and computing units in the storage and computing integrated chip; wherein,

[0198] The information is used to indicate one or more of the following:

[0199] The accuracy of the output result of the first model cannot meet the requirements;

[0200] Retraining the first model;

[0201] The second threshold is updated.

[0202] In actual application, the first determination module 1301, the first update module 1302, the second determination module, the third determination module, the deployment module, the second update module and the output module can be implemented by a processor in the model arrangement device.

[0203] It should be noted that: the above embodiment provides a model arrangement device, and only uses the division of the above program modules as an example when performing model arrangement. In actual applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the device is divided into different program modules to complete all or part of the processing described above. In addition, the model arrangement device and the model arrangement method embodiment provided in the above embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0204] Based on the hardware implementation of the above program modules, and in order to implement a model arrangement method provided in an embodiment of the present application, an electronic device is also provided in an embodiment of the present application, such as Fig.14 As shown, the electronic device 1400 includes:

[0205] Communication interface 1401, capable of exchanging information with other network nodes;

[0206] The processor 1402 is connected to the communication interface 1401 to implement information exchange with other network nodes, and is used to execute the method provided by one or more technical solutions when running a computer program. The computer program is stored in the memory 1403.

[0207] Specifically, the processor 1402 is used to determine the first task node among multiple task nodes of the first model deployed on the storage and computing integrated chip when the accuracy of the output result of the first model deployed on the storage and computing integrated chip is less than the first threshold; increase the number of weight parameters of the same first task node and update the first model; the first task node represents the task node that needs to copy the weight parameters; the input of the same first task node is the same.

[0208] In one embodiment, the processor 1402 is further configured to determine, in a case where the accuracy of the output result of the first model is greater than or equal to the first threshold, a second task node and a first value of the second task node among the multiple task nodes of the first model, the second task node representing a task node that needs to copy a weight parameter, and the first value representing the number of copies of the weight parameter of the same second task node; the inputs of the same second task node are different;

[0209] Determine a second model based on the first model, the second task node, and the first value of the second task node;

[0210] Deploy the second model onto the storage and computing integrated chip.

[0211] In one embodiment, after the second model is deployed on the storage and computing integrated chip, the processor 1402 is also used to update the first threshold and restore the first model on the storage and computing integrated chip when the accuracy of the output result of the second model deployed on the storage and computing integrated chip is less than the second threshold.

[0212] In one embodiment, the processor 1402 is further used to execute the step of determining the first task node among multiple task nodes of the first model when the accuracy of the output result of the first model restored on the storage and computing integrated chip is less than the updated first threshold.

[0213] In one embodiment, the processor 1402 is also used to execute the process of determining a second task node and a first value of the second task node among multiple task nodes of the first model when the accuracy of the output result of the first model restored on the storage and computing integrated chip is greater than or equal to the updated first threshold.

[0214] In one embodiment, the first threshold is determined based on the second threshold and the accuracy evaluation coefficient; the processor 1402 is specifically configured to correct the accuracy evaluation coefficient based on the second value to obtain a corrected accuracy evaluation coefficient; the second value is determined based on the second threshold and the accuracy of the output result of the second model deployed on the storage-computing integrated chip;

[0215] Based on the corrected accuracy evaluation coefficient and the second threshold, an updated first threshold is determined.

[0216] In one embodiment, the processor 1402 is specifically configured to determine a first task node from among a plurality of task nodes of the first model based on a third value of each task node of the first model; or

[0217] Based on the third value and the fourth value of each task node of the first model, a first task node is determined from a plurality of task nodes of the first model; wherein,

[0218] The third numerical value represents the deviation between the actual output result of the task node of the first model and the corresponding benchmark output result, and the fourth numerical value represents the number of storage and computing units corresponding to a weight parameter of the task node in the storage and computing integrated chip.

[0219] In one embodiment, the processor 1402 is specifically configured to copy the weight parameter of the incremented first task node to an idle storage and computing unit of the storage and computing integrated chip;

[0220] All output results of the same first task node are averaged and used as input of the next task node adjacent to the same first task node to update the first model.

[0221] In one embodiment, the first threshold is determined based on at least the second threshold; the processor 1402 is further configured to output information when the accuracy of the output result of the first model is less than the first threshold and the number of storage and computing units corresponding to a weight parameter of each task node of the first model in the storage and computing integrated chip is greater than the number of remaining storage and computing units in the storage and computing integrated chip; wherein,

[0222] The information is used to indicate one or more of the following:

[0223] The accuracy of the output result of the first model cannot meet the requirements;

[0224] Retraining the first model;

[0225] The second threshold is updated.

[0226] It should be noted that the specific processing process of the processor 1402 can be understood by referring to the above method.

[0227] Of course, in actual application, the various components in the electronic device 1400 are coupled together through the bus system 1404. It can be understood that the bus system 1404 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 1404 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Fig.14 Various buses are labeled as bus system 1404.

[0228] The memory 1403 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device 1400. Examples of such data include: any computer program used to operate on the electronic device 1400.

[0229] The method disclosed in the above embodiment of the present application can be applied to the processor 1402, or implemented by the processor 1402. The processor 1402 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor 1402 or an instruction in the form of software. The above-mentioned processor 1402 may be a general-purpose processor, a digital signal processor (DSP, DigitalSignal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 1402 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor may be a microprocessor or any conventional processor, etc. In combination with the steps of the method disclosed in the embodiment of the present application, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in the memory 1403, and the processor 1402 reads the information in the memory 1403 and completes the steps of the above method in combination with its hardware.

[0230] In an exemplary embodiment, the electronic device 1400 may be implemented by one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to execute the aforementioned method.

[0231] It can be understood that the memory 1403 of the embodiment of the present application can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 1403 described in the embodiments of the present application is intended to include but is not limited to these and any other suitable types of memories.

[0232] In an exemplary embodiment, the embodiment of the present application further provides an electronic device, including a processor and a memory for storing a computer program that can be run on the processor, wherein the processor is used to execute the steps of any of the above methods when running the computer program.

[0233] The embodiment of the present application also provides a storage medium, namely a computer storage medium, specifically a computer-readable storage medium, for example, including a memory 1403 storing a computer program, and the computer program can be executed by a processor 1402 of an electronic device 1400 to complete the steps of the aforementioned method. The computer-readable storage medium can be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface storage, optical disk, or CD-ROM.

[0234] An embodiment of the present application further provides a computer program product, including a computer program, which implements the steps of any of the above methods when executed by a processor.

[0235] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. The term "and / or" herein is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "one or more" herein represents any combination of at least two of any one or more of a plurality of items. For example, including one or more of A, B, and C can represent including any one or at least two or more elements selected from the set consisting of A, B, and C.

[0236] In addition, the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0237] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application.

Claims

1. A model arrangement method, characterized in that: The method comprises: When the accuracy of the output result of the first model deployed on the storage-computing integrated chip is less than the first threshold, a first task node is determined among the multiple task nodes of the first model, and the first task node represents the task node for which the weight parameter needs to be copied; the input of the same first task node is the same; The number of weight parameters of the same first task node is increased incrementally to update the first model.

2. The method according to claim 1, characterized in that The method further comprises: In the case where the accuracy of the output result of the first model is greater than or equal to the first threshold, determining a second task node and a first value of the second task node among the multiple task nodes of the first model, the second task node represents a task node that needs to copy a weight parameter, and the first value represents the number of copies of the weight parameter of the same second task node; the inputs of the same second task node are different; Determine a second model based on the first model, the second task node, and the first value of the second task node; Deploy the second model onto the storage and computing integrated chip.

3. The method according to claim 2, characterized in that After deploying the second model on the storage-computing integrated chip, the method further includes: When the accuracy of the output result of the second model deployed on the integrated storage and computing chip is less than a second threshold, the first threshold is updated and the first model is restored on the integrated storage and computing chip.

4. The method according to claim 3, characterized in that: The method further comprises: When the accuracy of the output result of the first model restored on the integrated storage and computing chip is less than the updated first threshold, the step of determining the first task node from the multiple task nodes of the first model is executed.

5. The method according to claim 3, characterized in that: The method further comprises: When the accuracy of the output result of the first model restored on the integrated computing and storage chip is greater than or equal to the updated first threshold, the step of determining the second task node and the first value of the second task node among the multiple task nodes of the first model is executed.

6. The method according to claim 3, characterized in that The first threshold is determined based on the second threshold and an accuracy evaluation coefficient; and the updating of the first threshold includes: The accuracy evaluation coefficient is corrected based on the second value to obtain a corrected accuracy evaluation coefficient; the second value is determined based on the second threshold and the accuracy of the output result of the second model deployed on the storage-computing integrated chip; Based on the corrected accuracy evaluation coefficient and the second threshold, an updated first threshold is determined.

7. The method according to any one of claims 1 to 6, characterized in that: The step of determining a first task node from among a plurality of task nodes of the first model comprises: determining a first task node from among a plurality of task nodes of the first model based on a third value of each task node of the first model; or, Based on the third value and the fourth value of each task node of the first model, a first task node is determined from a plurality of task nodes of the first model; wherein, The third numerical value represents the deviation between the actual output result of the task node of the first model and the corresponding benchmark output result, and the fourth numerical value represents the number of storage and computing units corresponding to a weight parameter of the task node in the storage and computing integrated chip.

8. The method according to any one of claims 1 to 6, characterized in that: The updating of the first model comprises: Copying the incremented weight parameter of the first task node to the idle storage and computing unit of the storage and computing integrated chip; All output results of the same first task node are averaged and used as input of the next task node adjacent to the same first task node to update the first model.

9. The method according to any one of claims 1 to 6, characterized in that: The first threshold is determined based on at least the second threshold; the method further comprises: When the accuracy of the output result of the first model is less than the first threshold, and the number of storage and computing units corresponding to a weight parameter of each task node of the first model in the storage and computing integrated chip is greater than the number of remaining storage and computing units in the storage and computing integrated chip, output information; wherein, The information is used to indicate one or more of the following: The accuracy of the output result of the first model cannot meet the requirements; Retraining the first model; The second threshold is updated.

10. A model arrangement device, characterized in that: The device comprises: A first determination module is used to determine a first task node among multiple task nodes of the first model deployed on the storage-computing integrated chip when the accuracy of the output result of the first model deployed on the storage-computing integrated chip is less than a first threshold, wherein the first task node represents a task node for which weight parameters need to be copied; and the inputs of the same first task node are the same; The first updating module is used to increase the number of weight parameters of the same first task node and update the first model.

11. An electronic device, characterized in that: include: Processor and communication interface; wherein, The processor is used to determine a first task node among multiple task nodes of a first model deployed on a storage-computing integrated chip when the accuracy of an output result of the first model is less than a first threshold; to increase the number of copies of weight parameters of the same first task node and update the first model; the first task node represents a task node that needs to copy weight parameters; and the input of the same first task node is the same.

12. An electronic device, characterized in that: comprising a processor and a memory for storing a computer program capable of being executed on the processor, Wherein, when the processor is used to run the computer program, it executes the steps of the method described in any one of claims 1 to 9.

13. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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