Data processing method and device, electronic equipment and computer readable storage medium

Abstract

The invention provides a data processing method and device, electronic equipment and a computer readable storage medium, and the method comprises the steps: responding to a received first processing instruction, and determining that to-be-processed data of the first processing instruction is in a first storage region in a storage unit of a first processing core; when the first processing instruction is executed, the address range of the first storage area is adjusted according to change information of the to-be-processed data, and the change information is used for indicating the consumption progress or the generation progress of the to-be-processed data. According to the embodiment of the invention, the utilization rate of storage resources can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing method and device, an electronic device, and a computer-readable storage medium. Background Art

[0002] With the growing demand for artificial intelligence and big data processing, the improvement of computing power has become a key driving force for the development of current science and technology. Many-core systems are gradually becoming an important choice for the next generation of intelligent computing infrastructure due to their flexibility and scalability.

[0003] One of the major advantages of many-core systems is that they can fully utilize the pipeline process between cores on a chip. However, in the related art, the storage resources in the many-core system cannot be fully utilized in parallel pipelines. Summary of the invention

[0004] The present disclosure provides a data processing method and device based on a many-core system, a processing core, an electronic device, and a computer-readable storage medium.

[0005] In a first aspect, the present disclosure provides a data processing method, which is applied to a first processing core of a many-core system, wherein the first processing core is one of multiple processing cores of the many-core system, and the data processing method includes: in response to receiving a first processing instruction, determining a first storage area in a storage unit of the first processing core where data to be processed of the first processing instruction is located; during execution of the first processing instruction, adjusting an address range of the first storage area according to change information of the data to be processed, wherein the change information is used to indicate a reading progress or a writing progress of the data to be processed.

[0006] In a second aspect, the present disclosure provides a data processing method, which includes: determining an instruction sequence to be executed by a first processing core in a many-core system, the many-core system including multiple processing cores, and the first processing core being one of the multiple processing cores; determining address adjustment information of the first processing instruction based on change information of the data to be processed of the first processing instruction in the instruction sequence; wherein the address adjustment information is used to indicate an address adjustment method for a first storage area in a storage unit of the first processing core according to the change information during the execution of the first processing instruction, and the change information is used to indicate a reading progress or a writing progress of the data to be processed; determining a second processing instruction from the instruction sequence that matches the address adjustment information of the first processing instruction; and mapping the first processing instruction and the second processing instruction to the first processing core in sequence, so that the first processing core executes the first processing instruction and the second processing instruction in sequence.

[0007] In a third aspect, the present disclosure provides a data processing device, which is applied to a first processing core of a many-core system, where the first processing core is one of a plurality of processing cores of the many-core system, and the data processing device includes:

[0008] a determination module, configured to determine, in response to receiving a first processing instruction, a first storage area in a storage unit of the first processing core where the data to be processed of the first processing instruction is located;

[0009] The adjustment module is used to adjust the address range of the first storage area according to the change information of the data to be processed during the execution of the first processing instruction, and the change information is used to indicate the reading progress or writing progress of the data to be processed.

[0010] In a fourth aspect, the present disclosure provides an electronic device, comprising: multiple processing cores; and an on-chip network configured to exchange data between the multiple processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the above-mentioned data processing method.

[0011] In a fifth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above-mentioned data processing method when executed by a processor / processing core.

[0012] In the embodiment of the present disclosure, in response to receiving the first processing instruction, the first processing core determines the first storage area of ​​the storage unit of the first processing core where the data to be processed of the first processing instruction is located; then, during the execution of the first processing instruction, the address range of the first storage area is adjusted according to the change information of the data to be processed. In this way, by dynamically adjusting the address range of the first storage area according to the change information of the data to be processed, the address range of the first storage area can change with the consumption progress or generation progress of the data to be processed. Among them, as the data to be processed is consumed, the first processing core can release the storage resources in the storage unit in time, which is conducive to improving the utilization rate of storage resources; as the data to be processed is generated, the first processing core can increase storage resources as needed, reducing the time to reserve storage resources for the first processing instruction, thereby reducing the waste of storage resources and improving the utilization rate of storage resources.

[0013] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0015] Figure 1 A schematic diagram of the architecture of a many-core system provided in an embodiment of the present disclosure;

[0016] Figure 2 A schematic diagram of a BSP communication model provided in an embodiment of the present disclosure;

[0017] Figure 3 It is a schematic diagram of a computational communication pipeline;

[0018] Figure 4 A schematic diagram of storage resource allocation in related technologies;

[0019] Figure 5 A flowchart of a data processing method provided by an embodiment of the present disclosure;

[0020] Figure 6 A data consumption schematic diagram provided for an embodiment of the present disclosure;

[0021] Figure 7 A data generation schematic diagram provided for an embodiment of the present disclosure;

[0022] Figure 8 A schematic diagram of data consumption and generation provided in an embodiment of the present disclosure

[0023] Fig. 9 A data block arrangement method provided in an embodiment of the present disclosure;

[0024] Fig.10 A schematic diagram of splicing storage areas provided in an embodiment of the present disclosure;

[0025] Fig.11 A schematic diagram of defragmentation provided for an embodiment of the present disclosure;

[0026] Fig.12 A flowchart of a data processing method provided by an embodiment of the present disclosure;

[0027] Fig.13 A block diagram of a data processing device provided in an embodiment of the present disclosure;

[0028] Fig.14 A block diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0030] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0031] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "including" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0034] Figure 1 The schematic diagram of the architecture of a multi-core system provided by the embodiment of the present disclosure is as follows. Figure 1As shown, the many-core system may include multiple processing cores, and each processing core may include a processing unit, a storage unit, and a routing unit. Among them, the number of processing units can be multiple, and the processing unit can be used to process data. The storage unit can be used to store data, and the processing unit can read data from the storage unit or write data to the storage unit. The data stored in the storage unit can also be sent to other processing cores through the routing unit, and the storage unit can also store data received from other processing cores through the routing unit. For example, the storage unit can be a random access memory (Random Access Memory, RAM), etc., which is not limited to the embodiments of the present disclosure. The routing unit and the routing node constitute an on-chip network (or routing system). Data transmission between processing cores and data transmission between processing cores and external devices can be achieved through the on-chip network.

[0035] In a many-core system, different processing cores can execute different tasks at the same time. The Bulk Synchronous Parallel model (BSP) is a parallel computing model mainly used for parallel control and signal processing. This model divides the task into multiple independently executed stages and performs global synchronization at the end of each stage to ensure that all processing cores execute the same operation at the same time. This synchronization mechanism helps to simplify the programming model and improve the efficiency of parallel computing.

[0036] Figure 2 A schematic diagram of a BSP communication model provided by an embodiment of the present disclosure. Figure 2 As shown in the figure, in the BSP communication model, for any processing core, the processing core performs data processing after receiving the synchronization signal, performs data transmission after the data processing is completed, and waits for other processing cores after the data transmission is completed. It can be seen that the data processing and data transmission of the processing core are executed serially. For different processing cores, each processing core starts the data processing process at the same time after waiting for the synchronization signal.

[0037] In a many-core system, a processing core can send data processing results to other processing cores or external devices while processing data. Alternatively, a processing core can process the received data while receiving data sent by other processing cores or external devices. This method is called computational communication pipelining.

[0038] Figure 3 This is a schematic diagram of a computational communication pipeline. Figure 3As shown, the many-core system includes processing core 1 and processing core 2. After processing data, processing core 1 stores the data processing results in the output cache, and while processing the data, sends the data processing results stored in the output cache to processing core 2. It can be seen that the computational communication pipeline is implemented in processing core 1. Processing core 2 receives the data sent by processing core 2, and while storing the received data in the input cache, processes the data received in the input cache. It can be seen that the computational communication pipeline is also implemented in processing core 2. It can be understood that Figure 3 The output buffer shown is located in the storage unit of processing core 1, and the input buffer is located in the storage unit of processing core 2.

[0039] In summary, in a many-core system, for any processing core, the processing unit of the processing core can store data into the storage unit of the processor, and other processing cores or external devices can also store data into the storage unit of the processor; and, the processing unit of the processor can read data from the storage unit of the processor, and other processing cores or external devices can also read data from the storage unit of the processor.

[0040] In the related art, scalar data is allocated to the storage unit of each processing core in the many-core system in the form of a heap or stack, and tensor data is allocated to each processing core in the many-core system in the form of a data block. That is, in the related art, an address range is directly allocated in the storage unit of the processing core to store a data block. Within a certain period of time, all storage resources in the address range are exclusively occupied by the data block. This results in insufficient utilization of the storage resources of the storage unit.

[0041] Figure 4 FIG. 1 is a schematic diagram of the allocation of storage resources in the related art. Figure 4 As shown in FIG. 1 , data block 1, data block 2, and data block 3 are respectively allocated fixed address ranges in the storage unit. At the same time, the address ranges allocated to data block 1, data block 2, and data block 3 are exclusively occupied. The address ranges and times occupied by data block 1, data block 2, and data block 3 are Figure 4 It is represented as a rectangular area. Figure 4 It can be seen that the storage resources of the storage unit are not fully utilized.

[0042] According to the data processing method provided by the embodiment of the present disclosure, in response to receiving the first processing instruction, the first processing core determines the first storage area of ​​the data to be processed of the first processing instruction in the storage unit of the first processing core; then during the execution of the first processing instruction, the address range of the first storage area is adjusted according to the change information of the data to be processed. In this way, the address range of the first storage area is dynamically adjusted according to the change information of the data to be processed, so that the address range of the first storage area can change with the consumption progress or generation progress of the data to be processed. Among them, as the data to be processed is consumed, the first processing core can release the storage resources in the storage unit in time, which is conducive to improving the utilization rate of storage resources; as the data to be processed is generated, the first processing core can increase storage resources as needed, reducing the time to reserve storage resources for the first processing instruction, thereby reducing the waste of storage resources and improving the utilization rate of storage resources.

[0043] Furthermore, according to the data processing method provided by the embodiment of the present disclosure, by saving the storage resources of the first processing core, the first processing core is able to support more processing instructions executed simultaneously, which is beneficial to improving the efficiency of the many-core system.

[0044] The data processing method according to the embodiment of the present disclosure may be applied to the first processing core of a many-core system. The many-core system may include multiple processing cores, and the first processing core may be one of the multiple processing cores of the many-core system. For example, the first processing core may be Figure 1 For example, the many-core system may be a many-core chip or board, or any electronic device including a many-core chip or board.

[0045] Figure 5 A flowchart of a data processing method provided by an embodiment of the present disclosure. Figure 1 , the method comprising:

[0046] In step S11 , in response to receiving a first processing instruction, a first storage area in a storage unit of the first processing core where the to-be-processed data of the first processing instruction is located is determined.

[0047] The first processing instruction may represent a processing instruction executed by the first processing core. The first processing instruction may be used to execute any one of an image processing task, a language processing task, a text processing task, and a video processing task. In the embodiment of the present disclosure, the first processing instruction is not limited.

[0048] The first storage area may represent a storage area in a storage unit of the first processing core. The first storage area may be represented by an address range in a storage unit of the first processing core. Storage resources in the first storage area are allocated to the first processing core for use. The first processing instruction may consume data stored in the first storage area, or may generate data and store the generated data in the first storage area. The data to be processed of the first processing instruction may represent data consumed or generated by the first processing instruction.

[0049] After receiving the first processing instruction, the first processing core determines the storage area of ​​the data to be processed of the first processing instruction in the storage unit of the first processing core, that is, the first storage area, in response to the first processing instruction. In one example, the first processing core determines an address range in the storage unit of the first processing core as the first storage area in response to the first processing instruction, and stores the data to be processed of the first processing instruction in the first storage area before being consumed or stores the data to be processed of the first processing instruction in the first storage area after being generated.

[0050] It should be noted that the first processing core may receive multiple first processing instructions at the same time, and these processing instructions may all be used to read data or all be used to write data, or some may be used to consume data and the other part may be used to generate data, which is not limited in this embodiment of the present disclosure.

[0051] In step S12, during the execution of the first processing instruction, the address range of the first storage area is adjusted according to the change information of the data to be processed.

[0052] During the execution of the first processing instruction, the first processing core may adjust the address range of the first storage area according to the change information of the data to be processed, wherein the change information may be used to indicate the consumption progress or generation progress of the data to be processed.

[0053] Since the data to be processed has been read out from the first storage area after being consumed, the first storage area does not need to continue storing the data to be processed. Therefore, the first processing core can adjust the address range of the first storage area according to the consumption progress of the data to be processed to release the storage resources in the storage unit of the first processing core for use by other processing instructions of the first processing core, thereby reducing the waste of storage resources and improving the utilization rate of storage resources.

[0054] Since the data to be processed cannot be written into the first storage area before it is generated, the first storage area does not need to store the data to be processed. Therefore, the first processing core can adjust the address range of the first storage area according to the generation progress of the data to be processed, so that the storage unit of the first processing core can increase storage resources for the first processing instruction as needed, reduce the time to reserve storage resources for the first processing instruction, thereby reducing the waste of storage resources and improving the utilization rate of storage resources.

[0055] According to the data processing method provided by the embodiment of the present disclosure, in response to receiving the first processing instruction, the first processing core determines the first storage area of ​​the data to be processed of the first processing instruction in the storage unit of the first processing core; then during the execution of the first processing instruction, the address range of the first storage area is adjusted according to the change information of the data to be processed. In this way, the address range of the first storage area is dynamically adjusted according to the change information of the data to be processed, so that the address range of the first storage area can change with the consumption progress or generation progress of the data to be processed. Among them, as the data to be processed is consumed, the first processing core can release the storage resources in the storage unit in time, which is conducive to improving the utilization rate of storage resources; as the data to be processed is generated, the first processing core can increase storage resources as needed, reducing the time to reserve storage resources for the first processing instruction, thereby reducing the waste of storage resources and improving the utilization rate of storage resources.

[0056] In some embodiments, the first storage area in step S12 includes a first start address and a first end address.

[0057] Among them, the first starting address may represent the starting address of the first storage area, and the first ending address may represent the ending address of the first storage area. The first storage area includes storage resources starting from the first starting address to the first ending address in the storage unit of the first processing core. The address of the first storage area is a linear address, and its address value is continuous. Therefore, the first starting address and the first ending address can be used to indicate the position of the first storage area in the storage unit of the first processing core. In an example, the first starting address and the first ending address can be address offsets in the storage unit of the first processing core.

[0058] In some possible implementations, the data to be processed in step S11 may include first data to be consumed.

[0059] The first data may represent data to be consumed by the first processing instruction. That is, the first data will be consumed in the process of the first processing core executing the first processing instruction. It is understandable that before the first data is consumed, the first data is stored in the storage unit of the first processing core; and after the first data is consumed, the first data no longer needs to occupy the storage resources in the storage unit of the first processing core.

[0060] For example, the way in which the first processing core consumes the first data may include: the first processing core locally processes the first data, for example, the processing unit of the first processing core reads and processes the first data; and / or, the first processing core sends the first data to the outside, for example, the first processing core sends the first data to other processing cores through a routing unit.

[0061] In some possible implementations, the change information in step S12 may include a data processing speed, where the data processing speed is used to characterize the amount of data read and processed from the first storage area by the first processing instruction in a unit time.

[0062] The first processing core may read data from the first storage area and process the read data. Therefore, the first data may be data read and processed by the first processing core from the first storage area. The change information of the first data may be the data processing speed of the first data, that is, the amount of first data read and processed from the first storage area by the first processing instruction within a unit time. The unit time may be set as required, such as 10 seconds, 1 minute, or half an hour, etc., which is not limited in the embodiments of the present disclosure.

[0063] Accordingly, adjusting the address range of the first storage area according to the change information of the data to be processed in step S12 may include step S121 and step S122:

[0064] In step S121, when the first processing instruction starts processing the first data from the first starting address, the address value of the first starting address is adjusted according to the data processing speed of the first data so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

[0065] In step S122, when the first processing instruction starts to process the first data from the first end address, the address value of the first end address is adjusted according to the data processing speed of the first data so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

[0066] The first processing instruction may start processing the first data from the first starting address, or may start processing the first data from the first ending address. In the process of starting processing the first data from the first starting address or the first ending address, the first processing instruction may adjust the address value of the first starting address or the first ending address according to the data processing speed of the first data to reduce the gap between the first starting address and the first ending address, thereby reducing the storage resources occupied by the first storage area in the storage unit of the first processing core, so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

[0067] Figure 6 A data consumption diagram provided by an embodiment of the present disclosure. Figure 6 As shown, the first processing instruction may instruct a processing unit of a first processing core to read and process first data from a storage unit.

[0068] Reference Figure 6 , when the first processing instruction starts to process the first data from the first starting address, as time t increases, the first starting address s(t) increases, and the first ending address e(t) remains unchanged. In this way, as the first processing instruction processes the first data, the gap between the first starting address s(t) and the first ending address e(t) decreases, that is, the address range of the first storage area is reduced, and the storage resources occupied by the first storage area in the storage unit of the first processing core are reduced. It can be understood that as the first processing instruction processes the first data, the real-time data volume of the first processing instruction is also reduced. Therefore, by adjusting the address value of the first starting address in step S121, the address range of the first storage area can match the real-time data volume of the first processing instruction.

[0069] Reference Figure 6 , when the first processing instruction starts to process the first data from the first end address, as time t increases, the first start address s(t) remains unchanged, and the first end address e(t) decreases. In this way, as the first processing instruction processes the first data, the gap between the first start address s(t) and the first end address e(t) decreases, that is, the address range of the first storage area is reduced, and the storage resources occupied by the first storage area in the storage unit of the first processing core are reduced. It can be understood that as the first processing instruction processes the first data, the real-time data volume of the first processing instruction is also reduced. Therefore, by adjusting the address value of the first end address in step S122, the address range of the first storage area can match the real-time data volume of the first processing instruction.

[0070] Reference Figure 6 , when the data processing speed of the first data is faster: when the first processing instruction starts to process the first data from the first starting address, the greater the change slope of the first starting address s(t), the more the first starting address s(t) increases within the same time length; when the first processing instruction starts to process the first data from the first ending address, the greater the change slope of the first ending address e(t), the more the first ending address e(t) decreases within the same time length.

[0071] In some possible implementations, the change information in step S12 may include a data transmission speed, where the data transmission speed is used to represent the amount of data sent from the first storage area to the outside by the first processing instruction in a unit time.

[0072] The first processing core may send data from the first storage area to the outside (including other processing cores and external devices). Therefore, the first data may be data sent from the first storage area to the outside. The change information of the first data may be the data sending speed of the first data, that is, the data volume of the first data sent from the first storage area to the outside by the first processing instruction in a unit time.

[0073] Accordingly, adjusting the address range of the first storage area according to the change information of the data to be processed in step S12 may include steps S123 and S124:

[0074] In step S123, when the first processing instruction sends the first data starting from the first starting address, the address value of the first starting address is adjusted according to the data sending speed of the first data so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

[0075] In step S124, when the first processing instruction sends the first data starting from the first end address, the address value of the first end address is adjusted according to the data sending speed of the first data so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

[0076] The first processing instruction may send the first data to the outside starting from the first starting address, or may send the first data to the outside starting from the first ending address. In the process of sending the first data from the first starting address or the first ending address, the first processing instruction may adjust the address value of the first starting address or the first ending address according to the sending speed of the first data to reduce the gap between the first starting address and the first ending address, thereby reducing the storage resources occupied by the first storage area in the storage unit of the first processing core, so that the address range of the first area matches the real-time data volume of the first processing instruction.

[0077] like Figure 6 As shown, the first processing instruction may also instruct the storage unit of the first processing core to send the first data to the outside. The case where the first processing instruction sends the first data to the outside is similar to the case where the first processing instruction processes the first data. Therefore, step S123 may refer to step S121, and step S124 may refer to step S122, which will not be repeated here.

[0078] In one example, assume that at time t, the first start address is s(t) and the first end address is e(t). If t0 represents the initial time of the first processing instruction, then s(t0) represents the initial address value of the first start address, and e(t0) represents the initial address value of the first end address. The data processing speed of the first number and the data transmission speed of the first data are denoted as p. Wherein, p is a positive number.

[0079] If the first data is consumed from the start address of the first storage area, that is, from a small address value, then s(t) = s(t0) + p*t, e(t) = e(t0). If the first data is consumed from the end address of the first storage area, that is, from a large address value, then s(t) = s(t0), e(t) = e(t0) - p*t.

[0080] It should be noted that when the first processing core reads and processes the first data from the first storage area and sends data from the first storage area to the outside at the same time, the change information of the first data includes the data processing speed and the data sending speed. In an example, the change information of the first data can be the sum of the data processing speed and the data sending speed.

[0081] In an embodiment of the present disclosure, the first starting address or the first ending address is adjusted according to the data processing speed and / or data sending speed of the first data, and the storage resources of the first storage area are reduced so that the address range of the first storage area matches the real-time data volume of the first processing instruction, thereby effectively improving the utilization rate of the storage resources.

[0082] In some possible implementations, the data to be processed in step S11 may include second data to be generated.

[0083] The second data may represent data to be generated by the first processing instruction. That is, the second data will be generated during the process of the first processing core executing the first processing instruction. It is understandable that before the second data is generated, the second data does not need to occupy the storage resources in the storage unit of the first processing core; and after the second data is generated, the second data is stored in the storage unit of the first processing core.

[0084] For example, the manner in which the first processing core generates the second data may include: the first processing core locally generates the second data, for example, the processing unit of the first processing core generates the second data; and / or the first processing core receives the second data from the outside, for example, the first processing core receives the second data sent by other processing cores through a routing unit.

[0085] In some possible implementations, the change information in S12 may include a data generation speed, where the data generation speed is used to represent the amount of data generated by the first processing instruction and stored in the first storage area within a unit time.

[0086] The first processing core may store the generated data in the first storage area. Therefore, the second data may be data generated by the first processing core and stored in the first storage area. The change information of the second data may be a data generation speed of the second data, that is, the amount of the second data generated by the first processing instruction and stored in the first storage area per unit time.

[0087] Accordingly, adjusting the address range of the first storage area according to the change information of the data to be processed in step S12 may include steps S125 and S126:

[0088] In step S125, when the first processing instruction starts to store the second data from the first starting address, the address value of the first starting address is adjusted according to the data generation speed of the second data so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

[0089] In step S126, when the first processing instruction starts to store the second data from the first end address, the address value of the first end address is adjusted according to the data generation speed of the second data so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

[0090] The first processing instruction may store the second data from the first starting address or the first ending address. In the process of storing the second data from the first starting address or the first ending address, the first processing instruction may adjust the address value of the first starting address or the first ending address according to the data generation speed of the second data to expand the gap between the first starting address and the first ending address, thereby increasing the storage resources occupied by the first storage area in the storage unit of the first processing core, so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

[0091] Figure 7 A data generation schematic diagram provided by an embodiment of the present disclosure. Figure 7 As shown, the first storage instruction may instruct the processing unit of the first processing core to store the generated second data into the storage unit.

[0092] Reference Figure 7, when the first processing instruction starts to store the second data from the first starting address, as time t increases, the first starting address s(t) decreases, and the first ending address e(t) remains unchanged. In this way, as the first processing instruction stores the second data, the gap between the first starting address s(t) and the first ending address e(t) increases, that is, the address range of the first storage area is expanded, and the storage resources occupied by the first storage area in the storage unit of the first processing core increase. It can be understood that as the first processing instruction stores the second data, the real-time data volume of the first processing instruction is also increasing. Therefore, by adjusting the address value of the first starting address in step S125, the address range of the first storage area can match the real-time data volume of the first processing instruction.

[0093] Reference Figure 7 , in the case where the first processing instruction starts to store the second data from the first end address, as time t increases, the first start address s(t) remains unchanged, and the first end address e(t) keeps increasing. In this way, as the first processing instruction stores the second data, the gap between the first start address s(t) and the first end address e(t) increases, that is, the address range of the first storage area is expanded, and the storage resources occupied by the first storage area in the storage unit of the first processing core increase. It can be understood that as the first processing instruction stores the second data, the real-time data volume of the first processing instruction is also increasing. Therefore, by adjusting the address value of the first end address in step S126, the address range of the first storage area can be matched with the real-time data volume of the first processing instruction.

[0094] In some possible implementations, the change information in step S12 may include a data receiving speed, where the data receiving speed is used to represent the amount of data received from the outside to the first storage area by the first processing instruction in a unit time.

[0095] The first processing core may receive data from the outside (including other processing cores and external devices). Therefore, the second data may be data received from the outside to the first storage area. The change information of the second data may be the data receiving speed of the second data, that is, the amount of second data received from the outside to the first storage area by the first processing instruction in a unit time.

[0096] Correspondingly, adjusting the address range of the first storage area according to the change information of the data to be processed in step S12 may include steps S127 and S128:

[0097] In step S127, when the first processing instruction starts to store the second data from the first starting address, the address value of the first starting address is adjusted according to the data receiving speed of the second data so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

[0098] In step S128, when the first processing instruction stores the second data starting from the first end address, the address value of the first end address is adjusted according to the data receiving speed of the second data so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

[0099] like Figure 7 As shown, the first processing instruction can also receive the second data from the outside and store it in the storage unit of the first processing core. The case where the first processing instruction receives the second data from the outside and stores it in the storage unit of the first processing core is similar to the case where the first processing instruction generates the second data and writes it into the storage unit of the first processing core. Therefore, step S127 can refer to step S125, and step S128 can refer to step S126, which will not be repeated here.

[0100] In one example, it is assumed that at time t, the first start address is s(t) and the first end address is e(t). If t0 represents the initial time of the first processing instruction, then s(t0) represents the initial address value of the first start address, and e(t0) represents the initial address value of the first end address. The data generation speed of the second data and the data receiving speed of the second data are both denoted as c. Wherein, c is a positive number.

[0101] If the second data is stored from the start address of the first storage area, that is, the newly added data is stored at a small address value, then s(t) = s(t0) - c*t, e(t) = e(t0). If the second data is stored from the end address of the first storage area, that is, the newly added data is stored at a large address value, then s(t) = s(t0), e(t) = e(t0) + c*t.

[0102] It should be noted that when the first processing core generates and stores the second data in the first storage area and the first processing core receives the second data from the outside and stores it in the first storage area simultaneously, the change information of the second data includes the data generation speed and the data reception speed. In an example, the change information of the second data can be the sum of the data generation speed and the data reception speed.

[0103] In an embodiment of the present disclosure, the first starting address or the first ending address is adjusted according to the data generation speed and / or data receiving speed of the second data, and the storage resources of the first storage area are increased so that the address range of the first storage area matches the real-time data volume of the first processing instruction, thereby effectively improving the utilization rate of the storage resources.

[0104] Furthermore, in some embodiments, the first processing core can process multiple first processing instructions at the same time, and the storage area of ​​these first processing instructions is the same storage area in the storage unit of the first processing core, that is, they are all first storage areas. Take two first processing instructions as an example. The data to be processed of one of the first processing instructions is the first data, and the data to be processed of the other first processing instruction is the second data. In other words, the first processing core can consume the first data and generate the second data at the same time, and during the execution of the two first processing instructions, the address range of the first storage area is adjusted according to the change information of the first data and the change information of the second data.

[0105] Figure 8 A schematic diagram of data consumption and generation provided by an embodiment of the present disclosure. Figure 8 As shown, the first processing core can write the second data received from the outside into the storage unit, and at the same time send the first data stored in the storage unit to the outside; the first processing core can write the second data received from the outside into the storage unit, and at the same time the processing unit can read the first data from the storage unit and process it; the first processing core can write the second data obtained by the processing unit into the storage unit, and at the same time send the first data stored in the storage unit to the outside. In the above process, the adjustment method of s(t) and e(t) can be referred to Figure 8 .

[0106] Considering that the first processing core can execute multiple processing instructions in parallel, in order to further improve the utilization rate of storage resources, the method provided in the embodiment of the present disclosure can also coordinately adjust the address ranges of the storage areas of different processing instructions when the first processing core executes multiple processing instructions at the same time, so that the storage areas of different processing instructions are closely arranged, so that more data blocks can be formed on the first processing core, thereby being able to run more processing instructions. This is conducive to improving the efficiency of the multi-core chip.

[0107] Fig. 9 A data block arrangement method provided by the embodiment of the present disclosure. Fig. 9As shown, the first processing core allocates storage areas for processing instruction 1, processing instruction 2 and processing instruction 3 in its storage unit, and the three storage areas are closely arranged. Among them, the change slope of the end address corresponding to processing instruction 1 is close to the change slope of the start address corresponding to processing instruction 3; the change slope of the end address corresponding to processing instruction 2 is close to the change slope of the start address corresponding to processing instruction 1 in a period of time, and is close to the change slope of the start address corresponding to processing instruction 3 in another period of time.

[0108] The data processing process of the multi-processing instruction is described in detail below.

[0109] In some embodiments, the method provided by the embodiments of the present disclosure may further include step S13 and step S14:

[0110] In step S13, when a second processing instruction is received during the execution of the first processing instruction, it is determined whether the address adjustment information of the first storage area matches the address adjustment information of the second storage area in the storage unit, the second storage area being used to store the data to be processed of the second processing instruction, and the address adjustment information is determined based on the change information of the data to be processed of the second processing instruction.

[0111] In step S14, when the address adjustment information of the first storage area matches the address adjustment information of the second storage area, the first storage area is concatenated with the second storage area.

[0112] The second processing instruction may represent a processing instruction executed by the first processing core. The second processing instruction corresponds to a different storage area than the first processing instruction. The storage area corresponding to the former is called the first storage area, and the storage area corresponding to the latter is called the second storage area. The first processing core may execute the first processing instruction and the second processing instruction simultaneously.

[0113] The second processing instruction may refer to the first processing instruction, and the data to be processed of the second processing instruction may refer to the data to be processed of the first processing instruction, which will not be described in detail in the embodiment of the present disclosure.

[0114] The second storage area may represent a storage area in the storage unit of the first processing core. At the same time, the intersection of the address range of the second storage area and the address range of the first storage area is an empty set. The second storage area may refer to the first storage area, which will not be described in detail here.

[0115] After receiving the second processing instruction, the first processing core determines the storage area of ​​the data to be processed of the second processing instruction in the storage unit of the first processing core, that is, the second storage area, in response to the second processing instruction. In one example, the first processing core determines an address range in the storage unit of the first processing core as the second storage area in response to the second processing instruction, and stores the data to be processed of the second processing instruction in the second storage area before being consumed or stores the data to be processed of the second processing instruction in the second storage area after being generated.

[0116] During the execution of the second processing instruction, the first processing core may adjust the address range of the second storage area according to the change information of the data to be processed of the second processing instruction. This process may refer to the process of adjusting the address range of the first storage area according to the change information of the data to be processed of the first processing instruction (see step S12), which will not be described in detail here.

[0117] When the second processing instruction is received during the execution of the first processing instruction, it means that the first processing core needs to execute the first processing instruction and the second processing instruction in parallel, and the first processing core can determine whether the address adjustment information of the first storage area matches the address adjustment information of the second storage area, and then perform subsequent processing based on the matching result.

[0118] The address adjustment information is determined according to the change information. The address adjustment information of the first storage area is determined according to the change information of the data to be processed of the first processing instruction. The address adjustment information of the second storage area is determined according to the change information of the data to be processed of the second processing instruction.

[0119] In some possible implementations, the first storage area includes a first start address and a first end address, the second storage area includes a second start address and a second end address, and the address adjustment information includes a change slope of the address value. The address adjustment information of the first storage area matches the address adjustment information of the second storage area in step S13, including: the difference between the change slope of the address value of the first start address and the change slope of the address value of the second end address is less than a first threshold; or the difference between the change slope of the address value of the first end address and the change slope of the address value of the second start address is less than the first threshold.

[0120] When the difference between the change slope of the address value of the first start address and the change slope of the address value of the second end address is less than the first threshold, it indicates that the address value of the first start address decreases at a speed similar to that of the second end address, or the address value of the first start address increases at a speed similar to that of the second end address, and as time goes by, at the same time, the intersection of the address ranges of the first storage area and the second storage area is always an empty set. It should be noted that in this case, at the same time, the address value of the first start address is greater than the address value of the second end address.

[0121] When the difference between the change slope of the address value of the first end address and the change slope of the address value of the second start address is less than the first threshold, it indicates that the address value of the first end address decreases at a speed similar to that of the second start address, or the address value of the first end address increases at a speed similar to that of the second start address, and as time goes by, at the same time, the intersection of the address ranges of the first storage area and the second storage area is always an empty set. It should be noted that in this case, at the same time, the address value of the first end address is less than the address value of the second start address.

[0122] The first threshold can be used to compare the change slope of the address value. The first threshold can be set as needed, and the first threshold can make the intersection of the address range of the first storage area and the second storage area always be an empty set during the parallel execution of the first processing instruction and the second processing instruction.

[0123] In the disclosed embodiment, by dynamically splicing and adjusting the storage areas of different processing instructions according to the storage requirements of different processing instructions, more processing instructions can be run simultaneously on the many-core system, thereby improving the operating efficiency.

[0124] Fig.10 FIG. 1 is a schematic diagram of splicing storage areas provided in an embodiment of the present disclosure. Fig.10 As shown, the multi-core system includes multiple data transmission paths. For the processing core in the second row and third column, the data generated by the processing unit thereon can be stored in the storage unit, and the storage unit thereon can also receive data from the outside and send data to the outside. For the processing core in the third row and third column, the storage unit thereon can receive data from the outside and send data to the outside, and the processing unit thereon can read data from the storage unit and process it.

[0125] See also Fig.10, for the processing core at row 3 and column 3, processing instruction 1 and processing instruction 2 are executed thereon. Processing instruction 1 is used to instruct the storage unit of the processing core to receive data from the outside, and the processing unit to read and process data from the storage unit. Processing instruction 2 is used to instruct the storage unit of the processing core to receive data from the outside and send data to the outside. It can be seen that both processing instruction 1 and processing instruction 2 indicate data consumption and data generation. Therefore, the starting address and the ending address of processing instruction 1 and processing instruction 2 are adjusted over time.

[0126] like Fig.10 As shown, since the change slope of the address value of the end address corresponding to processing instruction 1 is the same as the change slope of the address value of the start address corresponding to processing instruction 2, the storage area corresponding to processing instruction 1 and the storage area corresponding to processing instruction 2 can be spliced ​​together.

[0127] In some possible implementations, when the first storage area is spliced ​​with the second storage area, at the same moment, the address value of the first starting address is greater than the address value of the second ending address and the difference between the address value of the first starting address and the address value of the second ending address is less than a second threshold; or, at the same moment, the address value of the first ending address is less than the address value of the second starting address and the difference between the address value of the first ending address and the address value of the second starting address is less than the second threshold.

[0128] The second threshold value can be set as needed, and the embodiment of the present disclosure does not set a value for the second threshold value. In the embodiment of the present disclosure, setting the second threshold value can improve the fault tolerance rate.

[0129] In some embodiments, the first processing core includes a processing unit, a storage unit and a routing unit; the data to be processed includes one or more of the following: data processed by the processing unit (corresponding to the first data); data sent to the outside by the routing unit (corresponding to the first data); data generated by the processing unit (corresponding to the second data); data received from the outside by the routing unit (corresponding to the second data).

[0130] In some embodiments, the method provided by the embodiments of the present disclosure may further include step S15:

[0131] In step S15, when there is a free storage area between the first storage area and the third storage area, the storage position of the third data is adjusted until the first storage area is adjacent to the third storage area by simultaneous reading and writing or self-transmission and self-reception.

[0132] The third storage area represents an occupied storage area in the storage unit of the first processing core except the first storage area, and the third data represents data stored in the first storage area.

[0133] Fig.11 A schematic diagram of defragmentation provided by an embodiment of the present disclosure. Fig.11 As shown in Figure 1, before time t1, three areas in the first processing core are occupied. Fig.11 In the order from left to right, the third block area is the first storage area, the first block area and the second block area can be called the third storage area. The data stored in the third block area can be called the third data.

[0134] like Fig.11 As shown, starting from time t1, the first processing core adjusts the storage location of the third data by reading and writing at the same time or sending and receiving data by itself, so that the third block area is adjacent to the second block area, thereby solving the storage fragmentation of the storage unit of the first processing core, so that the storage unit of the first processing core has more continuous large storage areas. This is conducive to the first processing core to process more processing instructions in parallel, thereby improving the execution efficiency of the multi-core system.

[0135] like Fig.11 As shown on the left, starting from time t1, the first processing core can adjust the storage location of the third data based on the start address and end address of the first storage area at time t1. Fig.11 As shown on the right, starting from time t1, the first processing core can adjust the storage location of the third data based on the end address of the second block area. It should be noted that in the embodiment of the present disclosure, there is no restriction on the data transfer order of the third data, and it is sufficient to eventually make the first storage area adjacent to the third storage area.

[0136] In some embodiments, the first processing instruction is used to train a neural network, and multiple network layers of the neural network are distributed and deployed to multiple processing cores of the many-core system, and each processing core is deployed with at least one network layer of the neural network, wherein a training batch of the neural network training includes multiple sub-batches, and the first processing core interleaves forward propagation processes and back-propagation processes of different sub-batches in the training batch, and for any sub-batch of the training batch, the method further includes:

[0137] In the forward propagation process, the to-be-processed data generated by the current sub-batch is stored in the first storage area or in a fourth storage area, where the fourth storage area represents a storage area in a storage unit of a second processing core, the second processing core is one of the plurality of processing cores other than the first processing core, and the second processing core is communicatively connected to the first processing core;

[0138] During the back propagation process, the to-be-processed data consumed by the current sub-batch is read from the first storage area or the fourth storage area.

[0139] 1F1B pipeline parallelism refers to the pipeline parallelism in which the forward calculation process and the backward calculation process are executed alternately. In 1F1B pipeline parallelism, a training batch of a neural network is first split into multiple micro-batches, and then the forward calculation process and the backward calculation process of different micro-batches are executed alternately. Pipeline parallelism can improve efficiency, but it will produce many bubbles, that is, the processing cores in the multi-core system are idle for a long time.

[0140] For any sub-batch of a training batch, during the forward propagation process, the to-be-processed data generated by the current sub-batch can be stored in the first storage area or the fourth storage area; during the backward propagation process, the to-be-processed data consumed by the current sub-batch can be read from the first storage area or the fourth storage area, thereby realizing the storage sharing of the first processing core by the second processing core, thereby achieving storage balance between the first processing core and the second processing core, which is beneficial to improving training efficiency.

[0141] In some embodiments, the number of the multiple processing cores is N, and the multiple network layers of the neural network are deployed in sequence, the first processing core is the nth processing core among the N processing cores, the second processing core is the N-n+1th processing core, n and N are positive integers, 1≤n≤N, and the storing of the to-be-processed data generated by the current sub-batch in the first storage area or the fourth storage area includes:

[0142] When n≤N / 2, storing the to-be-processed data generated by the current sub-batch in the first storage area or the fourth storage area;

[0143] When n>N / 2, the to-be-processed data generated by the current sub-batch is stored in the first storage area.

[0144] In the case of n≤N / 2, it indicates that the first processing core is deployed at a relatively front network layer in the neural network, the first processing core requires a large amount of data storage, and the storage resources of the first processing core are relatively tight. Correspondingly, the second processing core is deployed at a relatively back network layer in the neural network, the second processing core requires a small amount of data storage, and the storage resources of the second processing core are relatively sufficient. Therefore, the first processing core can store the data to be processed (corresponding to the second data) in the first storage area of ​​the first processing core or the fourth storage area of ​​the second processing core. Among them, when the first processing core stores the data to be processed in the second processing core, the storage resources of the first processing core can be saved and the utilization rate of the storage resources of the second processing core can be improved.

[0145] In the case of n>N / 2, it indicates that the first processing core is deployed at a later network layer in the neural network, the first processing core requires a smaller amount of data storage, and the storage resources of the first processing core are relatively sufficient. Correspondingly, the second processing core is deployed at a later network layer in the neural network, the second processing core requires a larger amount of data storage, and the storage resources of the second processing core are relatively tight. Therefore, the first processing core can store the data to be processed in the first processing core, but will not store the data to be processed in the second processing core. At this time, the data generated by the second processing core can be stored in the first processing core to save the storage resources of the second processing core and improve the utilization rate of the storage resources of the first processing core.

[0146] Fig.12 A flowchart of a data processing method provided by an embodiment of the present disclosure. Fig.12 As shown, the method may include:

[0147] In step S21 , an instruction sequence to be executed by a first processing core in a many-core system is determined, the many-core system includes a plurality of processing cores, and the first processing core is one of the plurality of processing cores.

[0148] In step S22, address adjustment information of the first processing instruction is determined according to change information of the to-be-processed data of the first processing instruction in the instruction sequence.

[0149] The address adjustment information is used to indicate the address adjustment method of the first storage area in the storage unit of the first processing core according to the change information during the execution of the first processing instruction, and the change information is used to indicate the consumption progress or generation progress of the data to be processed. This step can refer to step S11 and step S12 and will not be repeated here.

[0150] In step S23, a second processing instruction matching the address adjustment information of the first processing instruction is determined from the instruction sequence.

[0151] In step S24, the first processing instruction and the second processing instruction are mapped to the first processing core in sequence, so that the first processing core executes the first processing instruction and the second processing instruction in sequence.

[0152] In the disclosed embodiment, the address range of the first storage area is dynamically adjusted according to the change information of the data to be processed, so that the address range of the first storage area can change with the consumption progress or generation progress of the data to be processed. As the data to be processed is consumed, the first processing core can release the storage resources in the storage unit in time, which is conducive to improving the utilization rate of storage resources; as the data to be processed is generated, the first processing core can increase storage resources as needed, reducing the time to reserve storage resources for the first processing instruction, thereby reducing the waste of storage resources and improving the utilization rate of storage resources.

[0153] Furthermore, according to the data processing method provided by the embodiment of the present disclosure, by saving the storage resources of the first processing core, the first processing core is able to support more processing instructions executed simultaneously, which is beneficial to improving the efficiency of the many-core system.

[0154] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0155] In addition, the present disclosure also provides a data processing device, an electronic device, and a computer-readable storage medium, all of which can be used to implement any data processing method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be repeated here.

[0156] Fig.13 A block diagram of a data processing device provided in an embodiment of the present disclosure.

[0157] Reference Fig.13 The embodiment of the present disclosure provides a data processing device, which is applied to a first processing core of a many-core system, where the first processing core is one of a plurality of processing cores of the many-core system. The data processing device 130 includes:

[0158] The determination module 131 is configured to determine, in response to receiving a first processing instruction, a first storage area in a storage unit of the first processing core where the to-be-processed data of the first processing instruction is located.

[0159] The adjustment module 132 is used to adjust the address range of the first storage area according to the change information of the data to be processed during the execution of the first processing instruction, and the change information is used to indicate the reading progress or writing progress of the data to be processed.

[0160] Fig.14 A block diagram of an electronic device provided in an embodiment of the present disclosure.

[0161] Reference Fig.14 An embodiment of the present disclosure provides an electronic device, which includes multiple processing cores 1001 and an on-chip network 1002, wherein the multiple processing cores 1001 are connected to the on-chip network 1002, and the on-chip network 1002 is used to exchange data between the multiple processing cores and external data.

[0162] One or more instructions are stored in one or more processing cores 1001, and the one or more instructions are executed by one or more processing cores 1001, so that one or more processing cores 1001 can execute the above-mentioned data processing method.

[0163] In some embodiments, the electronic device may be a brain-like chip, which can use vectorized computing and needs to load the weight information and other parameters of the neural network model through an external memory such as a double data rate (DDR) synchronous dynamic random access memory. Therefore, the batch processing used in the embodiments of the present disclosure has a higher computing efficiency.

[0164] The present disclosure also provides a computer-readable storage medium on which a computer program is stored, wherein the computer program implements the above-mentioned data processing method when executed by a processor / processing core. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0165] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above-mentioned data processing method.

[0166] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).

[0167] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A data processing method, characterized in that: The method is applied to a first processing core of a many-core system, where the first processing core is one of a plurality of processing cores of the many-core system, and the method includes: In response to receiving a first processing instruction, determining a first storage area in a storage unit of the first processing core where data to be processed of the first processing instruction is located; During the execution of the first processing instruction, the address range of the first storage area is adjusted according to the change information of the data to be processed, and the change information is used to indicate the consumption progress or generation progress of the data to be processed.

2. The method according to claim 1, characterized in that The first storage area includes a first starting address and a first ending address; the data to be processed includes first data to be consumed, and the change information includes a data processing speed, and the data processing speed is used to represent the amount of data read and processed from the first storage area by the first processing instruction in a unit time; The adjusting the address range of the first storage area according to the change information of the data to be processed includes: In a case where the first processing instruction starts processing the first data from the first starting address, adjusting the address value of the first starting address according to a data processing speed of the first data so that an address range of the first storage area matches a real-time data volume of the first processing instruction; When the first processing instruction starts processing the first data from the first end address, the address value of the first end address is adjusted according to the data processing speed of the first data so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

3. The method according to claim 1, characterized in that The first storage area includes a first starting address and a first ending address; the data to be processed includes first data to be consumed, and the change information includes a data transmission speed, and the data transmission speed is used to represent the amount of data sent from the first storage area to the outside by the first processing instruction in a unit time; The adjusting the address range of the first storage area according to the change information of the data to be processed includes: In the case where the first processing instruction starts to send the first data from the first starting address, adjusting the address value of the first starting address according to the data sending speed of the first data so that the address range of the first storage area matches the real-time data volume of the first processing instruction; When the first processing instruction sends the first data starting from the first end address, the address value of the first end address is adjusted according to the data sending speed of the first data so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

4. The method according to claim 1, characterized in that: The first storage area includes a first starting address and a first ending address; the data to be processed includes second data to be generated, and the change information includes a data generation speed, and the data generation speed is used to represent the amount of data generated by the first processing instruction in a unit time and stored in the first storage area; The adjusting the address range of the first storage area according to the change information of the data to be processed includes: In the case where the first processing instruction starts to store the second data from the first starting address, adjusting the address value of the first starting address according to the data generation speed of the second data so that the address range of the first storage area matches the real-time data volume of the first processing instruction; When the first processing instruction stores the second data starting from the first end address, the address value of the first end address is adjusted according to the data generation speed of the second data so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

5. The method according to claim 1, characterized in that The first storage area includes a first starting address and a first ending address; the data to be processed includes second data to be generated, and the change information includes a data receiving speed, and the data receiving speed is used to represent the amount of data received from the outside and stored in the first storage area by the first processing instruction in a unit time; The adjusting the address range of the first storage area according to the change information of the data to be processed includes: In the case where the first processing instruction starts to store the second data from the first starting address, adjusting the address value of the first starting address according to the data receiving speed of the second data so that the address range of the first storage area matches the real-time data volume of the first processing instruction; When the first processing instruction stores the second data starting from the first end address, the address value of the first end address is adjusted according to the data receiving speed of the second data so that the address range of the first storage area matches the real-time data volume of the first processing instruction.

6. The method according to claim 1, characterized in that The method further comprises: During the execution of the first processing instruction, when a second processing instruction is received, determining whether address adjustment information of the first storage area matches address adjustment information of a second storage area in the storage unit, the second storage area being used to store data to be processed of the second processing instruction, the address adjustment information being determined according to change information of the data to be processed of the second processing instruction; When the address adjustment information of the first storage area matches the address adjustment information of the second storage area, the first storage area is concatenated with the second storage area.

7. The method according to claim 6, characterized in that The first storage area includes a first start address and a first end address, the second storage area includes a second start address and a second end address, and the address adjustment information includes a change slope of the address value; The matching of the address adjustment information of the first storage area and the address adjustment information of the second storage area includes: A difference between a change slope of the address value of the first start address and a change slope of the address value of the second end address is less than a first threshold; or, A difference between a change slope of the address value of the first end address and a change slope of the address value of the second start address is smaller than the first threshold.

8. The method according to claim 7, characterized in that When the first storage area is spliced ​​with the second storage area, at the same time, the address value of the first start address is greater than the address value of the second end address and the difference between the address value of the first start address and the address value of the second end address is less than a second threshold; or, At the same time, the address value of the first end address is smaller than the address value of the second start address, and the difference between the address value of the first end address and the address value of the second start address is smaller than the second threshold.

9. The method according to claim 1, characterized in that: The first processing core includes a processing unit, a storage unit and a routing unit; The data to be processed includes one or more of the following: data processed by the processing unit; data sent by the routing unit to the outside; data generated by the processing unit; The routing unit receives data from the outside.

10. The method according to claim 1, characterized in that The method further comprises: In the case where there is a free storage area between the first storage area and the third storage area, the storage position of the third data is adjusted until the first storage area is adjacent to the third storage area by simultaneous reading and writing or self-transmission and self-reception. The third storage area represents an occupied storage area in the storage unit of the first processing core except the first storage area, and the third data represents the data stored in the first storage area.

11. The method according to claim 1, characterized in that: The first processing instruction is used to train a neural network, wherein multiple network layers of the neural network are distributed and deployed to multiple processing cores of the many-core system, and each processing core is deployed with at least one network layer of the neural network, wherein a training batch of the neural network training includes multiple sub-batches, and the first processing core interleaves forward propagation processes and back propagation processes of different sub-batches in the training batch, and for any sub-batch of the training batch, the method further includes: In the forward propagation process, the to-be-processed data generated by the current sub-batch is stored in the first storage area or in a fourth storage area, where the fourth storage area represents a storage area in a storage unit of a second processing core, the second processing core is one of the plurality of processing cores other than the first processing core, and the second processing core is communicatively connected to the first processing core; During the back propagation process, the to-be-processed data consumed by the current sub-batch is read from the first storage area or the fourth storage area.

12. A data processing method, characterized in that: The method comprises: Determining an instruction sequence to be executed by a first processing core in a many-core system, the many-core system comprising a plurality of processing cores, the first processing core being one of the plurality of processing cores; determining address adjustment information of the first processing instruction according to change information of the to-be-processed data of the first processing instruction in the instruction sequence; The address adjustment information is used to indicate a manner of adjusting the address of a first storage area in a storage unit of the first processing core according to the change information during the execution of the first processing instruction, and the change information is used to indicate a consumption progress or a generation progress of the data to be processed; Determining, from the instruction sequence, a second processing instruction that matches the address adjustment information of the first processing instruction; The first processing instruction and the second processing instruction are sequentially mapped to the first processing core, so that the first processing core executes the first processing instruction and the second processing instruction sequentially.

13. A data processing device, characterized in that: The device is applied to a first processing core of a many-core system, where the first processing core is one of a plurality of processing cores of the many-core system, and the device includes: a determination module, configured to determine, in response to receiving a first processing instruction, a first storage area in a storage unit of the first processing core where the data to be processed of the first processing instruction is located; An adjustment module is used to adjust the address range of the first storage area according to the change information of the data to be processed during the execution of the first processing instruction, and the change information is used to indicate the reading progress or writing progress of the data to be processed.

14. An electronic device, characterized in that: include: Multiple processing cores; as well as An on-chip network is configured to exchange data between the multiple processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the data processing method described in any one of claims 1-11.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computer program implements the data processing method according to any one of claims 1 to 11.

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