Bandwidth allocation method, module, server, electronic equipment, medium and product

Abstract

The invention discloses a bandwidth allocation method, a module, a server, an electronic device, a medium and a product, and relates to the technical field of servers, and the method comprises the steps: writing a gating signal into a switch chip in response to a platform controller center, and controlling the output end of the switch chip to be connected with the input end of the switch chip corresponding to a target root port of a central processing unit; wherein the target root port of the central processing unit is the root port of the central processing unit corresponding to the gating signal; the input end of the switch chip is connected with a bandwidth distribution signal line of a root port of the central processing unit; an output end signal of the switch chip is obtained through an input and output interface of the platform controller center, and bandwidth allocation is carried out on the root port according to the bandwidth allocation relation between the output end signal of the switch chip and the root port. According to the bandwidth allocation method provided by the invention, the bandwidth allocation function of the PCIe port of the CPU can be realized by using fewer input and output interfaces.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a bandwidth allocation method, a bandwidth allocation module, a server, an electronic device, a computer-readable storage medium, and a computer program product. Background Art

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion card standard, mainly used to connect the CPU (central processing unit) and various expansion cards, such as graphics cards, sound cards, network adapters, etc. The bandwidth of PCIe is closely related to its version and the number of Lanes. For example, the theoretical maximum bandwidth of the PCIe x1 slot is 1GB / s, which is suitable for devices with low data transmission requirements; the theoretical maximum bandwidth of the PCIe x4 slot is 4GB / s, which is suitable for devices with medium bandwidth requirements; the theoretical maximum bandwidth of the PCIe x8 slot is 8GB / s, which is suitable for devices with higher data transmission speed requirements; the PCIe x16 slot has the highest theoretical maximum bandwidth of 16GB / s, which is widely used to connect high-performance graphics cards.

[0003] The PICe interface on the server motherboard generally uses a PCIe x8 slot or a PCIe x16 slot, which is convenient for plugging in different types of expansion cards later. Even if the gold finger on the expansion card is x2 or x4, it can still be plugged into the PCIe x8 slot or PCIex16 slot. However, the bandwidth that the CPU directly provides to the PCIe x8 slot and PCIe x16 slot is the maximum bandwidth. When a PCIe device with a small number of lanes is inserted, the PCIe device cannot be identified, and the CPU also allocates the maximum bandwidth, resulting in a waste of PCIe resources and a loss of CPU function.

[0004] However, in the related art, when allocating CPU RootPort bandwidth, multiple GPIOs (General Purpose Input / Output) are generally set for each CPU root port to achieve automatic bandwidth allocation, resulting in more GPIO resources being used. Summary of the invention

[0005] The present application provides a bandwidth allocation method, module, server, electronic device, medium and product to at least solve the problem of using more GPIO resources when automatically allocating bandwidth in the related art.

[0006] In a first aspect, the present application provides a bandwidth allocation method, comprising: In response to the platform controller center writing a strobe signal to the switch chip, the output end of the switch chip is controlled to be connected to the input end of the switch chip corresponding to the target root port of the central processing unit; wherein the target root port of the central processing unit is the root port of the central processing unit corresponding to the strobe signal; the input end of the switch chip is connected to the bandwidth allocation signal line of the root port of the central processing unit; The output terminal signal of the switch chip is obtained through the input and output interface of the platform controller center, and the bandwidth of the root port is allocated according to the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port.

[0007] In a second aspect, the present application also provides a bandwidth allocation module, including: BIOS storage devices, platform controller hub, switch chips and central processing units; The BIOS storage device is configured to store a bandwidth allocation program; The central processing unit is configured to read the bandwidth allocation program stored in the BIOS storage device, and in response to the platform controller center writing a selection signal to the switch chip, control the output end of the switch chip to be connected with the input end of the switch chip corresponding to the target root port of the central processing unit; and obtain the output end signal of the switch chip through the input and output interface of the platform controller center, and allocate bandwidth to the root port according to the bandwidth allocation relationship between the output end signal of the switch chip and the root port; The target root port of the central processing unit is the root port of the central processing unit corresponding to the selection signal; the input end of the switch chip is connected to the bandwidth allocation signal line of the root port of the central processing unit.

[0008] In a third aspect, the present application further provides a server, comprising the bandwidth allocation module as described in the second aspect.

[0009] In a fourth aspect, the present application further provides an electronic device, including: Memory for storing computer programs; A processor is used to implement the steps of the bandwidth allocation method as described in the first aspect when executing the computer program.

[0010] In a fifth aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the bandwidth allocation method described in the first aspect are implemented. In a sixth aspect, the present application further provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the bandwidth allocation method as described in the first aspect.

[0011] Through the present application, since each input end of the switch chip corresponds to each root port of the central processing unit, and the input end of the switch chip is connected to the bandwidth allocation signal line of the corresponding root port of the central processing unit, the input end of the switch chip can receive the bandwidth allocation signal line information of the corresponding root port of the central processing unit. The central processing unit can respond to the platform controller center to write a selection signal to the switch chip. Different selection signals control the different input ends of the switch chip to be connected with the output end of the switch chip, and the different input ends of the switch chip correspond to different root ports of the central processing unit, and then the output end of the switch chip can be controlled to be connected with the input end of the switch chip corresponding to the target root port of the central processing unit. Therefore, the output end signal of the switch chip obtained through the input and output interface of the platform controller center is the bandwidth allocation signal line information of the target root port of the selected central processing unit. The central processing unit can find the bandwidth corresponding to the bandwidth allocation signal line information according to the bandwidth allocation relationship between the output end signal of the switch chip and the root port, so as to allocate bandwidth to the root port. Compared with the prior art, which requires multiple input and output interfaces to be set for each PCIe root port of the central processing unit to realize bandwidth allocation, the present application can use a set of input and output interfaces to provide a selection signal for each root port of the central processing unit, and poll to allocate bandwidth to each root port by means of the selection signal control, so there is no need to set multiple input and output interfaces for each root port to allocate bandwidth as in the prior art. The bandwidth allocation method provided by the present application can realize the bandwidth allocation function of the CPU PCIe port using fewer input and output interfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0013] Figure 1 A schematic diagram of a bandwidth allocation framework provided in an embodiment of the present application; Figure 2 A flow chart of a bandwidth allocation method provided in an embodiment of the present application; Figure 3 A schematic diagram of another bandwidth allocation framework provided in an embodiment of the present application; Figure 4 A schematic diagram of another bandwidth allocation framework provided in an embodiment of the present application; Figure 5 A schematic diagram of another bandwidth allocation framework provided in an embodiment of the present application; Figure 6A schematic diagram of another bandwidth allocation framework provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of a switch chip provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of a server provided in an embodiment of the present application; Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0015] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0016] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0017] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion card standard, mainly used to connect the CPU and various expansion cards, such as graphics cards, sound cards, and network adapters.

[0018] PCIe has made fundamental changes in bus structure, which are mainly reflected in two aspects: one is the change from parallel bus to serial bus; the other is the point-to-point interconnection. The bus connecting the devices under the bridge in the original parallel bus structure is changed into a link. A link can contain one or more paths. Each path consists of two pairs of differential signal lines to form a dual-simplex serial transmission channel. There are no dedicated data, address, control and clock lines. Various transactions on the bus are organized into information packets for transmission. Another feature of PCIe that breaks through the traditional bus is the point-to-point interconnection method. Each device is connected by an independent link and has exclusive bandwidth. This is an effective solution to increase the transmission rate. The PCIe bus structure regards a link as a bus, thereby maintaining compatibility with the traditional PCI bus in terms of address space, configuration mechanism and software. A PCIe device occupies a bus (link), so there are many bridges and buses in a PCIe-based computer. Traditional PCI devices can also run on the PCIe platform. Through the PCIe to PCI (or PCI-X) bridge, the PCI (or PCI-X) bus can be brought out. Traditional PCI devices can be integrated into the PCIExpress structure by hanging on such a bus.

[0019] Here are the details of the different versions of PCIe and their bandwidth: PCIe 1.0: The online bit transfer rate is 2.5Gb / s, using 8 / 10 encoding, so the bandwidth of PCIe 1.0x1 is 250MB / s.

[0020] PCIe 2.0: The online bit transfer rate is doubled to 5Gb / s, using 8 / 10 encoding, so the bandwidth of PCIe 2.0x 1 is 500MB / s.

[0021] PCIe 3.0: The online bit transfer rate is 8Gb / s, using 128 / 130 encoding, so the bandwidth of PCIe 3.0x 1 is 1GB / s.

[0022] PCIe 4.0: The online bit transfer rate is increased to 16GT / s.

[0023] PCIe 5.0: The online bit transfer rate can reach up to 32GT / s.

[0024] In addition, the bandwidth of PCIe is also related to the number of its lanes. For example, the theoretical maximum bandwidth of the PCIe x1 slot is 1GB / s, which is suitable for devices with low data transmission requirements; the theoretical maximum bandwidth of the PCIe x4 slot is 4GB / s, which is suitable for devices with medium bandwidth requirements; the theoretical maximum bandwidth of the PCIe x8 slot is 8GB / s, which is suitable for devices with higher data transmission speed requirements; the PCIe x16 slot has the highest theoretical maximum bandwidth of 16GB / s, which is widely used to connect high-performance graphics cards.

[0025] The PICe interface on the server motherboard generally uses PCIe x8 slots and PCIe x16 slots to facilitate the later insertion of different types of expansion cards. Even if the gold finger on the expansion card is x2 or x4, it can still be inserted into the PCIe x8 slot or PCIex16 slot. However, the bandwidth directly provided by the CPU to the PCIe x8 slot and PCIe x16 slot is the maximum bandwidth, which causes the expansion card with a small number of lanes to be unable to be effectively identified. The CPU still allocates the maximum bandwidth, resulting in a waste of PCIe resources and a loss of CPU function. For example, two PCIe x8 devices are inserted into two PCIe x16 slots, but it is impossible to support two x8 devices in one x16 slot; PCIe cannot automatically identify and allocate bandwidth.

[0026] At present, in the related art, when automatically allocating bandwidth to the CPU root port, multiple GPIOs (General Purpose Input / Output) are generally set for each CPU root port to achieve automatic bandwidth allocation, resulting in more GPIO resources being used.

[0027] An embodiment of the present application provides a bandwidth allocation method. The specific application environment architecture or specific hardware architecture on which the execution of the bandwidth allocation method depends is described below.

[0028] This application uses a switch chip, and in combination with a bandwidth allocation program stored in a BIOS storage device, can realize automatic identification and allocation of CPUPCIe port bandwidth. Figure 1 A schematic diagram of a bandwidth allocation framework is shown. Figure 1 As shown, the server includes a central processing unit (CPU), a PCH (Platform Controller Hub), a BIOS storage device, and a switch chip. Among them, the input end of the switch chip can receive the bandwidth allocation signal line information of the root port of the central processing unit. Each group of input ends of the switch chip corresponds to a root port of the central processing unit. Each root port of the central processing unit corresponds to two bandwidth allocation signal lines. Figure 1 The exemplary configuration of the central processing unit CPU includes four root ports, namely CPU0 PE0, CPU0 PE1, CPU0 PE2, and CPU0 PE3. Each root port corresponds to two bandwidth allocation signal lines. Figure 1 The exemplary switch chip includes 4 groups of input terminals: the first group of input terminals U1Y0 and U2Y0; the second group of input terminals U1Y1 and U2Y1; the third group of input terminals U1Y2 and U2Y2; and the fourth group of input terminals U1Y3 and U2Y3. Among them, the first group of input terminals U1Y0 and U2Y0 correspond to CPU0 PE3; the second group of input terminals U1Y1 and U2Y1 ​​correspond to CPU0 PE2; the third group of input terminals U1Y2 and U2Y2 correspond to CPU0 PE1; and the fourth group of input terminals U1Y3 and U2Y3 correspond to CPU0 PE0. The bandwidth allocation signal line information of each root port can be preset.

[0029] PCH can write a selection signal to the switch chip through the input and output interface. The switch chip selects which group of input ends to be connected to the output end of the switch chip according to the selection signal. Then the output end of the switch chip can transmit the corresponding root port bandwidth allocation signal line information received by the selected input end to PCH through the output end. Figure 1 U1Z and U2Z in the figure are the output terminals of the switch chip. S0, S1, and S2 are the terminals in the switch chip that receive the selection signal. In terms of software, the bandwidth allocation program is stored in the BIOS storage device, and the bandwidth allocation program is used to design the bandwidth allocation program for the root port. The CPU can read the bandwidth allocation program stored in the BIOS storage device. After the server is turned on, the PCH loads the bandwidth allocation program into the memory, and the CPU executes the bandwidth allocation program. Specifically, the selection signal corresponding to the root port is determined, and the selection signal is written to the switch chip through the input and output interface of the platform controller center. The switch chip controls the output terminal of the switch chip to be connected with the input terminal of the switch chip corresponding to the target root port of the central processor according to the selection signal, and then reads the data of the output terminals U1Z and U2Z of the switch chip, and finds the bandwidth required to be allocated to the root port based on the read data of U1Z and U2Z and the output terminal signal of the switch chip and the bandwidth allocation of the root port, and allocates bandwidth to the root port according to the bandwidth found.

[0030] Figure 2 It is a flow chart of a bandwidth allocation method provided in an embodiment of the present application. The bandwidth allocation method provided in an embodiment of the present application can be applied to a central processing unit. Figure 2is a flow chart of a bandwidth allocation method according to an embodiment of the present invention. It should be noted that the steps shown in the flow chart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical sequence is shown in the flow chart, in some cases, the steps shown or described can be executed in a different order than that shown here. Figure 2 As shown, the bandwidth allocation method provided by this application includes: S101, in response to the platform controller center writing a selection signal to the switch chip, controlling the output end of the switch chip to be connected to the input end of the switch chip corresponding to the target root port of the central processor.

[0031] The BIOS storage device stores the bandwidth allocation program designed for the root port. After the server is turned on, the PCH loads the bandwidth allocation program into the memory, and the CPU executes the bandwidth allocation program. Specifically, the CPU determines the selection signal corresponding to the root port, responds to the platform controller center writing the selection signal to the switch chip, and controls the output end of the switch chip to be connected to the input end of the switch chip corresponding to the target root port of the central processor. Figure 1 S0 and S1 are the terminals in the switch chip that receive the selection signal. After the CPU writes the selection signal to the switch chip through the input and output interface of the PCH, it can control the switch chip to select which group of input terminals to be connected to the output terminal of the switch chip according to the selection signal. Then the output terminal of the switch chip can transmit the corresponding root port bandwidth allocation signal line information received by the selected input terminal to the PCH through the output terminal. Figure 1 U1Z and U2Z in the figure are the output terminals of the switch chip. E represents the enable signal terminal of the switch chip.

[0032] The target root port of the CPU is the root port of the CPU corresponding to the selection signal. Figure 1 In the introduction of the framework diagram, the input end of the switch chip is connected to the bandwidth allocation signal line of the root port of the central processor. For example, when the selection signal is "LLL", the root port of the central processor corresponding to the selection signal is CPU0 PE3, that is, the input end of the switch chip corresponding to the root port CPU0 PE3 is connected to the output end of the switch chip. "L" represents a low level.

[0033] Since the input end of the switch chip is connected to the two bandwidth allocation signal lines of the corresponding root port, the bandwidth allocation signal line information of each root port can be preset, so the output end of the switch chip can output the bandwidth allocation signal line information of the root port selected by the selection signal to the PCH.

[0034] S102: Acquire the output signal of the switch chip through the input and output interface of the platform controller center, and allocate bandwidth to the root port according to the bandwidth allocation relationship between the output signal of the switch chip and the root port.

[0035] Since in step S101, the central processing unit CPU selects the root port that needs to be configured with bandwidth through the selection signal, for example, when the selection signal "LLL" is selected in the above distance, the input end of the switch chip corresponding to the root port CPU0 PE3 is connected with the output end of the switch chip, that is, the bandwidth is allocated to the root port CPU0 PE3 this time. The present application is provided with a bandwidth allocation relationship between the output end signal of the switch chip and the root port, that is, the output end signal of the switch chip has a certain correlation with the bandwidth of the root port, and the output end signal of the switch chip is the bandwidth allocation signal line information of the root port selected by the switch chip according to the selection signal. Therefore, the central processing unit can determine the bandwidth corresponding to the output end signal of the received switch chip according to the bandwidth allocation relationship between the output end signal of the switch chip and the root port, and allocate the bandwidth determined by the search as the bandwidth of the currently selected root port.

[0036] The present application can use a set of input and output interfaces to provide a selection signal for each root port of the central processing unit, and poll to allocate the bandwidth of each root port by means of the selection signal control method, so as to allocate the required bandwidth to each CPU port, avoid the waste of PCIe resources, and do not need to set multiple input and output interfaces for each root port to allocate bandwidth as in the prior art. The bandwidth allocation method provided by the present application can use fewer input and output interfaces to realize the bandwidth allocation function of the CPU PCIe port.

[0037] In some optional implementations, the above step S101 "in response to the platform controller center writing a strobe signal to the switch chip, controlling the output end of the switch chip to be connected to the input end of the switch chip corresponding to the target root port of the central processor" may specifically include: The switch chip selection truth table is queried, and in response to the platform controller center polling and writing the selection signal corresponding to each root port to the switch chip, the output end of the switch chip is controlled to be connected with the input end of the switch chip corresponding to the target root port of the central processor.

[0038] The switch chip gating truth table includes the corresponding relationship between the conduction conditions of different input terminals and output terminals of the switch chip and the level of the gating signal.

[0039] In this embodiment, a switch chip gating truth table can be pre-set, and the switch chip gating truth table includes the corresponding relationship between the conduction conditions of different input terminals and output terminals of the switch chip and the level of the gating signal. Table 1 is a specific example of a switch chip gating truth table provided in an embodiment of the present application. As shown in Table 1, "L" represents a low level and "H" represents a high level. Figure 1Taking the framework shown as an example, "U1Y0, U2Y0" and "U1Z, U2Z" are turned on, which means that the first group of input terminals U1Y0, U2Y0 and output terminals U1Z, U2Z of the switch chip are turned on. Since the first group of input terminals U1Y0, U2Y0 are connected to the two bandwidth signal lines of the root port CPU0 PE3, when the first group of input terminals U1Y0, U2Y0 and output terminals U1Z, U2Z are turned on, the corresponding signals of the two bandwidth signal lines of the root port CPU0 PE3 can be output. The conduction of "U1Y1, U2Y1" and "U1Z, U2Z" indicates that the second group of input terminals U1Y1, U2Y1 ​​and output terminals U1Z, U2Z of the switch chip are conducted. Since the second group of input terminals U1Y1, U2Y1 ​​are connected to the two bandwidth signal lines of the root port CPU0 PE2, when the second group of input terminals U1Y1, U2Y1 ​​and output terminals U1Z, U2Z are conducted, the corresponding signals of the two bandwidth signal lines of the root port CPU0 PE2 can be output. The conduction of "U1Y2, U2Y2" and "U1Z, U2Z" indicates that the third group of input terminals U1Y2, U2Y2 and output terminals U1Z, U2Z of the switch chip are conducted. Since the third group of input terminals U1Y2, U2Y2 are connected to the two bandwidth signal lines of the root port CPU0 PE1, when the third group of input terminals U1Y2, U2Y2 and output terminals U1Z, U2Z are conducted, the corresponding signals of the two bandwidth signal lines of the root port CPU0 PE1 can be output. The conduction of "U1Y3, U2Y3" and "U1Z, U2Z" indicates that the fourth group of input terminals U1Y3, U2Y3 of the switch chip are connected to the output terminals U1Z, U2Z. Since the fourth group of input terminals U1Y3, U2Y3 are connected to the two bandwidth signal lines of the root port CPU0PE0, when the fourth group of input terminals U1Y3, U2Y3 and the output terminals U1Z, U2Z are conducted, the corresponding signals of the two bandwidth signal lines of the root port CPU0 PE0 can be output. The select signal can be selected through the switch chip select truth table to select the output terminal of the switch chip to output the signals on the two bandwidth allocation signal lines of the CPU's root port.

[0040]

[0041] In some optional implementations, the above step S102 of "obtaining the output end signal of the switch chip through the input and output interface of the platform controller center, and allocating bandwidth to the root port according to the bandwidth allocation relationship between the output end signal of the switch chip and the root port" may specifically include: The output signal of the switch chip is obtained through the input and output interface of the platform controller center, the bandwidth allocation table is queried, the root port bandwidth corresponding to the output signal of the switch chip is determined, and the bandwidth of the root port is configured according to the determined root port bandwidth.

[0042] The bandwidth allocation table includes the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port.

[0043] Table 2 is an example of a bandwidth allocation table provided in an embodiment of the present application. As shown in Table 2, the bandwidth allocation table includes the bandwidth allocation relationship between the output signal of the switch chip and the root port. The output signal of the switch chip is the signal of the input end of the switch chip selected by the selection signal, and the signal of the input end of the switch chip selected by the selection signal is the signal of the bandwidth allocation signal line of the corresponding CPU root port. The present application can pre-set the level signal of the bandwidth allocation signal line of each root port. Figure 1 Taking the framework shown as an example, in Table 2, the level signal of the bandwidth allocation signal line of the root port CPU0 PE0 is 00, the level signal of the bandwidth allocation signal line of the root port CPU0 PE1 is 01, the level signal of the bandwidth allocation signal line of the root port CPU0 PE2 is 10, and the level signal of the bandwidth allocation signal line of the root port CPU0 PE3 is 11. After the central processing unit CPU obtains the output signal of the switch chip through the input and output interface of the platform controller center PCH, it can query the bandwidth allocation table to determine the root port bandwidth corresponding to the output signal of the switch chip, and configure the bandwidth of the root port according to the determined root port bandwidth. For example, if the output signal of the switch chip is 00, it means that the switch chip input terminals U1Y3 and U2Y3 corresponding to the CPU root port are connected to the output terminal of the switch chip, and the corresponding output is the level signal of the bandwidth allocation signal line of the root port CPU0 PE0. By looking up the table, it can be seen that the bandwidth of the root port CPU0 PE0 corresponding to the output signal 00 of the switch chip is x8x8, so the bandwidth of the root port CPU0 PE0 can be configured according to the determined bandwidth x8x8 of the root port CPU0 PE0.

[0044]

[0045] In the prior art, 16 GPIOs are required for a single-channel processor (CPU includes 4 root ports). This application can only set 1 enable signal terminal (E), 2 output terminals (U1Z, U2Z), and 2 selection signal terminals (S0, S1) for a single-channel processor, a total of 5 GPIOs. Therefore, the occupied resources of GPIO can be significantly reduced.

[0046] It should be noted that, for the convenience of description, the signals transmitted in this application, and the terminals or interfaces for sending and receiving the signals use the same figure marks.

[0047] In some optional implementations, before the output end of the switch chip is controlled to be connected to the input end of the switch chip corresponding to the target root port of the central processor in response to the platform controller center writing a strobe signal to the switch chip, the following may be included: Configure the bandwidth of each root port in the CPU to the maximum bandwidth.

[0048] In actual use, there may be some CPU root ports that do not participate in bandwidth configuration. Before bandwidth configuration, the embodiment of the present application first configures the bandwidth of each root port in the central processing unit to the maximum bandwidth by default, so that all root ports have corresponding bandwidths. Since the unused root ports use the maximum bandwidth, the hardware resource allocation logic can also be kept simple, without the need to dynamically split or reorganize channels, reducing the overhead of logic circuits, simplifying state management and reducing the complexity of the physical layer, and reducing overall resource occupancy. In addition, at the beginning, the bandwidth of each root port in the central processing unit is configured to be the maximum bandwidth by default, and further operations can be avoided when the bandwidth of the root port corresponding to the output signal of the switch chip is not found. For example, before writing the selection signal to the switch chip through the input and output interface of the platform controller center, the central processing unit CPU sets a default x16 bandwidth for each root port.

[0049] In some optional implementations, the bandwidth allocation method provided by the present application may further include: The output signal of the switch chip is obtained through the input and output interface of the platform controller center, and the root port that does not participate in the bandwidth allocation is determined based on the bandwidth allocation relationship between the output signal of the switch chip and the root port, and the bandwidth of the root port that does not participate in the bandwidth allocation is configured as the maximum bandwidth.

[0050] After obtaining the output signal of the switch chip through the input and output interface of the platform controller center PCH, if the bandwidth of the root port corresponding to the output signal of the switch chip cannot be found based on the bandwidth allocation relationship between the output signal of the switch chip and the root port, it means that the CPU root port corresponding to the output signal is a root port that does not participate in bandwidth allocation. When the embodiment of the present application determines that there is a root port that does not participate in bandwidth allocation through the above method, the bandwidth of the root port that does not participate in bandwidth allocation is configured as the maximum bandwidth.

[0051] In some optional implementations, before the output end of the switch chip is controlled to be connected to the input end of the switch chip corresponding to the target root port of the central processor in response to the platform controller center writing a strobe signal to the switch chip, the method further includes: Write an enable signal to the switch chip through the input and output interface of the platform controller center.

[0052] refer to Figure 1 The input and output interface of the platform controller center includes an enable signal terminal E, and the platform controller center writes an enable signal to the switch chip through the enable signal terminal. In some embodiments, when the enable signal terminal E outputs a low level, the switch chip is enabled and starts working. When the enable signal terminal E receives a high level, the other pins of the switch chip are not connected. Figure 1 In the embodiment, the switch chip is also provided with an enable signal terminal for receiving an enable signal, which is indicated by the same reference numeral “E”.

[0053] In some optional implementations, in the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port, the minimum combined bandwidth is 4 channels.

[0054] In the embodiment of the present application, the signal level combination of the two bandwidth signal lines is used to represent different bandwidth modes. The levels of the two bandwidth signal lines are output through the output end of the switch chip, so the level combination of the GPIO pin at the output end of the switch chip (00, 01, 10, 11 as shown in Table 2) represents different bandwidth modes. If a smaller bandwidth unit is used, the number of combinations will be huge, resulting in increased complexity, which exceeds the range that can be represented by the GPIO pin level combination.

[0055] In order to avoid introducing more GPIO pins or more complex encoding, the embodiment of the present application sets the minimum combined bandwidth in the bandwidth allocation relationship between the output signal of the switch chip and the root port to 4 channels, which can simplify circuit design and state management and avoid the increase in the number of bandwidth combinations and hardware complexity caused by the introduction of finer-grained bandwidth (such as x2).

[0056] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0057] An embodiment of the present application also provides a bandwidth allocation module, including: a platform controller center, at least one switch chip and at least one central processing unit.

[0058] The BIOS memory device is configured to store a bandwidth allocation program.

[0059] The central processing unit is configured to read the bandwidth allocation program stored in the BIOS storage device, respond to the platform controller center writing a selection signal to the switch chip, control the output end of the switch chip to be connected with the input end of the switch chip corresponding to the target root port of the central processing unit, and obtain the output end signal of the switch chip through the input and output interface of the platform controller center, and allocate bandwidth to the root port according to the bandwidth allocation relationship between the output end signal of the switch chip and the root port.

[0060] The target root port of the central processing unit is the root port of the central processing unit corresponding to the selection signal; the input end of the switch chip is connected to the bandwidth allocation signal line of the root port of the central processing unit.

[0061] The framework and data interaction of the bandwidth allocation module in the server provided by the embodiment of the present application are similar to Figure 1 The embodiments of the present application will not elaborate on the above-mentioned details and the corresponding explanations.

[0062] Figure 1 The switch chip in the embodiment is a device with a gating function. The switch chip may be in the form of Figure 1 The one chip shown can also be used in the form of two chips according to the selected device function, for example Figure 3 As shown, the switch chip includes a first switch chip U1 and a second switch chip U2. Multiple input terminals of the switch chip correspond to multiple root ports one by one. The input terminal of the switch chip includes an input pin of the first switch chip and an input pin of the second switch chip. For example, the input terminals U1Y3 and U2Y3 of the switch chip include an input pin Y3 of the first switch chip U1 and an input pin Y3 of the second switch chip U2. The input pin of the first switch chip and the input pin of the second switch chip at the input terminal of the switch chip are connected to the two bandwidth allocation signal lines of the corresponding root port one by one. The input pin Y3 of the first switch chip U1 and the input pin Y3 of the second switch chip U2 are connected to the two bandwidth allocation signal lines of the root port CPU0 PE0 one by one. The first switch chip U1 and the second switch chip U2 multiplex the selection signal. Figure 3 The first switch chip U1 and the second switch chip U2 jointly control which input terminal is connected to the output terminal according to the selection signal, so as to realize which root port of CPU0 has a bandwidth allocation signal line whose signal is output to the output terminal.

[0063] It should be noted that Figure 1 The exemplary display only includes a CPU framework. In other optional implementations, the bandwidth allocation module can also configure the number of switch chips and central processing units according to actual usage requirements.

[0064] In some optional embodiments, the bandwidth allocation module provided in the embodiments of the present application can also be used in a dual-way processor. The bandwidth allocation module applicable to the dual-way processor includes a dual-way processor bandwidth allocation unit. The dual-way processor bandwidth allocation unit includes a first central processing unit, a second central processing unit, a first switch chip, and a second switch chip.

[0065] The switch chip comprises a first switch chip and a second switch chip; a plurality of input ends of the switch chip correspond one-to-one to a plurality of root ports; the input end of the switch chip comprises an input pin of the first switch chip and an input pin of the second switch chip; the input pin of the first switch chip and the input pin of the second switch chip at the input end of the switch chip are connected one-to-one to two bandwidth allocation signal lines of the corresponding root port; the first switch chip and the second switch chip multiplex the selection signal.

[0066] Figure 4 A schematic diagram of another bandwidth allocation framework provided in an embodiment of the present application. Figure 4 As shown, the bandwidth allocation module includes a dual-processor bandwidth allocation unit. The dual-processor bandwidth allocation unit includes a first central processor CPU0, a second central processor CPU1, a first switch chip U1 and a second switch chip U2. The switch chip includes a first switch chip U1 and a second switch chip U2. Multiple input terminals of the switch chip correspond one-to-one to multiple root ports.

[0067] Figure 4 In the exemplary configuration, the first central processor CPU0 includes four root ports, namely CPU0 PE0, CPU0 PE1, CPU0 PE2, and CPU0 PE3. The second central processor CPU1 includes four root ports, namely CPU1 PE0, CPU1 PE1, CPU1 PE2, and CPU1 PE3.

[0068] The multiple input terminals of the switch chip include a first group of input terminals U1Y0 and U2Y0; a second group of input terminals U1Y1 and U2Y1; a third group of input terminals U1Y2 and U2Y2; a fourth group of input terminals U1Y3 and U2Y3; a fifth group of input terminals U1Y4 and U2Y4; a sixth group of input terminals U1Y5 and U2Y5; a seventh group of input terminals U1Y6 and U2Y6; and an eighth group of input terminals U1Y7 and U2Y7. The first group of input terminals U1Y0 and U2Y0 correspond to CPU0 PE3; the second group of input terminals U1Y1 and U2Y1 ​​correspond to CPU0 PE2; the third group of input terminals U1Y2 and U2Y2 correspond to CPU0 PE1; and the fourth group of input terminals U1Y3 and U2Y3 correspond to CPU0 PE0. The fifth group of input terminals U1Y4 and U2Y4 correspond to CPU1 PE0; the sixth group of input terminals U1Y5 and U2Y5 correspond to CPU1 PE1; the seventh group of input terminals U1Y6 and U2Y6 correspond to CPU1 PE2; and the eighth group of input terminals U1Y7 and U2Y7 correspond to CPU1 PE3.

[0069] Each input end of the switch chip corresponds to two pins, including an input pin of a first switch chip and an input pin of a second switch chip. The input pin of the first switch chip and the input pin of the second switch chip at the input end of the switch chip are connected to the two bandwidth allocation signal lines of the corresponding root port in a one-to-one correspondence, so as to obtain the signals of the two bandwidth allocation signal lines of the corresponding root port.

[0070] For example, the first group of input terminals U1Y0 and U2Y0 include the input pin Y0 of the first switch chip U1 and the input pin Y0 of the second switch chip U2. The second group of input terminals U1Y1 and U2Y1 ​​include the input pin Y1 of the first switch chip U1 and the input pin Y1 of the second switch chip U2. The third group of input terminals U1Y2 and U2Y2 include the input pin Y2 of the first switch chip U1 and the input pin Y2 of the second switch chip U2. The fourth group of input terminals U1Y3 and U2Y3 include the input pin Y3 of the first switch chip U1 and the input pin Y3 of the second switch chip U2. The fifth group of input terminals U1Y4 and U2Y4 include the input pin Y4 of the first switch chip U1 and the input pin Y4 of the second switch chip U2. The sixth group of input terminals U1Y5 and U2Y5 include the input pin Y5 of the first switch chip U1 and the input pin Y5 of the second switch chip U2. The seventh group of input terminals U1Y6, U2Y6 includes the input pin Y6 of the first switch chip U1 and the input pin Y6 of the second switch chip U2. The eighth group of input terminals U1Y7, U2Y7 includes the input pin Y7 of the first switch chip U1 and the input pin Y7 of the second switch chip U2.

[0071] like Figure 4 As shown, the first switch chip U1 and the second switch chip U2 both include three selection signal terminals S0, S1, and S2. The first switch chip U1 and the second switch chip U2 multiplex the selection signal, that is, the first switch chip U1 and the second switch chip U2 are applicable to the same set of selection signals, and the first switch chip U1 and the second switch chip U2 are connected to the same selection signal GPIO pin of the PCH. This setting can reduce the number of GPIO pins used.

[0072] Figure 4 The bandwidth allocation module shown includes two CPUs, a total of 8 root ports, and only two GPIOs ( Figure 4 The bandwidth allocation function of the CPU root port of the dual-core server can be realized by using U1Z and U2Z in the figure. The input ends of the two switch chips receive the information on the bandwidth allocation signal lines of the eight root ports of the two CPUs.

[0073]

[0074] In this embodiment, a switch chip gating truth table can be pre-set, and the switch chip gating truth table includes the corresponding relationship between the conduction conditions of different input terminals and output terminals of the switch chip and the level of the gating signal. Figure 4A specific example of the switch chip selection truth table of the bandwidth allocation framework is shown. As shown in Table 3, "L" represents a low level and "H" represents a high level. The conduction of "U1Y0, U2Y0" and "U1Z, U2Z" indicates that the first group of input terminals U1Y0, U2Y0 of the first switch chip U1 is connected to the output terminals U1Z, U2Z. Since the first group of input terminals U1Y0, U2Y0 are connected to the two bandwidth signal lines of the root port CPU0 PE3, when the first group of input terminals U1Y0, U2Y0 and the output terminals U1Z, U2Z are connected, the corresponding signals of the two bandwidth signal lines of the root port CPU0 PE3 can be output. The conduction of "U1Y1, U2Y1" and "U1Z, U2Z" indicates that the second group of input terminals U1Y1, U2Y1 ​​and output terminals U1Z, U2Z of the switch chip CPU0 are conducted. Since the second group of input terminals U1Y1, U2Y1 ​​are connected to the two bandwidth signal lines of the root port CPU0 PE2, when the second group of input terminals U1Y1, U2Y1 ​​and output terminals U1Z, U2Z are conducted, the corresponding signals of the two bandwidth signal lines of the root port CPU0 PE2 can be output. The conduction of "U1Y2, U2Y2" and "U1Z, U2Z" indicates that the third group of input terminals U1Y2, U2Y2 and output terminals U1Z, U2Z of the switch chip CPU0 are conducted. Since the third group of input terminals U1Y2, U2Y2 are connected to the two bandwidth signal lines of the root port CPU0 PE1, when the third group of input terminals U1Y2, U2Y2 and output terminals U1Z, U2Z are conducted, the corresponding signals of the two bandwidth signal lines of the root port CPU0 PE1 can be output. The conduction of "U1Y3, U2Y3" and "U1Z, U2Z" indicates that the fourth group of input terminals U1Y3, U2Y3 and output terminals U1Z, U2Z of the switch chip CPU0 are conducted. Since the fourth group of input terminals U1Y3, U2Y3 are connected to the two bandwidth signal lines of the root port CPU0 PE0, when the fourth group of input terminals U1Y3, U2Y3 and output terminals U1Z, U2Z are conducted, the corresponding signals of the two bandwidth signal lines of the root port CPU0 PE0 can be output. The conduction of "U1Y4, U2Y4" and "U1Z, U2Z" indicates that the fifth group of input terminals U1Y4, U2Y4 and output terminals U1Z, U2Z of the switch chip CPU1 are conducted. Since the fifth group of input terminals U1Y4, U2Y4 are connected to the two bandwidth signal lines of the root port CPU1 PE0, when the fifth group of input terminals U1Y4, U2Y4 and output terminals U1Z, U2Z are conducted, the corresponding signals of the two bandwidth signal lines of the root port CPU1 PE0 can be output.The conduction of "U1Y5, U2Y5" and "U1Z, U2Z" indicates that the sixth group of input terminals U1Y5, U2Y5 and output terminals U1Z, U2Z of the switch chip CPU1 are conducted. Since the sixth group of input terminals U1Y5, U2Y5 are connected to the two bandwidth signal lines of the root port CPU1 PE1, when the sixth group of input terminals U1Y5, U2Y5 and output terminals U1Z, U2Z are conducted, the corresponding signals of the two bandwidth signal lines of the root port CPU1 PE1 can be output. The conduction of "U1Y6, U2Y6" and "U1Z, U2Z" indicates that the seventh group of input terminals U1Y6, U2Y6 and output terminals U1Z, U2Z of the switch chip CPU1 are conducted. Since the seventh group of input terminals U1Y6, U2Y6 are connected to the two bandwidth signal lines of the root port CPU1 PE2, when the seventh group of input terminals U1Y6, U2Y6 and output terminals U1Z, U2Z are conducted, the corresponding signals of the two bandwidth signal lines of the root port CPU1 PE2 can be output. The conduction of "U1Y7, U2Y7" and "U1Z, U2Z" indicates that the eighth group of input terminals U1Y7, U2Y7 and output terminals U1Z, U2Z of the switch chip CPU0 are conducted. Since the eighth group of input terminals U1Y7, U2Y7 are connected to the two bandwidth signal lines of the root port CPU1 PE3, when the eighth group of input terminals U1Y7, U2Y7 and output terminals U1Z, U2Z are conducted, the corresponding signals of the two bandwidth signal lines of the root port CPU1 PE3 can be output.

[0075] The switch chips CPU0 and CPU1 are provided with an enable signal terminal E. When the signal received by the enable signal terminal E is a low level "L", the switch chip is enabled and starts working. When the enable signal terminal E receives a high level "H", the other pins of the switch chip are not connected. The "X" in Table 3 indicates that the corresponding pin is not connected.

[0076] In this embodiment, a bandwidth allocation table can be pre-set, and the bandwidth allocation table includes the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port. Figure 4 The bandwidth allocation table of the bandwidth allocation framework is shown as a specific example. As shown in Table 4, the level signal of the bandwidth allocation signal line of the root port CPU0 PE0 is 00, the level signal of the bandwidth allocation signal line of the root port CPU0 PE1 is 01, the level signal of the bandwidth allocation signal line of the root port CPU0 PE2 is 10, the level signal of the bandwidth allocation signal line of the root port CPU0 PE3 is 11, the level signal of the bandwidth allocation signal line of the root port CPU1 PE2 is 10, and the level signal of the bandwidth allocation signal line of the root port CPU1 PE3 is 11.

[0077]

[0078] After the central processing unit CPU obtains the output signal of the switch chip through the input and output interface of the platform controller center PCH, it can query the bandwidth allocation table to determine the root port bandwidth corresponding to the output signal of the switch chip, and configure the bandwidth of the root port according to the determined root port bandwidth. For example, if the output signal of the switch chip is 00, it means that the input terminals U1Y3 and U2Y3 of the switch chip corresponding to the CPU root port are connected to the output terminal of the switch chip, and the corresponding output is the level signal of the bandwidth allocation signal line of the root port CPU0 PE0. By looking up the table, it can be seen that the bandwidth of the root port CPU0 PE0 corresponding to the output signal 00 of the switch chip is x8x8, so the bandwidth of the root port CPU0 PE0 can be configured according to the determined bandwidth x8x8 of the root port CPU0 PE0. In Table 4, the output signal of the switch chip corresponding to the root port CPU1 PE0 and the root port CPU1 PE1 is "NC", indicating that the root port CPU1 PE0 and the root port CPU1 PE1 do not participate in the bandwidth configuration, and the root port CPU1 PE0 and the root port CPU1 PE1 are set to x16 by default.

[0079] In some optional embodiments, the platform controller center includes an enable signal terminal for writing an enable signal to the switch chip. The first switch chip and the second switch chip are connected to the same enable signal terminal.

[0080] See also Figure 4 In the embodiment of the present application, when implementing bandwidth allocation for dual-path processors, a first switch chip and a second switch chip are connected to the same enable signal terminal of the platform controller center. Under the same enable signal, the conduction selection of different input terminals and output terminals is realized through the level combination of the selection signals S0, S1, and S2, which can reduce the number of PCH GPIO pins.

[0081] In some optional embodiments, the bandwidth allocation module includes a four-way processor bandwidth allocation unit, the four-way processor bandwidth allocation unit includes two dual-way processor bandwidth allocation units, namely a first dual-way processor bandwidth allocation unit and a second dual-way processor bandwidth allocation unit; the first dual-way processor bandwidth allocation unit and the second dual-way processor bandwidth allocation unit are connected to different enable signal terminals; the first dual-way processor bandwidth allocation unit and the second dual-way processor bandwidth allocation unit multiplex the selection signal.

[0082] In the prior art, a dual-channel processor (two CPUs each including four root ports) requires 32 GPIOs. However, by adopting the method of the present application, the bandwidth is automatically configured through the bandwidth signal line bandwidth setting of the CPU root port, thereby avoiding the waste of PCIe resources. In addition, only one enable signal terminal (E), two output terminals (U1Z, U2Z), and three selection signal terminals (S0, S1, S2) can be set for the dual-channel processor, for a total of six GPIOs. Therefore, the occupied resources of GPIO can be significantly reduced.

[0083] The embodiment of the present application may be applicable to bandwidth allocation of a four-way processor. Figure 5 A schematic diagram of another bandwidth allocation framework provided in an embodiment of the present application. Figure 5 As shown, the four-way processor bandwidth allocation unit includes two dual-way processor bandwidth allocation units, namely a first dual-way processor bandwidth allocation unit A1 and a second dual-way processor bandwidth allocation unit A2. The first dual-way processor bandwidth allocation unit A1 and the second dual-way processor bandwidth allocation unit A2 can refer to the above Figure 4 The first dual-path processor bandwidth allocation unit A1 and the second dual-path processor bandwidth allocation unit A2 are connected to different enable signal terminals of the PCH. Figure 5 The enable signal end of the PCH, the first dual-way processor bandwidth allocation unit A1 and the second dual-way processor bandwidth allocation unit A2 correspond to the ports of the same enable signal and are represented by the same figure mark. The enable signal end E1 of the first dual-way processor bandwidth allocation unit A1 receives the enable signal of the enable signal end E1 of the PCH, and the enable signal end E2 of the second dual-way processor bandwidth allocation unit A2 receives the enable signal of the enable signal end E2 of the PCH. The output end of the switch chip in the first dual-way processor bandwidth allocation unit A1 is represented by U1Z and U1Z, and the output end of the switch chip in the second dual-way processor bandwidth allocation unit A2 is represented by U3Z and U4Z. The two central processors of the first dual-way processor bandwidth allocation unit A1 are represented by CPU0 and CPU1, and the two central processors of the second dual-way processor bandwidth allocation unit A2 are represented by CPU2 and CPU3. The first dual-path processor bandwidth allocation unit A1 and the second dual-path processor bandwidth allocation unit A2 multiplex the selection signal, that is, the first dual-path processor bandwidth allocation unit A1 and the second dual-path processor bandwidth allocation unit A2 both receive the same set of selection signals of the PCH, for example Figure 5 The first dual-path processor bandwidth allocation unit A1 and the second dual-path processor bandwidth allocation unit A2 are connected to three GPIO pins of the PCH for inputting selection signals S0, S1, and S2.

[0084] In some optional embodiments, the bandwidth allocation module includes a four-way processor bandwidth allocation unit, which includes two dual-way processor bandwidth allocation units, namely a first dual-way processor bandwidth allocation unit and a second dual-way processor bandwidth allocation unit; the first dual-way processor bandwidth allocation unit is connected to the enable signal end of the platform controller center; the second dual-way processor bandwidth allocation unit is connected to the enable signal end of the first dual-way processor bandwidth allocation unit through an inverter; the first dual-way processor bandwidth allocation unit and the second dual-way processor bandwidth allocation unit multiplex the selection signal.

[0085] The embodiment of the present application may also be applicable to bandwidth allocation of a four-way processor. Figure 6 A schematic diagram of another bandwidth allocation framework provided in an embodiment of the present application. Figure 6 As shown, the four-way processor bandwidth allocation unit includes two dual-way processor bandwidth allocation units, namely a first dual-way processor bandwidth allocation unit A1 and a second dual-way processor bandwidth allocation unit A2. The first dual-way processor bandwidth allocation unit A1 and the second dual-way processor bandwidth allocation unit A2 can refer to the above Figure 4 The first dual-path processor bandwidth allocation unit A1 is connected to the enable signal terminal E of the PCH, Figure 6 The enable signal terminal of the first dual-way processor bandwidth allocation unit A1 is marked as E1. The enable signal terminal E2 of the second dual-way processor bandwidth allocation unit A2 is connected to the enable signal terminal connected to the first dual-way processor bandwidth allocation unit A1 through an inverter B, and the enable signal terminal of the second dual-way processor bandwidth allocation unit A2 is marked as E2. The output terminals of the switch chip in the first dual-way processor bandwidth allocation unit A1 are represented by U1Z and U1Z, and the output terminals of the switch chip in the second dual-way processor bandwidth allocation unit A2 are represented by U3Z and U4Z. The two central processors of the first dual-way processor bandwidth allocation unit A1 are represented by CPU0 and CPU1, and the two central processors of the second dual-way processor bandwidth allocation unit A2 are represented by CPU2 and CPU3. The first dual-way processor bandwidth allocation unit A1 and the second dual-way processor bandwidth allocation unit 2 multiplex the selection signal, that is, the first dual-way processor bandwidth allocation unit A1 and the second dual-way processor bandwidth allocation unit A2 both receive the same set of selection signals of PCH, for example Figure 6 The first dual-path processor bandwidth allocation unit A1 and the second dual-path processor bandwidth allocation unit A2 are connected to three GPIO pins of the PCH for inputting selection signals S0, S1, and S2.

[0086] In the embodiment of the present application, a first dual-path processor bandwidth allocation unit A1 is connected to the enable signal terminal E of the PCH, and a second dual-path processor bandwidth allocation unit A2 is connected to the enable signal terminal connected to the first dual-path processor bandwidth allocation unit A1 through an inverter B, which can further save the number of CPIO pins of the PCH.

[0087] In some optional embodiments, the bandwidth allocation module may further include i four-way processor bandwidth allocation units; different four-way processor bandwidth allocation units are connected to different enable signal terminals; and different four-way processor bandwidth allocation units multiplex the selection signal. Where i is a positive integer greater than 1.

[0088] The embodiment of the present application can be applied to the case of 8-way or more processors. For example, when the bandwidth allocation module also includes two four-way processor bandwidth allocation units, it can be applied to 8-way processors. The specific structure and implementation principle of the four-way processor bandwidth allocation unit can be referred to the introduction in the above embodiment and similar embodiments. Figure 5 or Figure 6 Different four-way processor bandwidth allocation units are set to connect different enable signal terminals of PCH to implement the enable polling configuration of each CPU root port.

[0089] In the prior art, a two-way processor uses 32 GPIOs of the PCH. The current PCH may still provide enough GPIOs for its use. However, for a four-way processor, due to the limited number of GPIOs of the PCH, the prior art uses a GPIO expansion chip to expand the GPIO to provide GPIO for bandwidth allocation of the four-way processor. Therefore, for a four-way or more processor, the prior art not only requires the participation of the GPIO expansion chip, but also requires the configuration of the corresponding program reading, which is relatively complicated and has poor stability.

[0090] If the prior art allocates bandwidth for a single-way processor, for example, the root port CPU0 PE0 is configured using GPIO5 ~ GPIO8. If it is changed to another motherboard design, the root port may be replaced with another set of GPIO. Once the CPU root port is changed, the configuration program must be rewritten. If it is for a multi-way processor, the prior art also needs to add a GPIO expansion chip. The GPIO extended by the expansion chip corresponds to a certain root port of a certain CPU, which is not fixed. For different CPUs and different root ports, the program needs to be rewritten to correspond, and the reading configuration of the present application can be fixed and universal. Even if the server model changes (for example, the motherboard or system design is different) and the server CPU root port connection form changes, the same BIOS program can be used to allocate the CPU root port bandwidth.

[0091] In some optional embodiments, the bandwidth allocation module further includes a bandwidth signal line level configuration circuit. The bandwidth signal line level configuration circuit is electrically connected to the input end of the switch chip and is used to configure the level signal of the input end of the switch chip.

[0092] The bandwidth signal line level configuration circuit includes, for example, a pull-up resistor, a pull-down resistor, etc., which is grounded for a low level and connected to a power supply for a high level. The embodiment of the present application does not limit the specific circuit composition of the bandwidth signal line level configuration circuit, and the level information of the bandwidth allocation signal line is set by the bandwidth signal line level configuration circuit, thereby configuring the level signal of the input end of the switch chip.

[0093] In some optional embodiments, the bandwidth signal line level configuration circuit is disposed on a mainboard or an expansion card.

[0094] In the case where a fixed slot is provided on the server mainboard, the level information of the bandwidth allocation signal line can be set by providing a bandwidth signal line level configuration circuit on the mainboard.

[0095] In the case where an expansion card is arranged in a general slot on a mainboard, the level information of the bandwidth allocation signal line can be set by a bandwidth signal line level configuration circuit on the expansion card.

[0096] In some optional embodiments, the platform controller center includes n strobe signal input and output interfaces for writing strobe signals to the switch chip; the number n of the strobe signal input and output interfaces satisfies: 2 n =m; where m is the number of root ports.

[0097] The embodiment of the present application can flexibly set the number of PCH strobe signal input and output interfaces according to the number of root ports to provide a strobe signal to the switch chip. In the present application, the PCH strobe signal input and output interface can be referred to as a GPIO pin.

[0098] For example Figure 3 The single-socket server shown includes four root ports, the number of root ports m=4, the number of selection signal input and output interfaces n is set to 2, and the PCH provides the selection signal to the switch chip through two GPIO pins.

[0099] For example Figure 4 The dual-core server shown includes 8 root ports, the number of root ports m=8, the number of selection signal input and output interfaces n is set to 3, and the PCH provides the selection signal to the switch chip through three GPIO pins.

[0100] In some optional embodiments, the switch chip may include, for example, a logic level conversion module and a decoder. Figure 7As shown, the switch chip includes a logic level conversion module and a decoder. The logic level conversion module is used to convert the level of the input signal into a level suitable for the operation of the internal circuit, and may include multiple inverters and buffers. By cascading the inverters and buffers, the signal can be amplified and shaped to ensure the stability and integrity of the signal. The logic level conversion module includes input terminals S0, S1, S2 and E. The input terminals S0, S1, S2 are used to receive the selection signal, and the input terminal E is used to receive the enable signal. The output terminal of the logic level conversion module is connected to the decoder module. The logic level conversion module also includes power supply terminals: Vcc and GND. If Figure 4 In the switch chip of the shown architecture, the decoder of the switch chip decodes the 3-bit binary address signal into 8 independent output signals, of which only one output signal is high and the rest are low. When the input address signal changes, only one output signal is high and the rest are low. The decoder is usually composed of multiple AND gates and OR gates to realize the decoding function. The input terminals C1, C2, C3, and C4 of the decoder are connected to the output terminals of the logic level conversion module. The output terminals D0, D1, D2, D3, D4, D5, D6, and D7 of the decoder control which input terminal (Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7) of the switch chip is connected to the output terminal Z of the switch chip. The logic level conversion module and the decoder inside the switch chip jointly realize the function of an 8-channel analog multiplexer / demultiplexer. The logic level conversion module ensures the stability and integrity of the input signal, and the decoder realizes the decoding of the input address signal, thereby realizing the functions of multiplexing and demultiplexing.

[0101] This embodiment also provides a server, such as Figure 8 As shown, the server includes the bandwidth allocation module in any of the above embodiments. The bandwidth allocation module includes a BIOS storage device, a platform controller center PCH, a switch chip and a central processing unit CPU. The BIOS storage device is configured to store a bandwidth allocation program; the central processing unit is configured to read the bandwidth allocation program stored in the BIOS storage device, in response to the platform controller center writing a selection signal to the switch chip, control the output end of the switch chip to be connected with the input end of the switch chip corresponding to the target root port of the central processing unit, and obtain the output end signal of the switch chip through the input and output interface of the platform controller center, and allocate bandwidth to the root port according to the bandwidth allocation relationship between the output end signal of the switch chip and the root port. Among them, the target root port of the central processing unit is the root port of the central processing unit corresponding to the selection signal; the input end of the switch chip is connected to the bandwidth allocation signal line of the root port of the central processing unit.

[0102] The functional descriptions of the BIOS storage device, platform controller center, switch chip and central processing unit in the server are the same as those in the above-mentioned corresponding embodiments and will not be repeated here. The present application also provides an electronic device. Fig. 9 , which is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device includes a memory 100 and a processor 200. The memory 100 is used to store a computer program; the processor 200 is used to implement the steps of the bandwidth allocation method provided in any of the above embodiments when executing the computer program.

[0103] The electronic device provided in the embodiment of the present application is used to execute the bandwidth allocation method provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0104] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned bandwidth allocation method embodiments when running.

[0105] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0106] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned bandwidth allocation method embodiments are implemented.

[0107] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned bandwidth allocation method embodiments are implemented.

[0108] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0109] The above is a detailed introduction to a bandwidth allocation method provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A bandwidth allocation method, characterized in that: include: In response to the platform controller center writing a strobe signal to the switch chip, the output end of the switch chip is controlled to be connected to the input end of the switch chip corresponding to the target root port of the central processing unit; wherein the target root port of the central processing unit is the root port of the central processing unit corresponding to the strobe signal; the input end of the switch chip is connected to the bandwidth allocation signal line of the root port of the central processing unit; The output terminal signal of the switch chip is obtained through the input and output interface of the platform controller center, and the bandwidth of the root port is allocated according to the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port.

2. The bandwidth allocation method according to claim 1, characterized in that: The step of controlling the output end of the switch chip to be connected to the input end of the switch chip corresponding to the target root port of the central processor in response to the platform controller center writing a strobe signal to the switch chip comprises: Query the switch chip gating truth table, and in response to the platform controller center polling and writing the gating signal corresponding to each root port to the switch chip, control the output end of the switch chip to be connected with the input end of the switch chip corresponding to the target root port of the central processor; The switch chip gating truth table includes the corresponding relationship between the conduction conditions of different input terminals and output terminals of the switch chip and the levels of the gating signal.

3. The bandwidth allocation method according to claim 1, characterized in that: The step of acquiring the output terminal signal of the switch chip through the input and output interface of the platform controller center, and allocating bandwidth to the root port according to the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port, comprises: Obtaining the output signal of the switch chip through the input and output interface of the platform controller center, querying the bandwidth allocation table, determining the root port bandwidth corresponding to the output signal of the switch chip, and configuring the bandwidth of the root port according to the determined root port bandwidth; The bandwidth allocation table includes a bandwidth allocation relationship between an output terminal signal of a switch chip and a root port.

4. The bandwidth allocation method according to claim 1, characterized in that: Before the step of responding to the platform controller center writing a strobe signal to the switch chip and controlling the output end of the switch chip to be connected to the input end of the switch chip corresponding to the target root port of the central processor, the step includes: The bandwidth of each of the root ports in the central processor is configured to be the maximum bandwidth.

5. The bandwidth allocation method according to claim 1, characterized in that: Also includes: The output signal of the switch chip is obtained through the input and output interface of the platform controller center, and the root port that does not participate in bandwidth allocation is determined based on the bandwidth allocation relationship between the output signal of the switch chip and the root port, and the bandwidth of the root port that does not participate in bandwidth allocation is configured as the maximum bandwidth.

6. The bandwidth allocation method according to claim 1, characterized in that: Before the step of responding to the platform controller center writing a strobe signal to the switch chip and controlling the output end of the switch chip to be connected to the input end of the switch chip corresponding to the target root port of the central processor, the step further includes: Write an enable signal to the switch chip through the input and output interface of the platform controller center.

7. A bandwidth allocation module, characterized in that: include: BIOS storage devices, platform controller hub, switch chips and central processing units; The BIOS storage device is configured to store a bandwidth allocation program; The central processing unit is configured to read the bandwidth allocation program stored in the BIOS storage device, and in response to the platform controller center writing a selection signal to the switch chip, control the output end of the switch chip to be connected with the input end of the switch chip corresponding to the target root port of the central processing unit; and obtain the output end signal of the switch chip through the input and output interface of the platform controller center, and allocate bandwidth to the root port according to the bandwidth allocation relationship between the output end signal of the switch chip and the root port; The target root port of the central processing unit is the root port of the central processing unit corresponding to the selection signal; the input end of the switch chip is connected to the bandwidth allocation signal line of the root port of the central processing unit.

8. The bandwidth allocation module according to claim 7, characterized in that: It also includes a bandwidth signal line level configuration circuit; the bandwidth signal line level configuration circuit is electrically connected to the input end of the switch chip and is used to configure the level signal of the input end of the switch chip.

9. The bandwidth allocation module according to claim 8, characterized in that: The bandwidth signal line level configuration circuit is arranged on the main board.

10. The bandwidth allocation module according to claim 8, characterized in that: The bandwidth signal line level configuration circuit is arranged on the expansion card.

11. The bandwidth allocation module according to claim 8, characterized in that: The platform controller center includes n strobe signal input and output interfaces for writing strobe signals to the switch chip; the number n of the strobe signal input and output interfaces satisfies: 2 n =m; where m is the number of root ports.

12. The bandwidth allocation module according to claim 8, characterized in that: The bandwidth allocation module includes a dual-path processor bandwidth allocation unit; the dual-path processor bandwidth allocation unit includes a first central processing unit, a second central processing unit, a first switch chip and a second switch chip; the switch chip includes the first switch chip and the second switch chip; the multiple input ends of the switch chip correspond one-to-one to the multiple root ports; the input end of the switch chip includes an input pin of the first switch chip and an input pin of the second switch chip; the input pin of the first switch chip and the input pin of the second switch chip at the input end of the switch chip are connected one-to-one to two bandwidth allocation signal lines of the corresponding root port; the first switch chip and the second switch chip multiplex the selection signal.

13. The bandwidth allocation module according to claim 12, characterized in that: The platform controller center includes an enable signal terminal for writing an enable signal to the switch chip; the first switch chip and the second switch chip are connected to the same enable signal terminal.

14. The bandwidth allocation module according to claim 13, characterized in that: The bandwidth allocation module includes a four-way processor bandwidth allocation unit, and the four-way processor bandwidth allocation unit includes two dual-way processor bandwidth allocation units, namely a first dual-way processor bandwidth allocation unit and a second dual-way processor bandwidth allocation unit; the first dual-way processor bandwidth allocation unit and the second dual-way processor bandwidth allocation unit are connected to different enable signal terminals; the first dual-way processor bandwidth allocation unit and the second dual-way processor bandwidth allocation unit multiplex the selection signal.

15. The bandwidth allocation module according to claim 13, characterized in that: The bandwidth allocation module includes a four-way processor bandwidth allocation unit, and the four-way processor bandwidth allocation unit includes two dual-way processor bandwidth allocation units, namely a first dual-way processor bandwidth allocation unit and a second dual-way processor bandwidth allocation unit; the first dual-way processor bandwidth allocation unit is connected to the enable signal end of the platform controller center; the second dual-way processor bandwidth allocation unit is connected to the enable signal end connected to the first dual-way processor bandwidth allocation unit through an inverter; the first dual-way processor bandwidth allocation unit and the second dual-way processor bandwidth allocation unit multiplex the selection signal.

16. The bandwidth allocation module according to claim 13, characterized in that: The bandwidth allocation module comprises i four-way processor bandwidth allocation units; different four-way processor bandwidth allocation units are connected to different enable signal terminals; different four-way processor bandwidth allocation units multiplex the selection signal; Wherein, i is a positive integer greater than 1.

17. A server, characterized in that: Comprising a bandwidth allocation module as described in any one of claims 7 to 16.

18. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the bandwidth allocation method according to any one of claims 1 to 6 when executing the computer program.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the bandwidth allocation method according to any one of claims 1 to 6.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the bandwidth allocation method according to any one of claims 1 to 6 are implemented.

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