Inter-core synchronization system and method

Abstract

The invention relates to the technical field of synchronous communication, in particular to an inter-core synchronization system and method.The system comprises a plurality of processor cores, and each processor core is correspondingly provided with a synchronous processing module and a synchronous router module; the synchronous processing module is used for receiving and processing a synchronous instruction sent by the corresponding processor core, and is also used for receiving or generating synchronous hand raising information and hand raising completion notification information based on the synchronous instruction; the synchronization instruction is used for carrying synchronization information among the plurality of processor cores; and the synchronous router module is used for receiving and routing the synchronous hand raising information and the hand raising completion notification information sent by the synchronous processing module, and sending the received synchronous hand raising information and the hand raising completion notification information to a target processor core. The synchronous network based on the synchronous processing module and the synchronous routing module is utilized to realize synchronization among a plurality of cores, and the synchronization requirements of a plurality of processor cores are met.

Description

Technical Field

[0001] The present invention relates to the field of synchronous communication technology, and in particular to an inter-core synchronization system and method. Background Art

[0002] With the development of integrated circuit technology and the increasing demand for chip performance, the number of processor cores in a chip has increased from single core to multi-core or many-core. Each core in a chip can perform tasks independently or together. If multiple cores in a chip perform a task together, each core has its own information and shared information, so synchronous communication is required between the cores. Otherwise, if a core modifies the information, the same data may be seen differently from the perspective of different cores, causing consistency issues.

[0003] However, different cores in a multi-processing core system may perform different tasks, or all cores may perform the same task together, or some cores may perform the same task while the remaining cores perform other tasks. Therefore, not all cores in a chip need to be synchronized at the same time, and different cores may perform different synchronizations at the same time. Therefore, an efficient inter-core synchronization mechanism is very important in a multi-core system. At present, the synchronization system of the prior art (such as the patent "CN112052099A") only synchronizes the cores within the synchronization range, and the synchronization process is controlled by only one synchronization control unit, which can meet the synchronization requirements of multiple cores of the chip when there are relatively few processing cores. However, when the number of cores in the chip is large, such as dozens or even hundreds, if different cores need to perform different synchronizations, there may be dozens of different synchronizations in the chip at the same time, and the synchronization requirements cannot be met by controlling only one synchronization control unit. Summary of the invention

[0004] In view of this, the present invention provides an inter-core synchronization system and method to solve the problem that the existing solution cannot meet the synchronization requirements by relying on only one synchronization control unit for control.

[0005] In a first aspect, the present invention provides an inter-core synchronization system, the system comprising:

[0006] Multiple processor cores, each processor core is correspondingly equipped with a synchronous processing module and a synchronous router module;

[0007] The synchronization processing module is used to receive and process the synchronization instruction issued by the corresponding processor core, and is also used to receive or generate synchronization hand-raising information and hand-raising completion notification information based on the synchronization instruction; the synchronization instruction is used to carry the synchronization information between the multiple processor cores;

[0008] The synchronous router module is used to receive and route the synchronous hand-raising information and the hand-raising completion notification information sent by the synchronous processing module, and send the received synchronous hand-raising information and the hand-raising completion notification information to the target processor core.

[0009] In an optional implementation, the multiple processor cores are arranged in rows and columns, and each processor core is respectively connected to the synchronization processing module and the synchronization router module corresponding to the processor core to form a synchronization network;

[0010] The ID address of the synchronization processing module and the ID address of the synchronization router module connected to the same processor core are the same, and are both the row and column numbers of the corresponding processor core in the synchronization network.

[0011] In an optional implementation, the synchronization instruction includes a synchronization mechanism instruction, and the synchronization mechanism instruction includes a blocking synchronization instruction and a non-blocking synchronization instruction;

[0012] The blocking synchronization instruction is used to instruct the corresponding processor core to suspend the execution of other instructions when executing the current synchronization instruction until the processor core receives the current synchronization end notification issued by the corresponding synchronization processing module;

[0013] The non-blocking synchronization instruction is used to instruct the corresponding processor core to execute subsequent instructions while executing the current synchronization instruction.

[0014] In an optional implementation, the synchronization instruction includes a synchronization mode instruction, and the synchronization mode instruction includes a row synchronization instruction, a column synchronization instruction, and a point-to-point synchronization instruction;

[0015] The row synchronization instruction is used to instruct the corresponding processor core to perform synchronization operation on the processor cores of the target row in the synchronization network when executing the current synchronization instruction;

[0016] The column synchronization instruction is used to instruct the corresponding processor core to synchronize the processor cores of the target column in the synchronization network when executing the current synchronization instruction;

[0017] The point-to-point synchronization instruction is used to instruct the corresponding processor core to synchronize the first target processor core and the second target processor core in the synchronization network when executing the current synchronization instruction.

[0018] In an optional implementation, the synchronization instruction includes a synchronization range instruction, and the synchronization range instruction is used to instruct all processor cores participating in this synchronization to perform a synchronization operation.

[0019] In an optional implementation, the processor cores participating in synchronization among the multiple processor cores are divided into synchronization representatives and synchronization participants;

[0020] The synchronization representative is used to receive the synchronization hand-raising request sent by the synchronization participants in this synchronization, and send a hand-raising completion notification to the corresponding synchronization participants after receiving all the synchronization hand-raising requests;

[0021] The synchronization participant is used to send a synchronization hand-raising request to the synchronization representative based on the synchronization instruction of this synchronization, and wait to receive a hand-raising completion notification issued by the synchronization representative after sending the synchronization hand-raising request.

[0022] In a second aspect, the present invention provides an inter-core synchronization method, the method is applied to an inter-core synchronization system as described above, the method comprising:

[0023] Receiving and processing the synchronization instruction issued by the processor core through the synchronization processing module corresponding to the processor core, and receiving or generating the synchronization hand raising information and the hand raising completion notification information based on the synchronization instruction;

[0024] The synchronous router module corresponding to the processor core receives and routes the synchronous hand-raising information and the hand-raising completion notification information issued by the synchronous processing module, and sends the received synchronous hand-raising information and the hand-raising completion notification information to the target processor core to complete the inter-core synchronization of the inter-core synchronization system.

[0025] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to thereby execute an inter-core synchronization method of the first aspect or any corresponding embodiment thereof.

[0026] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute an inter-core synchronization method according to the first aspect or any corresponding embodiment thereof.

[0027] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute an inter-core synchronization method according to the first aspect or any corresponding embodiment thereof.

[0028] The technical solution provided by the present invention may include the following beneficial effects:

[0029] The present invention proposes an inter-core synchronization mechanism based on non-blocking and blocking synchronization instructions, and uses a synchronization network based on a synchronization processing module and a synchronization routing module to achieve synchronization between multiple cores. In the synchronization network, the synchronization processing module and the synchronization routing module are two independent modules, which are responsible for different synchronization functions respectively. Similarly, the synchronization processing module and the synchronization routing module can be merged into one synchronization module to achieve synchronization processing and synchronization routing functions at the same time. The synchronization mechanism proposed by the present invention supports blocking synchronization and non-blocking synchronization, and the synchronization mode supports row synchronization, column synchronization and point-to-point synchronization. The synchronization mechanism and synchronization mode can be optionally partially or fully supported. The present invention significantly improves the efficiency and flexibility of synchronization operations in a multi-core processor system, allowing the core to continue to execute other instructions while executing synchronization instructions, thereby reducing waiting time and improving the parallelism and overall performance of the system. At the same time, by equipping each core with a synchronization processing module and supporting multiple synchronization modes, the mechanism also meets the flexibility requirements under different application scenarios and synchronization requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 is a schematic diagram of the structure of an inter-core synchronization system according to an embodiment of the present invention;

[0032] Figure 2 is a flow chart of an inter-core synchronization method according to an embodiment of the present invention;

[0033] Figure 3 is a schematic diagram of a synchronous hand-raising process of inter-core blocking synchronization according to an embodiment of the present invention;

[0034] Figure 4 is a schematic diagram of a hand-raising completion notification process for inter-core blocking synchronization according to an embodiment of the present invention;

[0035] Figure 5 is a schematic diagram of a non-blocking and synchronous hand-raising completion notification process between cores according to an embodiment of the present invention;

[0036] Figure 6 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0038] In this embodiment, a core synchronization system is provided. Figure 1 is a schematic diagram of the structure of an inter-core synchronization system according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0039] The system includes:

[0040] Multiple processor cores, each processor core is correspondingly equipped with a synchronous processing module and a synchronous router module;

[0041] The synchronization processing module is used to receive and process the synchronization instruction issued by the corresponding processor core, and is also used to receive or generate synchronization hand-raising information and hand-raising completion notification information based on the synchronization instruction; the synchronization instruction is used to carry the synchronization information between the multiple processor cores;

[0042] The synchronous router module is used to receive and route the synchronous hand-raising information and the hand-raising completion notification information sent by the synchronous processing module, and send the received synchronous hand-raising information and the hand-raising completion notification information to the target processor core. The target processor core can be a local processor core.

[0043] Furthermore, the multiple processor cores are the basic computing units of the system, and each core can perform tasks independently or in collaboration with other cores. Each processor core is equipped with a synchronization processing module, which is responsible for processing operations related to synchronization. Similarly, each processor core is equipped with a synchronization router module, which is responsible for routing and transmitting synchronization information. The synchronization processing module receives synchronization instructions from the processor core, which contain all the information required for the synchronization operation, such as synchronization type, range, etc. According to the received synchronization instructions, the synchronization processing module performs the corresponding synchronization operation. Based on the synchronization instructions, the synchronization processing module can generate synchronization hand-raising information (indicating that the core is ready for synchronization) and hand-raising completion notification information (indicating that the synchronization operation has been completed).

[0044] The synchronization router module receives the synchronization hand-raising information and hand-raising completion notification information from the synchronization processing module, and correctly routes the synchronization hand-raising information and hand-raising completion notification information to the target processor core according to the routing information in the synchronization information (such as the target core ID). The synchronization hand-raising information and hand-raising completion notification information generated by the synchronization processing module are passed to the target core through the synchronization router module. The synchronization router module ensures that these information can accurately reach the specified target core to complete the synchronization operation. After the synchronization processing module of the target core receives the synchronization hand-raising information, it will perform the corresponding synchronization operation according to the synchronization instruction. Once the synchronization operation is completed, the synchronization processing module will generate a hand-raising completion notification message and send it to all cores participating in the synchronization through the synchronization router module to notify them that the synchronization is complete.

[0045] In an optional implementation, the multiple processor cores are arranged in rows and columns, and each processor core is respectively connected to the synchronization processing module and the synchronization router module corresponding to the processor core to form a synchronization network;

[0046] The ID address of the synchronization processing module and the ID address of the synchronization router module connected to the same processor core are the same, and are both the row and column numbers of the corresponding processor core in the synchronization network.

[0047] Further, such as Figure 1 As shown, in order to implement the synchronization mechanism proposed in this embodiment, multiple processor cores, a synchronization processing module for each processor core, a synchronization router module for each processor core, and synchronization instructions are required. The synchronization processing module is responsible for receiving and processing the synchronization instructions of the processor core, receiving or generating synchronization hand-raising information and hand-raising completion notification information. The synchronization router module is responsible for receiving and routing synchronization hand-raising information and hand-raising completion notification information, and sending the received synchronization hand-raising information and hand-raising completion notification information to the local processor core. The synchronization instruction is used to carry synchronization information between cores. As shown in FIG. Figure 1 As shown, assuming that the processor cores are arranged in m+1 rows and n+1 columns, the row and column numbers of each processor core are named as the addresses of the processor cores. For example, the processor core address id is xy (where x is the row number and 0≤x≤m, y is the column number and 0≤y≤n), and the synchronous processing module and synchronous routing module connected to the processor core address all use this processor core id address. Synchronous processing module and synchronous routing module composition Figure 1 The synchronization network shown in Figure 1 implements inter-core synchronization.

[0048] In an optional implementation, the synchronization instruction includes a synchronization mechanism instruction, and the synchronization mechanism instruction includes a blocking synchronization instruction and a non-blocking synchronization instruction;

[0049] The blocking synchronization instruction is used to instruct the corresponding processor core to suspend the execution of other instructions when executing this synchronization instruction until the processor core receives the synchronization end notification issued by the corresponding synchronization processing module; not only the synchronization instruction, but also when executing the blocking synchronization instruction, the processor core cannot execute all other instructions until the synchronization instruction is executed, that is, the processor receives the synchronization end notification issued by the corresponding synchronization processing module;

[0050] The non-blocking synchronization instruction is used to instruct the corresponding processor core to execute subsequent instructions when executing this synchronization instruction. The subsequent instruction is not necessarily a synchronization instruction. The concept of a blocking synchronization instruction is that when the processor core executes the blocking synchronization instruction, the processor pipeline is paused and no other instructions can be executed until the blocking synchronization instruction is executed and the pipeline can continue. The concept of a non-blocking instruction is that when the processor core executes the non-blocking synchronization instruction, it will not affect the pipeline and the processor core can execute subsequent instructions.

[0051] Furthermore, in order to achieve synchronization between cores, this embodiment defines a synchronization instruction specifically for executing synchronization between cores, and sends the synchronization instruction to the synchronization processing module for synchronization processing. The synchronization instruction carries synchronization-related information, including the synchronization mechanism, synchronization mode and synchronization range of this synchronization. Among them, the synchronization mechanism is whether this synchronization is blocking synchronization or non-blocking synchronization, the synchronization mode is the synchronization type of this synchronization, and the synchronization type includes a row of core synchronization, a column of core synchronization or synchronization between any two cores, and the synchronization range refers to which processor cores participate in this synchronization. The synchronization instruction is classified into blocking synchronization instructions and non-blocking synchronization instructions according to the synchronization mechanism. Among them, the blocking synchronization instruction means that the pipeline will pause when the processor core executes the synchronization instruction, and stop executing the subsequent instructions of the synchronization instruction until the synchronization ends, that is, the synchronization instruction is executed. The non-blocking synchronization instruction means that the pipeline will not pause when the processor core executes the instruction, and the synchronization instruction and other instructions can be executed together. When the synchronization instruction is sent to the synchronization processing module, it is considered that the instruction is executed.

[0052] In an optional implementation, the synchronization instruction includes a synchronization mode instruction, and the synchronization mode instruction includes a row synchronization instruction, a column synchronization instruction, and a point-to-point synchronization instruction;

[0053] The row synchronization instruction is used to instruct the corresponding processor core to perform synchronization operations on the processor cores of the target row in the synchronization network when executing this synchronization instruction;

[0054] The column synchronization instruction is used to instruct the corresponding processor core to perform synchronization operations on the processor cores of the target column in the synchronization network when executing the current synchronization instruction;

[0055] The point-to-point synchronization instruction is used to instruct the corresponding processor core to perform synchronization operations with the first target processor core and the second target processor core in the synchronization network when executing the current synchronization instruction.

[0056] Furthermore, the inter-core synchronization instructions are divided into row synchronization instructions, column synchronization instructions and point-to-point synchronization instructions according to the synchronization mode. The row synchronization instruction refers to an instruction to synchronize a row of cores in the synchronization network (it can be any number of cores in the row), the column synchronization instruction refers to an instruction to synchronize a column of cores in the synchronization network (it can be any number of cores in the column), and the point-to-point synchronization instruction refers to an instruction to synchronize any two cores in the synchronization network.

[0057] In an optional implementation, the synchronization instruction includes a synchronization range instruction, and the synchronization range instruction is used to instruct all processor cores participating in this synchronization to perform a synchronization operation.

[0058] Furthermore, the inter-core synchronization range is which processor cores need to be synchronized for this synchronization, and the range is given by the synchronization instruction. The row synchronization range is which processor cores in the row of processor cores in the synchronization network are synchronized. The column synchronization range is which processor cores in the column of processor cores in the synchronization network are synchronized. The point-to-point synchronization range is which two processor cores in the synchronization network are synchronized.

[0059] In an optional implementation, the processor cores participating in synchronization among the multiple processor cores are divided into synchronization representatives and synchronization participants;

[0060] The synchronization representative is used to receive the synchronization hand-raising request sent by the synchronization participant in this synchronization, and send a hand-raising completion notification to the corresponding synchronization participant after receiving all the synchronization hand-raising requests;

[0061] The synchronization participant is used to send a synchronization hand-raising request to the synchronization representative based on the synchronization instruction of this synchronization, and wait for the hand-raising completion notification issued by the synchronization representative after sending the synchronization hand-raising request. The synchronization instructions are all issued by the processor core. The synchronization participant receives the synchronization instruction sent by the core. After the hit judgment logic finds that it is not the synchronization representative, it will send a synchronization hand-raising request to the synchronization representative and wait for the hand-raising completion notification issued by the synchronization representative.

[0062] Furthermore, according to the synchronization instructions of different synchronization mechanisms, the processor cores in the synchronization network can perform synchronization of two mechanisms: blocking synchronization and non-blocking synchronization. Blocking synchronization means that the processor core has only received a blocking synchronization instruction, which is handled by the synchronization processing module. At this time, the processor core suspends the execution of subsequent instructions until the synchronization processing module notifies the processor core that the synchronization is over. The processor core can continue to execute subsequent instructions. Non-blocking synchronization means that the processor core first receives a non-blocking synchronization instruction, which is handled by the synchronization processing module. At this time, the processor core assumes that the execution of this instruction has been completed and can execute subsequent instructions, but the synchronization is not over. The processor core needs to wait for another blocking synchronization instruction. If the synchronization processing module of the processor core has completed the synchronization process of the non-blocking instruction and received the blocking synchronization instruction, the synchronization processing module notifies the processor core that the synchronization is over. In order to achieve synchronization between cores, this embodiment divides the processor cores participating in the synchronization into synchronization representatives and synchronization participants. The synchronization representative is the processor core responsible for receiving the synchronization hand-raising request from other cores in this synchronization, and determines whether all cores in the synchronization range have sent the synchronization hand-raising request for this synchronization. After receiving all the synchronization hand-raising requests, it sends a hand-raising completion notification to the other processor cores participating in the synchronization. The synchronization participant is the processor core that receives the synchronization instruction and sends a synchronization hand-raising request to the synchronization representative. After sending the synchronization hand-raising request, it waits to receive the hand-raising completion notification from the synchronization representative.

[0063] In summary, this embodiment proposes a core-to-core synchronization mechanism based on non-blocking and blocking synchronization instructions, and uses a synchronization network based on a synchronization processing module and a synchronization routing module to achieve synchronization between multiple cores. In the synchronization network, the synchronization processing module and the synchronization routing module are two independent modules, which are responsible for different synchronization functions respectively. Similarly, the synchronization processing module and the synchronization routing module can be merged into one synchronization module to simultaneously realize the synchronization processing and synchronization routing functions. The synchronization mechanism proposed in this embodiment supports blocking synchronization and non-blocking synchronization, and the synchronization mode supports row synchronization, column synchronization and point-to-point synchronization. The synchronization mechanism and synchronization mode can be partially or fully supported. This embodiment significantly improves the efficiency and flexibility of synchronization operations in a multi-core processor system, allowing the core to continue to execute other instructions while executing synchronization instructions, thereby reducing waiting time and improving the parallelism and overall performance of the system. At the same time, by equipping each core with a synchronization processing module and supporting multiple synchronization modes, the mechanism also meets the flexibility requirements under different application scenarios and synchronization requirements.

[0064] According to an embodiment of the present invention, an embodiment of an inter-core synchronization method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0065] In this embodiment, a method for synchronizing cores is provided. Figure 1 In an inter-core synchronization system shown, Figure 2 is a flow chart of an inter-core synchronization method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0066] Step S201, receiving and processing a synchronization instruction issued by the processor core through a synchronization processing module corresponding to the processor core, and receiving or generating synchronization hand raising information and hand raising completion notification information based on the synchronization instruction.

[0067] Furthermore, each processor core has a corresponding synchronization processing module. When the processor core has a synchronization requirement, it will issue a synchronization instruction. The synchronization processing module first receives the synchronization instruction from the processor core to which it belongs. This synchronization instruction includes the synchronization mechanism, synchronization mode, and synchronization range. After receiving the instruction, the synchronization processing module will parse and process it. It determines the role of this core in the synchronization process (synchronization participant or synchronization representative) and the operations to be performed based on the information in the instruction. For example, if it is a synchronization participant, it is necessary to prepare to send synchronous hand-raising information; if it is a synchronization representative, it is necessary to prepare to receive hand-raising information from other cores and perform statistical judgment. Based on the synchronization instruction, the synchronous hand-raising information and hand-raising completion notification information are received or generated. If the processor core is determined to be a synchronization participant after processing the synchronization instruction, the synchronization processing module will generate synchronous hand-raising information based on the information in the instruction. This hand-raising information indicates that the core is ready to participate in the synchronization process, including the routing information type (indicating that this is a hand-raising request), synchronization mode (indicating the type of this synchronization), source core information (i.e. the identification of the core that issued this hand-raising information) and target core information (which can indicate the routing object of the router module), etc., so that it can be correctly transmitted and processed in the subsequent routing process. When the core where the synchronization processing module is located is a synchronization representative, it will generate a hand-raising completion notification message after receiving the synchronization hand-raising information of other synchronization participants and judging that all cores that need to participate in synchronization have raised their hands (i.e., all synchronization hand-raising requests have been collected). This notification message contains similar routing-related information, which is used to inform synchronization participants that the synchronization preparation phase has been completed, and they can continue with subsequent synchronization-related operations, such as starting data sharing or executing the tasks of the next synchronization point.

[0068] Step S202, receiving and routing the synchronous hand-raising information and the hand-raising completion notification information sent by the synchronous processing module through the synchronous router module corresponding to the processor core, and sending the received synchronous hand-raising information and the hand-raising completion notification information to the target processor core to complete the inter-core synchronization of the inter-core synchronization system.

[0069] Furthermore, the synchronous router module closely cooperates with the synchronous processing module. The synchronous router module receives the synchronous hand-raising information and the hand-raising completion notification information from the synchronous processing module. The synchronous hand-raising information is sent from the synchronous processing module of the synchronous participant, while the hand-raising completion notification information is generated from the synchronous processing module of the synchronous representative. The synchronous router module determines the routing path according to the target core information in the information. For example, if it is a synchronous hand-raising information, the target core is the synchronous representative, and the synchronous router module will route the hand-raising information in the direction of the synchronous representative according to the connection relationship of the cores in the system (such as the connection between the cores arranged in rows and columns). If it is a hand-raising completion notification information, the target core is the synchronous participant, and it will send the notification information along the corresponding path to each synchronous participant. The synchronous router module accurately sends the synchronous hand-raising information to the processor core of the synchronous representative, so that the synchronous representative can collect the hand-raising requests of all synchronous participants, thereby judging whether the synchronization can enter the next step. When the synchronous representative generates the hand-raising completion notification information, the synchronous router module sends this notification information to the processor core of each synchronous participant. After receiving this notification, the synchronization processing module of the synchronization participant knows that the entire synchronization preparation has been completed, and the entire inter-core synchronization system can perform subsequent operations according to the predetermined synchronization mode (row synchronization, column synchronization or point-to-point synchronization). For example, in row synchronization, the cores of the row can start data exchange or jointly execute the next task stage, thereby realizing the synchronization between cores. This process ensures the accurate transmission of synchronization information between different cores and is the key link in realizing the entire inter-core synchronization mechanism.

[0070] In an optional implementation, the synchronization process of the inter-core synchronization includes a synchronous hand-raising process and a hand-raising completion notification process;

[0071] The hand-raising process is a process in which a synchronous participant sends a synchronous hand-raising request to a synchronous representative, and the hand-raising completion notification process is a process in which the synchronous representative sends a hand-raising completion notification to the synchronous participant after receiving all the synchronous hand-raising requests.

[0072] Furthermore, in order to achieve synchronization between cores, this embodiment divides the synchronization process into a synchronous hand-raising process and a hand-raising completion notification process. The hand-raising process is a process in which a synchronous participant sends a synchronous hand-raising request to a synchronous representative, and the hand-raising completion notification process is a process in which a synchronous representative sends a hand-raising completion notification to a synchronous participant after receiving all synchronous hand-raising requests. These two processes require the participation of a synchronous processing module and a synchronous routing module. The synchronous processing module is responsible for receiving and processing synchronization instructions, and generating or receiving synchronous hand-raising requests or hand-raising completion notifications. The synchronous routing module is responsible for routing the synchronous hand-raising request or hand-raising completion notification to the target core, the target core of the synchronous hand-raising request is the synchronous representative, and the target core of the hand-raising completion notification is the synchronous participant. In order to realize the routing function of the synchronous routing module, the synchronous hand-raising request and the hand-raising completion notification need to include routing information type, synchronization mode, source core information, target core information, and verification information and other information if necessary. The routing information type indicates whether the information to be routed is a hand-raising request or a notification request, the synchronization mode indicates which synchronization mode is used, the source core information indicates which core the request is sent from, the target core information indicates which core or cores the request needs to be sent to, and the verification information can check whether there is any data error in this request.

[0073] In an optional implementation, when the synchronization instruction is a blocking synchronization instruction, the synchronous hand raising process includes:

[0074] The blocking synchronization instruction issued by the processor core is received by the synchronization processing module corresponding to the processor core, and when it is determined that the processor core is a synchronization participant, a synchronization hand raising request is generated, and the request is routed to the synchronization representative by the synchronization routing module corresponding to the processor core;

[0075] The hand-raising completion notification process includes:

[0076] The blocking synchronization instruction issued by the processor core is received by the synchronization processing module corresponding to the processor core. When it is determined that the processor core is a synchronization representative, the synchronization information is recorded, and a hand-raising completion notification is generated after collecting all the synchronous hand-raising requests. The notification is routed to the synchronization participant through the synchronization routing module corresponding to the processor core; after receiving the hand-raising completion notification, the synchronization participant determines that the synchronization is completed.

[0077] For further information, see Figure 3The schematic diagram of the synchronous hand-raising process of blocking synchronization between cores is shown, and the synchronous participant hand-raising process is as follows: (1) The synchronous processing module of the processor core receives the blocking synchronization instruction and determines that the core is a synchronous participant; (2) Based on the information of the received synchronization instruction, a synchronous hand-raising request is generated, and the synchronous hand-raising request is sent to the synchronous routing module of the core; (3) The routing module of the processor core routes the synchronous hand-raising request to the next synchronous routing module according to the target core information in the synchronous hand-raising request; (4) The synchronous routing module receives the synchronous hand-raising request sent by other routing modules, and determines whether the target core is the current core. If not, the synchronous hand-raising request is sent to the next routing module. If it is determined that the target processor core is the current processor core, the synchronous hand-raising request is sent to the synchronous processing module.

[0078] See also Figure 4 The schematic diagram of the hand-raising completion notification process of inter-core blocking synchronization is shown. The inter-core blocking synchronization and synchronization representative hand-raising completion notification process is as follows: (1) The synchronization processing module of the processor core receives the blocking synchronization instruction, determines that the processor core is the synchronization representative, records the synchronization information of the instruction in the synchronization processing module, and waits to collect the synchronization hand-raising requests of the remaining synchronization participants; (2) After receiving the synchronization hand-raising request of the synchronization participant, synchronization statistics are performed according to the synchronization mode to determine whether all the synchronization hand-raising requests have been collected; (3) If the synchronization hand-raising requests of all cores in the synchronization range have been collected, the synchronization representative generates a hand-raising completion notification message. At this time, the synchronization representative of this synchronization End; (4) Send the hand-raising completion notification request to the synchronization routing module of this processor core, and the routing module routes the synchronization notification request to the next synchronization routing module according to the target core information in the synchronization notification request; (5) The synchronization routing module receives the synchronization notification request sent by other routing modules, and determines whether the target processor core is the current processor core. If it is not the current processor core, the synchronization notification request is sent to the next routing module. If it is determined that the target processor core is the current core, the synchronization notification request is sent to the synchronization processing module; (6) The processor core synchronization processing module receives the hand-raising completion notification and this synchronization ends.

[0079] In an optional implementation, when the synchronization instruction is a non-blocking synchronization instruction, the synchronous hand-raising process includes:

[0080] The non-blocking synchronization instruction issued by the processor core is received by the synchronization processing module corresponding to the processor core, and when it is determined that the processor core is a synchronization participant, a synchronization hand-raising request is generated, and the request is routed to the synchronization representative by the synchronization routing module corresponding to the processor core;

[0081] The hand-raising completion notification process includes:

[0082] The non-blocking synchronization instruction issued by the processor core is received by the synchronization processing module corresponding to the processor core. When it is determined that the processor core is a synchronization representative, the synchronization information is recorded, and a hand-raising completion notification is generated after collecting all the synchronous hand-raising requests. The notification is routed to the synchronization participant through the synchronization routing module corresponding to the processor core. After the synchronization participant receives the hand-raising completion notification, if a blocking synchronization instruction is received, it is determined that the synchronization is completed.

[0083] Furthermore, the synchronous hand-raising process of non-blocking synchronization between cores is consistent with that of blocking synchronization between cores. The synchronous hand-raising process of non-blocking synchronization between cores is as follows: (1) The synchronous processing module of the core receives the non-blocking synchronization instruction and determines that the core is a synchronous participant; (2) Based on the information of the received synchronization instruction, a synchronous hand-raising request is generated and the synchronous hand-raising request is sent to the synchronous routing module of the core; (3) The core routing module routes the synchronous hand-raising request to the next synchronous routing module based on the target core information in the synchronous hand-raising request; (4) The synchronous routing module receives the synchronous hand-raising request sent by other routing modules and determines whether the target core is the current core. If not, the synchronous hand-raising request is sent to the next routing module. If it is determined that the target core is the current core, the synchronous hand-raising request is sent to the synchronous processing module. Please refer to Figure 5 The schematic diagram of the inter-core non-blocking synchronous hand-raising completion notification process is shown. The inter-core non-blocking synchronization and synchronization representative hand-raising completion notification process are as follows: (1) The core's synchronization processing module receives a non-blocking synchronization instruction, determines that the core is a synchronization representative, and records the synchronization information of the instruction in the synchronization processing module, waiting to collect the synchronization hand-raising requests of the remaining synchronization participants; (2) Upon receiving the synchronization hand-raising requests of the synchronization participants, synchronization statistics are performed according to the synchronization mode to determine whether all the synchronization hand-raising requests have been collected; (3) If all the synchronization hand-raising requests of the cores in the synchronization range have been collected, the synchronization representative generates a hand-raising completion notification message, but at this time, whether the synchronization of the synchronization representative is completed depends on whether the blocking instruction of this synchronization has been received. If it has been received, the synchronization is completed at this time. If it has not been received, the synchronization is not completed, and the synchronization representative is waiting to receive the blocking instruction. step instruction; (4) send the hand-raising completion notification request to the synchronization routing module of this core, and the routing module routes the synchronization notification request to the next synchronization routing module according to the target core information in the synchronization notification request; (5) the synchronization routing module receives the synchronization notification request sent by other routing modules, and determines whether the target core is this core. If not, the synchronization notification request is sent to the next routing module. If it is determined that the target core is this core, the synchronization notification request is sent to the synchronization processing module; (6) the core synchronization processing module receives the hand-raising completion notification, indicating that this synchronization hand-raising has been completed. Whether this synchronization is completed depends on whether the blocking instruction of this synchronization has been received. If it has been received, the synchronization is completed at this time. If not, the synchronization is not completed and waiting for the reception of the blocking synchronization instruction.

[0084] In summary, this embodiment proposes a core-to-core synchronization mechanism based on non-blocking and blocking synchronization instructions, and uses a synchronization network based on a synchronization processing module and a synchronization routing module to achieve synchronization between multiple cores. In the synchronization network, the synchronization processing module and the synchronization routing module are two independent modules, which are responsible for different synchronization functions respectively. Similarly, the synchronization processing module and the synchronization routing module can be merged into one synchronization module to simultaneously realize the synchronization processing and synchronization routing functions. The synchronization mechanism proposed in this embodiment supports blocking synchronization and non-blocking synchronization, and the synchronization mode supports row synchronization, column synchronization and point-to-point synchronization. The synchronization mechanism and synchronization mode can be partially or fully supported. This embodiment significantly improves the efficiency and flexibility of synchronization operations in a multi-core processor system, allowing the core to continue to execute other instructions while executing synchronization instructions, thereby reducing waiting time and improving the parallelism and overall performance of the system. At the same time, by equipping each core with a synchronization processing module and supporting multiple synchronization modes, the mechanism also meets the flexibility requirements under different application scenarios and synchronization requirements.

[0085] The embodiment of the present invention also provides a computer device, see Figure 6 , Figure 6 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 6 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor 10 is taken as an example.

[0086] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0087] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0088] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0089] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0090] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0091] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0092] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0093] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the defined scope.

Claims

1. An inter-core synchronization system, characterized in that: The system comprises: Multiple processor cores, each processor core is correspondingly equipped with a synchronous processing module and a synchronous router module; The synchronization processing module is used to receive and process the synchronization instruction issued by the corresponding processor core, and is also used to receive or generate synchronization hand-raising information and hand-raising completion notification information based on the synchronization instruction; the synchronization instruction is used to carry the synchronization information between the multiple processor cores; The synchronous router module is used to receive and route the synchronous hand-raising information and the hand-raising completion notification information sent by the synchronous processing module, and send the received synchronous hand-raising information and the hand-raising completion notification information to the target processor core.

2. The system according to claim 1, characterized in that The multiple processor cores are arranged in rows and columns, and each processor core is respectively connected to the synchronization processing module and the synchronization router module corresponding to the processor core to form a synchronization network; The ID address of the synchronization processing module and the ID address of the synchronization router module connected to the same processor core are the same, and are both the row and column numbers of the corresponding processor core in the synchronization network.

3. The system according to claim 1, characterized in that The synchronization instructions include synchronization mechanism instructions, and the synchronization mechanism instructions include blocking synchronization instructions and non-blocking synchronization instructions; The blocking synchronization instruction is used to instruct the corresponding processor core to suspend the execution of other instructions when executing the current synchronization instruction until the processor core receives the current synchronization end notification issued by the corresponding synchronization processing module; The non-blocking synchronization instruction is used to instruct the corresponding processor core to execute subsequent instructions while executing the current synchronization instruction.

4. The system according to claim 2, characterized in that The synchronization instructions include synchronization mode instructions, and the synchronization mode instructions include row synchronization instructions, column synchronization instructions and point-to-point synchronization instructions; The row synchronization instruction is used to instruct the corresponding processor core to perform synchronization operation on the processor cores of the target row in the synchronization network when executing the current synchronization instruction; The column synchronization instruction is used to instruct the corresponding processor core to synchronize the processor cores of the target column in the synchronization network when executing the current synchronization instruction; The point-to-point synchronization instruction is used to instruct the corresponding processor core to synchronize the first target processor core and the second target processor core in the synchronization network when executing the current synchronization instruction.

5. The system according to claim 1, characterized in that The synchronization instruction includes a synchronization range instruction, and the synchronization range instruction is used to instruct all processor cores participating in this synchronization to perform a synchronization operation.

6. The system according to claim 1, characterized in that The processor cores participating in synchronization among the plurality of processor cores are divided into synchronization representatives and synchronization participants; The synchronization representative is used to receive the synchronization hand-raising request sent by the synchronization participants in this synchronization, and send a hand-raising completion notification to the corresponding synchronization participants after receiving all the synchronization hand-raising requests; The synchronization participant is used to send a synchronization hand-raising request to the synchronization representative based on the synchronization instruction of this synchronization, and wait to receive a hand-raising completion notification issued by the synchronization representative after sending the synchronization hand-raising request.

7. A method for synchronizing cores, characterized in that: The method is applied to an inter-core synchronization system according to any one of claims 1 to 6, and the method comprises: Receiving and processing the synchronization instruction issued by the processor core through the synchronization processing module corresponding to the processor core, and receiving or generating the synchronization hand raising information and the hand raising completion notification information based on the synchronization instruction; The synchronous router module corresponding to the processor core receives and routes the synchronous hand-raising information and the hand-raising completion notification information issued by the synchronous processing module, and sends the received synchronous hand-raising information and the hand-raising completion notification information to the target processor core to complete the inter-core synchronization of the inter-core synchronization system.

8. The method according to claim 7, characterized in that The synchronization process of the inter-core synchronization includes a synchronous hand-raising process and a hand-raising completion notification process; The hand-raising process is a process in which a synchronous participant sends a synchronous hand-raising request to a synchronous representative, and the hand-raising completion notification process is a process in which the synchronous representative sends a hand-raising completion notification to the synchronous participant after receiving all the synchronous hand-raising requests.

9. The method according to claim 7, characterized in that: When the synchronization instruction is a blocking synchronization instruction, the synchronous hand raising process includes: The blocking synchronization instruction issued by the processor core is received by the synchronization processing module corresponding to the processor core, and when it is determined that the processor core is a synchronization participant, a synchronization hand raising request is generated, and the request is routed to the synchronization representative by the synchronization routing module corresponding to the processor core; The hand-raising completion notification process includes: The blocking synchronization instruction issued by the processor core is received by the synchronization processing module corresponding to the processor core. When it is determined that the processor core is a synchronization representative, the synchronization information is recorded, and a hand-raising completion notification is generated after collecting all the synchronous hand-raising requests. The notification is routed to the synchronization participant through the synchronization routing module corresponding to the processor core; after receiving the hand-raising completion notification, the synchronization participant determines that the synchronization is completed.

10. The method according to claim 7, characterized in that When the synchronization instruction is a non-blocking synchronization instruction, the synchronous hand raising process includes: The non-blocking synchronization instruction issued by the processor core is received by the synchronization processing module corresponding to the processor core, and when it is determined that the processor core is a synchronization participant, a synchronization hand-raising request is generated, and the request is routed to the synchronization representative by the synchronization routing module corresponding to the processor core; The hand-raising completion notification process includes: The non-blocking synchronization instruction issued by the processor core is received by the synchronization processing module corresponding to the processor core. When the processor core is judged to be a synchronization representative, the synchronization information is recorded, and a hand-raising completion notification is generated after collecting all the synchronous hand-raising requests, which is routed to the synchronization participant through the synchronization routing module corresponding to the processor core; after the synchronous participant receives the hand-raising completion notification, if a blocking synchronization instruction is received, it is judged that the synchronization is ended.

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