On-chip fault-tolerant processing method and system, chip and electronic equipment

Abstract

The invention relates to the technical field of artificial intelligence chip design, in particular to an on-chip fault-tolerant processing method and system, a chip and electronic equipment. The system comprises a fault detection module, a fault diagnosis module and a fault repair module. The method comprises the following steps: collecting monitoring data of a chip assembly through a monitoring part of a fault detection module, judging whether a chip has a fault by utilizing a preset fault model, and if the chip has the fault, obtaining fault information containing an identifier of a fault assembly and fault data; the fault diagnosis module determines the fault position according to the identifier of the fault component, evaluates the performance degradation degree of the fault component and the influence of the performance degradation degree on the chip performance based on the fault data, and generates fault evaluation data. And the fault repair module formulates a fault repair strategy based on the evaluation data and implements fault repair. Therefore, automatic detection, accurate diagnosis and efficient repair of faults are realized in the chip, system downtime and maintenance cost caused by the faults are reduced, and fault-tolerant capability and reliability of the chip are effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of artificial intelligence chip design, and in particular to an on-chip fault-tolerant processing method, system, chip, and electronic device. Background Art

[0002] With the rapid development of semiconductor technology, the integration of chips is getting higher and higher, and the scale is getting larger and larger. However, as the integration and scale of chips continue to increase, the risk of chip failure has also increased significantly. Traditional chip failure handling methods mainly rely on fault-tolerant mechanisms such as redundant design and error correction codes. These mechanisms have improved the reliability of chips to a certain extent, but at the same time have also increased chip area and power consumption, which is a drawback that cannot be ignored for modern chip designs that pursue high performance and low power consumption.

[0003] Specifically, the traditional chip fault handling method has the following problems: 1. Large resource overhead: Traditional fault-tolerant mechanisms, such as redundant design and error correction codes, require additional hardware resources to implement, which increases the chip area and power consumption, thereby increasing production costs and limiting chip performance improvements.

[0004] 2. Poor adaptability: Traditional fault-tolerant mechanisms are often designed for a specific type of fault (such as soft errors or aging faults). For example, redundancy is used to deal with soft errors, while aging monitoring circuits are used to predict and mitigate aging effects. However, these methods have limitations when dealing with complex and changeable chip failures. Although redundant design can enhance the fault tolerance of chips, it does little to mitigate aging effects and may even accelerate the aging process due to additional heat generation. Although aging monitoring circuits can predict the degree of aging, they cannot repair faults when used alone. In addition, in modern chips, multiple fault types such as soft errors and aging faults may occur at the same time, which requires fault-tolerant mechanisms to be more targeted and adaptable.

[0005] 3. High maintenance cost: Traditional fault-tolerant mechanisms often require downtime for maintenance to repair faults after they occur, which not only affects the normal operation of the chip but also increases maintenance costs. In addition, for some unpredictable fault types (such as random soft errors), traditional fault-tolerant mechanisms may not be able to repair them in a timely and effective manner.

[0006] How to build necessary test support on the chip to achieve a self-sufficient fault handling mechanism without increasing chip area and power consumption, thereby effectively improving the chip's fault tolerance and reliability, is an urgent problem to be solved. Summary of the invention

[0007] In order to solve the problems in the related art, the embodiments of the present disclosure provide an on-chip fault-tolerant processing method, system, chip and electronic device.

[0008] In a first aspect, an on-chip fault-tolerant processing system is provided in an embodiment of the present disclosure, wherein the system is arranged on a chip, wherein the chip includes a plurality of chip components, wherein the system includes: a fault detection module, a fault diagnosis module, and a fault repair module, wherein the fault detection module, the fault diagnosis module, and the fault repair module are sequentially connected in communication, wherein the fault detection module includes: a monitoring component, wherein the monitoring component and the fault repair module are respectively connected in communication with one or more chip components, wherein: The fault detection module is configured to: based on the monitoring component, obtain monitoring data of the one or more chip components according to a preset period; determine whether the chip fails according to the monitoring data and a preset fault model; if a fault occurs, obtain fault information, and send the fault information to the fault diagnosis module, the fault information including: an identifier of a faulty component and fault data of the faulty component, the faulty component being the chip component in which the fault occurs among the one or more chip components; The fault diagnosis module is configured to: determine the fault location of the chip based on the identifier of the faulty component, determine the performance degradation degree of the faulty component based on the fault data of the faulty component, evaluate the performance impact of the faulty component on the chip according to the performance degradation degree of the faulty component and the fault location, and generate fault evaluation data of the faulty component; The fault repair module is configured to generate a fault repair strategy based on the fault assessment data, so as to perform fault repair on the fault component based on the fault repair strategy.

[0009] According to an embodiment of the present disclosure, the system further includes: a fault repair effect evaluation module, the fault repair effect evaluation module is respectively connected to the one or more chip components and the fault repair module in communication, and the fault repair effect evaluation module is configured to: Obtaining state parameters of the faulty component and / or performance parameters of the chip after the fault is repaired; Based on a preset analysis model, obtaining an evaluation result according to the state parameters of the faulty component and / or the performance parameters of the chip; The fault repair strategy is dynamically adjusted according to the evaluation result.

[0010] According to an embodiment of the present disclosure, the monitoring component includes: an aging monitoring circuit, the chip assembly includes: a monitored unit, the aging monitoring circuit is communicatively connected with the monitored unit in the chip assembly, the monitoring data includes: signal conversion data of the monitored unit within a preset protection period of a clock cycle, the signal conversion data is used to indicate whether a signal conversion occurs within the preset protection period of the clock cycle, and judging whether the chip fails according to the monitoring data and a preset fault model includes: When the signal conversion data indicates that the monitored unit has a signal conversion within the preset protection period of the clock cycle, an aging fault has occurred accordingly; When the aging fault occurs, the acquiring of fault information includes: acquiring the frequency of the signal conversion, and using the acquired frequency of the signal conversion as the fault data of the faulty component to form the fault information; The method of determining the degree of performance degradation of the faulty component based on the fault data of the faulty component includes: comparing the frequency at which the signal conversion occurs with a preset frequency threshold, obtaining the difference between the frequency at which the signal conversion occurs and the preset frequency threshold, and determining the degree of performance degradation corresponding to the difference based on the difference and a preset difference performance degradation degree comparison table.

[0011] According to an embodiment of the present disclosure, the chip component also includes: a fault adaptive repair unit, the fault repair module is communicatively connected to the fault adaptive repair unit in the chip component, and the fault repair module is further configured to: send the fault repair strategy to the fault adaptive repair unit in the fault component so that the fault adaptive repair unit in the fault component performs fault repair based on the fault repair strategy.

[0012] According to an embodiment of the present disclosure, the chip includes: a multi-core processor, the multi-core processor includes a plurality of core units, the plurality of chip components correspond to the plurality of core units respectively, the monitoring component includes: a plurality of performance counters, the plurality of performance counters correspond to the plurality of core units one by one, and the acquiring of monitoring data of the plurality of chip components according to a preset period includes: Acquire a code snippet set, the code snippet set comprising a plurality of code snippets of different categories, each category of code snippets comprising a plurality of instruction operations of different categories, and each category of instruction operations comprising a plurality of instruction operations corresponding to the category; Based on the performance counters corresponding to the core units, the performance parameters of the code snippets in the code snippet set respectively executed by the core units are obtained, and the performance parameters of the code snippets in the code snippet set respectively executed by the core units are used as the monitoring data of the multiple chip components; The determining whether the chip fails according to the monitoring data and a preset fault model includes: forming a health index of each core unit based on the performance parameters of each code snippet in the code snippet set respectively executed by each core unit and the performance parameters of the reference core unit, judging whether the chip fails based on the health index, and when the health index of any core unit is lower than a preset reference threshold, the any core unit has a degradation fault, and the chip component corresponding to the any core unit is regarded as a faulty component; When the degradation fault occurs, the acquiring of fault information includes: using the health index of the core unit where the degradation fault occurs as the fault data of the faulty component to form the fault information; Determining the performance degradation degree of the faulty component based on the fault data of the faulty component includes: comparing the health index of the core unit where the degradation fault occurs with a plurality of preset index value intervals, wherein each index value interval corresponds to a performance degradation characterization parameter; The performance degradation degree of the core unit where the degradation fault occurs is obtained based on the comparison result.

[0013] According to an embodiment of the present disclosure, the chip further includes: a built-in fault register, and the fault diagnosis module is further configured to: The performance degradation degree of the core unit with the degradation fault is saved in the built-in fault register, so that when the chip is working, the designated program reads the performance degradation degree of the core unit with the degradation fault stored in the built-in fault register, and schedules each core unit when allocating tasks based on the following method: first, the core unit without fault is selected for use, and then the corresponding remaining core units are selected for use in order of performance degradation degree from low to high until all core units are used.

[0014] According to an embodiment of the present disclosure, the chip includes: a processor, the processor includes multiple processor structures, the processor structure includes predefined ACE bits and non-ACE bits, the ACE bits are used to indicate that when a program is executed, if the value of the ACE bits changes, the program execution error will be caused, thereby affecting the digits of the program output result, and the non-ACE bits are used to indicate that when a program is executed, if the value of the non-ACE bits changes, the program execution error will not be caused, thereby not affecting the digits of the program output result, the multiple chip components correspond to the multiple processor structures, the monitoring component includes: an intermittent fault monitoring circuit, and judging whether the chip fails according to the monitoring data and a preset fault model includes: When it is determined based on the monitoring data acquired by the intermittent fault monitoring circuit that a specified digit in the processor structure is fixed to 1 or 0 within a specified time interval, an intermittent fixed 1 / 0 fault occurs accordingly.

[0015] When it is determined based on the monitoring data acquired by the intermittent fault monitoring circuit that the bit line of the processor structure is open or short-circuited, an intermittent open / short circuit fault occurs accordingly.

[0016] When it is determined based on the monitoring data acquired by the intermittent fault monitoring circuit that the circuit behavior of the processor structure does not conform to the preset behavior and thus causes a timing violation, an intermittent timing fault occurs accordingly.

[0017] The obtaining of fault information includes: when the chip has an intermittent fixed 1 / 0 fault, an intermittent open circuit / short circuit fault or an intermittent timing fault, determining whether the fault affects the value of the ACE bit of the processor structure; if so, determining an intermittent fault sensitivity parameter of the processor structure where the fault occurs based on the fault that occurs and the number of affected ACE bits in the processor structure where the fault occurs; using the intermittent fault sensitivity parameter of the processor structure where the fault occurs as the fault data of the fault component to form the fault information, wherein the intermittent fault sensitivity parameter is used to characterize the probability of the fault occurring in the processor structure appearing in the program output.

[0018] Determining the performance degradation degree of the faulty component based on the fault data of the faulty component includes: comparing the intermittent fault sensitivity parameter of the processor structure where the fault occurs with a plurality of preset sensitivity parameter intervals, wherein each sensitivity parameter interval corresponds to a sensitivity characterization parameter.

[0019] Based on the comparison result, a sensitivity characterization parameter of the processor structure where the fault occurs is obtained, and the obtained sensitivity characterization parameter is used as the degree of performance degradation.

[0020] According to an embodiment of the present disclosure, the step of determining the intermittent fault sensitivity parameter of the processor structure where the fault occurs based on the fault that occurs and the number of ACE bits affected in the processor structure where the fault occurs includes: When the fault is an intermittent fixed 1 / 0 fault, the intermittent fault sensitivity parameter of the processor structure where the intermittent fixed 1 / 0 fault occurs is determined by the following method: :

[0021] Wherein, B represents the total number of bits in the processor structure, a represents the specified position in the processor structure, L represents the duration of the intermittent fixed 1 / 0 fault, It is used to indicate whether the ACE bit at the specified position is changed by the intermittent fixed 1 / 0 fault within the burst duration. If it is changed, is 1, otherwise it is 0; Indicates the number of ACE bits that are changed during the duration of the intermittent fixed 1 / 0 fault.

[0022] When the fault is an intermittent open circuit / short circuit fault, the intermittent fault sensitivity parameter of the processor structure where the intermittent open circuit / short circuit fault occurs is determined by the following method: :

[0023] Wherein, N represents the number of intermittent open circuit / short circuit faults occurring in the processor structure, Indicates whether the ACE bit in the processor architecture has been changed to specify intermittent open / short faults. If changed, is 1 if the value is true, otherwise it is 0.

[0024] When the fault is an intermittent timing fault, the intermittent fault sensitivity parameter of the processor structure where the intermittent timing fault occurs is determined by the following method: :

[0025] Wherein, NUM represents the number of intermittent timing faults that occur during the execution of a specified program by the processor, Indicates the number of intermittent timing faults occurring in the processor structure, representing the number of said intermittent timing faults affecting only invalid data in said processor architecture, Represents the number of said intermittent timing faults that affect only non-ACE bits in said processor architecture.

[0026] According to an embodiment of the present disclosure, determining the fault location of the chip based on the identifier of the faulty component includes: searching for the physical location and / or logical location of the faulty component on the chip corresponding to the identifier according to a preset component mapping table, wherein each entry in the component mapping table includes the identifier of the chip component and the physical location and / or logical location corresponding to the chip component; The step of evaluating the performance impact of the faulty component on the chip according to the performance degradation degree of the faulty component and the fault location, and generating fault evaluation data of the faulty component, comprises: Analyze the connection and data flow between the faulty component and other chip components associated with the faulty component according to the physical location and / or logical location of the faulty component on the chip to determine the scope of the fault impact; According to the performance degradation degree of the faulty component and the scope of the fault impact, quantify the performance impact of the faulty component on the chip based on a preset performance impact model, and generate a performance impact quantification result; Fault assessment data of the faulty component is generated based on the identification of the faulty component, the degree of performance degradation of the faulty component, the fault location, the scope of the fault impact, and the performance impact quantification result.

[0027] According to an embodiment of the present disclosure, generating a fault repair strategy based on the fault assessment data includes: Determine, according to the fault assessment data, a repair method corresponding to the faulty component, the repair method including one or more of the following methods: When the faulty component cannot be repaired, decoupling the faulty component from the chip; When the faulty component is repairable and is a reconfigurable component, reconfiguring the faulty component includes: adjusting the operating frequency and / or operating mode of the faulty component; When the chip includes a spare component or a redundant path, enabling the spare component or the redundant path to replace the failed component; Dynamically adjusting the resource configuration of the chip according to the fault assessment data includes: reallocating memory and / or adjusting cache strategy.

[0028] According to an embodiment of the present disclosure, generating a fault repair strategy based on the fault assessment data includes: According to the fault assessment data, assess the severity and urgency of the fault to determine a repair priority corresponding to the faulty component; When there are multiple faulty components, the faulty components are sorted in order of their repair priorities, so that the faulty components are repaired in the sorted order.

[0029] In a second aspect, an on-chip fault-tolerant processing method is provided in an embodiment of the present disclosure, and the method is applied to an on-chip fault-tolerant processing system, the system is arranged on a chip, the chip includes a plurality of chip components, the system includes: a fault detection module, a fault diagnosis module and a fault repair module, the fault detection module, the fault diagnosis module and the fault repair module are sequentially connected in communication, the fault detection module includes: a monitoring component, the monitoring component and the fault repair module are respectively connected in communication with one or more chip components, and the method includes: The fault detection module obtains monitoring data of the one or more chip components according to a preset period based on the monitoring component; determines whether the chip fails according to the monitoring data and a preset fault model; if a fault occurs, obtains fault information, and sends the fault information to the fault diagnosis module, the fault information including: an identifier of a faulty component and fault data of the faulty component, the faulty component being the chip component in which the fault occurs among the one or more chip components; Determine the fault location of the chip based on the identifier of the faulty component by the fault diagnosis module, determine the performance degradation degree of the faulty component based on the fault data of the faulty component, evaluate the performance impact of the faulty component on the chip according to the performance degradation degree of the faulty component and the fault location, and generate fault evaluation data of the faulty component; A fault repair strategy is generated by the fault repair module based on the fault assessment data, so as to perform fault repair on the faulty component based on the fault repair strategy.

[0030] According to an embodiment of the present disclosure, the system further includes: a fault repair effect evaluation module, wherein the fault repair effect evaluation module is respectively connected to one or more chip components and the fault repair module for communication, and the method further includes: The fault repair effect evaluation module is used to obtain the state parameters of the fault component and / or the performance parameters of the chip after the fault repair; based on a preset analysis model, an evaluation result is obtained according to the state parameters of the fault component and / or the performance parameters of the chip; and the fault repair strategy is dynamically adjusted according to the evaluation result.

[0031] In a third aspect, a chip is provided in an embodiment of the present disclosure, comprising the system described in any one of the first aspect; or, comprising a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement any one of the methods described in the second aspect.

[0032] In a fourth aspect, an electronic device is provided in an embodiment of the present disclosure, comprising a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement any method described in the second aspect.

[0033] In a fifth aspect, an embodiment of the present disclosure provides a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, the method described in any one of the second aspects is implemented.

[0034] In a sixth aspect, a computer program product is provided in an embodiment of the present disclosure, comprising a computer program, wherein when the computer program is executed by a processor, the method described in any one of the second aspects is implemented.

[0035] According to the technical solution provided by the embodiment of the present disclosure, an on-chip fault-tolerant processing system is proposed, which includes a fault detection module, a fault diagnosis module and a fault repair module. The monitoring data of the chip components are collected by the monitoring component of the fault detection module, and a preset fault model is used to determine whether the chip fails. If a fault occurs, the fault information including the identification of the faulty component and the fault data is obtained; the fault diagnosis module determines the fault location according to the identification of the faulty component, and evaluates the performance degradation degree of the faulty component and its impact on the chip performance based on the fault data, and generates fault evaluation data. The fault repair module formulates a fault repair strategy based on the evaluation data and implements fault repair. In this way, automatic detection, accurate diagnosis and efficient repair of faults are realized inside the chip, which reduces the system downtime and maintenance costs caused by faults, and effectively improves the fault tolerance and reliability of the chip without increasing the chip area and power consumption.

[0036] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings: Figure 1 A structural block diagram of an on-chip fault-tolerant processing system according to an embodiment of the present disclosure is shown.

[0038] Figure 2 A structural block diagram of another on-chip fault-tolerant processing system according to an embodiment of the present disclosure is shown.

[0039] Figure 3 A specific example of an on-chip fault-tolerant processing system according to an embodiment of the present disclosure is shown.

[0040] Figure 4 Another specific example of the on-chip fault-tolerant processing system according to the embodiment of the present disclosure is shown.

[0041] Figure 5 Another specific example of the on-chip fault-tolerant processing system according to the embodiment of the present disclosure is shown.

[0042] Figure 6 A flow chart of an on-chip fault tolerance processing method according to an embodiment of the present disclosure is shown.

[0043] Figure 7A flow chart of another on-chip fault tolerance processing method according to an embodiment of the present disclosure is shown.

[0044] Figure 8 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0045] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0046] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0047] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0048] As described above, due to some defects in the traditional chip fault handling method, the traditional chip fault handling method can no longer meet the needs of modern chip design that pursues high performance and low power consumption.

[0049] In order to make up for the defects in traditional chip fault handling methods, without increasing the chip area and power consumption, the necessary test support is built on the chip to achieve a self-sufficient fault handling mechanism, thereby effectively improving the reliability of the chip. After repeated demonstrations and careful research, the inventors of the present invention have proposed an on-chip fault-tolerant processing system that can autonomously detect, diagnose and repair faults at the chip level.

[0050] When designing the on-chip fault-tolerant processing system of the present disclosure, the inventors of the present disclosure noticed that: As for fault detection, in the prior art, fault detection is usually achieved through dual module redundancy in space or time dimensions. For example, in fault detection schemes based on thread-level redundancy (TLR), core-level redundancy (CLR) and execution-level redundancy (ELR), TLR or CLR detects faults by executing the same calculation in different threads or on different processor cores at the expense of computing throughput, while ELR detects faults by re-executing the same code segment, which results in extremely high hardware or performance overhead. Therefore, in order to provide a more economical detection method to achieve chip-level fault tolerance, that is, to ensure that the chip can continue to work or at least not fail completely when certain faults occur, the inventors of the present disclosure design a fault detection scheme based on the principle of probability rather than the principle of determinism, that is, to use statistical and probability theory methods to analyze, predict and judge possible faults in the system. On the one hand, by establishing reasonable fault models based on the characteristics and historical data of the system, these fault models may include the probability distribution of fault occurrence, the correlation between fault type and fault cause, etc., and then collect the system operation data through sensors, performance counters or other monitoring means, and use statistical methods to analyze these data to extract characteristic information related to the fault; on the other hand, according to the analysis results of the fault model and monitoring data, set reasonable thresholds. When the monitoring data exceeds these thresholds, it is considered that the system may have a fault. The threshold setting here is based on probability, and the threshold can be adjusted based on the statistics of historical fault detection data, so that it can more accurately determine whether a fault has occurred.

[0051] For fault diagnosis, traditional fault diagnosis mainly relies on silicon scan testing and complex logic diagnostic tools, which are usually performed outside the production line (offline) to ensure that there is no interference with the normal production process. The main goal is to help locate the defective physical or electrical environment to guide designers to improve the physical design, thereby improving the yield learning rate. In addition, traditional fault diagnosis is performed at a finer-grained level such as logic gates or standard cells, and the fault model is mainly aimed at silicon-level defects such as bridging, abnormal leakage, etc., which means that the diagnostic program needs to be accurate to a single logic element or circuit unit inside the chip, thereby increasing the resource consumption and complexity of the diagnostic process. In order to provide a simpler and more accurate way to achieve fault diagnosis, the present disclosure innovatively uses chip components as diagnostic units, relies on built-in logic, and uses a coarse-grained diagnostic method based on identifying and locating faulty components for fault diagnosis. For the identified faulty components, multiple methods are used based on different fault types to evaluate their performance degradation degree, and the performance impact of the faulty components on the chip is comprehensively evaluated in combination with the location where the fault occurs, while reducing the resource consumption and complexity of the diagnostic process and improving the diagnostic efficiency, while ensuring the accuracy of fault diagnosis.

[0052] For fault repair, in traditional fault repair, it is generally achieved by setting redundant components in the chip, for example: an N-core processor is equipped with M redundant cores as spare cores. When a core among the N cores fails, the spare core can be used to replace the faulty core to ensure the normal operation of the chip. Although this redundancy mechanism ensures that the chip performance will not be affected by the fault to a certain extent, it increases the chip cost and the complexity of chip design. In order to provide a more economical and simple way to achieve fault repair, the present disclosure formulates a fault repair strategy based on the performance degradation degree of the faulty component. According to the different conditions of the faulty component, different repair methods are adopted accordingly. For example: for the unrepairable faulty component, the faulty component is decoupled from the chip to achieve fault isolation. In this case, even if some components fail, the system can still use the remaining intact components to work normally and maintain a certain performance level, so that the normal operation of the chip is not affected in the event of a fault; for another example: for the repairable and reconfigurable faulty component, the faulty component can be repaired by adjusting the working frequency and / or working mode of the faulty component, such as: if a core fails, it can be used at a reduced frequency instead of being completely abandoned or replaced. Especially for chip components that can be adaptively repaired, adaptive repair can be performed directly through the fault adaptive repair unit of the fault component without the need for additional redundant components. In addition, the present disclosure implements fault repair on the chip in an all-round way based on three levels: unit level, processor structure level, and core level, so that the corresponding repair plan can be selected according to the characteristics and design requirements of the chip, making the chip design more flexible and scalable, and thus can adapt to different application scenarios and performance requirements. Compared with the redundant mechanism, the present disclosure pays more attention to the optimization and maintenance of performance during the fault repair process, avoiding the high cost brought by the redundant mechanism.

[0053] Figure 1 FIG. 2 shows a structural block diagram of an on-chip fault-tolerant processing system according to an embodiment of the present disclosure. Figure 1 As shown, the on-chip fault-tolerant processing system is set on a chip, and the chip includes multiple chip components, where "chip components" refer to various functional units or modules inside the chip, such as: processor, cache structure, memory unit, etc., which work together to realize the overall function of the chip. In addition, the chip component can be a hardware component, a software component, or a combination of hardware and software components.

[0054] Specifically, the system includes: a fault detection module, a fault diagnosis module and a fault repair module, wherein the fault detection module, the fault diagnosis module and the fault repair module are sequentially connected in communication, and the fault detection module includes: a monitoring component, wherein the monitoring component and the fault repair module are respectively connected in communication with one or more chip components ( Figure 1A chip component is used as an example in the figure). Among them, the "monitoring component" as the core part of the fault detection module is responsible for collecting and analyzing the operating status data of the chip component in real time or periodically, so as to timely discover and report potential fault conditions; the monitoring component may include specialized hardware sensors, such as temperature sensors, voltage monitors, current sensors, etc., which are used to directly measure the physical parameters inside the chip. In some cases, the monitoring component may also exist in the form of software agents, which run on specific processors or controllers on the chip and are responsible for collecting key data about the chip's operating status, such as voltage levels, current consumption, temperature readings, signal integrity, etc. The data collected depends on the monitoring objectives and the specific requirements of the chip design.

[0055] Specifically, the fault detection module is configured to: based on the monitoring component, obtain monitoring data of the one or more chip components according to a preset period; determine whether the chip fails according to the monitoring data and a preset fault model; if a fault occurs, obtain fault information, and send the fault information to the fault diagnosis module, the fault information includes: an identifier of a faulty component and fault data of the faulty component, the faulty component being the chip component in which the fault occurs among the one or more chip components; The fault diagnosis module is configured to: determine the fault location of the chip based on the identifier of the faulty component, determine the performance degradation degree of the faulty component based on the fault data of the faulty component, evaluate the performance impact of the faulty component on the chip according to the performance degradation degree of the faulty component and the fault location, and generate fault evaluation data of the faulty component; The fault repair module is configured to generate a fault repair strategy based on the fault assessment data, so as to perform fault repair on the fault component based on the fault repair strategy.

[0056] Figure 2 FIG. 2 shows a structural block diagram of another on-chip fault-tolerant processing system according to an embodiment of the present disclosure. Figure 2 As shown, the on-chip fault-tolerant processing system includes, in addition to a fault detection module, a fault diagnosis module and a fault repair module, a fault repair effect evaluation module, wherein the fault repair effect evaluation module is respectively connected to one or more chip components and the fault repair module in communication, wherein: The fault repair effect evaluation module is configured to: obtain the state parameters of the fault component and / or the performance parameters of the chip after the fault is repaired; based on a preset analysis model, obtain an evaluation result according to the state parameters of the fault component and / or the performance parameters of the chip; and dynamically adjust the fault repair strategy according to the evaluation result.

[0057] The on-chip fault-tolerant processing system of the embodiment of the present disclosure is illustrated and described in detail below using three different specific implementation scenarios.

[0058] Figure 3 A specific example of an on-chip fault-tolerant processing system according to an embodiment of the present disclosure is shown.

[0059] In this specific example, the on-chip fault-tolerant processing system is aimed at the soft errors and aging delays (hereinafter these two problems are collectively referred to as "aging failures") that occur in the processing chip. Among them, soft errors are partly caused by high-energy particles, such as temporary changes in data values ​​in memory. According to the way particles affect storage cells, soft errors can be divided into single event upsets (SEU), single event transients (SET) and multi-bit upsets (MBU). SEU refers to the flipping of the storage value of a storage cell due to particle impact, SET refers to particles causing the combinational logic node to collect enough charge to generate transient current pulses, thereby affecting the operation of the circuit, and MBU refers to the simultaneous flipping of multiple storage bits due to particle impact; aging is generally due to the degradation of silicon materials, resulting in a gradual decline in transistor performance, or long-term use and continuous electrical stress can also cause material aging, thereby causing aging delays.

[0060] During the project development, the inventors of the present disclosure found that: whether it is a soft error or an aging delay, it largely manifests itself as the same signal behavior. In the circuit, the signal should usually remain stable within a specific time period to meet the timing requirements. However, when an aging fault occurs in the circuit, the signal may undergo unexpected conversions during these time periods, that is, stability violations. For example: the aging of transistors may cause their switching speeds to slow down, thereby increasing the delay of the circuit. This increase in delay may cause the circuit that originally met the timing requirements to become unsatisfactory, or to convert during the time period that should remain stable, thereby causing functional failures. Therefore, in order to enable the system to cope with both types of faults at the same time, the present disclosure proposes a model for detecting faults by analyzing the signal behavior in the circuit. By analyzing the signal behavior in the circuit, especially detecting stability violations, aging faults in the circuit can be effectively identified.

[0061] In order to be able to perceive the aging status of chip components, the monitoring components include but are not limited to: aging monitoring circuit. The aging monitoring circuit is deployed at the key nodes of the circuit to monitor and evaluate the aging status of the circuit. It has high precision and high sensitivity, can capture tiny signal changes, and can promptly detect abnormal conditions such as clock jitter or frequency offset by monitoring the clock signal. In a specific implementation scenario, the aging monitoring circuit includes: a high-precision signal acquisition function module, a clock signal monitoring function module, a signal stability detection function module, etc., to obtain and analyze whether the signal in the circuit is converted within a specific time period of the clock cycle.

[0062] Correspondingly, the chip component includes: a monitored unit, the aging monitoring circuit is communicatively connected to the monitored unit in the chip component, and the monitoring data includes: signal conversion data of the monitored unit within a preset protection period of a clock cycle, and the signal conversion data is used to indicate whether a signal conversion occurs within the preset protection period of the clock cycle, that is, whether a signal conversion occurs within a time period that should remain stable.

[0063] The determining whether the chip fails according to the monitoring data and a preset fault model includes: When the signal conversion data indicates that the monitored unit has a signal conversion within the preset protection period of the clock cycle, an aging fault has occurred accordingly.

[0064] When the aging fault occurs, the acquiring of fault information includes: acquiring the frequency of the signal conversion, and using the acquired frequency of the signal conversion as the fault data of the faulty component to form the fault information.

[0065] Among them, the frequency of signal conversion refers to the number of times the signal of the monitored unit is converted within a specific time period (such as a preset protection period within one or more clock cycles). Specifically, when the performance of transistors or other components in the circuit degrades due to aging, they may not be able to stably maintain the signal state within the specified time, resulting in unexpected signal conversion during the time period that should remain stable. This signal conversion frequency reflects the degree of influence of circuit aging on signal stability and is an important indicator for determining whether a circuit fails and the severity of the failure. When acquiring, the number of recorded signal conversion events can be counted within a specific time period (such as a preset protection period within a clock cycle), and then the number of signal conversion events can be divided by the length of the time period to calculate the frequency of signal conversion.

[0066] According to an embodiment of the present disclosure, the determining the performance degradation degree of the faulty component based on the fault data of the faulty component includes: comparing the frequency of the signal conversion with a preset frequency threshold, obtaining the difference between the frequency of the signal conversion and the preset frequency threshold, and determining the performance degradation degree corresponding to the difference based on the difference and a preset difference performance degradation degree comparison table. The higher the frequency of the signal conversion, the higher the corresponding performance degradation degree.

[0067] like Figure 3As shown, the chip component also includes: a fault adaptive repair unit, the fault repair module is communicatively connected to the fault adaptive repair unit in the chip component, and the fault repair module is also configured to: send the fault repair strategy to the fault adaptive repair unit in the fault component, so that the fault adaptive repair unit in the fault component performs fault repair based on the fault repair strategy.

[0068] In this specific example, the chip component can be a pipeline stage processing unit, which refers to a processing unit that is responsible for processing each stage after dividing the execution process of the instruction into multiple stages based on the pipeline operation mechanism. The pipeline stage processing unit includes: a logic unit and a trigger (the logic unit corresponds to the monitored unit, and the trigger corresponds to the fault adaptive repair unit), wherein the logic unit is responsible for completing the operation task of the instruction, and is usually composed of multiple gate circuits (such as AND gates, OR gates, NOT gates, etc.) and registers to realize various operations on binary data. The trigger is usually used to store the intermediate results and status information of the instruction, and is composed of multiple transistors to achieve stable storage and reliable read and write operations.

[0069] The present disclosure is directed to some specific chip components, such as the pipeline stage processing unit mentioned above. When the logic unit therein has an aging fault and the signal conversion is delayed to a preset protection period (the signal conversion occurs during the preset protection period), the trigger contained therein can be used to adjust the timing of the trigger based on the timing adjustment amount in the fault repair strategy sent by the fault repair module (involving adjusting the frequency, phase or duty cycle of the clock signal) to repair the aging fault and ensure the normal operation of the circuit. Through the built-in adaptive repair mechanism, the reliance on traditional repair methods (such as replacing faulty components) can be avoided or reduced, which helps to reduce maintenance costs and time costs, and the fault repair can be performed in real time, which improves the response speed and automation of the system; in addition, the adaptive repair mechanism can ensure that the system can continue to operate when a fault occurs, thereby improving the availability of the system.

[0070] In addition, the present invention can not only detect soft errors and aging delays simultaneously by analyzing the signal behavior in the circuit, but also repair the aging faults through corresponding repair strategies after detection. Compared with the prior art, on the one hand, there is no need to set up special sensors for soft errors and aging delays respectively, but the two faults can be detected simultaneously by analyzing the signal behavior in the circuit, thereby reducing chip space occupancy and hardware costs.

[0071] Figure 4 Another specific example of the on-chip fault-tolerant processing system according to the embodiment of the present disclosure is shown.

[0072] In this specific example, the on-chip fault-tolerant processing system is aimed at intermittent faults in the processing chip. Intermittent faults refer to faults in electronic systems or microprocessors that do not exist continuously but occur occasionally or intermittently. These faults may be caused by a variety of reasons, including but not limited to physical damage, material aging, environmental factors (such as temperature fluctuations), electromagnetic interference, etc. Intermittent faults pose a serious threat to the stability and reliability of the system because they are difficult to predict and diagnose, and may cause system failure at critical moments.

[0073] In the present disclosure, three types of intermittent faults are considered, including: intermittent fixed 1 / 0 fault, intermittent open circuit / short circuit fault and intermittent timing fault. Among them, intermittent fixed 1 / 0 fault means that a signal line or logic gate is incorrectly fixed to a high level (1) or a low level (0) in a specific time interval. Although the signal or logic gate may work normally in most cases, at some point in time, it will suddenly become unreliable and continuously output wrong level values; intermittent open circuit / short circuit fault is manifested in two situations, namely open circuit fault and short circuit fault. Open circuit fault refers to a sudden disconnection of a connection in the circuit, resulting in the inability of current to flow, while short circuit fault refers to two or more A conductive path is suddenly established between nodes that should not be connected. All of these faults are not persistent but occur intermittently, which means that the circuit may work normally at some points in time and fail at other points in time due to open or short circuits; intermittent timing faults refer to circuit behavior that is not as expected due to reasons such as signal propagation delays or clock offsets. This timing problem is not persistent but occurs intermittently, which may cause the circuit to work normally in some clock cycles and fail in other cycles due to timing problems. For example, a data signal may arrive at its destination correctly in one clock cycle, but fail to arrive in time in the next cycle due to delays.

[0074] In order to quantify the impact of intermittent faults on the chip processor structure, the present invention innovatively proposes corresponding intermittent fault sensitivity parameters for the above three intermittent faults to characterize the sensitivity of the processor structure to intermittent faults, so that chip designers can use this parameter to analyze which part of the processor is more susceptible to intermittent faults and select the best protection technology in the early stage of design.

[0075] In this specific example, the chip includes: a processor, the processor includes multiple processor structures, the processor structure includes predefined ACE bits and non-ACE bits, the ACE bits are used to indicate that when a program is executed, if the value of the ACE bits changes, it will cause the program execution error and thus affect the digits of the program output result, and the non-ACE bits are used to indicate that when a program is executed, if the value of the non-ACE bits changes, it will not cause the program execution error and thus will not affect the digits of the program output result, that is, the ACE bits are key bits in the processor structure, and the non-ACE bits are non-key bits, and the multiple chip components correspond to the multiple processor structures, that is, each chip component is a processor structure.

[0076] The processor structure may be a reorder buffer, a register file, an instruction queue, a load / store queue, and an L1 / L2 cache in the processor. The reorder buffer is used to temporarily store the instruction results after out-of-order execution. Each instruction to be executed will be dispatched to the ROB and assigned an entry. When the instruction is executed, its result will be written back to the corresponding entry in the ROB. When the instruction reaches the submission stage, the ROB submits the result to the register file or memory in program order.

[0077] Regarding how to predefine the ACE bit and non-ACE bit in the processor structure, take the reorder buffer as an example. Since each entry in the reorder buffer usually contains the result of the instruction, status information (such as whether it has been completed, whether it has been submitted, etc.), and possible metadata, then in the reorder buffer entry, the data directly related to the program output (such as the result of arithmetic operations, the result of logical operations, the result of memory access, etc.) should be regarded as ACE bits, while some status information in the reorder buffer (such as the flag indicating whether the instruction has been completed) is important for internal operations, but usually does not affect the final output result of the program, so it can be regarded as non-ACE bits. In the design of the reorder buffer entry, a mark is added to each field that may contain an ACE bit to indicate whether it is an ACE bit.

[0078] Correspondingly, the monitoring component includes: an intermittent fault monitoring circuit. The intermittent fault monitoring circuit is connected to the key structure of the processor and is used to monitor the key digital bits or signal paths of the processor structure. In a specific implementation scenario, the intermittent fault monitoring circuit may include: a current / voltage sensor for monitoring the current or voltage changes in the circuit to detect open circuit (zero current) or short circuit (abnormally high current or voltage) conditions, and may also include a dual-state comparator for continuously monitoring the current value of the digital bit and comparing it with the value of the previous clock cycle. If it is detected that the digital bit value remains unchanged (and does not conform to the expected change) for multiple consecutive clock cycles (configurable threshold), a fixed 1 / 0 fault alarm is triggered; it may also include a timing monitor for measuring the time of signal propagation and comparing it with the expected timing constraints. If it is detected that the signal propagation delay exceeds the threshold (or arrives early), a timing fault alarm is triggered.

[0079] According to an embodiment of the present disclosure, judging whether the chip fails according to the monitoring data and a preset fault model includes: When it is determined based on the monitoring data obtained by the intermittent fault monitoring circuit that a specified digit in the processor structure is fixed to 1 or 0 within a specified time interval, an intermittent fixed 1 / 0 fault occurs. In a specific implementation scenario, when determining whether a specified digit in the processor structure is fixed to 1 or 0 within a specified time interval, a time interval (i.e., a monitoring window) and a configurable threshold (i.e., the number of consecutive and unchanged clock cycles) can be pre-set. Within the monitoring window, if the dual-state comparator continuously detects that the digit value remains unchanged (and this value is either 1 or 0), and the number of consecutive and unchanged clock cycles exceeds the preset threshold, a fixed 1 / 0 fault alarm is triggered.

[0080] When it is determined based on the monitoring data obtained by the intermittent fault monitoring circuit that the bit line of the processor structure is open or short-circuited, an intermittent open / short circuit fault occurs. In a specific implementation scenario, when determining whether the bit line of the processor structure is open or short-circuited, reasonable current and voltage thresholds can be set based on the normal working characteristics of the processor structure and the electrical parameters of the bit line to use a current / voltage sensor to determine whether the bit line has an open or short circuit fault. For example, for an open circuit fault, a lower current threshold can be set. If the current monitored by the sensor is lower than the threshold, it may indicate that the bit line is open. For a short circuit fault, a higher voltage or current threshold can be set. If the voltage or current monitored by the sensor exceeds the threshold, it may indicate that the bit line is short-circuited.

[0081] When it is determined based on the monitoring data obtained by the intermittent fault monitoring circuit that the circuit behavior of the processor structure does not conform to the preset behavior and thus causes a timing violation, an intermittent timing fault occurs. In a specific implementation scenario, when determining whether the circuit behavior of the processor structure conforms to the preset behavior, the timing behavior of the processor structure during normal operation can be first clarified, which usually includes key parameters such as signal propagation time, clock cycle, and data path delay. Then, the actual propagation time of the signal is recorded in each monitoring cycle by the timing monitor, and compared with the preset timing constraints. If the actual propagation time is detected to exceed or fall below the preset threshold (i.e., a delay or early arrival occurs), an intermittent timing fault occurs.

[0082] According to an embodiment of the present disclosure, the obtaining of fault information includes: when the chip has an intermittent fixed 1 / 0 fault, an intermittent open circuit / short circuit fault or an intermittent timing fault, determining whether the fault affects the value of the ACE bit of the processor structure; if so, determining an intermittent fault sensitivity parameter of the processor structure where the fault occurs based on the fault that occurs and the number of affected ACE bits in the processor structure where the fault occurs; using the intermittent fault sensitivity parameter of the processor structure where the fault occurs as the fault data of the fault component to further form the fault information, wherein the intermittent fault sensitivity parameter is used to characterize the probability of the fault occurring in the processor structure appearing in the program output.

[0083] In order to evaluate the impact of intermittent faults on program execution, it is necessary to determine whether the fault propagates to the processor structure during its life cycle and changes the ACE bit therein. For intermittent fixed 1 / 0 faults, since they only affect a single location, it is necessary to check whether the affected location contains the ACE bit, and then analyze whether the ACE bit is disturbed during the activity of the fault (within the duration of the burst). Only when the affected location contains the ACE bit and the ACE bit is changed will it affect program execution. For intermittent open / short faults, they may damage two adjacent bit lines. When such faults occur, it is necessary to determine whether the fault propagates to the processor structure and changes the ACE bit therein; for intermittent timing faults, they may cause timing violations and affect write operations. Only when the intermittent timing fault is captured by the processor structure and changes the ACE bit therein, it will affect program execution.

[0084] Specifically, when the intermittent fault monitoring circuit detects a fault in the processor structure (such as a fixed 1 / 0 fault, an open circuit / short circuit fault, or a timing fault), a corresponding fault alarm is generated, and includes information about the location where the fault occurred (i.e., which digital bit or signal path) and the type of fault. The metadata or configuration file of the processor structure is then accessed to obtain information about the ACE bit. By comparing the location where the fault occurred with the location of the ACE bit, it can be determined whether the fault directly affects the ACE bit. Finally, based on the number of affected ACE bits (i.e., causing the value stored in the ACE bit to change) and the fault type, the intermittent fault sensitivity parameter of the processor structure corresponding to the fault type is calculated.

[0085] According to an embodiment of the present disclosure, determining the performance degradation degree of the faulty component based on the fault data of the faulty component includes: The intermittent fault sensitivity parameter of the processor structure where the fault occurs is compared with multiple preset sensitivity parameter intervals to determine in which interval the parameter falls, thereby obtaining the corresponding sensitivity characterization parameter, wherein these intervals should cover the possible intermittent fault sensitivity parameter range, and each sensitivity parameter interval corresponds to a sensitivity characterization parameter, which can be quantitative (such as performance degradation percentage, error rate increase, etc.) or qualitative (such as slight degradation, moderate degradation, severe degradation, etc.), and can accurately reflect the performance changes of the processor structure when it is affected by intermittent faults.

[0086] Based on the comparison result, a sensitivity characterization parameter of the processor structure where the fault occurs is obtained, and the obtained sensitivity characterization parameter is used as the degree of performance degradation.

[0087] According to an embodiment of the present disclosure, the step of determining the intermittent fault sensitivity parameter of the processor structure where the fault occurs based on the fault that occurs and the number of ACE bits affected in the processor structure where the fault occurs includes: When the fault is an intermittent fixed 1 / 0 fault, the intermittent fault sensitivity parameter of the processor structure where the intermittent fixed 1 / 0 fault occurs is determined by the following method: :

[0088] Wherein, B represents the total number of bits in the processor structure, a represents the specified position in the processor structure, and the specified position specifically refers to the hardware or data position that has undergone a state change or been disturbed due to the occurrence of a fault, which may be physical (such as a bit in a storage unit) or logical (such as a variable or register during program execution). L represents the outbreak duration of the intermittent fixed 1 / 0 fault, that is, the duration of the fault. It is used to indicate whether the ACE bit at the specified position is changed by the intermittent fixed 1 / 0 fault within the burst duration. If it is changed, is 1, otherwise it is 0; Indicates the number of ACE bits that are changed during the duration of the intermittent fixed 1 / 0 fault.

[0089] When the fault is an intermittent open circuit / short circuit fault, the intermittent fault sensitivity parameter of the processor structure where the intermittent open circuit / short circuit fault occurs is determined by the following method: :

[0090] Wherein, N represents the number of intermittent open circuit / short circuit faults occurring in the processor structure, Indicates whether the ACE bit in the processor architecture has been changed to specify intermittent open / short faults. If changed, is 1 if the value is true, otherwise it is 0.

[0091] When the fault is an intermittent timing fault, the intermittent fault sensitivity parameter of the processor structure where the intermittent timing fault occurs is determined by the following method: :

[0092] Wherein, NUM represents the number of intermittent timing faults that occur during the execution of a specified program by the processor, Indicates the number of intermittent timing faults occurring in the processor structure, represents the number of said intermittent timing faults that affect only invalid data in said processor structure (i.e., data stored in said structure is an invalid value), Represents the number of said intermittent timing faults that affect only non-ACE bits in said processor architecture.

[0093] The present disclosure evaluates the sensitivity of a specific processor structure to intermittent faults by paying attention to whether the ACE bit in the processor structure is changed, and quantifies the degree of performance degradation of the faulty component based on the intermittent fault sensitivity parameter reflecting the sensitivity. If the intermittent fault sensitivity parameter value of the faulty component is larger, it means that it is more sensitive to the corresponding intermittent fault, that is, it is more susceptible to the fault and the probability of error is greater. In this case, the degree of performance degradation of the faulty component is higher. Since the ACE bit has a specific position and function in the processor structure, when the ACE bit is detected to be changed, the processor structure or component where the fault occurs can be quickly located, the scope of fault detection can be reduced, the efficiency of fault detection can be improved, and the reliability of the system can be improved without sacrificing too much performance.

[0094] Figure 5 Another specific example of the on-chip fault-tolerant processing system according to the embodiment of the present disclosure is shown.

[0095] In this specific example, the on-chip fault-tolerant processing system is aimed at the core performance degradation problem in the processing chip. The core performance degradation is mainly due to the progressive aging mechanism in the multi-core processor, which includes time-dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI) and random telegraph noise (RTN), etc. These mechanisms will cause the processor performance to decrease, resulting in performance degradation of the processor.

[0096] The present disclosure uses "health status" to characterize the degree of core degradation. In order to evaluate the "health status" of each core in multi-core processing and quantify core performance, the present disclosure proposes to use the performance parameters of each core when executing a specified code snippet as an indicator for quantifying core performance, and to use the health index formed based on the comparison result of the core's performance parameters with the performance parameters of the reference core as a standard for measuring whether the core has performance degradation.

[0097] Specifically, the chip includes: a multi-core processor, the multi-core processor includes multiple core units, and the multiple chip components correspond to the multiple core units respectively. Among them, the multi-core processor refers to a processor that integrates multiple independent processing core units (or "cores") in a single computing chip (or "processor package"), and each core unit can independently execute instructions and process data.

[0098] Correspondingly, the monitoring component includes: a plurality of performance counters, and the plurality of performance counters correspond to the plurality of core units one by one. That is to say, a performance counter is used to monitor and record various performance parameters of a core unit when executing a task, and these performance parameters include but are not limited to: the number of instructions executed within a specified time, cache access and miss rate (i.e., the number of times the core unit accesses the cache and the number of times it fails to read data from the cache), branch prediction success rate (the accuracy of the core unit in predicting the direction of program branches), the number of clock cycles required to execute a specific task, the processing speed and efficiency of the core unit when performing floating-point operations, etc. The specific performance parameters used to reflect the health status of the core unit can be selected according to actual needs.

[0099] According to an embodiment of the present disclosure, acquiring the monitoring data of the plurality of chip components according to a preset period includes: A code snippet set is obtained, where the code snippet set includes a plurality of code snippets of different categories, each category of code snippets includes a plurality of instruction operations of different categories, and each category of instruction operations includes a plurality of instruction operations corresponding to the category.

[0100] The code snippet is used to describe the dynamic flow of instruction operations. Therefore, the characteristics of the code snippet are determined by the combination of various operation instructions and their corresponding quantities, which are expressed using mathematical vectors as follows:

[0101] in, represents the instruction operation of the i-th type, Indicates the number of occurrences of instruction operations of the i-th type.

[0102] For example: code snippet Represents a code snippet consisting of 60 floating-point (FP) multiplication operations, 35 FP addition operations, and 5 branch operations, containing three different types of instruction operations (floating-point multiplication, floating-point addition, and branch operations).

[0103] Among them, if two code snippets are composed of the same type of instruction operations, and the number of instruction operations of each type is also the same, then the two code snippets belong to the same category, otherwise they belong to different categories. In a specific implementation scenario, when judging whether two code snippets belong to the same category, the classification requirements can also be relaxed. As long as the number of instruction operations of each type in the two code snippets does not differ by more than a preset tolerance, the two code snippets can be regarded as belonging to the same category. This tolerance setting helps to more flexibly handle the quantity fluctuations in actual tests, making the code snippet classification more practical and robust.

[0104] For example: and , both code snippets are composed of the same type of instruction operations (floating-point multiplication, floating-point addition, and branch operations). Even if the number of floating-point multiplication and floating-point addition instruction operations is different, if the difference in number satisfies the preset tolerance, then the two code snippets s1 and s2 are also the same code snippets.

[0105] Specifically, when obtaining a code snippet set, you can proceed as follows: First, the evaluation objectives need to be clearly defined, that is, the core unit performance indicators to be evaluated and the workload scenarios that may be encountered are determined to determine which categories of code snippets the code snippet collection needs to include.

[0106] Then, based on the evaluation results, instruction operations that can reflect the target performance indicators and workload scenarios are selected from the processor's instruction set. These instruction operations will constitute the basic unit of the code snippet.

[0107] Afterwards, the selected instruction operations are combined into code snippets according to a specific logic and order. Each code snippet should focus on a specific performance metric or workload scenario and contain enough instruction operations to provide reliable evaluation results.

[0108] Finally, the designed code snippets are organized into code snippet collections by category to ensure that the code snippets in the collection can fully cover various workload scenarios and performance indicators that the processor may encounter. In addition, in the subsequent specific operation, the code snippets are adjusted and optimized as needed to ensure that the code snippet collection can accurately reflect the performance characteristics and degradation degree of the processor.

[0109] Based on the performance counters corresponding to each core unit, the performance parameters of each core unit executing each code fragment in the code fragment set are obtained, and the performance parameters of each core unit executing each code fragment in the code fragment set are used as monitoring data of the multiple chip components.

[0110] According to an embodiment of the present disclosure, judging whether the chip fails according to the monitoring data and a preset fault model includes: A health index of each core unit is formed based on the performance parameters of each code fragment in the code fragment set executed by each core unit and the performance parameters of the reference core unit. Whether the chip fails is determined based on the health index. When the health index of any core unit is lower than a preset reference threshold, a degradation failure occurs in any core unit, and the chip component corresponding to any core unit is regarded as a failed component.

[0111] The reference core unit is a hypothetical core unit with perfect performance, which is used as a benchmark for evaluating the performance degradation of other core units. In practical applications, if it is impossible to find a completely non-degraded physical core unit as a reference, a performance benchmark can be constructed by selecting the core unit with the best performance or based on the performance data of a large number of core units as a reference baseline.

[0112] Specifically, when generating the health index of each core unit, for each core unit to be evaluated, its deviation from the reference baseline on each performance evaluation indicator can be calculated. Here, the deviation can be an absolute difference or a relative percentage difference, depending on the nature of the evaluation objective and the performance indicator. Alternatively, a weight can be assigned to each performance evaluation indicator based on the importance of the evaluation objective and the performance indicator. The weight is used to reflect the relative importance of the indicator to the health status assessment of the core unit. Then, a comprehensive score, namely the health index, is calculated based on the deviation of each core unit on each performance evaluation indicator and the corresponding weight.

[0113] According to an embodiment of the present disclosure, when the degradation fault occurs, the acquiring of fault information includes: using the health index of the core unit where the degradation fault occurs as the fault data of the faulty component to form the fault information.

[0114] According to an embodiment of the present disclosure, determining the performance degradation degree of the faulty component based on the fault data of the faulty component includes: comparing the health index of the core unit where the degradation fault occurs with a plurality of preset index value intervals, wherein each index value interval corresponds to a performance degradation characterization parameter; and obtaining the performance degradation degree of the core unit where the degradation fault occurs based on the comparison result.

[0115] The present disclosure can more comprehensively cover various workload scenarios and performance indicators that a processor may encounter by constructing a collection of code snippets of multiple different categories. In this way, when evaluating the performance of each core unit, the performance of the core unit under different operations and tasks can be more accurately reflected, thereby improving the accuracy and reliability of the evaluation. In addition, the design of the code snippet collection can be flexibly adjusted according to the evaluation objectives and possible workload scenarios. This means that as processor technology develops and workloads change, the code snippet collection can be updated or expanded to adapt to new evaluation requirements and maintain the timeliness and effectiveness of the evaluation method.

[0116] In addition, the present disclosure evaluates the degree of performance degradation of the core unit based on the health index, which makes the evaluation results more objective, comparable and easy to understand. Through the health index, the performance status of the core unit, as well as the degree and trend of performance degradation can be intuitively understood. In addition, the health index can also be used to monitor slight changes in the performance of the core unit, thereby achieving early warning of performance degradation, which helps to promptly discover and deal with potential performance problems, and avoid further deterioration of the problem and leading to more serious consequences. Moreover, by analyzing the changes and trends of the health index, the main causes and key factors of performance degradation can be determined, so that targeted optimization measures can be taken to improve the performance stability and reliability of the core unit.

[0117] In summary, the present disclosure evaluates the performance of each core unit based on a set of code snippets of multiple different categories, and uses a health index to evaluate the degree of performance degradation of each core unit, thereby achieving a comprehensive, accurate, flexible and quantitative evaluation of processor performance, providing strong support for processor optimization and maintenance.

[0118] According to an embodiment of the present disclosure, the chip further includes: a built-in fault register, and the fault diagnosis module is further configured to: The performance degradation degree of the core unit with the degradation fault is saved in the built-in fault register, so that when the chip is working, the designated program reads the performance degradation degree of the core unit with the degradation fault stored in the built-in fault register, and schedules each core unit when allocating tasks based on the following method: first, the core unit without fault is selected for use, and then the corresponding remaining core units are selected for use in order of performance degradation degree from low to high until all core units are used.

[0119] The present disclosure can record and save the performance degradation information of the core unit in real time through the setting of the built-in fault register, which is essential for continuously monitoring the health status of the chip, so that the system can timely understand which core units have degradation faults and their severity. In addition, by reading the information in the built-in fault register, the specified program can adopt a more optimized scheduling strategy when allocating tasks, for example: first choose to use the core unit without faults to ensure that high-performance tasks can be executed smoothly; then choose to use the remaining core units in order from low to high performance degradation. This strategy helps to balance the overall performance and resource utilization, avoid allocating important tasks to the core unit whose performance has been significantly degraded, thereby improving the overall efficiency and stability of the system; and the existence of the built-in fault register enables the system to identify and respond to potential faulty core units in advance. Through reasonable task scheduling, it can avoid over-reliance on the core unit with degraded performance, reduce the risk of system crash caused by core unit failure, and significantly improve the reliability and stability of the chip.

[0120] It should be noted that: Figure 3-5 The implementation methods in the three specific examples described can be used alone or in combination in specific applications. For example, an aging monitoring circuit, a performance counter, and an intermittent fault monitoring circuit can be set up in the chip at the same time, so that the detection of aging faults, intermittent faults, and core unit degradation faults can be supported at the same time. In this way, fault monitoring, diagnosis, and repair at the three levels of circuit, structure, and core unit are fully covered, which significantly improves the comprehensiveness and accuracy of fault detection and effectively improves the fault tolerance and reliability of the chip.

[0121] According to an embodiment of the present disclosure, determining the fault location of the chip based on the identification of the faulty component includes: searching for the physical location and / or logical location of the faulty component on the chip corresponding to the identification according to a preset component mapping table, wherein each entry in the component mapping table includes the identification of the chip component and the physical location and / or logical location corresponding to the chip component.

[0122] The step of evaluating the performance impact of the faulty component on the chip according to the performance degradation degree of the faulty component and the fault location, and generating fault evaluation data of the faulty component, comprises: The connection and data flow between the faulty component and other chip components associated with the faulty component are analyzed according to the physical location and / or logical location of the faulty component on the chip to determine the scope of the fault impact.

[0123] According to the performance degradation degree of the faulty component and the scope of the fault impact, the performance impact of the faulty component on the chip is quantified based on a preset performance impact model to generate a performance impact quantification result. The performance impact model can be established based on historical data or simulation results to evaluate the degree of performance degradation under different fault conditions.

[0124] Fault assessment data of the faulty component is generated based on the identification of the faulty component, the degree of performance degradation of the faulty component, the fault location, the scope of the fault impact, and the performance impact quantification result. Specifically, By considering the specific location of the faulty component on the chip (whether physical or logical), the present disclosure can more accurately identify which components or functions may be directly affected, thereby improving the accuracy of fault judgment. At the same time, by understanding the location and impact range of the faulty component, it is helpful to more accurately locate the root cause of the fault, so that more targeted repair measures can be taken.

[0125] According to an embodiment of the present disclosure, generating a fault repair strategy based on the fault assessment data includes: Determine, according to the fault assessment data, a repair method corresponding to the faulty component, the repair method including one or more of the following methods: When the faulty component cannot be repaired, the faulty component is decoupled from the chip. For example, the faulty component is so damaged that it cannot be repaired by existing technical means, or the cost of repair is too high to be economically viable. In this case, it is usually necessary to remove or decouple the faulty component from the system to avoid it from causing greater impact on the entire system. When decoupling, it can be achieved by marking the faulty component as unavailable.

[0126] When the faulty component is repairable and is a reconfigurable component, reconfiguring the faulty component includes: adjusting the operating frequency and / or operating mode of the faulty component. For example, the core units initially have the same maximum frequency Fmax, but as they age and degrade, the Fmax of each core unit may be different. If the critical path delay of a core unit increases due to aging, the function can be maintained by reducing the operating frequency to accommodate the additional delay.

[0127] When the chip includes a spare component or a redundant path, the spare component or the redundant path is enabled to replace the failed component.

[0128] Dynamically adjusting the resource configuration of the chip according to the fault assessment data includes: reallocating memory and / or adjusting cache strategy.

[0129] According to an embodiment of the present disclosure, generating a fault repair strategy based on the fault assessment data includes: The severity and urgency of the fault are evaluated according to the fault evaluation data to determine a repair priority corresponding to the faulty component.

[0130] When there are multiple faulty components, the faulty components are sorted in order of their repair priorities, so that the faulty components are repaired in the sorted order.

[0131] When faced with multiple faulty components, the present disclosure determines the repair priority by evaluating the severity and urgency of each fault, thereby ensuring that the most urgent and important faults are resolved first, which helps to optimize the allocation of maintenance resources and avoid waste and delays of resources.

[0132] Figure 6 A flowchart of an on-chip fault-tolerant processing method according to an embodiment of the present disclosure is shown. The method is applied to an on-chip fault-tolerant processing system, the system is set on a chip, the chip includes multiple chip components, the system includes: a fault detection module, a fault diagnosis module and a fault repair module, the fault detection module, the fault diagnosis module and the fault repair module are sequentially connected in communication, the fault detection module includes: a monitoring component, the monitoring component and the fault repair module are respectively connected in communication with one or more chip components, such as Figure 6 As shown, the method includes the following steps S610~S630: In step S610, the fault detection module obtains monitoring data of the one or more chip components according to a preset period based on the monitoring component; determines whether the chip fails based on the monitoring data and a preset fault model; if a fault occurs, obtains fault information, and sends the fault information to the fault diagnosis module, the fault information includes: an identifier of the faulty component and fault data of the faulty component, the faulty component being the chip component in which the fault occurs among the one or more chip components.

[0133] In step S620, the fault diagnosis module determines the fault location of the chip based on the identification of the faulty component, determines the degree of performance degradation of the faulty component based on the fault data of the faulty component, evaluates the impact of the faulty component on the performance of the chip according to the performance degradation degree of the faulty component and the fault location, and generates fault assessment data of the faulty component.

[0134] In step S630, a fault repair strategy is generated by the fault repair module based on the fault assessment data, so as to perform fault repair on the fault component based on the fault repair strategy.

[0135] Figure 7 A flowchart of another on-chip fault-tolerant processing method according to an embodiment of the present disclosure is shown. In addition to the fault detection module, the fault diagnosis module and the fault repair module, the on-chip fault-tolerant processing system further includes: a fault repair effect evaluation module, the fault repair effect evaluation module is respectively connected to one or more chip components and the fault repair module, such as Figure 7 As shown, in addition to the above steps S610-630, the method further includes the following step S640: In step S640, the state parameters of the faulty component and / or the performance parameters of the chip after the fault is repaired are obtained through the fault repair effect evaluation module; based on a preset analysis model, an evaluation result is obtained according to the state parameters of the faulty component and / or the performance parameters of the chip; and the fault repair strategy is dynamically adjusted according to the evaluation result.

[0136] Figure 8 FIG. 1 shows a structural block diagram of an electronic device according to an embodiment of the present disclosure. Figure 8 As shown, the electronic device includes a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method described in any one of the above method embodiments.

[0137] The present disclosure also provides a chip, comprising a system as described in any one of the above system embodiments; or, comprising a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement a method as described in any one of the above method embodiments.

[0138] The present disclosure also provides a computer-readable storage medium, which may be a computer-readable storage medium included in the electronic device or computer system in the above embodiment; or a computer-readable storage medium that exists independently and is not assembled into a device. The computer-readable storage medium stores one or more programs, and the programs are used by one or more processors to execute the method described in the present disclosure.

[0139] The present disclosure also provides a computer program product, including a computer program, which implements any method described in the present disclosure when the computer program is executed by a processor.

[0140] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. An on-chip fault-tolerant processing system, characterized in that: The system is arranged on a chip, the chip includes a plurality of chip components, the system includes: a fault detection module, a fault diagnosis module and a fault repair module, the fault detection module, the fault diagnosis module and the fault repair module are sequentially connected in communication, the fault detection module includes: a monitoring component, the monitoring component and the fault repair module are respectively connected in communication with one or more chip components, wherein: The fault detection module is configured to: based on the monitoring component, obtain monitoring data of the one or more chip components according to a preset period; determine whether the chip fails according to the monitoring data and a preset fault model; if a fault occurs, obtain fault information, and send the fault information to the fault diagnosis module, the fault information including: an identifier of a faulty component and fault data of the faulty component, the faulty component being the chip component in which the fault occurs among the one or more chip components; The fault diagnosis module is configured to: determine the fault location of the chip based on the identifier of the faulty component, determine the performance degradation degree of the faulty component based on the fault data of the faulty component, evaluate the performance impact of the faulty component on the chip according to the performance degradation degree of the faulty component and the fault location, and generate fault evaluation data of the faulty component; The fault repair module is configured to generate a fault repair strategy based on the fault assessment data, so as to perform fault repair on the fault component based on the fault repair strategy.

2. The system according to claim 1, characterized in that The system further includes: a fault repair effect evaluation module, wherein the fault repair effect evaluation module is respectively connected to the one or more chip components and the fault repair module for communication, and the fault repair effect evaluation module is configured to: Obtaining state parameters of the faulty component and / or performance parameters of the chip after the fault is repaired; Based on a preset analysis model, obtaining an evaluation result according to the state parameters of the faulty component and / or the performance parameters of the chip; The fault repair strategy is dynamically adjusted according to the evaluation result.

3. The system according to claim 1, characterized in that The monitoring component includes: an aging monitoring circuit, the chip assembly includes: a monitored unit, the aging monitoring circuit is in communication connection with the monitored unit in the chip assembly, the monitoring data includes: signal conversion data of the monitored unit within a preset protection period of a clock cycle, the signal conversion data is used to indicate whether a signal conversion occurs within the preset protection period of the clock cycle, and judging whether the chip fails according to the monitoring data and a preset fault model includes: When the signal conversion data indicates that the monitored unit has a signal conversion within the preset protection period of the clock cycle, an aging fault has occurred accordingly; When the aging fault occurs, the acquiring of fault information includes: acquiring the frequency of the signal conversion, and using the acquired frequency of the signal conversion as the fault data of the faulty component to form the fault information; The method of determining the degree of performance degradation of the faulty component based on the fault data of the faulty component includes: comparing the frequency at which the signal conversion occurs with a preset frequency threshold, obtaining the difference between the frequency at which the signal conversion occurs and the preset frequency threshold, and determining the degree of performance degradation corresponding to the difference based on the difference and a preset difference performance degradation degree comparison table.

4. The system according to claim 3, characterized in that The chip component also includes: a fault adaptive repair unit, the fault repair module is communicatively connected to the fault adaptive repair unit in the chip component, and the fault repair module is further configured to: send the fault repair strategy to the fault adaptive repair unit in the fault component, so that the fault adaptive repair unit in the fault component performs fault repair based on the fault repair strategy.

5. The system according to claim 1, characterized in that The chip includes: a multi-core processor, the multi-core processor includes a plurality of core units, the plurality of chip components correspond to the plurality of core units respectively, the monitoring component includes: a plurality of performance counters, the plurality of performance counters correspond to the plurality of core units one by one respectively, and the monitoring data of the plurality of chip components are obtained according to a preset period, including: Acquire a code snippet set, the code snippet set comprising a plurality of code snippets of different categories, each category of code snippets comprising a plurality of instruction operations of different categories, and each category of instruction operations comprising a plurality of instruction operations corresponding to the category; Based on the performance counters corresponding to the core units, the performance parameters of the code snippets in the code snippet set respectively executed by the core units are obtained, and the performance parameters of the code snippets in the code snippet set respectively executed by the core units are used as the monitoring data of the multiple chip components; The determining whether the chip fails according to the monitoring data and a preset fault model includes: forming a health index of each core unit based on the performance parameters of each code snippet in the code snippet set respectively executed by each core unit and the performance parameters of the reference core unit, judging whether the chip fails based on the health index, and when the health index of any core unit is lower than a preset reference threshold, the any core unit has a degradation fault, and the chip component corresponding to the any core unit is regarded as a faulty component; When the degradation fault occurs, the acquiring of fault information includes: using the health index of the core unit where the degradation fault occurs as the fault data of the faulty component to form the fault information; Determining the performance degradation degree of the faulty component based on the fault data of the faulty component includes: comparing the health index of the core unit where the degradation fault occurs with a plurality of preset index value intervals, wherein each index value interval corresponds to a performance degradation characterization parameter; The performance degradation degree of the core unit where the degradation fault occurs is obtained based on the comparison result.

6. The system according to claim 5, characterized in that in, The chip further includes: a built-in fault register, and the fault diagnosis module is further configured to: The performance degradation degree of the core unit with the degradation fault is saved in the built-in fault register, so that when the chip is working, the designated program reads the performance degradation degree of the core unit with the degradation fault stored in the built-in fault register, and schedules each core unit when allocating tasks based on the following method: first, the core unit without fault is selected for use, and then the corresponding remaining core units are selected for use in order of performance degradation degree from low to high until all core units are used.

7. The system according to claim 1, characterized in that The chip includes: a processor, the processor includes a plurality of processor structures, the processor structure includes a predefined ACE bit and a non-ACE bit, the ACE bit is used to indicate that when a program is executed, if the value of the ACE bit changes, it will cause the program execution error and thus affect the digit of the program output result, and the non-ACE bit is used to indicate that when a program is executed, if the value of the non-ACE bit changes, it will not cause the program execution error and thus will not affect the digit of the program output result, the plurality of chip components correspond to the plurality of processor structures, the monitoring component includes: an intermittent fault monitoring circuit, the judging whether the chip fails according to the monitoring data and a preset fault model includes: When it is determined based on the monitoring data acquired by the intermittent fault monitoring circuit that a specified digit in the processor structure is fixed to 1 or 0 within a specified time interval, an intermittent fixed 1 / 0 fault occurs accordingly; When it is determined based on the monitoring data obtained by the intermittent fault monitoring circuit that the bit line of the processor structure is open or short-circuited, an intermittent open / short circuit fault occurs accordingly; When it is determined based on the monitoring data obtained by the intermittent fault monitoring circuit that the circuit behavior of the processor structure does not conform to the preset behavior and thus causes a timing violation, an intermittent timing fault occurs accordingly; The obtaining of fault information includes: when the chip has an intermittent fixed 1 / 0 fault, an intermittent open circuit / short circuit fault or an intermittent timing fault, determining whether the fault affects the value of the ACE bit of the processor structure, and if so, determining an intermittent fault sensitivity parameter of the processor structure where the fault occurs based on the fault that occurs and the number of affected ACE bits in the processor structure where the fault occurs, and using the intermittent fault sensitivity parameter of the processor structure where the fault occurs as the fault data of the fault component to form the fault information, wherein the intermittent fault sensitivity parameter is used to characterize the probability of the fault occurring in the processor structure being manifested in the program output; The determining the performance degradation degree of the faulty component based on the fault data of the faulty component comprises: comparing the intermittent fault sensitivity parameter of the processor structure where the fault occurs with a plurality of preset sensitivity parameter intervals, wherein each sensitivity parameter interval corresponds to a sensitivity characterization parameter; Based on the comparison result, a sensitivity characterization parameter of the processor structure where the fault occurs is obtained, and the obtained sensitivity characterization parameter is used as the degree of performance degradation.

8. The system according to claim 7, characterized in that The determining of the intermittent fault sensitivity parameter of the processor structure where the fault occurs based on the fault that occurs and the number of ACE bits affected in the processor structure where the fault occurs comprises: When the fault is an intermittent fixed 1 / 0 fault, the intermittent fault sensitivity parameter of the processor structure where the intermittent fixed 1 / 0 fault occurs is determined by the following method: : Wherein, B represents the total number of bits in the processor structure, a represents the specified position in the processor structure, L represents the duration of the intermittent fixed 1 / 0 fault, It is used to indicate whether the ACE bit at the specified position is changed by the intermittent fixed 1 / 0 fault within the burst duration. If it is changed, is 1, otherwise it is 0; represents the number of ACE bits changed during the duration of the intermittent fixed 1 / 0 fault; When the fault is an intermittent open circuit / short circuit fault, the intermittent fault sensitivity parameter of the processor structure where the intermittent open circuit / short circuit fault occurs is determined by the following method: : Wherein, N represents the number of intermittent open circuit / short circuit faults occurring in the processor structure, Indicates whether the ACE bit in the processor architecture has been changed to specify intermittent open / short faults. If changed, is 1, otherwise it is 0; When the fault is an intermittent timing fault, the intermittent fault sensitivity parameter of the processor structure where the intermittent timing fault occurs is determined by the following method: : Wherein, NUM represents the number of intermittent timing faults that occur during the execution of a specified program by the processor, Indicates the number of intermittent timing faults occurring in the processor structure, representing the number of said intermittent timing faults affecting only invalid data in said processor architecture, Represents the number of said intermittent timing faults that affect only non-ACE bits in said processor architecture.

9. The system according to claim 1, characterized in that The determining the fault location of the chip based on the identifier of the faulty component comprises: searching for the physical location and / or logical location of the faulty component on the chip corresponding to the identifier according to a preset component mapping table, wherein each entry in the component mapping table comprises the identifier of the chip component and the physical location and / or logical location corresponding to the chip component; The step of evaluating the performance impact of the faulty component on the chip according to the performance degradation degree of the faulty component and the fault location, and generating fault evaluation data of the faulty component, comprises: Analyze the connection and data flow between the faulty component and other chip components associated with the faulty component according to the physical location and / or logical location of the faulty component on the chip to determine the scope of the fault impact; According to the performance degradation degree of the faulty component and the scope of the fault impact, quantify the performance impact of the faulty component on the chip based on a preset performance impact model, and generate a performance impact quantification result; Fault assessment data of the faulty component is generated based on the identification of the faulty component, the degree of performance degradation of the faulty component, the fault location, the scope of the fault impact, and the performance impact quantification result.

10. The system according to claim 1, characterized in that Generating a fault repair strategy based on the fault assessment data includes: Determine, according to the fault assessment data, a repair method corresponding to the faulty component, the repair method including one or more of the following methods: When the faulty component cannot be repaired, decoupling the faulty component from the chip; When the faulty component is repairable and is a reconfigurable component, reconfiguring the faulty component includes: adjusting the operating frequency and / or operating mode of the faulty component; When the chip includes a spare component or a redundant path, enabling the spare component or the redundant path to replace the failed component; Dynamically adjusting the resource configuration of the chip according to the fault assessment data includes: reallocating memory and / or adjusting cache strategy.

11. The system according to claim 1, characterized in that Generating a fault repair strategy based on the fault assessment data includes: According to the fault assessment data, assess the severity and urgency of the fault to determine a repair priority corresponding to the faulty component; When there are multiple faulty components, the faulty components are sorted in order of their repair priorities, so that the faulty components are repaired in the sorted order.

12. An on-chip fault tolerance processing method, characterized in that: The method is applied to an on-chip fault-tolerant processing system, the system is arranged on a chip, the chip includes a plurality of chip components, the system includes: a fault detection module, a fault diagnosis module and a fault repair module, the fault detection module, the fault diagnosis module and the fault repair module are sequentially connected in communication, the fault detection module includes: a monitoring component, the monitoring component and the fault repair module are respectively connected in communication with one or more chip components, the method includes: The fault detection module obtains monitoring data of the one or more chip components according to a preset period based on the monitoring component; determines whether the chip fails according to the monitoring data and a preset fault model; if a fault occurs, obtains fault information, and sends the fault information to the fault diagnosis module, the fault information including: an identifier of a faulty component and fault data of the faulty component, the faulty component being the chip component in which the fault occurs among the one or more chip components; Determine the fault location of the chip based on the identifier of the faulty component by the fault diagnosis module, determine the performance degradation degree of the faulty component based on the fault data of the faulty component, evaluate the performance impact of the faulty component on the chip according to the performance degradation degree of the faulty component and the fault location, and generate fault evaluation data of the faulty component; A fault repair strategy is generated by the fault repair module based on the fault assessment data, so as to perform fault repair on the faulty component based on the fault repair strategy.

13. The method according to claim 12, characterized in that The system further includes: a fault repair effect evaluation module, wherein the fault repair effect evaluation module is respectively connected to one or more chip components and the fault repair module for communication. The method further includes: The fault repair effect evaluation module is used to obtain the state parameters of the fault component and / or the performance parameters of the chip after the fault repair; based on a preset analysis model, an evaluation result is obtained according to the state parameters of the fault component and / or the performance parameters of the chip; and the fault repair strategy is dynamically adjusted according to the evaluation result.

14. A chip, characterized in that: A system comprising any one of claims 1 to 11; or comprising a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method of any one of claims 12 to 13.

15. An electronic device, characterized in that: Comprising a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method described in any one of claims 12 to 13.

16. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the method according to any one of claims 12 to 13 is implemented.

17. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 12 to 13 is implemented.

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