Data backup method and device based on cache line, processor and computing equipment

Abstract

The invention discloses a data backup method and device based on a cache line, a processor and computing equipment, and belongs to the technical field of storage. In the method, in response to a first data writing instruction, data in the first data writing instruction is written into a first cache line in a cache, so that the state of the first cache line is a modified state, and a backup cache line of the first cache line is stored in the cache. In the method, the modified state indicates that the data in the first cache line is the new data, does not exist in other caches and is inconsistent with the data in the memory, so that the backup cache line storing the first cache line in the cache can avoid the problem of data inconsistency caused by errors of the data in the first cache line.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a cache line-based data backup method, device, processor and computing equipment. Background Art

[0002] Cache memory (cache for short) is a high-speed, small-capacity memory between the central processing unit (CPU) and the memory in the hierarchical structure of the computer storage system. The cache is divided into the first-level cache (L1 cache), the second-level cache (L2 cache) and the third-level cache (L3 cache). The first-level cache, the second-level cache and the third-level cache are located away from the CPU in turn, and the capacity increases in turn, and the speed of querying data also slows down in turn. For a multi-core processor, each core has its own exclusive first-level cache and second-level cache, and all cores share the third-level cache. When the CPU writes data, it will first write the data to the cache; when the CPU reads data, it will first query the cache. When the required data is not found in the cache, it will read the data from the memory. The unit for storing data in the cache is the cache line.

[0003] In the related art, when any core in the CPU initiates a write instruction to the memory, the operating system first writes the data corresponding to the write instruction into the cache line in the cache corresponding to the core, and marks the status of the cache line based on the cache consistency protocol (modified exclusive shared invalid, MESI), wherein the status of the cache line is used to indicate the consistency status of the data in the caches corresponding to multiple CPU cores and the memory. For example, if the cache line is marked as modified (modified, M), it indicates that the data in the cache line is new data and is inconsistent with the data that does not exist in other caches and is inconsistent with the data in the memory.

[0004] However, in the above method, since the data in the cache line marked as modified in the cache is inconsistent with the data in other caches and the memory and only one copy is stored, the longer the data exists in the cache, the probability of bit flipping of the data will increase significantly, resulting in data errors in the cache, thereby reducing the reliability of the data. Summary of the invention

[0005] The embodiments of the present application provide a cache line-based data backup method, apparatus, processor and computing device, which can improve the reliability of stored data. The technical solution is as follows.

[0006] In a first aspect, a cache line-based data backup method is provided, the method comprising:

[0007] In response to a first data write instruction, data in the data write instruction is written to a first cache line in the cache, so that the state of the first cache line is a modified state, and the modified state indicates that the data in the first cache line is new data, does not exist in other caches and is inconsistent with the data in the memory.

[0008] The first data is data corresponding to the first write instruction, and the state of the first data is a modified state, which indicates that the first data is valid, exists only in the cache, and is inconsistent with the data in the memory. The first data satisfies the write-back condition, which means that the first cache line storing the first data needs to be used to store other data or backup data of other data, that is, the data in the first cache line needs to be replaced.

[0009] In the above method, since the state of the first data is a modified state, that is, it only exists in the cache and is inconsistent with the data in the memory, therefore, storing the backup data of the first data in the cache can avoid data inconsistency problems caused by errors in the first data, and only the backup data is stored in the cache for the data in the modified state, while the backup data for the data in the exclusive state (the data is consistent with the data in the memory) and the data in the shared state (the data also exists in other caches and is consistent with the data in the memory) are not stored in the cache, which can avoid excessive occupation of the cache by redundant backup data, thereby ensuring the cache hit rate while ensuring data reliability.

[0010] Optionally, in response to a first data write instruction, writing data in the first data write instruction into a first cache line in a cache includes:

[0011] In response to a write instruction to a memory address, data in the write instruction is written to a first cache line.

[0012] Optionally, in response to a first data write instruction, writing data in the first data write instruction into a first cache line in a cache includes:

[0013] In response to a write-back instruction to the cache at an upper level, data in the write-back instruction is written into the first cache line.

[0014] Optionally, the cache includes a plurality of groups, each group includes a plurality of cache lines, and a backup cache line of the first cache line is stored in the cache, including:

[0015] A backup cache line of the first cache line is stored in the group where the first cache line is located.

[0016] Optionally, storing a backup cache line of the first cache line in the group where the first cache line of the cache is located includes:

[0017] At least one second cache line is determined in the group where the first cache line is located; and the first cache line is copied to the at least one second cache line.

[0018] Optionally, the group to which the first cache line belongs includes 2N cache lines, wherein the i-th cache line corresponds to the N+i-th cache line, N is an integer greater than 1, and i is an integer greater than or equal to 0 and less than N;

[0019] Determining at least one second cache line in the group where the first cache line is located includes: determining a cache line corresponding to the first cache line in the group where the first cache line is located as the second cache line.

[0020] Optionally, determining at least one second cache line in the group where the first cache line is located includes any of the following:

[0021] Based on a least recently used algorithm, at least one second cache line is determined in the group where the first cache line is located; based on a first-in-first-out algorithm, at least one second cache line is determined in the group where the first cache line is located; based on a random replacement algorithm, at least one second cache line is determined in the group where the first cache line is located.

[0022] Among them, the least recently used algorithm (LRU) is used to determine the cache line that has been least accessed in the recent period as the second cache line; the first in first out (FIFO) algorithm is used to determine the cache line with the longest existence time as the second cache line; the random replacement algorithm (RAND, rand) is used to determine the cache line determined according to a random number as the second cache line.

[0023] Optionally, copying the first cache line to the at least one second cache line comprises:

[0024] If the state of the second cache line is exclusive, shared or invalid, the first cache line is copied to the second cache line; if the state of the second cache line is modified, the data in the second cache line is written back to the memory and the first cache line is copied to the second cache line.

[0025] Among them, the exclusive state indicates that the data in the second cache line does not exist in other caches and is consistent with the data in the memory, the shared state indicates that the data in the second cache line also exists in other caches and is consistent with the data in the memory, and the invalid state indicates that the data in the second cache line is invalid.

[0026] The second cache line may have stored other data before storing the first data, and the stored data may only exist in the cache, or may exist in both the cache and the memory or other caches. In order to avoid the problem of data loss caused by overwriting the data originally stored in the second cache line when writing and copying the first data to the second cache line, the computing device copies the first data to at least one second cache line based on the state of the data stored in the second cache line.

[0027] Optionally, the first cache line further includes a memory mirror mark, which is used to indicate whether data in a memory address corresponding to the first cache line has a backup in the memory, and storing a backup cache line of the first cache line in the cache includes:

[0028] If the memory mirror mark in the first cache line indicates that the data in the memory address corresponding to the first data write instruction has a backup in the memory, a backup cache line of the first cache line is stored in the cache.

[0029] Optionally, the method further comprises:

[0030] In response to a read instruction to the memory address, a first cache line and a backup cache line of a second cache line in the cache are checked respectively, the first cache line being the cache line corresponding to the memory address; if both the first cache line and the backup cache line of the first cache line are successfully checked, the data in the first cache line is returned; if only one of the first cache line and the backup cache line of the first cache line is successfully checked, the data in the successfully checked cache line is returned, and the cache line that failed to be checked is restored based on the successfully checked cache line.

[0031] Optionally, the cache line includes a tag, state information, a memory mirroring mark and data, the tag is used to indicate a memory address corresponding to the cache line, and the method further includes:

[0032] Error checking and correcting (ECC) is used to protect the tags, status information and memory mirroring tags in the cache line respectively, and cyclic redundancy check (CRC) is used to protect the data in the cache line.

[0033] Optionally, the method further comprises:

[0034] In response to a second data write instruction, the data in the second data write instruction is written into the first cache line in the cache; and the data in the backup cache line of the first cache line is overwritten with the data in the second data write instruction.

[0035] The second data write instruction may be a write instruction to a memory address or a write-back instruction to an upper-level cache.

[0036] In a second aspect, a cache line-based data backup device is provided, the device comprising at least one functional module, and the at least one functional module is used to execute the cache line-based data backup method provided by the first aspect or any possible implementation of the first aspect.

[0037] According to a third aspect, a processor is provided, wherein the processor is used to execute the cache line-based data backup method provided by the aforementioned first aspect or any possible implementation of the first aspect.

[0038] In a fourth aspect, a computing device is provided, which includes a processor and a memory, the memory storing program code, and the processor being used to execute the program code, so that the computing device executes the cache line-based data backup method provided by the first aspect or any possible implementation of the first aspect.

[0039] In a fifth aspect, a storage medium is provided, which is used to store at least one section of program code, and the at least one section of program code is used to execute the cache line-based data backup method provided by the first aspect or any possible implementation of the first aspect.

[0040] Based on the implementations provided in the above aspects, the present application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0042] Figure 2 It is a schematic diagram of a cache consistency architecture provided by an embodiment of the present application;

[0043] Figure 3 is a flow chart of a cache line-based data backup method provided by an embodiment of the present application;

[0044] Figure 4 It is a flow chart of a data backup method based on a cache line provided in an embodiment of the present application;

[0045] Figure 5 It is a flow chart of a data reading method in a cache line-based data backup method provided in an embodiment of the present application;

[0046] Figure 6 It is a flow chart of a data writing method in a cache line-based data backup method provided in an embodiment of the present application;

[0047] Figure 7 It is a structural schematic diagram of a cache line-based data backup device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0049] First, the structure of a computing device provided by an embodiment of the present application is introduced.

[0050] like Figure 1 As shown, Figure 1 1 is a schematic diagram of a computing device provided in an embodiment of the present application. The computing device 100 may be a host, a server, or a personal computer, etc. The computing device 100 may be implemented by a general bus architecture.

[0051] The computing device 100 includes at least one processor 101 , a communication bus 102 , a memory 103 , and at least one communication interface 104 .

[0052] The processor 101 is, for example, a general-purpose central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, the processor 101 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0053] The communication bus 102 is used to transmit information between the above components. The communication bus 102 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 1The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0054] The memory 103 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 103 is, for example, independent and connected to the processor 101 via the communication bus 102. The memory 103 can also be integrated with the processor 101.

[0055] The communication interface 104 uses any transceiver-like device for communicating with other devices or communication networks. The communication interface 104 includes a wired communication interface and may also include a wireless communication interface. Among them, the wired communication interface may be, for example, an Ethernet interface. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. The wireless communication interface may be a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof, etc.

[0056] As an embodiment, the processor 101 may include one or more CPUs.

[0057] As an embodiment, the computing device 100 may include multiple processors, each of which may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits and / or processing cores for processing data (such as program code).

[0058] As an embodiment, the computing device 100 may further include an output device and an input device. The output device communicates with the processor 101 and may display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 101 and may receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0059] In some embodiments, the memory 103 is used to store program codes for executing the solution of the present application, and the processor 101 can execute the program codes stored in the memory 103. That is, the computing device 100 can implement the cache line-based data backup method provided by the method embodiment through the processor 101 and the program codes in the memory 103.

[0060] The present application embodiment relates to a cache consistency architecture in a computing device. To facilitate understanding of the content of the present application embodiment, the following is combined with Figure 2 Explain several technical terms involved in cache consistency architecture.

[0061] Figure 2 is a schematic diagram of a cache consistency architecture provided by an embodiment of the present application, such as Figure 2 As shown, the cache consistency architecture includes multiple CPU cores (core1 and core2), cache memory and memory.

[0062] Among them, cache memory (cache): referred to as cache or cache, is a high-speed, small-capacity memory between the CPU and the memory in the hierarchical structure of the computer storage system. When the CPU needs a piece of data, it will first query the cache. When the required data is not found in the cache, the data will be read from the memory. The cache is divided into a first-level cache (L1cache), a second-level cache (L2 cache) and a third-level cache (L3cache). Among them, the first-level cache, the second-level cache and the third-level cache are successively farther away from the CPU, the capacity increases successively, and the speed of querying data also slows down successively. When the CPU needs a piece of data, it will first query the first-level cache. When the data is not found in the first-level cache, it will query the second-level cache. When the data is not found in the second-level cache, it will query the third-level cache. If the data is not found in the third-level cache, it will query the memory. For multi-core processors, each core has its own corresponding first-level cache and second-level cache, and all cores share the third-level cache. Since the data required by the CPU changes over time, part of the data stored in the cache will become data that is not frequently accessed by the CPU over time. These data that are not frequently accessed by the CPU will be written back to the memory level by level to avoid excessive occupation of the cache. Among them, level-by-level write-back means that when the data in the high-level cache meets the write-back condition, the data is written to the low-level cache, and when the data in the lowest level cache meets the write-back condition, the data is written to the memory. For example, when the data in the first-level cache meets the write-back condition, the data in the first-level cache is written to the second-level cache; when the data in the second-level cache meets the write-back condition, the data in the second-level cache is written to the third-level cache; when the data in the third-level cache meets the write-back condition, the data in the third-level cache is written to the memory.

[0063] Cache line: It is the unit for storing data in the cache and the smallest unit for data exchange between the cache and the memory. In some embodiments, the capacity of the cache line is limited to the amount of data that can be accessed in one storage cycle of the main memory (ie, the memory).

[0064] Entry: In this application, it refers to an entry in the cache that contains a tag, data, and attribute fields, corresponding to a cache line. Among them, tag is used to indicate the memory address, data is used to store data, and attribute is used to store the attribute information of the cache line. For multi-core CPUs, based on the cache consistency protocol, the MESI state is used to describe the state of the data in the cache line. Correspondingly, the attribute field in the entry stores the MESI state of the cache line, where the MESI state can be described in Table 1 below. For a single-core CPU, the state of the cache line is described by the value of the target bit (dirty valid) of the cache line. For example, the value of dirty valid is 00, indicating that the data in the cache line is invalid (corresponding to the I state in MESI), the value of dirty valid is 01, indicating that the data in the cache line is valid and has not been modified (corresponding to the E state in MESI), the value of dirty valid is 10, indicating that the state is illegal, and the value of dirty valid is 11, indicating that the data in the cache line is valid and has been modified (corresponding to the M state in MESI). Correspondingly, the attribute field in the entry stores the dirty valid of the data. In some embodiments, the attribute field in the entry also stores a memory mirroring flag (mirroring flag, MF), which is used to indicate whether the data in the memory address corresponding to the cache line is backed up in the memory.

[0065] Table 1

[0066]

[0067] Snoop filter (SF): It is a part of the cache memory, at the same level as the third-level cache, and is used to solve the problem of cache consistency. SF will snoop the write instructions of other cores and invalidate the data in the local cache when necessary to ensure the consistency of the same data in the caches corresponding to multiple cores (this process is also the snoop process). SF records the tag of the cache line, the MESI status, and the core number where the cache line is located. Among them, snooping means that the local core sends the read / write request to other specific cores through the bus, allowing the core that receives the request to respond to the read / write request according to the local situation.

[0068] Write back: When the CPU initiates a write instruction to the memory, it is only temporarily written to the cache and marked with a flag. The data is not written from the cache to the memory until it is evicted, flushed, or snooped.

[0069] Based on the cache consistency structure in the computing device, the embodiment of the present application provides a data backup method based on a cache line, wherein, in response to a first data write instruction, the data in the first data write instruction is written into a first cache line in the cache, so that the state of the first cache line is a modified state, and a backup cache line of the first cache line is stored in the cache. In the above method, the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in the memory. Therefore, storing the backup cache line of the first cache line in the cache can avoid the data inconsistency problem caused by the error of the data in the first cache line, and only for the cache line in the modified state, its backup cache line is stored in the cache, and for the cache line in the exclusive state (the data only exists in the cache and is consistent with the data in the memory) and the shared state (the data also exists in other caches and is consistent with the data in the memory), its backup cache line is not stored in the cache, which can avoid excessive occupation of the cache by redundant backups, thereby ensuring the hit rate of the cache while ensuring data reliability.

[0070] The above introduces the basic process of a cache line-based data backup method provided by an embodiment of the present application. The following describes the process of the method in detail. Figure 3 is a flow chart of a cache line-based data backup method provided by an embodiment of the present application, such as Figure 3 As shown, taking the method executed by a computing device as an example, the method includes the following steps 301 to 304.

[0071] 301. In response to a first data write instruction, the computing device writes the data in the first data write instruction to a first cache line in a cache, so that the state of the first cache line is a modified state, and the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in the memory.

[0072] Wherein, the first data write instruction can be a write instruction to a memory address, and correspondingly, writing the data in the first data write instruction to the first cache line in the cache is to write the data in the write instruction to the first cache line; the first data write instruction can also be a write-back instruction to the cache of the previous level, and correspondingly, writing the data in the first data write instruction to the first cache line in the cache is to write the data in the write-back instruction to the first cache line. The cache refers to the cache corresponding to the CPU core that initiates the first data write instruction in the computing device, including the first-level cache, the second-level cache and the third-level cache corresponding to the CPU core. Correspondingly, other caches refer to other caches in the computing device except the cache corresponding to the CPU core. Since multiple CPU cores share the third-level cache, other caches are also the first-level cache and the second-level cache exclusively occupied by other CPU cores. The cache includes multiple cache lines, each of which stores a tag, data and attribute information. The attribute information includes the state of the cache line and the memory mirror mark.

[0073] The computing device determines a first cache line in the cache in response to the first data write instruction, and writes the data in the first data write instruction into the determined first cache line.

[0074] The computing device determines the first cache line in the cache by means of set associative mapping. In this mapping mode, the cache includes multiple groups, each group includes multiple cache lines, the first character string in the memory address carried by the first data write instruction is a comparison tag, the second character string is a group index, and the third character string is an offset. The process of the computing device determining the first cache line in the cache includes: determining the group corresponding to the group index in the cache according to the group index in the memory address; comparing the comparison tag in the memory address with the tags in the multiple cache lines in the determined group; if the tag of any cache line in the group is consistent with the comparison tag (that is, a write hit), then the cache line is determined as the first cache line; if the tags of each cache line in the group are inconsistent with the comparison tag, and the cache is full (that is, a write miss and the cache is full), then a cache line is determined in the cache as the first cache line; if the tags of each cache line in the group are inconsistent with the comparison tag, and the cache is not full (that is, a write miss and the cache is not full), then any idle cache line in the group is used as the first cache line. In the above three cases, the process of the computing device writing the data in the first data write instruction into the first cache line is different. The process of writing the data into the first cache line in the above three cases will be introduced below.

[0075] The first case: write hit. The computing device writes the data in the first data write instruction into the first cache line based on the state of the first cache line. If the original state of the first cache line is a modified state or an exclusive state, the computing device directly overwrites the data originally stored in the first cache line with the data in the first data write instruction; if the original state of the first cache line is a shared state, the computing device will snoop (snoop) to let other cores with the same data set the state of the corresponding cache line to an invalid state, so that the state of the first cache line in this cache is an exclusive state, and then overwrite the data originally stored in the first cache line with the data in the first data write instruction. This process can be understood as the need to modify the state of the first cache line to a modified state or an exclusive state before writing data.

[0076] The second situation: the write misses and the cache is full. The computing device writes the data in the first data write instruction to the first cache line based on the state of the first cache line. If the original state of the first cache line is a modified state, the computing device first writes back the data originally stored in the first cache line, and then sets the state of the first cache line to an invalid state; if the original state of the first cache line is an exclusive state or a shared state, the computing device directly sets the state of the first cache line to an invalid state, and notifies SF to update the state of the first cache line, and for the data originally stored in the first cache line, the computing device first queries the state recorded in SF, if there is no record in SF, then queries the third-level cache and memory, if other caches store the same data as the first cache line in the cache, then the local core uses snoop to let other cores with the same data set the state of the corresponding cache line to an invalid state, and then the local core writes the data in the first data write instruction to the first cache line.

[0077] The third case: write miss and cache is not full. The calculation first queries the status of the record in the query SF. If there is no record in the SF, the third-level cache and memory are queried. If other caches store the same data as the first cache line in the cache, the local core uses snoop to let other cores with the same data set the status of the corresponding cache line to invalid, and the local core then writes the data in the first data write instruction to the first cache line.

[0078] 302. The computing device determines at least one second cache line in the group where the first cache line is located.

[0079] Among them, the second cache line is used as a backup cache line for the first cache line, and the number of the second cache lines can be set according to actual needs. For example, if the reliability requirement for the data in the first cache line is higher, the number of backup cache lines for the first cache line is greater, that is, the number of second cache lines is greater; if the reliability requirement for the data in the first cache line is lower, the number of backup cache lines for the first cache line is smaller, that is, the number of second cache lines is smaller. The embodiment of the present application does not limit the number of backup cache lines for the first cache line, and thus does not limit the number of second cache lines.

[0080] The computing device determines the second cache line in the group where the first cache line is located based on a fixed strategy or a non-fixed strategy. The determination of the second cache line under the fixed strategy and the determination of the second cache line under the non-fixed strategy are respectively introduced below.

[0081] Fixed strategy: The position of the backup cache line corresponding to each cache line is fixed. The group where the first cache line is located includes 2N cache lines, where the i-th cache line corresponds to the N+i-th cache line, N is an integer greater than 1, and i is an integer greater than or equal to 0 and less than N; the computing device determines the cache line corresponding to the first cache line in the group where the first cache line is located as the second cache line. It should be noted that the above-mentioned cache line correspondence method is only exemplary, and the cache line correspondence method can be determined according to the number of backup cache lines, which is not limited in the embodiments of the present application.

[0082] Non-fixed strategy: The position of the backup cache line corresponding to each cache line is not fixed. The process of the computing device determining at least one second cache line in the group where the first cache line is located includes any of the following methods: the first method: based on the least recently used algorithm, at least one second cache line is determined in the group where the first cache line is located; the second method: based on the first-in-first-out algorithm, at least one second cache line is determined in the group where the first cache line is located; the third method: based on the random replacement algorithm, at least one second cache line is determined in the group where the first cache line is located. Among them, the least recently used algorithm (least recently used, LRU) is used to determine the cache line that has been least accessed in the recent period of time as the second cache line; the first-in first out algorithm (first in first out, FIFO) is used to determine the cache line with the longest existence time as the second cache line; the random replacement algorithm (RAND, rand) is used to determine the cache line determined according to a random number as the second cache line. It should be noted that the above three replacement algorithms are only exemplary and can be set according to actual needs. The embodiments of the present application do not limit this.

[0083] In some embodiments, the attribute information of the first cache line includes a memory mirroring mark. If the memory mirroring mark in the first cache line indicates that the data in the memory address corresponding to the first cache line has a backup in the memory, the computing device determines at least one second cache line in the group where the first cache line is located to store the backup cache line of the first cache line in the cache. In the above method, when the memory side performs mirroring protection for the data in the memory address corresponding to the first data write instruction, the backup of the data is stored on the cache side, that is, selectively mirroring is performed on the cache side, which can avoid the problem that the data protection effect of the cache side is greatly reduced due to the fact that the cache side performs mirroring but the memory side does not perform mirroring. At the same time, selectively mirroring on the cache side can increase the proportion of valid data in the cache while ensuring the reliability of the cache side data, and avoid excessive occupation of the cache by the backup data, resulting in a decrease in the cache hit rate.

[0084] 303. The computing device copies the first cache line to at least one second cache line based on a state of the at least one second cache line, so as to store a backup cache line of the first cache line in the cache.

[0085] The second cache line may have stored other data before storing the data in the first cache line, and the stored data may exist only in the cache, or may exist in both the cache and the memory or other caches.

[0086] Among them, taking copying the first cache line to any second cache line as an example, the computing device copies the first cache line to the second cache line based on the state of the second cache line, including: if the state of the second cache line is an exclusive state, a shared state or an invalid state, copying the first cache line to the second cache line; if the state of the second cache line is a modified state, writing the data in the second cache line back to the memory, and then copying the first cache line to the second cache line.

[0087] It should be noted that the above steps 302 and 303 are one implementation method of storing the backup cache line of the first cache line in the cache. In some embodiments, the steps are also implemented based on other methods, which is not limited in the embodiments of the present application.

[0088] 304. In response to the first cache line satisfying the write-back condition, the computing device writes the data in the first cache line back to the memory level by level.

[0089] Among them, the first cache line meets the write-back condition means that the first cache line needs to be used to store other data or backup data of other data, that is, the data in the first cache line needs to be replaced. Level-by-level write-back means that when the data in the high-level cache meets the write-back condition, the data is written to the low-level cache, and when the data in the lowest level cache meets the write-back condition, the data is written to the memory. For example, when the data in the first-level cache meets the write-back condition, the data in the first-level cache is written to the second-level cache; when the data in the second-level cache meets the write-back condition, the data in the second-level cache is written to the third-level cache; when the data in the third-level cache meets the write-back condition, the data in the third-level cache is written to the memory. After the computing device writes the first data back to the memory, it updates the record in the listening filter.

[0090] In some embodiments, in response to the first cache line satisfying the write-back condition, the computing device writes back the data in the first cache line to the memory level by level, and sets the status of the backup cache lines of the first cache line to an invalid state. In the above method, the first cache line satisfying the write-back condition indicates that the number of CPU accesses to the data in the first cache line is reduced, and writing back the data in the first cache line while setting the backup cache line of the first cache line to invalid can avoid excessive cache occupation and free up space for data with a high number of CPU accesses.

[0091] For a computing device including a multi-core CPU, in some embodiments, if the snoop filter intercepts a read instruction from other cores to the first cache line, the core modifies the state of the first cache line in the cache to a shared state, and modifies the state of the backup cache line of the first cache line to an invalid state; in the above method, when other cores need to read the first cache line, the first cache line is set to a shared state, so that other caches can synchronize the first cache line to meet the possible read requirements of other cores for the first cache line, and other CPU cores do not need to read the first cache line from the memory, which can improve the reading efficiency of the first cache line. At the same time, setting the backup cache line of the first cache line to an invalid state can avoid excessive occupation of the cache. In other embodiments, if the snoop filter intercepts a write instruction from other cores to the memory address or modifies the state of the cache line corresponding to the memory address in the cache to an exclusive state, the core modifies the state of both the first cache line and the backup cache line of the first cache line in the cache to an invalid state, and writes back the data in the first cache line.

[0092] It should be noted that step 304 is an optional step. In some embodiments, step 304 may not be performed, and the embodiments of the present application do not limit this.

[0093] Below Figure 4 As an example, the process shown in step 304 in the above step 301 is illustrated. Figure 4FIG. 1 is a flow chart of a data backup method based on a cache line provided in an embodiment of the present application. Figure 4 As shown, data "Data_x=3" and data "Data_y=2" are stored in the memory, the memory address corresponding to "Data_x=3" is mapped to the 2nd way cache line of the 1st group in the cache (that is, the first cache line), and the memory address corresponding to "Data_y=2" is mapped to the 4th way cache line of the 1st group in the cache. If the state of the 4th way cache line of the 1st group is an invalid state (I), a shared state (S) or an exclusive state (E), the process of the computing device executing the cache line-based data backup method includes: step ①: in response to the CPU executing a write instruction (write) on the 2nd way cache line of the 1st group in the cache, requesting the snoop filter (SF) The state of the 2nd cache line of the 1st group, SF returns the state E; the data "Data_x=3" in the 2nd cache line of the 1st group is modified to "Data_x=5", its state is set to the modified state (M), and SF is notified to update the record; Step ②: Select 1 cache line to store the backup cache line: Taking the LRU algorithm under the non-fixed strategy as an example, the least recently used cache line in the 1st group is determined to be the 4th cache line, and the 4th cache line of the 1st group is determined as the second cache line, and the state of the second cache line is I; Step ③: Copy (copy) the 2nd cache line "Data_x=5" of the 1st group to the 4th cache line of the 1st group, and set the state of the 4th cache line of the 1st group to M. If the state of the 4th cache line of the 1st group is the modified state (M), the process is the same as the above process. The difference is that before copying the 2nd cache line of the 1st group "Data_x=5" to the 4th cache line of the 1st group, the computing device first writes the data in the 4th cache line of the 1st group back to the memory. The similarities are not repeated here.

[0094] In the above method, the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in the memory. Therefore, storing the backup cache line of the first cache line in the cache can avoid the data inconsistency problem caused by the error of the data in the first cache line, and only the backup cache line of the modified cache line is stored in the cache, while for the cache line in the exclusive state (the data only exists in the cache and is consistent with the data in the memory) and the shared state (the data also exists in other caches and is consistent with the data in the memory), the backup cache line is not stored in the cache, which can avoid excessive occupation of the cache by redundant backups, thereby ensuring the hit rate of the cache while ensuring data reliability; further, when the memory side performs mirror protection for the data in the memory address corresponding to the first write instruction, the backup cache line of the first cache line is stored on the cache side, that is, selectively performing mirroring on the cache side, which can avoid the problem that the data protection effect of the cache side is greatly reduced due to the fact that the cache side performs mirroring but the memory side does not perform mirroring, and can further increase the proportion of valid data in the cache, and further avoid excessive occupation of the cache by the backup cache line, resulting in a decrease in the cache hit rate.

[0095] The above introduces the process of a cache line-based data backup method provided by an embodiment of the present application. Based on the above steps 301 to 303, the cache has stored a first cache line and a backup cache line of the first cache line. In some embodiments, the computing device can read the data in the first cache line from the cache. The process includes: in response to a read instruction to a memory address, respectively verifying the first cache line and the backup cache line of the second cache line in the cache, the first cache line being the cache line corresponding to the memory address; if both the first cache line and the backup cache line of the first cache line are verified successfully, then returning the data in the first cache line; if only one of the first cache line and the backup cache line of the first cache line is verified successfully, then returning the data in the successfully verified cache line, and recovering the cache line that failed to be verified based on the successfully verified cache line.

[0096] Among them, based on the above step 302, it can be known that if the computing device determines the second cache line in the group where the first cache line is located based on the fixed strategy, the position of the second cache line is fixed, that is, the position of the backup cache line of the first cache line is fixed. If the computing device determines the second cache line in the group where the first cache line is located based on the non-fixed strategy, the position of the second cache line is not fixed, that is, the position of the backup cache line of the first cache line is not fixed. The data reading process under the fixed strategy and the data reading process under the non-fixed strategy will be introduced respectively below.

[0097] The cache line includes a tag, data and attribute information, wherein the tag is used to indicate the memory address corresponding to the cache line, and the attribute information is used to indicate the state (MESI) and memory mirror mark (MF) of the cache line. If the tag is wrong, the computing device cannot hit the cache; if the data in the cache line is wrong, the computing device will read the wrong data; if the attribute information is wrong, the computing device will obtain the wrong state or memory mirror mark, so the computing device checks the cache line before reading the data from the cache. For the cache line with a backup cache line, error checking and correcting (ECC) is used to protect the tag, state (MESI) and memory mirror mark (MF) in the cache line, and cyclic redundancy check (CRC) is used to protect the data in the cache line; for the cache line without a backup cache line, ECC is used to protect the cache line. The computing device checks the cache line according to the verification method corresponding to the above protection method. It should be noted that the above description of the protection method and the verification method is only exemplary. In some embodiments, other methods can also be used to protect and verify the cache line, and the embodiments of the present application do not limit this.

[0098] First, the data reading process under the fixed strategy is introduced. The following uses the above-mentioned verification method as an example to illustrate the data reading process under the fixed strategy. Under the fixed strategy, in response to a read instruction to a memory address, the computing device first verifies multiple cache lines in the target group in the cache according to the above-mentioned verification method, and reads data based on the verification result. The target group is the group in the cache corresponding to the memory address. The data reading process under the fixed strategy includes the following two situations.

[0099] The first case: multiple cache lines are all verified successfully. If the tag of any cache line among the multiple cache lines matches the memory address in the read instruction, the computing device returns the data in the cache line; if the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, writes the cache line back to the next level cache or memory if the replaced cache line has a backup cache line, reads the data corresponding to the memory address from the next level cache or memory, writes the read data to the replaced cache line, and the CPU reads the data from the cache again.

[0100] The second situation: the first cache line is verified successfully, but the backup cache line of the first cache line fails to be verified. If the tag of the first cache line matches the memory address in the read instruction, the computing device returns the data in the first cache line, and then copies the first cache line to the backup cache line to restore the backup cache line; if the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, writes the cache line back to the next level cache or memory if the replaced cache line has a backup cache line, and then reads the data corresponding to the memory address from the next level cache or memory, writes the read data to the replaced cache line, and the CPU reads the data from the cache again. If there is still a cache line that fails to be verified at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful); wherein, if the backup cache lines of multiple cache lines fail to be verified, the computing device recovers the backup cache lines respectively, and the recovery process is the same as the process of recovering the backup cache line of the first cache line based on the first cache line in the second case, and will not be repeated.

[0101] The following describes the data reading process under a non-fixed strategy. The following uses the above-mentioned verification method as an example to illustrate the data reading process under a non-fixed strategy. Under a non-fixed strategy, in response to a read instruction to a memory address, the computing device first verifies multiple cache lines in a target group in the cache according to the above-mentioned verification method, and reads the data in the cache line based on the verification result. The target group is the group in the cache corresponding to the memory address. The data reading process under a non-fixed strategy includes the following four situations.

[0102] The first case: multiple cache lines are all verified successfully. If the tag of any cache line among the multiple cache lines matches the memory address in the read instruction, the computing device returns the data in the cache line; if the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, writes the cache line back to the next level cache or memory if the replaced cache line has a backup cache line, reads the data corresponding to the memory address from the next level cache or memory, writes the read data to the replaced cache line, and the CPU reads the data from the cache again.

[0103] The second case: the first cache line is successfully verified, there is a cache line whose tag verification fails, and the computing device does not find the backup cache line of the first cache line (that is, the first cache line is not paired), indicating that the cache line whose tag verification fails is the backup cache line of the first cache line. If the tag of the first cache line matches the memory address in the read instruction, the computing device returns the data in the first cache line, and then copies the first cache line to the backup cache line to restore the backup cache line; if the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, writes the cache line back to the next level cache or memory if the replaced cache line has a backup cache line, and then reads the data corresponding to the memory address from the next level cache or memory, writes the read data to the replaced cache line, and the CPU reads the data from the cache again. If there is still a cache line that fails to verify at this time, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful).

[0104] The third case: the first cache line is successfully verified, and there is a cache line with the same tag as the first cache line but the data (data) verification fails, then the cache line is the backup cache line of the first cache line. If the tag of the first cache line matches the memory address in the read instruction, the computing device returns the data in the first cache line, and the computing device copies the first cache line to the backup cache line of the first cache line to restore the backup cache line of the first cache line; if the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, writes the cache line back to the next level cache or memory if the replaced cache line has a backup cache line, and then reads the data corresponding to the memory address from the next level cache or memory, writes the read data to the replaced cache line, and the CPU reads the data from the cache again. If there is still a cache line that fails the verification at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds).

[0105] The fourth case: the first cache line is successfully verified, but there are multiple cache lines whose tags or data verification fails, and the computing device cannot find the backup cache line of the first cache line (that is, the first cache line is not paired). If the tag of the first cache line matches the memory address in the read instruction, the computing device returns the data in the first cache line, and the computing device arbitrarily determines a cache line from the multiple cache lines that failed verification as the backup cache line of the first cache line, and copies the first cache line to the determined backup cache line to restore the backup cache line of the first cache line; if the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, writes the cache line back to the next level cache or memory if the replaced cache line has a backup cache line, and then reads the data corresponding to the memory address from the next level cache or memory, writes the read data to the replaced cache line, and the CPU reads the data from the cache again. If there is still a cache line that failed verification at this time, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds). If there are multiple unpaired cache lines that originally have backup cache lines, the computing device restores the backup cache lines thereof respectively in the same manner as the first cache line, which will not be described in detail.

[0106] Below Figure 5 Take the data reading process as an example to illustrate the above data reading process. Figure 5 is a schematic diagram of a data reading method in a cache line-based data backup method provided in an embodiment of the present application, such as Figure 5 As shown, the data "Data_x=3" is stored in the memory, and the memory address corresponding to "Data_x=3" is mapped to the 2nd cache line of the 1st group (storing the data "Data_x=5", that is, the first cache line) and (storing the data "Data_x=5", that is, the backup cache line of the first cache line), and the states of the 2nd cache line of the 1st group and the 4th cache line of the 1st group are both M. In which, in response to the read instruction of the memory address, the computing device performs ECC check on multiple cache lines. If the ECC check of the 2nd cache line of the 1st group succeeds, and the ECC check of the 4th cache line of the 1st group fails, the computing device copies the 4th cache line of the 1st group to the 2nd cache line of the 1st group to perform cache line recovery; when the tag in the 2nd cache line of the 1st group matches the memory address, the computing device returns the data in the 2nd cache line of the 1st group, and when the tag in the 2nd cache line of the 1st group does not match the memory address, the computing device reads the data corresponding to the memory address from the next level cache or memory.

[0107] In the above method, since a backup cache line of the first cache line is stored in the cache, when data in the first cache line is read from the cache, if the backup cache line check of the first cache line fails, the data in the first cache line can be read and the backup cache line can be restored based on the first cache line. Similarly, the first cache line can be restored based on the backup cache line, thereby improving data reliability.

[0108] The above describes the process of reading the data in the first cache line in the cache. In some embodiments, the computing device can also modify the data in the first cache line, that is, write the new data into the first cache line. The process includes: in response to the second data write instruction, write the data in the second data write instruction into the first cache line in the cache; overwrite the data in the backup cache line of the first cache line with the data in the second data write instruction. Wherein, the computing device verifies the cache line before writing data into the cache. Wherein, for the cache line with the backup cache line, the tag (tag), state (MESI) and memory mirror mark (MF) in the cache line are verified respectively by ECC, and the data (data) in the cache line is verified by CRC; for the cache line without the backup cache line, the cache line is verified by ECC. It should be noted that the above description of the verification method is only exemplary. In some embodiments, other methods can also be used to verify the cache line, and the embodiments of the present application do not limit this.

[0109] Among them, based on the above step 302, it can be known that if the computing device determines the second cache line in the group where the first cache line is located based on the fixed strategy, the position of the second cache line is fixed, that is, the position of the backup cache line of the first cache line is fixed. If the computing device determines the second cache line in the group where the first cache line is located based on the non-fixed strategy, the position of the second cache line is not fixed, that is, the position of the backup cache line of the first cache line is not fixed. The data writing process under the fixed strategy and the data writing process under the non-fixed strategy will be introduced respectively below.

[0110] First, the data writing process under the fixed strategy is introduced. Taking the above-mentioned verification method as an example, the data writing process under the fixed strategy is illustrated. Under the fixed strategy, in response to the second data write instruction, the computing device first verifies the multiple cache lines in the target group in the cache according to the above-mentioned verification method, and writes the data based on the verification result. The target group is the group in the cache corresponding to the memory address. The data writing process under the fixed strategy includes the following two situations.

[0111] The first case: multiple cache lines are verified successfully. If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction to the first cache line, and overwrites the data in the backup cache line of the first cache line with the data in the second data write instruction; if the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, writes the replaced cache line back to the next level cache or memory if the replaced cache line has a backup cache line, and then writes the data in the second data write instruction to the determined cache line.

[0112] The second situation: the first cache line is verified successfully, but the backup cache line of the first cache line fails to be verified. If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction into the first cache line, and overwrites the data in the backup cache line of the first cache line with the data in the second data write instruction. If there is still a cache line that fails to be verified at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful); if the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, writes the cache line back to the next level cache or memory if the replaced cache line has a backup cache line, and then writes the data in the second data write instruction into the determined cache line. If there is still a cache line that fails to be verified at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful). Among them, if the backup cache line verification of multiple cache lines fails, the computing device restores the backup cache lines respectively. The recovery process is the same as the process of restoring the backup cache line of the first cache line based on the first cache line in the second case, and will not be repeated.

[0113] It should be noted that if the cache line hit by the memory address in the second data write instruction does not have a backup cache line (that is, the cache line is not in a modified state or the MF indicates that it does not have a backup cache line), the process in which the computing device writes the data in the second data write instruction into the cache is the same as the above process. Figure 3 The same is true for the embodiment shown in the figure, which will not be described in detail here. The process of the computing device writing the data in the second data write instruction into the cache line is also the same as the above Figure 3 The same is true for the embodiment shown, which will not be described again here.

[0114] The following describes the data writing process under a non-fixed strategy. Taking the above-mentioned verification method as an example, the data writing process under a non-fixed strategy is illustrated. Under a non-fixed strategy, in response to the second data write instruction, the computing device first verifies the multiple cache lines in the target group in the cache according to the above-mentioned verification method, and writes data based on the verification results. The target group is the group in the cache corresponding to the memory address. Among them, for a cache line that has a modified state and has a backup cache line in the cache (that is, the above-mentioned first cache line), the process of the computing device writing data to the first cache line based on the verification result includes the following four situations.

[0115] The first case: multiple cache lines are verified successfully. If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction into the first cache line, and overwrites the data in the backup cache line of the first cache line with the data in the second data write instruction; if the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, writes the replaced cache line back to the next level cache or memory if the replaced cache line has a backup cache line, and then writes the data in the second data write instruction into the determined cache line.

[0116] The second situation: the first cache line is verified successfully, there is a cache line whose tag verification fails, and the computing device does not find the backup cache line of the first cache line (that is, the first cache line is not paired), indicating that the cache line whose tag verification fails is the backup cache line of the first cache line. If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction into the first cache line, and overwrites the data in the backup cache line of the first cache line with the data in the second data write instruction. If there is still a cache line that fails the verification at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful); if the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, writes the cache line back to the next level cache or memory if the replaced cache line has a backup cache line, and then writes the data in the second data write instruction into the determined cache line. If there is still a cache line that fails the verification at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful).

[0117] The third case: the first cache line is verified successfully, and there is a cache line with the same tag as the first cache line but the data verification fails. If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction into the first cache line, and overwrites the data in the backup cache line of the first cache line with the data in the second data write instruction. If there is still a cache line that fails the verification at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds); if the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, writes the cache line back to the next level cache or memory if the replaced cache line has a backup cache line, and then writes the data in the second data write instruction into the determined cache line. If there is still a cache line that fails the verification at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds).

[0118] The fourth situation: the first cache line is verified successfully, but there are multiple cache lines whose tags or data verification fails, and the computing device cannot find a backup cache line for the first cache line (that is, the first cache line is not paired). If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction into the first cache line, and the computing device arbitrarily determines a cache line from multiple cache lines that have failed verification as a backup cache line of the first cache line, and overwrites the data in the backup cache line of the first cache line with the data in the second data write instruction. If there is still a cache line that has failed verification at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful); if the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, writes the cache line back to the next level cache or memory if the replaced cache line has a backup cache line, and then writes the data in the second data write instruction into the determined cache line. If there is still a cache line that has failed verification at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful). If there are multiple unpaired cache lines that originally have backup cache lines, the computing device restores the backup cache lines thereof respectively in the same manner as the first cache line, which will not be described in detail.

[0119] It should be noted that if the cache line hit by the memory address in the second data write instruction does not have a backup cache line (that is, the cache line is not in a modified state or the MF indicates that it does not have a backup cache line), the process in which the computing device writes the data in the second data write instruction into the cache is the same as the above process. Figure 3 The same is true for the embodiment shown in the figure, which will not be described in detail here. The process of the computing device writing the data in the second data write instruction into the cache line is also the same as the above Figure 3 The same is true for the embodiment shown, which will not be described again here.

[0120] Below Figure 6 Take the data writing process as an example to illustrate the above data writing process. Figure 6 is a flow chart of a data writing method in a cache line-based data backup method provided in an embodiment of the present application, such as Figure 6 As shown, the data "Data_x=3" is stored in the memory, and the memory address corresponding to "Data_x=3" is mapped to the 2nd cache line of the 1st group (that is, the first cache line, storing the data "Data_x=5") and (that is, the backup cache line of the first cache line, storing the data "Data_x=5") in the cache, and the states of the 2nd cache line of the 1st group and the 4th cache line of the 1st group are both M. The process of writing data by the computing device includes: step ①: in response to the CPU executing the second data write instruction (write) on the 2nd cache line of the 1st group in the cache, the data in the 2nd cache line of the 1st group is modified from "Data_x=5" to "Data_x=6"; step ②: copying the data "Data_x=6" in the 2nd cache line of the 1st group to the 4th cache line of the 1st group to achieve backup data synchronization.

[0121] Figure 7 70 is a schematic diagram of the structure of a cache line-based data backup device provided in an embodiment of the present application. The device includes a writing module 701 and a storage module 702.

[0122] The write module 701 is used to respond to a first data write instruction and write the data in the first data write instruction to a first cache line in the cache, so that the state of the first cache line is a modified state, and the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in the memory;

[0123] The storage module 702 is used to store a backup cache line of the first cache line in the cache.

[0124] Optionally, the writing module 701 is used to:

[0125] In response to a write instruction to a memory address, data in the write instruction is written to a first cache line.

[0126] Optionally, the writing module 701 is used to include:

[0127] In response to a write-back instruction to the cache at an upper level, data in the write-back instruction is written into the first cache line.

[0128] Optionally, the cache includes multiple groups, each group includes multiple cache lines, and the storage module 702 includes a storage unit:

[0129] A backup cache line of the first cache line is stored in the group where the first cache line is located.

[0130] Optionally, the storage unit is used to:

[0131] At least one second cache line is determined in the group where the first cache line is located; and the first cache line is copied to the at least one second cache line.

[0132] Optionally, the group to which the first cache line belongs includes 2N cache lines, wherein the i-th cache line corresponds to the N+i-th cache line, N is an integer greater than 1, and i is an integer greater than or equal to 0 and less than N;

[0133] The storage unit is used to determine a cache line in the group where the first cache line is located and corresponding to the first cache line as a second cache line.

[0134] Optionally, the storage unit is used for any of the following:

[0135] Based on a least recently used algorithm, at least one second cache line is determined in the group where the first cache line is located; based on a first-in-first-out algorithm, at least one second cache line is determined in the group where the first cache line is located; based on a random replacement algorithm, at least one second cache line is determined in the group where the first cache line is located.

[0136] Optionally, the storage module 702 is used to:

[0137] If the state of the second cache line is exclusive, shared or invalid, the first cache line is copied to the second cache line; if the state of the second cache line is modified, the data in the second cache line is written back to the memory and the first cache line is copied to the second cache line.

[0138] Optionally, the first cache line further includes a memory mirroring mark, and the memory mirroring mark is used to indicate whether data in a memory address corresponding to the first cache line is backed up in the memory. The storage module 702 is used to:

[0139] If the memory mirror mark in the first cache line indicates that the data in the memory address corresponding to the first data write instruction has a backup in the memory, a backup cache line of the first cache line is stored in the cache.

[0140] Optionally, the device further includes a reading module, including:

[0141] A checking unit, configured to check respectively a first cache line and a backup cache line of a second cache line in the cache in response to a read instruction to the memory address, wherein the first cache line is a cache line corresponding to the memory address;

[0142] A return unit is used to return the data in the first cache line if both the first cache line and the backup cache line of the first cache line are successfully verified, and to return the data in the successfully verified cache line if only one of the first cache line and the backup cache line of the first cache line is successfully verified, and to recover the cache line that failed to be verified based on the successfully verified cache line.

[0143] Optionally, the cache line includes a tag, state information, a memory mirroring mark and data, the tag is used to indicate a memory address corresponding to the cache line, and the method further includes:

[0144] The protection module is used to protect the tag, state information and memory mirror tag in the cache line respectively by using error checking and correction (ECC), and to protect the data in the cache line by using cyclic redundancy check (CRC).

[0145] Optionally, the writing module 701 is further used for:

[0146] In response to a second data write instruction, the data in the second data write instruction is written into the first cache line in the cache; and the data in the backup cache line of the first cache line is overwritten with the data in the second data write instruction.

[0147] The writing module 701 and the storage module 702 can be implemented by software or hardware. For example, the implementation of the writing module 701 is described below by taking the writing module 701 as an example. Similarly, the implementation of the storage module 702 can refer to the implementation of the writing module 701.

[0148] As an example of a software functional unit, the write module 701 may include code running on a computing instance. Among them, the computing instance may include at least one of a physical host (computing device), a virtual machine, and a container. Further, the above-mentioned computing instance may be one or more. For example, the write module 701 may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed in the same region (region) or in different regions. Furthermore, the multiple hosts / virtual machines / containers used to run the code may be distributed in the same availability zone (AZ) or in different AZs, each AZ including a data center or multiple data centers with similar geographical locations. Among them, usually a region may include multiple AZs.

[0149] Similarly, multiple hosts / virtual machines / containers used to run the code can be distributed in the same virtual private cloud (VPC) or in multiple VPCs. Usually, a VPC is set up in a region. For cross-region communication between two VPCs in the same region and between VPCs in different regions, a communication gateway needs to be set up in each VPC to achieve interconnection between VPCs through the communication gateway.

[0150] As an example of a hardware functional unit, the write module 701 may include at least one computing device, such as a server, etc. Alternatively, the write module 701 may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0151] The multiple computing devices included in the write module 701 can be distributed in the same region or in different regions. The multiple computing devices included in the write module 701 can be distributed in the same AZ or in different AZs. Similarly, the multiple computing devices included in the write module 701 can be distributed in the same VPC or in multiple VPCs. The multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0152] It should be noted that, in other embodiments, the steps that the above modules are responsible for implementing can be specified as needed, and the above modules respectively implement different steps in the above cache line-based data backup method to achieve all the functions of the above device. That is, the cache line-based data backup device provided in the above embodiment only uses the division of the above functional modules as an example when implementing the cache line-based data backup method. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the device provided in the above embodiment belongs to the same concept as the corresponding method embodiment, and its specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0153] An embodiment of the present application provides a processor, which is used to execute a cache line-based data backup method provided in the aforementioned method embodiment or any possible implementation manner of the method embodiment.

[0154] An embodiment of the present application provides a storage medium, which is used to store at least one section of program code, and the at least one section of program code is used to execute the cache line-based data backup method provided by the aforementioned method embodiment or any possible implementation of the method embodiment.

[0155] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions. For example, the data involved in this application are all obtained with full authorization.

[0156] Those of ordinary skill in the art will appreciate that the various method steps and units described in the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0157] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0158] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the unit is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or it can be an electrical, mechanical or other form of connection.

[0159] The unit described as a separate component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, it may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment of the present application.

[0160] In addition, each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or software unit.

[0161] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computing device (which can be a personal computer, a server, or a computing device, etc.) to execute all or part of the steps of the method in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0162] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first data write instruction may be referred to as a second data write instruction, and similarly, a second data write instruction may be referred to as a first data write instruction. Both the first data write instruction and the second data write instruction may be write instructions, and in some cases, may be separate and different data write instructions.

[0163] The term "at least one" in this application means one or more, and the term "multiple" in this application means two or more, for example, multiple cache lines means two or more cache lines. The terms "system" and "network" are often used interchangeably herein.

[0164] It should also be understood that the term "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Similarly, the phrase "if it is determined that ..." or "if [a stated condition or event] is detected" may be interpreted to mean "upon determining that ..." or "in response to determining that ..." or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0165] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0166] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. When the computer program instructions are loaded and executed on a computer, the process or function in accordance with the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0167] The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital video disc (DVD), or a semiconductor medium (e.g., a solid-state drive)), etc.

[0168] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0169] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data backup method based on a cache line, characterized in that: The method comprises: In response to a first data write instruction, write data in the first data write instruction into a first cache line in a cache, so that the state of the first cache line is a modified state, and the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with data in a memory; A backup cache line of the first cache line is stored in the cache.

2. The method according to claim 1, characterized in that The step of writing the data in the first data write instruction to a first cache line in the cache in response to the first data write instruction comprises: In response to a write instruction to a memory address, data in the write instruction is written into the first cache line.

3. The method according to claim 1, characterized in that: The step of writing the data in the first data write instruction to a first cache line in the cache in response to the first data write instruction comprises: In response to a write-back instruction to the cache at an upper level, data in the write-back instruction is written into the first cache line.

4. The method according to any one of claims 1 to 3, characterized in that: The cache includes a plurality of groups, each group includes a plurality of cache lines, and a backup cache line of the first cache line is stored in the cache, including: A backup cache line of the first cache line is stored in the group where the first cache line is located.

5. The method according to claim 4, characterized in that The storing a backup cache line of the first cache line in the group where the first cache line is located comprises: determining at least one second cache line in the group where the first cache line is located; The first cache line is copied to the at least one second cache line.

6. The method according to claim 5, characterized in that The group to which the first cache line belongs includes 2N cache lines, wherein the i-th cache line corresponds to the N+i-th cache line, N is an integer greater than 1, and i is an integer greater than or equal to 0 and less than N; The step of determining at least one second cache line in the group where the first cache line is located comprises: A cache line in the group where the first cache line is located and corresponding to the first cache line is determined as the second cache line.

7. The method according to claim 5, characterized in that The determining at least one second cache line in the group where the first cache line is located includes any one of the following: Determine at least one second cache line in the group where the first cache line is located based on a least recently used algorithm; Based on a first-in-first-out algorithm, determining at least one second cache line in the group where the first cache line is located; Based on a random replacement algorithm, at least one second cache line is determined in the group where the first cache line is located.

8. The method according to claim 5, characterized in that The copying the first cache line to the at least one second cache line comprises: If the state of the second cache line is an exclusive state, a shared state or an invalid state, copying the first cache line to the second cache line, the exclusive state indicates that the data in the second cache line does not exist in other caches and is consistent with the data in the memory, the shared state indicates that the data in the second cache line also exists in other caches and is consistent with the data in the memory, and the invalid state indicates that the data in the second cache line is invalid; If the state of the second cache line is a modified state, the data in the second cache line is written back to the memory, and the first cache line is copied to the second cache line.

9. The method according to any one of claims 1 to 8, characterized in that The first cache line further includes a memory mirror mark, and the memory mirror mark is used to indicate whether data in a memory address corresponding to the first cache line is backed up in the memory, and the backup cache line storing the first cache line in the cache includes: If the memory mirror mark in the first cache line indicates that the data in the memory address corresponding to the first data write instruction has a backup in the memory, a backup cache line of the first cache line is stored in the cache.

10. The method according to claim 1, characterized in that The method further comprises: In response to a read instruction to a memory address, respectively checking a first cache line in the cache and a backup cache line of the first cache line, the first cache line being a cache line corresponding to the memory address; If both the first cache line and the backup cache line of the first cache line are verified successfully, returning the data in the first cache line; If only one of the first cache line and the backup cache line of the first cache line is successfully verified, the data in the successfully verified cache line is returned, and the cache line that failed to be verified is restored based on the successfully verified cache line.

11. The method according to claim 1, characterized in that: The cache line includes a tag, status information, a memory mirroring mark and data, the tag is used to indicate a memory address corresponding to the cache line, and the method further includes: Error checking and correction (ECC) is used to protect the tags, status information and memory mirroring tags in the cache line respectively, and cyclic redundancy check (CRC) is used to protect the data in the cache line.

12. The method according to claim 1, characterized in that The method further comprises: In response to a second data write instruction, writing data in the second data write instruction into the first cache line in the cache; The data in the backup cache line of the first cache line is overwritten with the data in the second data write instruction.

13. A data backup device based on a cache line, characterized in that: The device comprises: a writing module, configured to write data in the first data writing instruction into a first cache line in a cache in response to a first data writing instruction, so that the state of the first cache line is a modified state, wherein the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with data in a memory; A storage module is used to store a backup cache line of the first cache line in the cache.

14. A processor, characterized in that: The processor is used to execute the cache line-based data backup method according to any one of claims 1 to 12.

15. A computing device, characterized in that: The computing device comprises a processor and a memory, wherein the memory stores a program code, and the processor is configured to execute the program code, so that the computing device executes the cache line-based data backup method according to any one of claims 1 to 12.

16. A storage medium, characterized in that: The storage medium is used to store at least one section of program code, and the at least one section of program code is used to execute the cache line-based data backup method according to any one of claims 1 to 12.

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