Chip adaptive fault processing system and method

Abstract

The invention provides a chip adaptive fault processing system and method, the system comprises a configuration unit, a signal acquisition unit, a signal processing unit and an output control unit, the configuration unit is used for carrying out mode information configuration based on information obtained from a CPU, the signal acquisition unit is used for obtaining an acquisition signal of a target module based on the mode information, and the signal processing unit is used for outputting the acquisition signal. The signal processing unit is used for processing the collected signal based on the mode information and obtaining a reset signal when it is judged that triggering is abnormal, and the output control unit is used for outputting the reset signal to the target module to achieve resetting of the target module. According to the scheme, resetting does not need to be executed depending on the CPU, the processing burden of the CPU is reduced, fault recovery can be smoothly executed when the CPU is abnormal, and the problem that the whole server system is seriously abnormal is avoided.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip adaptive fault processing system and method. Background Art

[0002] With the advent of the AI ​​era, AI servers are becoming more and more common, and the requirements for the transmission of various high-speed signals in AI servers are getting higher and higher. Therefore, the demand for the number of chips in the server and the performance requirements for chips are also getting higher and higher. With the widespread application of chips, the demand for chip internal parameter statistics, fault diagnosis, and fault repair technologies is becoming more and more urgent.

[0003] However, when handling faults, existing chips often need to rely on the CPU to assist in fault handling and fault recovery. For example, the retimer chip, which is widely used in servers, is currently in its infancy and does not have complete and perfect fault diagnosis and fault repair technology. When a retimer chip fails, it cannot actively and independently complete fault repair. The CPU is often required to generate a reset signal based on the interrupt signal when the chip fails, and then reset the faulty module in the chip. On the one hand, the existing processing method increases the processing burden of the CPU. On the other hand, if the CPU also has abnormalities, it cannot assist the chip in fault recovery, which causes the entire server system to fail, further leading to serious abnormalities. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a chip adaptive fault processing system and method to reduce the CPU processing burden and avoid serious abnormalities.

[0005] In a first aspect, the present invention provides a chip adaptive fault processing system, which is applied to a fault processing module in a chip including multiple modules, the system comprising a configuration unit, a signal acquisition unit, a signal processing unit and an output control unit, the configuration unit is respectively connected to a CPU in a server, the signal acquisition unit, and the signal processing unit, the signal acquisition unit is also connected to the signal processing unit, and the signal processing unit is also connected to the output control unit; The configuration unit is used to configure mode information based on information obtained from the CPU; The signal acquisition unit is used to acquire signals from the target module based on the mode information to obtain acquisition signals; The signal processing unit is used to process the collected signal based on the mode information, and obtain a corresponding reset signal when determining that a trigger abnormality occurs; The output control unit is used to output the reset signal to the target module to achieve the reset of the target module.

[0006] In an optional embodiment, the signal processing unit includes a trigger control subunit, an isolation processing subunit, an adaptive processing subunit and an output control subunit; The trigger control subunit is used to determine whether the acquisition signal triggers an abnormality based on the mode information; The isolation processing subunit is used for determining whether to maintain or filter out the abnormality based on the signal type of the acquisition signal when the trigger control subunit determines that the abnormality is triggered; The adaptive processing subunit is used to determine whether to output a reset signal in combination with the determination result of the trigger control subunit and the determination result of the isolation processing subunit; The output control subunit is used for outputting the reset signal to the output control unit when the adaptive processing subunit determines to output the reset signal.

[0007] In an optional implementation, the mode information includes an abnormal trigger mode, the abnormal trigger mode includes a timestamp trigger mode, and the timestamp trigger mode includes a trigger signal type, a trigger mode, and a waiting time; The signal processing unit is used for triggering an exception after the waiting time is satisfied when it is determined that the acquisition signal is a trigger signal type in the timestamp trigger mode and the acquisition signal conforms to the trigger mode in the timestamp trigger mode.

[0008] In an optional embodiment, the system further comprises a storage unit; The signal acquisition unit is also used to store the acquired signal into the storage unit; The signal processing unit is further configured to extract a signal segment within the waiting time of the acquisition signal from the storage unit and output the signal segment to the output control unit when determining that the acquisition signal triggers the timestamp trigger mode; The output control unit is further used to output the signal segment to other units of the chip used for signal analysis.

[0009] In a second aspect, the present invention provides a chip adaptive fault processing method, which is applied to any one of the above chip adaptive fault processing systems, wherein the system comprises a configuration unit, a signal acquisition unit, a signal processing unit and an output control unit, and the chip adaptive fault processing method comprises: The configuration unit performs mode information configuration based on information obtained from the CPU; The signal acquisition unit acquires signals from the target module based on the mode information to obtain acquisition signals; The signal processing unit processes the collected signal based on the mode information, and obtains a corresponding reset signal when determining that a trigger abnormality occurs; The output control unit outputs the reset signal to the target module to achieve the reset of the target module.

[0010] The chip adaptive fault processing system and method provided by the embodiment of the present invention include a configuration unit, a signal acquisition unit, a signal processing unit and an output control unit, wherein the configuration unit is used to configure the mode information based on the information obtained from the CPU, the signal acquisition unit is used to obtain the acquisition signal of the target module based on the mode information, the signal processing unit is used to process the acquisition signal based on the mode information, and obtain a reset signal when determining that an abnormality is triggered, and the output control unit is used to output the reset signal to the target module to achieve the reset of the target module. In this solution, there is no need to rely on the CPU to perform reset, which reduces its processing burden, and fault recovery can be smoothly performed when the CPU is abnormal, avoiding the problem of serious abnormalities in the entire server system. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A schematic diagram of the structure of a chip provided by an embodiment of the present invention; Figure 2 A structural block diagram of a chip adaptive fault processing system provided by an embodiment of the present invention; Figure 3 A structural block diagram of a configuration unit provided in an embodiment of the present invention; Figure 4 A structural block diagram of a signal acquisition unit provided in an embodiment of the present invention; Figure 5 A structural block diagram of a signal processing unit provided by an embodiment of the present invention; Figure 6 A structural block diagram of an output control unit provided by an embodiment of the present invention; Figure 7 The present invention provides a flowchart of a chip adaptive fault processing method according to an embodiment of the present invention.

[0013] Icons: 10-fault handling module; 11-configuration unit; 111-interface subunit; 112-acquisition configuration subunit; 113-abnormal configuration subunit; 114-other configuration subunits; 12-signal acquisition unit; 121-signal acquisition selection subunit; 122-read-write control subunit; 123-signal processing control subunit; 13-signal processing unit; 131-trigger control subunit; 132-isolation processing subunit; 133-adaptive processing subunit; 134-output control subunit; 14-output control unit; 141-interface processing subunit; 142-reset output interface subunit; 143-interrupt output interface subunit; 144-backup output interface subunit; 15-storage unit. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the drawings in the present invention. Obviously, the described technical solutions are part of the technical solutions of the present invention, but not all of the technical solutions. Generally, the components of the technical solutions of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0015] Therefore, the following detailed description of the technical solutions of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents the selected technical solutions of the present invention. Based on the technical solutions in the present invention, all other technical solutions obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0016] As mentioned in the background technology, the chips in existing servers often need to rely on the CPU in the server to assist in the implementation when performing fault recovery. For example, the retimer chip, which is widely used in servers, is currently in its infancy and does not have complete and perfect fault diagnosis and fault repair technology. When a retimer chip fails, it cannot actively and independently complete the fault repair, which may lead to problems such as failure of the entire server system.

[0017] To solve the above technical problems, please refer to Figure 1 The present invention provides a chip adaptive fault processing system. The adaptive fault processing system is applied to a fault processing module 10 included in a chip in a server, and the chip can be but is not limited to a retimer chip. The chip includes multiple modules, including the fault processing module 10 and other modules such as a data processing module, a control module, etc. The fault processing module 10 can be used to perform fault diagnosis and fault recovery processing on other modules in the chip.

[0018] Please refer to Figure 2 The fault processing module 10 includes a configuration unit 11, a signal acquisition unit 12, a signal processing unit 13 and an output control unit 14. The configuration unit 11 is connected to the CPU, the signal acquisition unit 12 and the signal processing unit 13 in the server. In addition, the signal acquisition unit 12 is also connected to the signal processing unit 13, and the signal processing unit 13 is also connected to the output control unit 14.

[0019] In this embodiment, the various units in the fault processing module 10 can be connected through metal wiring, polysilicon wiring, etc.

[0020] The functions of each functional unit in the chip adaptive fault handling system provided by this embodiment are implemented as follows: The configuration unit 11 is used to configure the mode information based on the information obtained from the CPU.

[0021] The signal acquisition unit 12 is used to acquire signals from the target module based on the mode information to obtain acquired signals.

[0022] The signal processing unit 13 is used to process the collected signal based on the mode information and obtain a corresponding reset signal when it is determined that the trigger is abnormal; The output control unit 14 is used to output a reset signal to the target module to achieve the reset of the target module.

[0023] In this embodiment, the signal acquisition unit 12 and the signal processing unit 13 respectively implement signal acquisition and signal processing based on the mode information pre-configured by the CPU, wherein the target module is any other module in the chip except the fault processing module 10, for example Figure 1 Data processing module, control module, etc.

[0024] During implementation, the acquisition of required signals can be realized based on the configuration related to actual needs, and the signal processing can be realized based on the configuration related to processing under actual needs, so as to meet the relevant needs of acquisition and processing. In addition, flexible information configuration can be supported to meet the diverse acquisition and processing methods.

[0025] In addition, in this embodiment, since the signal processing unit 13 can process the collected signal based on the pre-configured mode information, and obtain the reset signal when determining that the trigger is abnormal, and the reset signal is output to the target module through the output control unit 14 to achieve reset. However, in the existing method, it is necessary to rely on the CPU to reset the module that needs to be reset, and there is a problem of heavy CPU processing burden. Moreover, in the existing method, when the CPU fails, it is impossible to reset other modules, resulting in the inability to achieve fault recovery. Therefore, this solution can avoid the problem of heavy CPU processing burden in the existing method, and can avoid the problem that the CPU cannot be reset when it fails due to the need to rely on the CPU for reset, thereby causing serious abnormalities in the entire server system.

[0026] As an optional implementation, Figure 3 As shown in , the configuration unit 11 includes an interface subunit 111, a collection configuration subunit 112 and an abnormal configuration subunit 113. The interface subunit 111 is connected to the collection configuration subunit 112 and the abnormal configuration subunit 113 respectively.

[0027] The interface subunit 111 may be an Advanced High-performance Bus (AHB) subunit. The interface subunit 111 may be connected to the CPU in the server to receive relevant information configured by the CPU, and send the received information to the acquisition configuration subunit 112 and the abnormality configuration subunit 113. Such information includes the range information of signal acquisition, the definition of signal abnormality, the information related to signal storage, the information of signal reporting, etc.

[0028] The acquisition configuration subunit 112 can be used to configure the acquisition mode based on the information obtained. Based on this, in this embodiment, the mode information includes multiple acquisition modes, each of which corresponds to an acquisition port and a signal type of the chip. Each signal type under each acquisition port corresponds to each module in the chip. In this way, when a signal of a certain signal type is acquired for a certain acquisition port, the target module corresponding to the acquired signal can be determined.

[0029] The acquisition mode configured by the acquisition configuration subunit 112 may be provided to the signal processing unit 13 to perform operations related to signal acquisition.

[0030] It can be seen that each acquisition mode includes multiple types of information, such as acquisition port, signal type, etc., and the acquisition port may also include multiple port information, and the signal type may also include multiple types of information. That is, the amount of information data contained in each acquisition mode is huge.

[0031] In order to facilitate fast and smooth processing during the implementation of fault handling, the configuration unit 11, specifically the collection configuration subunit 112 in the configuration unit 11, can also be used to uniformly configure the port information of the corresponding collection ports in each collection mode and the signal information corresponding to the signal type into a mode template.

[0032] In this way, by configuring the pattern template, the relevant pattern template can be directly called when performing signal acquisition processing, and signal acquisition can be performed based on the information in the pattern template, without having to extract multiple pieces of information, combine the multiple pieces of information, and then perform signal acquisition based on the combined information. The uniformly configured pattern template can greatly improve the speed and fluency of the signal acquisition process.

[0033] In this embodiment, the configured acquisition mode may be composed of: mode number, acquisition port, signal type. Exemplarily, the configured acquisition mode may include the following: Mode 0: collects the RX-related signals of port a of the chip; Mode 1: Collect the RX-related signals of port b of the chip; Mode 2: Acquire EQ-related signals from port x of the chip (the port configured to acquire EQ signals); Mode 3: Collect deskew-related signals of port a of the chip; Mode 4: Collect deskew-related signals of port b of the chip; Mode 5: Collect other related signals from other ports of the chip.

[0034] In addition, the abnormal configuration subunit 113 can be used to configure the abnormal trigger mode based on the obtained information. Based on this, in this embodiment, the mode information also includes multiple abnormal trigger modes, each abnormal trigger mode includes a trigger method and a trigger signal type.

[0035] The abnormality triggering mode configured by the abnormality configuration subunit 113 can be provided to the signal processing unit 13 to perform signal processing and determine whether to trigger an abnormality.

[0036] Each abnormal trigger mode includes a trigger mode and a trigger signal type. Similarly, in order to improve the speed and fluency of the signal processing process, the abnormal configuration subunit 113 can configure the trigger mode and the trigger signal type in each abnormal trigger mode as a mode template. In this way, when performing signal processing, the mode template corresponding to each abnormal trigger mode can be directly called and abnormal judgment can be performed, which can greatly improve the processing efficiency.

[0037] In this embodiment, the triggering methods in each abnormal trigger mode include triggering events, the number of triggering events and combinations. The triggering events include rising edge events, falling edge events and preset level width events, and the combinations include multiple methods each consisting of at least one triggering event.

[0038] That is to say, the trigger event can be, for example, triggering an exception when a preset number of rising edge events are detected, or triggering an exception when a preset number of falling edge events are detected, or triggering an exception when a preset number of preset level widths are detected, or triggering an exception when at least two combinations of rising edge events, falling edge events, and preset level width events of a certain signal are detected, or triggering an exception when two signals are detected to satisfy a set combination of rising edge events, falling edge events, and preset level width events, and so on.

[0039] In addition, in order to obtain complete abnormal information of the abnormal acquisition signal, the abnormal trigger mode includes a timestamp trigger mode, which includes the trigger signal type, trigger mode and waiting time. That is, the timestamp trigger mode increases the waiting time compared to the various abnormal trigger modes mentioned above. The meaning of the waiting time is that the signal segment of the acquisition signal within the waiting time can be collected. In this way, in the scenario of performing chip testing, the complete abnormal information of the acquisition signal under abnormal circumstances can be obtained, and then used for detailed analysis and other processing, which is convenient for analyzing the cause of the abnormality, determining the corresponding plan for the abnormality, etc.

[0040] Based on this, in this embodiment, exemplarily, the configured multiple abnormal trigger modes can be as follows: Trigger mode 0: rising edge trigger, trigger times, trigger signal type; Trigger mode 1: falling edge trigger, trigger times, trigger signal type; Trigger mode 2: preset level width trigger, trigger times, trigger signal type; Trigger mode 3: mixed trigger (a mixture of rising edge, falling edge, preset level width, etc. of a single signal), trigger times, trigger signal type; Trigger mode 4: Pattern trigger (a mixture of rising edge, falling edge, preset level width, etc. of two or more signals), trigger times, trigger signal type; Trigger mode 5: timestamp trigger, trigger times, trigger signal type, and wait time.

[0041] In this embodiment, the configuration unit 11 includes, in addition to the above-mentioned collection configuration subunit 112 and abnormal configuration subunit 113, other configuration subunit 114, which is used for other configurations of related information such as signal backup storage and signal reporting.

[0042] Based on this, in this embodiment, the configuration information also includes storage mode information and off-chip storage address. The storage mode information is used to provide the signal acquisition unit 12 to store the acquired signal in the on-chip storage unit 15, and the off-chip storage address is used to provide the output control unit 14 to store the required backup storage signal in the off-chip storage unit.

[0043] In this embodiment, when the fault handling module 10 determines that there is an abnormality in the target module, it can also generate an interrupt signal and report it to the CPU. After receiving the interrupt signal, the CPU can configure a reset signal based on the interrupt signal, and then reset the target module based on the reset signal through the CPU.

[0044] Therefore, the configuration information may also include signal reporting information, and the signal reporting information includes information such as the type of interrupt signal required to be reported to the CPU, the interrupt number carried during reporting, and the like.

[0045] The signal reporting information is mainly used to provide to the output control unit 14 to perform the signal reporting operation.

[0046] In one possible implementation, please refer to Figure 4 The signal acquisition unit 12 in this embodiment includes a signal acquisition selection subunit 121, a read-write control subunit 122, and a signal processing control subunit 123. The signal acquisition selection subunit 121 is connected to the read-write control subunit 122 and the signal processing control subunit 123.

[0047] The signal acquisition selection subunit 121 is used to perform signal acquisition based on the acquisition mode obtained from the configuration unit 11. As can be seen from the above, the mode information includes multiple acquisition modes, each of which corresponds to an acquisition port and signal type of the chip.

[0048] Based on this, the signal acquisition unit 12 (specifically, the signal acquisition selection subunit 121 ) is used to determine the target acquisition port and the target signal type based on the acquisition mode in the mode information, and acquire the signal corresponding to the target signal type based on the target acquisition port to obtain the acquisition signal.

[0049] The port and signal types indicated by the acquisition mode include port a and rx signal in mode 0, port b and rx signal in mode 1, EQ signal of port x (based on configuration) in mode 2, port a and deskew signal in mode 3, port b and deskew signal in mode 4, and other ports and other signals in mode 5.

[0050] Based on this, the signal collection selection subunit 121 can select a signal collection source based on the specific port information and signal type information in the configuration information, and perform signal collection.

[0051] Combined with reference Figure 2 In this embodiment, the fault processing module 10 further includes a storage unit 15, which can be an SRAM unit. As can be seen from the above, the mode information also includes storage mode information, and the signal acquisition unit 12 (specifically, the read-write control subunit 122) can be used to store the acquired signal in the storage unit 15 based on the storage mode information.

[0052] The storage mode information may include, for example, the processing mode and storage mode of the collected signal, wherein the processing mode includes, for example, the packaging mode and filtering mode of the collected signal, etc. The storage mode includes, for example, the byte order mode and the byte information stored corresponding to each storage bit in the storage unit 15, etc.

[0053] Byte order refers to the order in which bytes of multi-byte data are arranged in the storage unit 15, mainly including big-endian mode and little-endian mode. In big-endian mode, the highest-order byte of a data is stored at the lowest memory address, and the lowest-order byte is stored at the highest memory address. That is, the byte order of the data is consistent with the growth mode of the memory address. In little-endian mode, the lowest-order byte of a data is stored at the lowest memory address, and the highest-order byte is stored at the highest memory address. Contrary to the big-endian mode, the byte order of the data is opposite to the growth direction of the memory address.

[0054] Different computer system architectures may use different byte orders, so the specific byte order can be determined based on the configuration.

[0055] In addition, the signal processing control subunit 123 is mainly used to connect with the signal processing unit 13 and read relevant signals from the storage unit 15 based on the instruction information of the signal processing unit 13 for other related analysis and processing.

[0056] In this embodiment, the signal processing unit 13 is the core unit of the exception handling system. Figure 5 As shown in , the signal processing unit 13 includes a trigger control subunit 131, an isolation processing subunit 132, an adaptive processing subunit 133 and an output control subunit 134. The trigger control subunit 131 is connected to the isolation processing subunit 132, the adaptive processing subunit 133 and the output control subunit 134 respectively, and the adaptive processing subunit 133 is also connected to the isolation processing subunit 132 and the output control subunit 134.

[0057] The trigger control subunit 131 is used to determine whether the acquisition signal triggers an abnormality based on the mode information. The isolation processing subunit 132 is used to determine whether to maintain the abnormality or filter out the abnormality based on the signal type of the acquisition signal when the trigger control subunit 131 determines that the abnormality is triggered. The adaptive processing subunit 133 is used to determine whether to output a reset signal based on the determination result of the trigger control subunit 131 and the determination result of the isolation processing subunit 132. The output control subunit 134 is used to output the reset signal to the output control unit 14 when the adaptive processing subunit 133 determines that the reset signal is output.

[0058] Specifically, the trigger control subunit 131 is connected to the configuration unit 11 and the signal acquisition unit 12, and is used to receive the acquisition signal sent by the signal acquisition unit 12, and obtain the mode information configured by the configuration unit 11, and determine whether the acquisition signal triggers an abnormality based on the abnormal trigger mode included in the mode information.

[0059] Based on the above description of the abnormal trigger mode, the abnormal trigger mode includes a trigger mode and a trigger signal type. Therefore, the signal processing unit 13 (specifically, the trigger control subunit 131) can be used to determine the target trigger signal type corresponding to the acquisition signal, and determine whether the acquisition signal triggers an abnormality based on the target trigger mode corresponding to the target trigger signal type.

[0060] For example, in the configured abnormal trigger mode, the abnormal trigger for signal a is to trigger an abnormality after detecting three rising edge events of signal a. In the case where the acquisition signal is signal a, that is, the target trigger signal type corresponding to the acquisition signal is signal a, then the corresponding target trigger mode can be obtained as detecting three rising edge events. Therefore, if it is detected that the acquisition signal has three rising edge events, it can be determined that the abnormality is triggered.

[0061] As can be seen from the above, the configuration unit 11 can configure multiple abnormal trigger modes, including trigger mode 0-trigger mode 5, which are rising edge trigger, falling edge trigger, preset level width trigger, mixed trigger, pattern trigger, and timestamp trigger.

[0062] The structure of each abnormal trigger mode can be unified into: trigger event, number of trigger events, combination method, and trigger signal type.

[0063] Based on this, when the signal processing unit 13 (specifically the trigger control subunit 131) performs abnormality judgment, the abnormality judgment can be implemented in one or more of the following ways based on the configured abnormal trigger mode: When the abnormal trigger mode is rising edge trigger, the trigger event is a rising edge event, the number of trigger events is A times, the combination mode is a separate signal (i.e., separate signals are analyzed separately), and the trigger signal type is signal a. If the trigger control subunit 131 detects that the acquisition signal is signal a, then if it is detected that signal a reaches A rising edge events, it can be determined that the trigger is abnormal.

[0064] When the abnormal trigger mode is falling edge trigger, the trigger event is a falling edge event, the number of trigger events is B times, the combination mode is a single signal, and the trigger signal type is signal b. If the trigger control subunit 131 detects that the acquisition signal is signal b, if it is detected that signal b reaches B falling edge events, it can be determined that the trigger is abnormal.

[0065] When the abnormal trigger mode is a preset level width trigger, the trigger event is a preset level width event, the number of trigger events is C times, the combination mode is a single signal, and the trigger signal type is signal C. If the trigger control subunit 131 detects that the acquisition signal is signal c, then if it is detected that signal c reaches C preset level width events, it can be determined that the trigger is abnormal.

[0066] When the abnormal trigger mode is mixed trigger, the trigger event can be any one or combination of falling edge event, rising edge event, and preset level width event based on the configuration, the number of trigger events is D times, the combination mode is a single signal, and the trigger signal type is signal d. If the trigger control subunit 131 detects that the acquisition signal is signal d, if it is detected that signal d reaches any one or combination of the configured trigger events D times, it can be determined that the trigger is abnormal.

[0067] When the abnormal trigger mode is Pattern trigger, the trigger event can be any one or a combination of a falling edge event, a rising edge event, and a preset level width event (such as a rising edge event and a falling edge event), the number of trigger events is E times and F times (exemplary), the combination mode is a combination of two signals (exemplary), and the trigger signal type is signal e and signal f. If the trigger control subunit 131 detects that the acquisition signal is signal e and signal f, then if it is detected that signal e reaches E times of rising edge events and then signal f has F times of falling edge events, it can be determined that the trigger is abnormal.

[0068] In addition, for the timestamp trigger mode, the control processing unit (specifically the trigger control subunit 131) is used to trigger an exception after satisfying the waiting time when it is determined that the acquisition signal is the trigger signal type in the timestamp trigger mode and the acquisition signal conforms to the trigger method in the timestamp trigger mode.

[0069] That is, compared with the above-mentioned abnormal trigger modes, the timestamp trigger mode increases the waiting time. The purpose of increasing the waiting time is to collect complete abnormal signal information for certain types of signals, so as to be used for other analyses, such as fault cause analysis, fault location, etc., which helps to achieve thorough fault analysis and recovery.

[0070] Based on this, when the abnormal trigger mode is the timestamp trigger mode, the trigger event is any one or a combination of a falling edge event, a rising edge event, and a preset level width event, the number of trigger events is G times, the combination mode is a single signal, the trigger signal type is signal g, and the waiting time is t milliseconds. If the trigger control subunit 131 detects that the acquisition signal is signal g, after detecting that signal g reaches the configured trigger event G times and after waiting for t milliseconds, it can be determined that the trigger is abnormal.

[0071] As can be seen from the above, after obtaining the acquisition signal, the signal acquisition unit 12 stores the acquisition signal in the storage unit 15. The signal processing unit 13 can also be used to extract the signal segment within the waiting time of the acquisition signal from the storage unit 15 when determining the acquisition signal triggering the timestamp trigger mode, and output it to the output control unit 14. The output control unit 14 can also be used to output the signal segment to other modules of the chip for signal analysis.

[0072] Considering that after the acquisition signal is triggered abnormally, the acquisition of the acquisition signal may be interrupted, so that the complete abnormal signal information of the acquisition signal cannot be obtained. Therefore, in this embodiment, in the timestamp trigger mode, the abnormality is triggered after the waiting time when it is determined that the acquisition signal is abnormal. In this way, the signal segment within the waiting time of the acquisition signal after the abnormality is determined can be obtained, so that it can be provided to other modules to analyze the signal segment, analyze the cause of the fault, locate the fault, find a fault solution, etc.

[0073] The above is the detection and judgment process of whether the acquisition signal triggers an abnormality based on the abnormal trigger mode executed by the trigger control subunit 131 in the signal processing unit 13. Considering that during the operation of the chip, the detection and judgment based on the trigger control subunit 131 may frequently trigger abnormalities, and then frequently upload interrupt signals to the CPU or frequently reset other modules, etc., thereby causing the CPU to be overloaded and the processing flow to be frequently interrupted.

[0074] Therefore, in this embodiment, the problem is alleviated by isolating the processing subunit 132. The isolation processing subunit 132 can determine whether the abnormality needs to be filtered out based on the signal type of the collected signal when the trigger control subunit 131 determines that the abnormality is triggered. Filtering here can mean eliminating the abnormality, or downgrading the abnormality. For example, if the originally triggered abnormality requires uploading an interrupt signal to the CPU, it can be downgraded to only recording the abnormality without uploading the interrupt signal to the CPU.

[0075] When determining whether to filter out an abnormality based on the signal type of the collected signal, the signal type of the collected signal may be compared with a pre-configured signal type. If the signal type of the collected signal matches the pre-configured signal type, it may be determined that the abnormality can be filtered out. If the signal type of the collected signal does not match the pre-configured signal type, it may be determined that the abnormality is maintained.

[0076] The pre-configured signal types may be signal types that have little impact on system operation and will not cause serious errors, such as CRC signals.

[0077] In this way, some signals that have little impact on the operation of the system, even if the signal triggers an exception, can be filtered out after being judged and processed by the isolation processing sub-unit 132, thereby avoiding such signals from frequently triggering exceptions, thereby causing excessive CPU processing load, or frequently causing processing flow interruptions, etc.

[0078] On this basis, the adaptive processing subunit 133 in the signal processing unit 13 can determine whether to output a reset signal to the output control subunit 134 in combination with the determination result of the trigger control subunit 131 and the determination result of the isolation processing subunit 132 .

[0079] Specifically, if the trigger control subunit 131 triggers an abnormality of outputting a reset signal, and the isolation processing subunit 132 determines to maintain the abnormality, the adaptive processing subunit 133 may determine to output a reset signal.

[0080] If the trigger control subunit 131 triggers an abnormality in outputting a reset signal, and the isolation processing subunit 132 determines to filter out the abnormality, the adaptive processing subunit 133 may determine that there is no need to output a reset signal.

[0081] Similarly, if the trigger control subunit 131 triggers an abnormality of outputting an interrupt signal, and the isolation processing subunit 132 determines to maintain the abnormality, the adaptive processing subunit 133 may determine to output the interrupt signal.

[0082] If the trigger control subunit 131 triggers an abnormality in outputting an interrupt signal, and the isolation processing subunit 132 determines to filter out the abnormality, the adaptive processing subunit 133 may determine that there is no need to output the interrupt signal.

[0083] In this embodiment, the final output is determined by the adaptive processing sub-unit 133 in combination with the determination result of the trigger control sub-unit 131 and the determination result of the isolation processing sub-unit 132, and the reset signal and the interrupt signal can be decided independently. On the one hand, it can ensure the accurate processing of important signals and avoid further errors caused by abnormalities of important signals. On the other hand, it can reduce unnecessary processing burden and achieve the purpose of speeding up fault handling efficiency to a certain extent.

[0084] Based on the above, in this embodiment, the output control unit 14 can output a reset signal to the target module to reset the target module. The output control unit 14 can also output an interrupt signal to the CPU to execute an interrupt operation through the CPU.

[0085] Please refer to Figure 6 In this embodiment, the output control unit 14 includes an interface processing subunit 141, a reset output interface subunit 142, an interrupt output interface subunit 143, and a backup output interface subunit 144. The interface processing subunit 141 is connected to the reset output interface subunit 142, the interrupt output interface subunit 143, and the backup output interface subunit 144 respectively.

[0086] The interface processing subunit 141 is used to determine whether to send the signal to the reset output interface subunit 142 , the interrupt output interface subunit 143 or the backup output interface subunit 144 after receiving the signal.

[0087] For example, if the interface processing subunit 141 receives a reset signal, it determines to send the reset signal to the reset output interface subunit 142, so that the reset signal is sent to the target module through the reset output interface subunit 142 to reset the target module.

[0088] In this embodiment, the reset output interface subunit 142 can directly output the reset signal to the target module to achieve the reset of the target module. This process does not require the CPU to participate and makes autonomous decisions, which reduces the CPU load pressure and realizes a faster and more flexible fault handling method based on the chip.

[0089] If the interface processing subunit 141 receives an interrupt signal, it determines to send the interrupt signal to the interrupt output interface subunit 143, so that the interrupt signal is sent to the CPU through the interrupt output interface subunit 143, so that the CPU performs an interrupt operation on the target module.

[0090] In addition, the output control unit 14 can also back up the signals that need to be backed up to an off-chip Flash, that is, a non-volatile storage medium outside the chip.

[0091] In this embodiment, the mode information pre-configured by the configuration unit 11 also includes an off-chip storage address, and the off-chip storage address mainly refers to the starting address of the off-chip Flash recording information.

[0092] Based on this, the output control unit 14 can be used to store the required backup signal into the off-chip Flash based on the off-chip storage address, for example, storing the signal segment within the waiting time extracted from the above timestamp exception mode into the off-chip Flash.

[0093] Specifically, after obtaining the required backup signal, the interface processing subunit 141 in the output control unit 14 determines to send the required backup signal to the backup output interface subunit 144, so as to output the required backup signal to the off-chip Flash through the backup output interface subunit 144 to achieve backup. In this way, the required backup signal is saved in the off-chip Flash, and the abnormal scene can be restored later.

[0094] The chip adaptive fault handling system provided in this embodiment can flexibly collect signals from other modules inside the chip according to the configuration of the CPU, so as to facilitate fault monitoring and recovery of debugging simulation, operation monitoring, etc. at different stages of the chip.

[0095] This solution supports multiple abnormal trigger modes. In the timestamp trigger mode, when it is determined that the collected signal is abnormal, the abnormality is triggered after the waiting time is reached. In this way, the signal information of the collected signal within the waiting time can be retained, so as to facilitate the further analysis of the abnormal information of the collected signal.

[0096] In addition, in this solution, an isolation processing subunit 132 is added to isolate the abnormalities that have occurred. On the one hand, it can ensure the timely discovery and recovery of faults of important signals, and on the other hand, it can avoid the frequent triggering of abnormalities of signals that have little impact on system operation, thereby reducing the processing load of the CPU.

[0097] Furthermore, the adaptive processing subunit 133 in this solution can autonomously decide whether to generate a reset signal, an interrupt signal, etc., thereby avoiding the time delay caused by the CPU decision, thereby accelerating the efficiency of fault recovery.

[0098] Based on the same inventive concept, please refer to Figure 7 The embodiment of the present invention further provides a chip adaptive fault processing method, which can be applied to the chip adaptive fault processing system in any one of the implementation modes in the above embodiments, and the method comprises the following steps: S11 , the configuration unit 11 performs mode information configuration based on the information obtained from the CPU.

[0099] S12, the signal acquisition unit 12 acquires signals from the target module based on the mode information to obtain acquired signals.

[0100] S13, the signal processing unit 13 processes the collected signal based on the mode information, and obtains a corresponding reset signal when determining that a trigger abnormality occurs.

[0101] S14, the output control unit 14 outputs a reset signal to the target module to reset the target module.

[0102] In the chip adaptive fault handling method provided in this embodiment, the chip can flexibly realize signal collection based on the configuration of the CPU, and perform abnormal detection processing on the collected signal, and then generate a reset signal when the abnormality is triggered, and the reset of the target module in the chip can be realized based on the reset signal. In this solution, there is no need to completely rely on the CPU to perform reset operations, etc. The chip can make independent decisions and perform reset operations, which reduces the processing burden of the CPU, and can also perform fault recovery on the CPU when an abnormality occurs in the CPU, avoiding serious abnormalities in the entire server system.

[0103] As a possible implementation, the signal processing unit 13 includes a trigger control subunit 131, an isolation processing subunit 132, an adaptive processing subunit 133 and an output control subunit 134. The signal processing unit 13 can process the collected signal in the following manner: The trigger control subunit 131 determines whether the acquisition signal triggers an abnormality based on the mode information; When the trigger control subunit 131 determines that an abnormality is triggered, the isolation processing subunit 132 determines whether to maintain the abnormality or filter out the abnormality based on the signal type of the collected signal; The adaptive processing subunit 133 determines whether to output a reset signal in combination with the determination result of the trigger control subunit 131 and the determination result of the isolation processing subunit 132; When the adaptive processing subunit 133 determines to output the reset signal, the output control subunit 134 outputs the reset signal to the output control unit 14 .

[0104] As a possible implementation, the abnormal trigger mode includes a timestamp trigger mode, and the timestamp trigger mode includes a trigger signal type, a trigger mode, and a waiting time. The signal processing unit 13 can determine whether an abnormality is triggered in the following manner: When the signal processing unit 13 determines that the acquisition signal is a trigger signal type in the timestamp trigger mode and the acquisition signal conforms to the trigger mode in the timestamp trigger mode, the signal processing unit 13 triggers an exception after the waiting time is satisfied.

[0105] As a possible implementation manner, the chip adaptive fault processing method may further include the following steps: The signal acquisition unit 12 stores the acquired signal into the storage unit 15; When the signal processing unit 13 determines that the acquisition signal triggers the timestamp trigger mode, it extracts the signal segment within the waiting time of the acquisition signal from the storage unit 15 and outputs it to the output control unit 14; The output control unit 14 outputs the signal segment to other modules of the chip for signal analysis.

[0106] As a possible implementation, the mode information includes storage mode information and an off-chip storage address, and the chip adaptive fault processing method further includes the following steps: The signal acquisition unit 12 stores the acquired signal into the storage unit 15 based on the storage mode information; The output control unit 14 stores the required backup signal into the off-chip Flash based on the off-chip storage address.

[0107] As a possible implementation, the mode information includes multiple abnormal trigger modes, each abnormal trigger mode includes a trigger mode and a trigger signal type, and the signal processing unit 13 determines whether the acquisition signal triggers an abnormality in the following manner: The signal processing unit 13 determines the target trigger signal type corresponding to the acquisition signal, and determines whether the acquisition signal triggers an abnormality based on the target trigger mode corresponding to the target trigger signal type.

[0108] As a possible implementation method, the triggering method includes a triggering event, the number of triggering events, and a combination method; The trigger events include rising edge events, falling edge events and preset level width events, and the combination methods include multiple methods composed of at least one trigger event.

[0109] As a possible implementation, the mode information includes multiple acquisition modes, each of which corresponds to an acquisition port and a signal type of the chip. The signal acquisition unit 12 obtains the acquisition signal in the following manner: The signal acquisition unit 12 determines a target acquisition port and a target signal type based on the acquisition mode in the mode information, and acquires a signal corresponding to the target signal type based on the target acquisition port to obtain an acquisition signal.

[0110] As a possible implementation manner, the configuration unit 11 is used to uniformly configure the port information of the corresponding collection ports in each collection mode and the signal information corresponding to the signal type into a mode template.

[0111] The chip adaptive fault handling method provided in this embodiment is applied to the chip adaptive fault handling system in any one of the implementation modes of the above embodiments, and has the same, corresponding or similar technical features and beneficial effects as the above chip adaptive fault handling system. Therefore, for the details not provided in this embodiment, please refer to the relevant description of the above chip adaptive fault handling system, and this embodiment will not be elaborated here.

[0112] In summary, the chip adaptive fault processing system and method provided by the embodiment of the present invention includes a configuration unit 11, a signal acquisition unit 12, a signal processing unit 13 and an output control unit 14, wherein the configuration unit 11 is used to configure the mode information based on the information obtained from the CPU, the signal acquisition unit 12 is used to obtain the acquisition signal of the target module based on the mode information, the signal processing unit 13 is used to process the acquisition signal based on the mode information, and obtain a reset signal when it is determined that an abnormality is triggered, and the output control unit 14 is used to output the reset signal to the target module to achieve reset. In this solution, the chip can perform the processing of the acquisition signal based on the configuration of the CPU, and then generate a reset signal to perform reset when an abnormality is triggered, without relying on the CPU to perform reset, reducing the processing burden of the CPU, and can also perform fault recovery on the CPU when an abnormality occurs in the CPU, avoiding the problem of serious abnormalities in the entire server system.

[0113] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0114] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A chip adaptive fault handling system, characterized in that: A fault processing module applied to a chip including multiple modules, the system includes a configuration unit, a signal acquisition unit, a signal processing unit and an output control unit, the configuration unit is respectively connected to a CPU in a server, the signal acquisition unit, and the signal processing unit, the signal acquisition unit is also connected to the signal processing unit, and the signal processing unit is also connected to the output control unit; The configuration unit is used to configure mode information based on information obtained from the CPU; The signal acquisition unit is used to acquire signals from the target module based on the mode information to obtain acquisition signals; The signal processing unit is used to process the collected signal based on the mode information, and obtain a corresponding reset signal when determining that a trigger abnormality occurs; The output control unit is used to output the reset signal to the target module to achieve the reset of the target module.

2. The chip adaptive fault processing system according to claim 1, characterized in that: The signal processing unit includes a trigger control subunit, an isolation processing subunit, an adaptive processing subunit and an output control subunit; The trigger control subunit is used to determine whether the acquisition signal triggers an abnormality based on the mode information; The isolation processing subunit is used for determining whether to maintain or filter out the abnormality based on the signal type of the acquisition signal when the trigger control subunit determines that the abnormality is triggered; The adaptive processing subunit is used to determine whether to output a reset signal in combination with the determination result of the trigger control subunit and the determination result of the isolation processing subunit; The output control subunit is used for outputting the reset signal to the output control unit when the adaptive processing subunit determines to output the reset signal.

3. The chip adaptive fault processing system according to claim 1, characterized in that: The mode information includes an abnormal trigger mode, the abnormal trigger mode includes a timestamp trigger mode, and the timestamp trigger mode includes a trigger signal type, a trigger mode, and a waiting time; The signal processing unit is used for triggering an exception after the waiting time is satisfied when it is determined that the acquisition signal is a trigger signal type in the timestamp trigger mode and the acquisition signal conforms to the trigger mode in the timestamp trigger mode.

4. The chip adaptive fault processing system according to claim 3, characterized in that: The system also includes a storage unit; The signal acquisition unit is also used to store the acquired signal into the storage unit; The signal processing unit is further configured to extract a signal segment within the waiting time of the acquisition signal from the storage unit and output the signal segment to the output control unit when determining that the acquisition signal triggers the timestamp trigger mode; The output control unit is further used to output the signal segment to other modules of the chip used for signal analysis.

5. The chip adaptive fault processing system according to claim 1, characterized in that: The system further comprises a storage unit, wherein the mode information comprises storage mode information and an off-chip storage address; The signal acquisition unit is used to store the acquired signal into the storage unit based on the storage mode information; The output control unit is further used to store the required backup signal into the off-chip Flash based on the off-chip storage address.

6. The chip adaptive fault processing system according to claim 1, characterized in that: The mode information includes a plurality of abnormal trigger modes, each of which includes a triggering method and a triggering signal type; The signal processing unit is used to determine the target trigger signal type corresponding to the acquisition signal, and judge whether the acquisition signal triggers an abnormality based on the target trigger mode corresponding to the target trigger signal type.

7. The chip adaptive fault processing system according to claim 6, characterized in that: The triggering method includes triggering events, the number of triggering events and the combination method; The trigger events include rising edge events, falling edge events and preset level width events, and the combination methods include multiple methods each consisting of at least one trigger event.

8. The chip adaptive fault processing system according to claim 1, characterized in that: The mode information includes a plurality of acquisition modes, each of which corresponds to an acquisition port and a signal type of the chip; The signal acquisition unit is used to determine a target acquisition port and a target signal type based on the acquisition mode in the mode information, and acquire a signal corresponding to the target signal type based on the target acquisition port to obtain an acquisition signal.

9. The chip adaptive fault processing system according to claim 8, characterized in that: The configuration unit is used to uniformly configure the port information of the corresponding collection ports in each of the collection modes and the signal information corresponding to the signal type into a mode template.

10. A chip adaptive fault processing method, characterized in that: The chip adaptive fault processing system applied to any one of claims 1 to 9 comprises a configuration unit, a signal acquisition unit, a signal processing unit and an output control unit, and the chip adaptive fault processing method comprises: The configuration unit performs mode information configuration based on information obtained from the CPU; The signal acquisition unit acquires signals from the target module based on the mode information to obtain acquisition signals; The signal processing unit processes the collected signal based on the mode information, and obtains a corresponding reset signal when determining that a trigger abnormality occurs; The output control unit outputs the reset signal to the target module to achieve the reset of the target module.

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